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Remove low_latency flag setting from nozomi and mxser drivers
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / crypto / ixp4xx_crypto.c
blobfdcd0ab3aa0b0cfb68d8bd72d8d255be472a6e72
1 /*
2 * Intel IXP4xx NPE-C crypto driver
3 *
4 * Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmapool.h>
15 #include <linux/crypto.h>
16 #include <linux/kernel.h>
17 #include <linux/rtnetlink.h>
18 #include <linux/interrupt.h>
19 #include <linux/spinlock.h>
20
21 #include <crypto/ctr.h>
22 #include <crypto/des.h>
23 #include <crypto/aes.h>
24 #include <crypto/sha.h>
25 #include <crypto/algapi.h>
26 #include <crypto/aead.h>
27 #include <crypto/authenc.h>
28 #include <crypto/scatterwalk.h>
29
30 #include <mach/npe.h>
31 #include <mach/qmgr.h>
32
33 #define MAX_KEYLEN 32
34
35 /* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */
36 #define NPE_CTX_LEN 80
37 #define AES_BLOCK128 16
38
39 #define NPE_OP_HASH_VERIFY 0x01
40 #define NPE_OP_CCM_ENABLE 0x04
41 #define NPE_OP_CRYPT_ENABLE 0x08
42 #define NPE_OP_HASH_ENABLE 0x10
43 #define NPE_OP_NOT_IN_PLACE 0x20
44 #define NPE_OP_HMAC_DISABLE 0x40
45 #define NPE_OP_CRYPT_ENCRYPT 0x80
46
47 #define NPE_OP_CCM_GEN_MIC 0xcc
48 #define NPE_OP_HASH_GEN_ICV 0x50
49 #define NPE_OP_ENC_GEN_KEY 0xc9
50
51 #define MOD_ECB 0x0000
52 #define MOD_CTR 0x1000
53 #define MOD_CBC_ENC 0x2000
54 #define MOD_CBC_DEC 0x3000
55 #define MOD_CCM_ENC 0x4000
56 #define MOD_CCM_DEC 0x5000
57
58 #define KEYLEN_128 4
59 #define KEYLEN_192 6
60 #define KEYLEN_256 8
61
62 #define CIPH_DECR 0x0000
63 #define CIPH_ENCR 0x0400
64
65 #define MOD_DES 0x0000
66 #define MOD_TDEA2 0x0100
67 #define MOD_3DES 0x0200
68 #define MOD_AES 0x0800
69 #define MOD_AES128 (0x0800 | KEYLEN_128)
70 #define MOD_AES192 (0x0900 | KEYLEN_192)
71 #define MOD_AES256 (0x0a00 | KEYLEN_256)
72
73 #define MAX_IVLEN 16
74 #define NPE_ID 2 /* NPE C */
75 #define NPE_QLEN 16
76 /* Space for registering when the first
77 * NPE_QLEN crypt_ctl are busy */
78 #define NPE_QLEN_TOTAL 64
79
80 #define SEND_QID 29
81 #define RECV_QID 30
82
83 #define CTL_FLAG_UNUSED 0x0000
84 #define CTL_FLAG_USED 0x1000
85 #define CTL_FLAG_PERFORM_ABLK 0x0001
86 #define CTL_FLAG_GEN_ICV 0x0002
87 #define CTL_FLAG_GEN_REVAES 0x0004
88 #define CTL_FLAG_PERFORM_AEAD 0x0008
89 #define CTL_FLAG_MASK 0x000f
90
91 #define HMAC_IPAD_VALUE 0x36
92 #define HMAC_OPAD_VALUE 0x5C
93 #define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE
94
95 #define MD5_DIGEST_SIZE 16
96
97 struct buffer_desc {
98 u32 phys_next;
99 u16 buf_len;
100 u16 pkt_len;
101 u32 phys_addr;
102 u32 __reserved[4];
103 struct buffer_desc *next;
104 enum dma_data_direction dir;
105 };
106
107 struct crypt_ctl {
108 u8 mode; /* NPE_OP_* operation mode */
109 u8 init_len;
110 u16 reserved;
111 u8 iv[MAX_IVLEN]; /* IV for CBC mode or CTR IV for CTR mode */
112 u32 icv_rev_aes; /* icv or rev aes */
113 u32 src_buf;
114 u32 dst_buf;
115 u16 auth_offs; /* Authentication start offset */
116 u16 auth_len; /* Authentication data length */
117 u16 crypt_offs; /* Cryption start offset */
118 u16 crypt_len; /* Cryption data length */
119 u32 aadAddr; /* Additional Auth Data Addr for CCM mode */
120 u32 crypto_ctx; /* NPE Crypto Param structure address */
121
122 /* Used by Host: 4*4 bytes*/
123 unsigned ctl_flags;
124 union {
125 struct ablkcipher_request *ablk_req;
126 struct aead_request *aead_req;
127 struct crypto_tfm *tfm;
128 } data;
129 struct buffer_desc *regist_buf;
130 u8 *regist_ptr;
131 };
132
133 struct ablk_ctx {
134 struct buffer_desc *src;
135 struct buffer_desc *dst;
136 };
137
138 struct aead_ctx {
139 struct buffer_desc *buffer;
140 struct scatterlist ivlist;
141 /* used when the hmac is not on one sg entry */
142 u8 *hmac_virt;
143 int encrypt;
144 };
145
146 struct ix_hash_algo {
147 u32 cfgword;
148 unsigned char *icv;
149 };
150
151 struct ix_sa_dir {
152 unsigned char *npe_ctx;
153 dma_addr_t npe_ctx_phys;
154 int npe_ctx_idx;
155 u8 npe_mode;
156 };
157
158 struct ixp_ctx {
159 struct ix_sa_dir encrypt;
160 struct ix_sa_dir decrypt;
161 int authkey_len;
162 u8 authkey[MAX_KEYLEN];
163 int enckey_len;
164 u8 enckey[MAX_KEYLEN];
165 u8 salt[MAX_IVLEN];
166 u8 nonce[CTR_RFC3686_NONCE_SIZE];
167 unsigned salted;
168 atomic_t configuring;
169 struct completion completion;
170 };
171
172 struct ixp_alg {
173 struct crypto_alg crypto;
174 const struct ix_hash_algo *hash;
175 u32 cfg_enc;
176 u32 cfg_dec;
177
178 int registered;
179 };
180
181 static const struct ix_hash_algo hash_alg_md5 = {
182 .cfgword = 0xAA010004,
183 .icv = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
184 "\xFE\xDC\xBA\x98\x76\x54\x32\x10",
185 };
186 static const struct ix_hash_algo hash_alg_sha1 = {
187 .cfgword = 0x00000005,
188 .icv = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
189 "\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
190 };
191
192 static struct npe *npe_c;
193 static struct dma_pool *buffer_pool = NULL;
194 static struct dma_pool *ctx_pool = NULL;
195
196 static struct crypt_ctl *crypt_virt = NULL;
197 static dma_addr_t crypt_phys;
198
199 static int support_aes = 1;
200
201 static void dev_release(struct device *dev)
202 {
203 return;
204 }
205
206 #define DRIVER_NAME "ixp4xx_crypto"
207 static struct platform_device pseudo_dev = {
208 .name = DRIVER_NAME,
209 .id = 0,
210 .num_resources = 0,
211 .dev = {
212 .coherent_dma_mask = DMA_32BIT_MASK,
213 .release = dev_release,
214 }
215 };
216
217 static struct device *dev = &pseudo_dev.dev;
218
219 static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt)
220 {
221 return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl);
222 }
223
224 static inline struct crypt_ctl *crypt_phys2virt(dma_addr_t phys)
225 {
226 return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl);
227 }
228
229 static inline u32 cipher_cfg_enc(struct crypto_tfm *tfm)
230 {
231 return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_enc;
232 }
233
234 static inline u32 cipher_cfg_dec(struct crypto_tfm *tfm)
235 {
236 return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_dec;
237 }
238
239 static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm)
240 {
241 return container_of(tfm->__crt_alg, struct ixp_alg, crypto)->hash;
242 }
243
244 static int setup_crypt_desc(void)
245 {
246 BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64);
247 crypt_virt = dma_alloc_coherent(dev,
248 NPE_QLEN * sizeof(struct crypt_ctl),
249 &crypt_phys, GFP_KERNEL);
250 if (!crypt_virt)
251 return -ENOMEM;
252 memset(crypt_virt, 0, NPE_QLEN * sizeof(struct crypt_ctl));
253 return 0;
254 }
255
256 static spinlock_t desc_lock;
257 static struct crypt_ctl *get_crypt_desc(void)
258 {
259 int i;
260 static int idx = 0;
261 unsigned long flags;
262
263 spin_lock_irqsave(&desc_lock, flags);
264
265 if (unlikely(!crypt_virt))
266 setup_crypt_desc();
267 if (unlikely(!crypt_virt)) {
268 spin_unlock_irqrestore(&desc_lock, flags);
269 return NULL;
270 }
271 i = idx;
272 if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
273 if (++idx >= NPE_QLEN)
274 idx = 0;
275 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
276 spin_unlock_irqrestore(&desc_lock, flags);
277 return crypt_virt +i;
278 } else {
279 spin_unlock_irqrestore(&desc_lock, flags);
280 return NULL;
281 }
282 }
283
284 static spinlock_t emerg_lock;
285 static struct crypt_ctl *get_crypt_desc_emerg(void)
286 {
287 int i;
288 static int idx = NPE_QLEN;
289 struct crypt_ctl *desc;
290 unsigned long flags;
291
292 desc = get_crypt_desc();
293 if (desc)
294 return desc;
295 if (unlikely(!crypt_virt))
296 return NULL;
297
298 spin_lock_irqsave(&emerg_lock, flags);
299 i = idx;
300 if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
301 if (++idx >= NPE_QLEN_TOTAL)
302 idx = NPE_QLEN;
303 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
304 spin_unlock_irqrestore(&emerg_lock, flags);
305 return crypt_virt +i;
306 } else {
307 spin_unlock_irqrestore(&emerg_lock, flags);
308 return NULL;
309 }
310 }
311
312 static void free_buf_chain(struct device *dev, struct buffer_desc *buf,u32 phys)
313 {
314 while (buf) {
315 struct buffer_desc *buf1;
316 u32 phys1;
317
318 buf1 = buf->next;
319 phys1 = buf->phys_next;
320 dma_unmap_single(dev, buf->phys_next, buf->buf_len, buf->dir);
321 dma_pool_free(buffer_pool, buf, phys);
322 buf = buf1;
323 phys = phys1;
324 }
325 }
326
327 static struct tasklet_struct crypto_done_tasklet;
328
329 static void finish_scattered_hmac(struct crypt_ctl *crypt)
330 {
331 struct aead_request *req = crypt->data.aead_req;
332 struct aead_ctx *req_ctx = aead_request_ctx(req);
333 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
334 int authsize = crypto_aead_authsize(tfm);
335 int decryptlen = req->cryptlen - authsize;
336
337 if (req_ctx->encrypt) {
338 scatterwalk_map_and_copy(req_ctx->hmac_virt,
339 req->src, decryptlen, authsize, 1);
340 }
341 dma_pool_free(buffer_pool, req_ctx->hmac_virt, crypt->icv_rev_aes);
342 }
343
344 static void one_packet(dma_addr_t phys)
345 {
346 struct crypt_ctl *crypt;
347 struct ixp_ctx *ctx;
348 int failed;
349
350 failed = phys & 0x1 ? -EBADMSG : 0;
351 phys &= ~0x3;
352 crypt = crypt_phys2virt(phys);
353
354 switch (crypt->ctl_flags & CTL_FLAG_MASK) {
355 case CTL_FLAG_PERFORM_AEAD: {
356 struct aead_request *req = crypt->data.aead_req;
357 struct aead_ctx *req_ctx = aead_request_ctx(req);
358
359 free_buf_chain(dev, req_ctx->buffer, crypt->src_buf);
360 if (req_ctx->hmac_virt) {
361 finish_scattered_hmac(crypt);
362 }
363 req->base.complete(&req->base, failed);
364 break;
365 }
366 case CTL_FLAG_PERFORM_ABLK: {
367 struct ablkcipher_request *req = crypt->data.ablk_req;
368 struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
369
370 if (req_ctx->dst) {
371 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
372 }
373 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
374 req->base.complete(&req->base, failed);
375 break;
376 }
377 case CTL_FLAG_GEN_ICV:
378 ctx = crypto_tfm_ctx(crypt->data.tfm);
379 dma_pool_free(ctx_pool, crypt->regist_ptr,
380 crypt->regist_buf->phys_addr);
381 dma_pool_free(buffer_pool, crypt->regist_buf, crypt->src_buf);
382 if (atomic_dec_and_test(&ctx->configuring))
383 complete(&ctx->completion);
384 break;
385 case CTL_FLAG_GEN_REVAES:
386 ctx = crypto_tfm_ctx(crypt->data.tfm);
387 *(u32*)ctx->decrypt.npe_ctx &= cpu_to_be32(~CIPH_ENCR);
388 if (atomic_dec_and_test(&ctx->configuring))
389 complete(&ctx->completion);
390 break;
391 default:
392 BUG();
393 }
394 crypt->ctl_flags = CTL_FLAG_UNUSED;
395 }
396
397 static void irqhandler(void *_unused)
398 {
399 tasklet_schedule(&crypto_done_tasklet);
400 }
401
402 static void crypto_done_action(unsigned long arg)
403 {
404 int i;
405
406 for(i=0; i<4; i++) {
407 dma_addr_t phys = qmgr_get_entry(RECV_QID);
408 if (!phys)
409 return;
410 one_packet(phys);
411 }
412 tasklet_schedule(&crypto_done_tasklet);
413 }
414
415 static int init_ixp_crypto(void)
416 {
417 int ret = -ENODEV;
418
419 if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
420 IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
421 printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
422 return ret;
423 }
424 npe_c = npe_request(NPE_ID);
425 if (!npe_c)
426 return ret;
427
428 if (!npe_running(npe_c)) {
429 npe_load_firmware(npe_c, npe_name(npe_c), dev);
430 }
431
432 /* buffer_pool will also be used to sometimes store the hmac,
433 * so assure it is large enough
434 */
435 BUILD_BUG_ON(SHA1_DIGEST_SIZE > sizeof(struct buffer_desc));
436 buffer_pool = dma_pool_create("buffer", dev,
437 sizeof(struct buffer_desc), 32, 0);
438 ret = -ENOMEM;
439 if (!buffer_pool) {
440 goto err;
441 }
442 ctx_pool = dma_pool_create("context", dev,
443 NPE_CTX_LEN, 16, 0);
444 if (!ctx_pool) {
445 goto err;
446 }
447 ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0);
448 if (ret)
449 goto err;
450 ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0);
451 if (ret) {
452 qmgr_release_queue(SEND_QID);
453 goto err;
454 }
455 qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL);
456 tasklet_init(&crypto_done_tasklet, crypto_done_action, 0);
457
458 qmgr_enable_irq(RECV_QID);
459 return 0;
460 err:
461 if (ctx_pool)
462 dma_pool_destroy(ctx_pool);
463 if (buffer_pool)
464 dma_pool_destroy(buffer_pool);
465 npe_release(npe_c);
466 return ret;
467 }
468
469 static void release_ixp_crypto(void)
470 {
471 qmgr_disable_irq(RECV_QID);
472 tasklet_kill(&crypto_done_tasklet);
473
474 qmgr_release_queue(SEND_QID);
475 qmgr_release_queue(RECV_QID);
476
477 dma_pool_destroy(ctx_pool);
478 dma_pool_destroy(buffer_pool);
479
480 npe_release(npe_c);
481
482 if (crypt_virt) {
483 dma_free_coherent(dev,
484 NPE_QLEN_TOTAL * sizeof( struct crypt_ctl),
485 crypt_virt, crypt_phys);
486 }
487 return;
488 }
489
490 static void reset_sa_dir(struct ix_sa_dir *dir)
491 {
492 memset(dir->npe_ctx, 0, NPE_CTX_LEN);
493 dir->npe_ctx_idx = 0;
494 dir->npe_mode = 0;
495 }
496
497 static int init_sa_dir(struct ix_sa_dir *dir)
498 {
499 dir->npe_ctx = dma_pool_alloc(ctx_pool, GFP_KERNEL, &dir->npe_ctx_phys);
500 if (!dir->npe_ctx) {
501 return -ENOMEM;
502 }
503 reset_sa_dir(dir);
504 return 0;
505 }
506
507 static void free_sa_dir(struct ix_sa_dir *dir)
508 {
509 memset(dir->npe_ctx, 0, NPE_CTX_LEN);
510 dma_pool_free(ctx_pool, dir->npe_ctx, dir->npe_ctx_phys);
511 }
512
513 static int init_tfm(struct crypto_tfm *tfm)
514 {
515 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
516 int ret;
517
518 atomic_set(&ctx->configuring, 0);
519 ret = init_sa_dir(&ctx->encrypt);
520 if (ret)
521 return ret;
522 ret = init_sa_dir(&ctx->decrypt);
523 if (ret) {
524 free_sa_dir(&ctx->encrypt);
525 }
526 return ret;
527 }
528
529 static int init_tfm_ablk(struct crypto_tfm *tfm)
530 {
531 tfm->crt_ablkcipher.reqsize = sizeof(struct ablk_ctx);
532 return init_tfm(tfm);
533 }
534
535 static int init_tfm_aead(struct crypto_tfm *tfm)
536 {
537 tfm->crt_aead.reqsize = sizeof(struct aead_ctx);
538 return init_tfm(tfm);
539 }
540
541 static void exit_tfm(struct crypto_tfm *tfm)
542 {
543 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
544 free_sa_dir(&ctx->encrypt);
545 free_sa_dir(&ctx->decrypt);
546 }
547
548 static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target,
549 int init_len, u32 ctx_addr, const u8 *key, int key_len)
550 {
551 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
552 struct crypt_ctl *crypt;
553 struct buffer_desc *buf;
554 int i;
555 u8 *pad;
556 u32 pad_phys, buf_phys;
557
558 BUILD_BUG_ON(NPE_CTX_LEN < HMAC_PAD_BLOCKLEN);
559 pad = dma_pool_alloc(ctx_pool, GFP_KERNEL, &pad_phys);
560 if (!pad)
561 return -ENOMEM;
562 buf = dma_pool_alloc(buffer_pool, GFP_KERNEL, &buf_phys);
563 if (!buf) {
564 dma_pool_free(ctx_pool, pad, pad_phys);
565 return -ENOMEM;
566 }
567 crypt = get_crypt_desc_emerg();
568 if (!crypt) {
569 dma_pool_free(ctx_pool, pad, pad_phys);
570 dma_pool_free(buffer_pool, buf, buf_phys);
571 return -EAGAIN;
572 }
573
574 memcpy(pad, key, key_len);
575 memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len);
576 for (i = 0; i < HMAC_PAD_BLOCKLEN; i++) {
577 pad[i] ^= xpad;
578 }
579
580 crypt->data.tfm = tfm;
581 crypt->regist_ptr = pad;
582 crypt->regist_buf = buf;
583
584 crypt->auth_offs = 0;
585 crypt->auth_len = HMAC_PAD_BLOCKLEN;
586 crypt->crypto_ctx = ctx_addr;
587 crypt->src_buf = buf_phys;
588 crypt->icv_rev_aes = target;
589 crypt->mode = NPE_OP_HASH_GEN_ICV;
590 crypt->init_len = init_len;
591 crypt->ctl_flags |= CTL_FLAG_GEN_ICV;
592
593 buf->next = 0;
594 buf->buf_len = HMAC_PAD_BLOCKLEN;
595 buf->pkt_len = 0;
596 buf->phys_addr = pad_phys;
597
598 atomic_inc(&ctx->configuring);
599 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
600 BUG_ON(qmgr_stat_overflow(SEND_QID));
601 return 0;
602 }
603
604 static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned authsize,
605 const u8 *key, int key_len, unsigned digest_len)
606 {
607 u32 itarget, otarget, npe_ctx_addr;
608 unsigned char *cinfo;
609 int init_len, ret = 0;
610 u32 cfgword;
611 struct ix_sa_dir *dir;
612 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
613 const struct ix_hash_algo *algo;
614
615 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
616 cinfo = dir->npe_ctx + dir->npe_ctx_idx;
617 algo = ix_hash(tfm);
618
619 /* write cfg word to cryptinfo */
620 cfgword = algo->cfgword | ( authsize << 6); /* (authsize/4) << 8 */
621 *(u32*)cinfo = cpu_to_be32(cfgword);
622 cinfo += sizeof(cfgword);
623
624 /* write ICV to cryptinfo */
625 memcpy(cinfo, algo->icv, digest_len);
626 cinfo += digest_len;
627
628 itarget = dir->npe_ctx_phys + dir->npe_ctx_idx
629 + sizeof(algo->cfgword);
630 otarget = itarget + digest_len;
631 init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
632 npe_ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx;
633
634 dir->npe_ctx_idx += init_len;
635 dir->npe_mode |= NPE_OP_HASH_ENABLE;
636
637 if (!encrypt)
638 dir->npe_mode |= NPE_OP_HASH_VERIFY;
639
640 ret = register_chain_var(tfm, HMAC_OPAD_VALUE, otarget,
641 init_len, npe_ctx_addr, key, key_len);
642 if (ret)
643 return ret;
644 return register_chain_var(tfm, HMAC_IPAD_VALUE, itarget,
645 init_len, npe_ctx_addr, key, key_len);
646 }
647
648 static int gen_rev_aes_key(struct crypto_tfm *tfm)
649 {
650 struct crypt_ctl *crypt;
651 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
652 struct ix_sa_dir *dir = &ctx->decrypt;
653
654 crypt = get_crypt_desc_emerg();
655 if (!crypt) {
656 return -EAGAIN;
657 }
658 *(u32*)dir->npe_ctx |= cpu_to_be32(CIPH_ENCR);
659
660 crypt->data.tfm = tfm;
661 crypt->crypt_offs = 0;
662 crypt->crypt_len = AES_BLOCK128;
663 crypt->src_buf = 0;
664 crypt->crypto_ctx = dir->npe_ctx_phys;
665 crypt->icv_rev_aes = dir->npe_ctx_phys + sizeof(u32);
666 crypt->mode = NPE_OP_ENC_GEN_KEY;
667 crypt->init_len = dir->npe_ctx_idx;
668 crypt->ctl_flags |= CTL_FLAG_GEN_REVAES;
669
670 atomic_inc(&ctx->configuring);
671 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
672 BUG_ON(qmgr_stat_overflow(SEND_QID));
673 return 0;
674 }
675
676 static int setup_cipher(struct crypto_tfm *tfm, int encrypt,
677 const u8 *key, int key_len)
678 {
679 u8 *cinfo;
680 u32 cipher_cfg;
681 u32 keylen_cfg = 0;
682 struct ix_sa_dir *dir;
683 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
684 u32 *flags = &tfm->crt_flags;
685
686 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
687 cinfo = dir->npe_ctx;
688
689 if (encrypt) {
690 cipher_cfg = cipher_cfg_enc(tfm);
691 dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT;
692 } else {
693 cipher_cfg = cipher_cfg_dec(tfm);
694 }
695 if (cipher_cfg & MOD_AES) {
696 switch (key_len) {
697 case 16: keylen_cfg = MOD_AES128 | KEYLEN_128; break;
698 case 24: keylen_cfg = MOD_AES192 | KEYLEN_192; break;
699 case 32: keylen_cfg = MOD_AES256 | KEYLEN_256; break;
700 default:
701 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
702 return -EINVAL;
703 }
704 cipher_cfg |= keylen_cfg;
705 } else if (cipher_cfg & MOD_3DES) {
706 const u32 *K = (const u32 *)key;
707 if (unlikely(!((K[0] ^ K[2]) | (K[1] ^ K[3])) ||
708 !((K[2] ^ K[4]) | (K[3] ^ K[5]))))
709 {
710 *flags |= CRYPTO_TFM_RES_BAD_KEY_SCHED;
711 return -EINVAL;
712 }
713 } else {
714 u32 tmp[DES_EXPKEY_WORDS];
715 if (des_ekey(tmp, key) == 0) {
716 *flags |= CRYPTO_TFM_RES_WEAK_KEY;
717 }
718 }
719 /* write cfg word to cryptinfo */
720 *(u32*)cinfo = cpu_to_be32(cipher_cfg);
721 cinfo += sizeof(cipher_cfg);
722
723 /* write cipher key to cryptinfo */
724 memcpy(cinfo, key, key_len);
725 /* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */
726 if (key_len < DES3_EDE_KEY_SIZE && !(cipher_cfg & MOD_AES)) {
727 memset(cinfo + key_len, 0, DES3_EDE_KEY_SIZE -key_len);
728 key_len = DES3_EDE_KEY_SIZE;
729 }
730 dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len;
731 dir->npe_mode |= NPE_OP_CRYPT_ENABLE;
732 if ((cipher_cfg & MOD_AES) && !encrypt) {
733 return gen_rev_aes_key(tfm);
734 }
735 return 0;
736 }
737
738 static struct buffer_desc *chainup_buffers(struct device *dev,
739 struct scatterlist *sg, unsigned nbytes,
740 struct buffer_desc *buf, gfp_t flags,
741 enum dma_data_direction dir)
742 {
743 for (;nbytes > 0; sg = scatterwalk_sg_next(sg)) {
744 unsigned len = min(nbytes, sg->length);
745 struct buffer_desc *next_buf;
746 u32 next_buf_phys;
747 void *ptr;
748
749 nbytes -= len;
750 ptr = page_address(sg_page(sg)) + sg->offset;
751 next_buf = dma_pool_alloc(buffer_pool, flags, &next_buf_phys);
752 if (!next_buf) {
753 buf = NULL;
754 break;
755 }
756 sg_dma_address(sg) = dma_map_single(dev, ptr, len, dir);
757 buf->next = next_buf;
758 buf->phys_next = next_buf_phys;
759 buf = next_buf;
760
761 buf->phys_addr = sg_dma_address(sg);
762 buf->buf_len = len;
763 buf->dir = dir;
764 }
765 buf->next = NULL;
766 buf->phys_next = 0;
767 return buf;
768 }
769
770 static int ablk_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
771 unsigned int key_len)
772 {
773 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
774 u32 *flags = &tfm->base.crt_flags;
775 int ret;
776
777 init_completion(&ctx->completion);
778 atomic_inc(&ctx->configuring);
779
780 reset_sa_dir(&ctx->encrypt);
781 reset_sa_dir(&ctx->decrypt);
782
783 ctx->encrypt.npe_mode = NPE_OP_HMAC_DISABLE;
784 ctx->decrypt.npe_mode = NPE_OP_HMAC_DISABLE;
785
786 ret = setup_cipher(&tfm->base, 0, key, key_len);
787 if (ret)
788 goto out;
789 ret = setup_cipher(&tfm->base, 1, key, key_len);
790 if (ret)
791 goto out;
792
793 if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
794 if (*flags & CRYPTO_TFM_REQ_WEAK_KEY) {
795 ret = -EINVAL;
796 } else {
797 *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
798 }
799 }
800 out:
801 if (!atomic_dec_and_test(&ctx->configuring))
802 wait_for_completion(&ctx->completion);
803 return ret;
804 }
805
806 static int ablk_rfc3686_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
807 unsigned int key_len)
808 {
809 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
810
811 /* the nonce is stored in bytes at end of key */
812 if (key_len < CTR_RFC3686_NONCE_SIZE)
813 return -EINVAL;
814
815 memcpy(ctx->nonce, key + (key_len - CTR_RFC3686_NONCE_SIZE),
816 CTR_RFC3686_NONCE_SIZE);
817
818 key_len -= CTR_RFC3686_NONCE_SIZE;
819 return ablk_setkey(tfm, key, key_len);
820 }
821
822 static int ablk_perform(struct ablkcipher_request *req, int encrypt)
823 {
824 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
825 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
826 unsigned ivsize = crypto_ablkcipher_ivsize(tfm);
827 struct ix_sa_dir *dir;
828 struct crypt_ctl *crypt;
829 unsigned int nbytes = req->nbytes;
830 enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
831 struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
832 struct buffer_desc src_hook;
833 gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
834 GFP_KERNEL : GFP_ATOMIC;
835
836 if (qmgr_stat_full(SEND_QID))
837 return -EAGAIN;
838 if (atomic_read(&ctx->configuring))
839 return -EAGAIN;
840
841 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
842
843 crypt = get_crypt_desc();
844 if (!crypt)
845 return -ENOMEM;
846
847 crypt->data.ablk_req = req;
848 crypt->crypto_ctx = dir->npe_ctx_phys;
849 crypt->mode = dir->npe_mode;
850 crypt->init_len = dir->npe_ctx_idx;
851
852 crypt->crypt_offs = 0;
853 crypt->crypt_len = nbytes;
854
855 BUG_ON(ivsize && !req->info);
856 memcpy(crypt->iv, req->info, ivsize);
857 if (req->src != req->dst) {
858 struct buffer_desc dst_hook;
859 crypt->mode |= NPE_OP_NOT_IN_PLACE;
860 /* This was never tested by Intel
861 * for more than one dst buffer, I think. */
862 BUG_ON(req->dst->length < nbytes);
863 req_ctx->dst = NULL;
864 if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,
865 flags, DMA_FROM_DEVICE))
866 goto free_buf_dest;
867 src_direction = DMA_TO_DEVICE;
868 req_ctx->dst = dst_hook.next;
869 crypt->dst_buf = dst_hook.phys_next;
870 } else {
871 req_ctx->dst = NULL;
872 }
873 req_ctx->src = NULL;
874 if (!chainup_buffers(dev, req->src, nbytes, &src_hook,
875 flags, src_direction))
876 goto free_buf_src;
877
878 req_ctx->src = src_hook.next;
879 crypt->src_buf = src_hook.phys_next;
880 crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK;
881 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
882 BUG_ON(qmgr_stat_overflow(SEND_QID));
883 return -EINPROGRESS;
884
885 free_buf_src:
886 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
887 free_buf_dest:
888 if (req->src != req->dst) {
889 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
890 }
891 crypt->ctl_flags = CTL_FLAG_UNUSED;
892 return -ENOMEM;
893 }
894
895 static int ablk_encrypt(struct ablkcipher_request *req)
896 {
897 return ablk_perform(req, 1);
898 }
899
900 static int ablk_decrypt(struct ablkcipher_request *req)
901 {
902 return ablk_perform(req, 0);
903 }
904
905 static int ablk_rfc3686_crypt(struct ablkcipher_request *req)
906 {
907 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
908 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
909 u8 iv[CTR_RFC3686_BLOCK_SIZE];
910 u8 *info = req->info;
911 int ret;
912
913 /* set up counter block */
914 memcpy(iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
915 memcpy(iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);
916
917 /* initialize counter portion of counter block */
918 *(__be32 *)(iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
919 cpu_to_be32(1);
920
921 req->info = iv;
922 ret = ablk_perform(req, 1);
923 req->info = info;
924 return ret;
925 }
926
927 static int hmac_inconsistent(struct scatterlist *sg, unsigned start,
928 unsigned int nbytes)
929 {
930 int offset = 0;
931
932 if (!nbytes)
933 return 0;
934
935 for (;;) {
936 if (start < offset + sg->length)
937 break;
938
939 offset += sg->length;
940 sg = scatterwalk_sg_next(sg);
941 }
942 return (start + nbytes > offset + sg->length);
943 }
944
945 static int aead_perform(struct aead_request *req, int encrypt,
946 int cryptoffset, int eff_cryptlen, u8 *iv)
947 {
948 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
949 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
950 unsigned ivsize = crypto_aead_ivsize(tfm);
951 unsigned authsize = crypto_aead_authsize(tfm);
952 struct ix_sa_dir *dir;
953 struct crypt_ctl *crypt;
954 unsigned int cryptlen;
955 struct buffer_desc *buf, src_hook;
956 struct aead_ctx *req_ctx = aead_request_ctx(req);
957 gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
958 GFP_KERNEL : GFP_ATOMIC;
959
960 if (qmgr_stat_full(SEND_QID))
961 return -EAGAIN;
962 if (atomic_read(&ctx->configuring))
963 return -EAGAIN;
964
965 if (encrypt) {
966 dir = &ctx->encrypt;
967 cryptlen = req->cryptlen;
968 } else {
969 dir = &ctx->decrypt;
970 /* req->cryptlen includes the authsize when decrypting */
971 cryptlen = req->cryptlen -authsize;
972 eff_cryptlen -= authsize;
973 }
974 crypt = get_crypt_desc();
975 if (!crypt)
976 return -ENOMEM;
977
978 crypt->data.aead_req = req;
979 crypt->crypto_ctx = dir->npe_ctx_phys;
980 crypt->mode = dir->npe_mode;
981 crypt->init_len = dir->npe_ctx_idx;
982
983 crypt->crypt_offs = cryptoffset;
984 crypt->crypt_len = eff_cryptlen;
985
986 crypt->auth_offs = 0;
987 crypt->auth_len = req->assoclen + ivsize + cryptlen;
988 BUG_ON(ivsize && !req->iv);
989 memcpy(crypt->iv, req->iv, ivsize);
990
991 if (req->src != req->dst) {
992 BUG(); /* -ENOTSUP because of my lazyness */
993 }
994
995 /* ASSOC data */
996 buf = chainup_buffers(dev, req->assoc, req->assoclen, &src_hook,
997 flags, DMA_TO_DEVICE);
998 req_ctx->buffer = src_hook.next;
999 crypt->src_buf = src_hook.phys_next;
1000 if (!buf)
1001 goto out;
1002 /* IV */
1003 sg_init_table(&req_ctx->ivlist, 1);
1004 sg_set_buf(&req_ctx->ivlist, iv, ivsize);
1005 buf = chainup_buffers(dev, &req_ctx->ivlist, ivsize, buf, flags,
1006 DMA_BIDIRECTIONAL);
1007 if (!buf)
1008 goto free_chain;
1009 if (unlikely(hmac_inconsistent(req->src, cryptlen, authsize))) {
1010 /* The 12 hmac bytes are scattered,
1011 * we need to copy them into a safe buffer */
1012 req_ctx->hmac_virt = dma_pool_alloc(buffer_pool, flags,
1013 &crypt->icv_rev_aes);
1014 if (unlikely(!req_ctx->hmac_virt))
1015 goto free_chain;
1016 if (!encrypt) {
1017 scatterwalk_map_and_copy(req_ctx->hmac_virt,
1018 req->src, cryptlen, authsize, 0);
1019 }
1020 req_ctx->encrypt = encrypt;
1021 } else {
1022 req_ctx->hmac_virt = NULL;
1023 }
1024 /* Crypt */
1025 buf = chainup_buffers(dev, req->src, cryptlen + authsize, buf, flags,
1026 DMA_BIDIRECTIONAL);
1027 if (!buf)
1028 goto free_hmac_virt;
1029 if (!req_ctx->hmac_virt) {
1030 crypt->icv_rev_aes = buf->phys_addr + buf->buf_len - authsize;
1031 }
1032
1033 crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD;
1034 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
1035 BUG_ON(qmgr_stat_overflow(SEND_QID));
1036 return -EINPROGRESS;
1037 free_hmac_virt:
1038 if (req_ctx->hmac_virt) {
1039 dma_pool_free(buffer_pool, req_ctx->hmac_virt,
1040 crypt->icv_rev_aes);
1041 }
1042 free_chain:
1043 free_buf_chain(dev, req_ctx->buffer, crypt->src_buf);
1044 out:
1045 crypt->ctl_flags = CTL_FLAG_UNUSED;
1046 return -ENOMEM;
1047 }
1048
1049 static int aead_setup(struct crypto_aead *tfm, unsigned int authsize)
1050 {
1051 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1052 u32 *flags = &tfm->base.crt_flags;
1053 unsigned digest_len = crypto_aead_alg(tfm)->maxauthsize;
1054 int ret;
1055
1056 if (!ctx->enckey_len && !ctx->authkey_len)
1057 return 0;
1058 init_completion(&ctx->completion);
1059 atomic_inc(&ctx->configuring);
1060
1061 reset_sa_dir(&ctx->encrypt);
1062 reset_sa_dir(&ctx->decrypt);
1063
1064 ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len);
1065 if (ret)
1066 goto out;
1067 ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len);
1068 if (ret)
1069 goto out;
1070 ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey,
1071 ctx->authkey_len, digest_len);
1072 if (ret)
1073 goto out;
1074 ret = setup_auth(&tfm->base, 1, authsize, ctx->authkey,
1075 ctx->authkey_len, digest_len);
1076 if (ret)
1077 goto out;
1078
1079 if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
1080 if (*flags & CRYPTO_TFM_REQ_WEAK_KEY) {
1081 ret = -EINVAL;
1082 goto out;
1083 } else {
1084 *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
1085 }
1086 }
1087 out:
1088 if (!atomic_dec_and_test(&ctx->configuring))
1089 wait_for_completion(&ctx->completion);
1090 return ret;
1091 }
1092
1093 static int aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
1094 {
1095 int max = crypto_aead_alg(tfm)->maxauthsize >> 2;
1096
1097 if ((authsize>>2) < 1 || (authsize>>2) > max || (authsize & 3))
1098 return -EINVAL;
1099 return aead_setup(tfm, authsize);
1100 }
1101
1102 static int aead_setkey(struct crypto_aead *tfm, const u8 *key,
1103 unsigned int keylen)
1104 {
1105 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1106 struct rtattr *rta = (struct rtattr *)key;
1107 struct crypto_authenc_key_param *param;
1108
1109 if (!RTA_OK(rta, keylen))
1110 goto badkey;
1111 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
1112 goto badkey;
1113 if (RTA_PAYLOAD(rta) < sizeof(*param))
1114 goto badkey;
1115
1116 param = RTA_DATA(rta);
1117 ctx->enckey_len = be32_to_cpu(param->enckeylen);
1118
1119 key += RTA_ALIGN(rta->rta_len);
1120 keylen -= RTA_ALIGN(rta->rta_len);
1121
1122 if (keylen < ctx->enckey_len)
1123 goto badkey;
1124
1125 ctx->authkey_len = keylen - ctx->enckey_len;
1126 memcpy(ctx->enckey, key + ctx->authkey_len, ctx->enckey_len);
1127 memcpy(ctx->authkey, key, ctx->authkey_len);
1128
1129 return aead_setup(tfm, crypto_aead_authsize(tfm));
1130 badkey:
1131 ctx->enckey_len = 0;
1132 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1133 return -EINVAL;
1134 }
1135
1136 static int aead_encrypt(struct aead_request *req)
1137 {
1138 unsigned ivsize = crypto_aead_ivsize(crypto_aead_reqtfm(req));
1139 return aead_perform(req, 1, req->assoclen + ivsize,
1140 req->cryptlen, req->iv);
1141 }
1142
1143 static int aead_decrypt(struct aead_request *req)
1144 {
1145 unsigned ivsize = crypto_aead_ivsize(crypto_aead_reqtfm(req));
1146 return aead_perform(req, 0, req->assoclen + ivsize,
1147 req->cryptlen, req->iv);
1148 }
1149
1150 static int aead_givencrypt(struct aead_givcrypt_request *req)
1151 {
1152 struct crypto_aead *tfm = aead_givcrypt_reqtfm(req);
1153 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1154 unsigned len, ivsize = crypto_aead_ivsize(tfm);
1155 __be64 seq;
1156
1157 /* copied from eseqiv.c */
1158 if (!ctx->salted) {
1159 get_random_bytes(ctx->salt, ivsize);
1160 ctx->salted = 1;
1161 }
1162 memcpy(req->areq.iv, ctx->salt, ivsize);
1163 len = ivsize;
1164 if (ivsize > sizeof(u64)) {
1165 memset(req->giv, 0, ivsize - sizeof(u64));
1166 len = sizeof(u64);
1167 }
1168 seq = cpu_to_be64(req->seq);
1169 memcpy(req->giv + ivsize - len, &seq, len);
1170 return aead_perform(&req->areq, 1, req->areq.assoclen,
1171 req->areq.cryptlen +ivsize, req->giv);
1172 }
1173
1174 static struct ixp_alg ixp4xx_algos[] = {
1175 {
1176 .crypto = {
1177 .cra_name = "cbc(des)",
1178 .cra_blocksize = DES_BLOCK_SIZE,
1179 .cra_u = { .ablkcipher = {
1180 .min_keysize = DES_KEY_SIZE,
1181 .max_keysize = DES_KEY_SIZE,
1182 .ivsize = DES_BLOCK_SIZE,
1183 .geniv = "eseqiv",
1184 }
1185 }
1186 },
1187 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1188 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1189
1190 }, {
1191 .crypto = {
1192 .cra_name = "ecb(des)",
1193 .cra_blocksize = DES_BLOCK_SIZE,
1194 .cra_u = { .ablkcipher = {
1195 .min_keysize = DES_KEY_SIZE,
1196 .max_keysize = DES_KEY_SIZE,
1197 }
1198 }
1199 },
1200 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192,
1201 .cfg_dec = CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192,
1202 }, {
1203 .crypto = {
1204 .cra_name = "cbc(des3_ede)",
1205 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1206 .cra_u = { .ablkcipher = {
1207 .min_keysize = DES3_EDE_KEY_SIZE,
1208 .max_keysize = DES3_EDE_KEY_SIZE,
1209 .ivsize = DES3_EDE_BLOCK_SIZE,
1210 .geniv = "eseqiv",
1211 }
1212 }
1213 },
1214 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1215 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1216 }, {
1217 .crypto = {
1218 .cra_name = "ecb(des3_ede)",
1219 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1220 .cra_u = { .ablkcipher = {
1221 .min_keysize = DES3_EDE_KEY_SIZE,
1222 .max_keysize = DES3_EDE_KEY_SIZE,
1223 }
1224 }
1225 },
1226 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_ECB | KEYLEN_192,
1227 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_ECB | KEYLEN_192,
1228 }, {
1229 .crypto = {
1230 .cra_name = "cbc(aes)",
1231 .cra_blocksize = AES_BLOCK_SIZE,
1232 .cra_u = { .ablkcipher = {
1233 .min_keysize = AES_MIN_KEY_SIZE,
1234 .max_keysize = AES_MAX_KEY_SIZE,
1235 .ivsize = AES_BLOCK_SIZE,
1236 .geniv = "eseqiv",
1237 }
1238 }
1239 },
1240 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1241 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1242 }, {
1243 .crypto = {
1244 .cra_name = "ecb(aes)",
1245 .cra_blocksize = AES_BLOCK_SIZE,
1246 .cra_u = { .ablkcipher = {
1247 .min_keysize = AES_MIN_KEY_SIZE,
1248 .max_keysize = AES_MAX_KEY_SIZE,
1249 }
1250 }
1251 },
1252 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_ECB,
1253 .cfg_dec = CIPH_DECR | MOD_AES | MOD_ECB,
1254 }, {
1255 .crypto = {
1256 .cra_name = "ctr(aes)",
1257 .cra_blocksize = AES_BLOCK_SIZE,
1258 .cra_u = { .ablkcipher = {
1259 .min_keysize = AES_MIN_KEY_SIZE,
1260 .max_keysize = AES_MAX_KEY_SIZE,
1261 .ivsize = AES_BLOCK_SIZE,
1262 .geniv = "eseqiv",
1263 }
1264 }
1265 },
1266 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1267 .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1268 }, {
1269 .crypto = {
1270 .cra_name = "rfc3686(ctr(aes))",
1271 .cra_blocksize = AES_BLOCK_SIZE,
1272 .cra_u = { .ablkcipher = {
1273 .min_keysize = AES_MIN_KEY_SIZE,
1274 .max_keysize = AES_MAX_KEY_SIZE,
1275 .ivsize = AES_BLOCK_SIZE,
1276 .geniv = "eseqiv",
1277 .setkey = ablk_rfc3686_setkey,
1278 .encrypt = ablk_rfc3686_crypt,
1279 .decrypt = ablk_rfc3686_crypt }
1280 }
1281 },
1282 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1283 .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1284 }, {
1285 .crypto = {
1286 .cra_name = "authenc(hmac(md5),cbc(des))",
1287 .cra_blocksize = DES_BLOCK_SIZE,
1288 .cra_u = { .aead = {
1289 .ivsize = DES_BLOCK_SIZE,
1290 .maxauthsize = MD5_DIGEST_SIZE,
1291 }
1292 }
1293 },
1294 .hash = &hash_alg_md5,
1295 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1296 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1297 }, {
1298 .crypto = {
1299 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1300 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1301 .cra_u = { .aead = {
1302 .ivsize = DES3_EDE_BLOCK_SIZE,
1303 .maxauthsize = MD5_DIGEST_SIZE,
1304 }
1305 }
1306 },
1307 .hash = &hash_alg_md5,
1308 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1309 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1310 }, {
1311 .crypto = {
1312 .cra_name = "authenc(hmac(sha1),cbc(des))",
1313 .cra_blocksize = DES_BLOCK_SIZE,
1314 .cra_u = { .aead = {
1315 .ivsize = DES_BLOCK_SIZE,
1316 .maxauthsize = SHA1_DIGEST_SIZE,
1317 }
1318 }
1319 },
1320 .hash = &hash_alg_sha1,
1321 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1322 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1323 }, {
1324 .crypto = {
1325 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1326 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1327 .cra_u = { .aead = {
1328 .ivsize = DES3_EDE_BLOCK_SIZE,
1329 .maxauthsize = SHA1_DIGEST_SIZE,
1330 }
1331 }
1332 },
1333 .hash = &hash_alg_sha1,
1334 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1335 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1336 }, {
1337 .crypto = {
1338 .cra_name = "authenc(hmac(md5),cbc(aes))",
1339 .cra_blocksize = AES_BLOCK_SIZE,
1340 .cra_u = { .aead = {
1341 .ivsize = AES_BLOCK_SIZE,
1342 .maxauthsize = MD5_DIGEST_SIZE,
1343 }
1344 }
1345 },
1346 .hash = &hash_alg_md5,
1347 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1348 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1349 }, {
1350 .crypto = {
1351 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1352 .cra_blocksize = AES_BLOCK_SIZE,
1353 .cra_u = { .aead = {
1354 .ivsize = AES_BLOCK_SIZE,
1355 .maxauthsize = SHA1_DIGEST_SIZE,
1356 }
1357 }
1358 },
1359 .hash = &hash_alg_sha1,
1360 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1361 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1362 } };
1363
1364 #define IXP_POSTFIX "-ixp4xx"
1365 static int __init ixp_module_init(void)
1366 {
1367 int num = ARRAY_SIZE(ixp4xx_algos);
1368 int i,err ;
1369
1370 if (platform_device_register(&pseudo_dev))
1371 return -ENODEV;
1372
1373 spin_lock_init(&desc_lock);
1374 spin_lock_init(&emerg_lock);
1375
1376 err = init_ixp_crypto();
1377 if (err) {
1378 platform_device_unregister(&pseudo_dev);
1379 return err;
1380 }
1381 for (i=0; i< num; i++) {
1382 struct crypto_alg *cra = &ixp4xx_algos[i].crypto;
1383
1384 if (snprintf(cra->cra_driver_name, CRYPTO_MAX_ALG_NAME,
1385 "%s"IXP_POSTFIX, cra->cra_name) >=
1386 CRYPTO_MAX_ALG_NAME)
1387 {
1388 continue;
1389 }
1390 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES)) {
1391 continue;
1392 }
1393 if (!ixp4xx_algos[i].hash) {
1394 /* block ciphers */
1395 cra->cra_type = &crypto_ablkcipher_type;
1396 cra->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1397 CRYPTO_ALG_ASYNC;
1398 if (!cra->cra_ablkcipher.setkey)
1399 cra->cra_ablkcipher.setkey = ablk_setkey;
1400 if (!cra->cra_ablkcipher.encrypt)
1401 cra->cra_ablkcipher.encrypt = ablk_encrypt;
1402 if (!cra->cra_ablkcipher.decrypt)
1403 cra->cra_ablkcipher.decrypt = ablk_decrypt;
1404 cra->cra_init = init_tfm_ablk;
1405 } else {
1406 /* authenc */
1407 cra->cra_type = &crypto_aead_type;
1408 cra->cra_flags = CRYPTO_ALG_TYPE_AEAD |
1409 CRYPTO_ALG_ASYNC;
1410 cra->cra_aead.setkey = aead_setkey;
1411 cra->cra_aead.setauthsize = aead_setauthsize;
1412 cra->cra_aead.encrypt = aead_encrypt;
1413 cra->cra_aead.decrypt = aead_decrypt;
1414 cra->cra_aead.givencrypt = aead_givencrypt;
1415 cra->cra_init = init_tfm_aead;
1416 }
1417 cra->cra_ctxsize = sizeof(struct ixp_ctx);
1418 cra->cra_module = THIS_MODULE;
1419 cra->cra_alignmask = 3;
1420 cra->cra_priority = 300;
1421 cra->cra_exit = exit_tfm;
1422 if (crypto_register_alg(cra))
1423 printk(KERN_ERR "Failed to register '%s'\n",
1424 cra->cra_name);
1425 else
1426 ixp4xx_algos[i].registered = 1;
1427 }
1428 return 0;
1429 }
1430
1431 static void __exit ixp_module_exit(void)
1432 {
1433 int num = ARRAY_SIZE(ixp4xx_algos);
1434 int i;
1435
1436 for (i=0; i< num; i++) {
1437 if (ixp4xx_algos[i].registered)
1438 crypto_unregister_alg(&ixp4xx_algos[i].crypto);
1439 }
1440 release_ixp_crypto();
1441 platform_device_unregister(&pseudo_dev);
1442 }
1443
1444 module_init(ixp_module_init);
1445 module_exit(ixp_module_exit);
1446
1447 MODULE_LICENSE("GPL");
1448 MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
1449 MODULE_DESCRIPTION("IXP4xx hardware crypto");
1450
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree