include/linux/spi/dw_spi.h

   1 #ifndef DW_SPI_HEADER_H
   2 #define DW_SPI_HEADER_H
   3 #include <linux/io.h>
   4
   5 /* Bit fields in CTRLR0 */
   6 #define SPI_DFS_OFFSET                  0
   7
   8 #define SPI_FRF_OFFSET                  4
   9 #define SPI_FRF_SPI                     0x0
  10 #define SPI_FRF_SSP                     0x1
  11 #define SPI_FRF_MICROWIRE               0x2
  12 #define SPI_FRF_RESV                    0x3
  13
  14 #define SPI_MODE_OFFSET                 6
  15 #define SPI_SCPH_OFFSET                 6
  16 #define SPI_SCOL_OFFSET                 7
  17 #define SPI_TMOD_OFFSET                 8
  18 #define SPI_TMOD_TR                     0x0             /* xmit & recv */
  19 #define SPI_TMOD_TO                     0x1             /* xmit only */
  20 #define SPI_TMOD_RO                     0x2             /* recv only */
  21 #define SPI_TMOD_EPROMREAD              0x3             /* eeprom read mode */
  22
  23 #define SPI_SLVOE_OFFSET                10
  24 #define SPI_SRL_OFFSET                  11
  25 #define SPI_CFS_OFFSET                  12
  26
  27 /* Bit fields in SR, 7 bits */
  28 #define SR_MASK                         0x7f            /* cover 7 bits */
  29 #define SR_BUSY                         (1 << 0)
  30 #define SR_TF_NOT_FULL                  (1 << 1)
  31 #define SR_TF_EMPT                      (1 << 2)
  32 #define SR_RF_NOT_EMPT                  (1 << 3)
  33 #define SR_RF_FULL                      (1 << 4)
  34 #define SR_TX_ERR                       (1 << 5)
  35 #define SR_DCOL                         (1 << 6)
  36
  37 /* Bit fields in ISR, IMR, RISR, 7 bits */
  38 #define SPI_INT_TXEI                    (1 << 0)
  39 #define SPI_INT_TXOI                    (1 << 1)
  40 #define SPI_INT_RXUI                    (1 << 2)
  41 #define SPI_INT_RXOI                    (1 << 3)
  42 #define SPI_INT_RXFI                    (1 << 4)
  43 #define SPI_INT_MSTI                    (1 << 5)
  44
  45 /* TX RX interrupt level threshhold, max can be 256 */
  46 #define SPI_INT_THRESHOLD               32
  47
  48 enum dw_ssi_type {
  49         SSI_MOTO_SPI = 0,
  50         SSI_TI_SSP,
  51         SSI_NS_MICROWIRE,
  52 };
  53
  54 struct dw_spi_reg {
  55         u32     ctrl0;
  56         u32     ctrl1;
  57         u32     ssienr;
  58         u32     mwcr;
  59         u32     ser;
  60         u32     baudr;
  61         u32     txfltr;
  62         u32     rxfltr;
  63         u32     txflr;
  64         u32     rxflr;
  65         u32     sr;
  66         u32     imr;
  67         u32     isr;
  68         u32     risr;
  69         u32     txoicr;
  70         u32     rxoicr;
  71         u32     rxuicr;
  72         u32     msticr;
  73         u32     icr;
  74         u32     dmacr;
  75         u32     dmatdlr;
  76         u32     dmardlr;
  77         u32     idr;
  78         u32     version;
  79         u32     dr;             /* Currently oper as 32 bits,
  80                                 though only low 16 bits matters */
  81 } __packed;
  82
  83 struct dw_spi {
  84         struct spi_master       *master;
  85         struct spi_device       *cur_dev;
  86         struct device           *parent_dev;
  87         enum dw_ssi_type        type;
  88
  89         void __iomem            *regs;
  90         unsigned long           paddr;
  91         u32                     iolen;
  92         int                     irq;
  93         u32                     max_freq;       /* max bus freq supported */
  94
  95         u16                     bus_num;
  96         u16                     num_cs;         /* supported slave numbers */
  97
  98         /* Driver message queue */
  99         struct workqueue_struct *workqueue;
 100         struct work_struct      pump_messages;
 101         spinlock_t              lock;
 102         struct list_head        queue;
 103         int                     busy;
 104         int                     run;
 105
 106         /* Message Transfer pump */
 107         struct tasklet_struct   pump_transfers;
 108
 109         /* Current message transfer state info */
 110         struct spi_message      *cur_msg;
 111         struct spi_transfer     *cur_transfer;
 112         struct chip_data        *cur_chip;
 113         struct chip_data        *prev_chip;
 114         size_t                  len;
 115         void                    *tx;
 116         void                    *tx_end;
 117         void                    *rx;
 118         void                    *rx_end;
 119         int                     dma_mapped;
 120         dma_addr_t              rx_dma;
 121         dma_addr_t              tx_dma;
 122         size_t                  rx_map_len;
 123         size_t                  tx_map_len;
 124         u8                      n_bytes;        /* current is a 1/2 bytes op */
 125         u8                      max_bits_per_word;      /* maxim is 16b */
 126         u32                     dma_width;
 127         int                     cs_change;
 128         int                     (*write)(struct dw_spi *dws);
 129         int                     (*read)(struct dw_spi *dws);
 130         irqreturn_t             (*transfer_handler)(struct dw_spi *dws);
 131         void                    (*cs_control)(u32 command);
 132
 133         /* Dma info */
 134         int                     dma_inited;
 135         struct dma_chan         *txchan;
 136         struct dma_chan         *rxchan;
 137         int                     txdma_done;
 138         int                     rxdma_done;
 139         u64                     tx_param;
 140         u64                     rx_param;
 141         struct device           *dma_dev;
 142         dma_addr_t              dma_addr;
 143
 144         /* Bus interface info */
 145         void                    *priv;
 146 #ifdef CONFIG_DEBUG_FS
 147         struct dentry *debugfs;
 148 #endif
 149 };
 150
 151 #define dw_readl(dw, name) \
 152         __raw_readl(&(((struct dw_spi_reg *)dw->regs)->name))
 153 #define dw_writel(dw, name, val) \
 154         __raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name))
 155 #define dw_readw(dw, name) \
 156         __raw_readw(&(((struct dw_spi_reg *)dw->regs)->name))
 157 #define dw_writew(dw, name, val) \
 158         __raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name))
 159
 160 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
 161 {
 162         dw_writel(dws, ssienr, (enable ? 1 : 0));
 163 }
 164
 165 static inline void spi_set_clk(struct dw_spi *dws, u16 div)
 166 {
 167         dw_writel(dws, baudr, div);
 168 }
 169
 170 static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
 171 {
 172         if (cs > dws->num_cs)
 173                 return;
 174         dw_writel(dws, ser, 1 << cs);
 175 }
 176
 177 /* Disable IRQ bits */
 178 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
 179 {
 180         u32 new_mask;
 181
 182         new_mask = dw_readl(dws, imr) & ~mask;
 183         dw_writel(dws, imr, new_mask);
 184 }
 185
 186 /* Enable IRQ bits */
 187 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
 188 {
 189         u32 new_mask;
 190
 191         new_mask = dw_readl(dws, imr) | mask;
 192         dw_writel(dws, imr, new_mask);
 193 }
 194
 195 /*
 196  * Each SPI slave device to work with dw_api controller should
 197  * has such a structure claiming its working mode (PIO/DMA etc),
 198  * which can be save in the "controller_data" member of the
 199  * struct spi_device
 200  */
 201 struct dw_spi_chip {
 202         u8 poll_mode;   /* 0 for contoller polling mode */
 203         u8 type;        /* SPI/SSP/Micrwire */
 204         u8 enable_dma;
 205         void (*cs_control)(u32 command);
 206 };
 207
 208 extern int dw_spi_add_host(struct dw_spi *dws);
 209 extern void dw_spi_remove_host(struct dw_spi *dws);
 210 extern int dw_spi_suspend_host(struct dw_spi *dws);
 211 extern int dw_spi_resume_host(struct dw_spi *dws);
 212 #endif /* DW_SPI_HEADER_H */