2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define assert(expr) \
49 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
50 #expr,__FILE__,__func__,__LINE__); \
52 #define dprintk(fmt, args...) \
53 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
55 #define assert(expr) do {} while (0)
56 #define dprintk(fmt, args...) do {} while (0)
57 #endif /* RTL8169_DEBUG */
59 #define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
62 #define TX_BUFFS_AVAIL(tp) \
63 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
65 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
66 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
67 static const int multicast_filter_limit
= 32;
69 /* MAC address length */
70 #define MAC_ADDR_LEN 6
72 #define MAX_READ_REQUEST_SHIFT 12
73 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
74 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
75 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
76 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
77 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
79 #define R8169_REGS_SIZE 256
80 #define R8169_NAPI_WEIGHT 64
81 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
82 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
83 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
84 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
85 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
87 #define RTL8169_TX_TIMEOUT (6*HZ)
88 #define RTL8169_PHY_TIMEOUT (10*HZ)
90 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
91 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
92 #define RTL_EEPROM_SIG_ADDR 0x0000
94 /* write/read MMIO register */
95 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
96 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
97 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
98 #define RTL_R8(reg) readb (ioaddr + (reg))
99 #define RTL_R16(reg) readw (ioaddr + (reg))
100 #define RTL_R32(reg) readl (ioaddr + (reg))
103 RTL_GIGA_MAC_VER_01
= 0,
136 RTL_GIGA_MAC_NONE
= 0xff,
139 enum rtl_tx_desc_version
{
144 #define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
147 static const struct {
149 enum rtl_tx_desc_version txd_version
;
151 } rtl_chip_infos
[] = {
153 [RTL_GIGA_MAC_VER_01
] =
154 _R("RTL8169", RTL_TD_0
, NULL
),
155 [RTL_GIGA_MAC_VER_02
] =
156 _R("RTL8169s", RTL_TD_0
, NULL
),
157 [RTL_GIGA_MAC_VER_03
] =
158 _R("RTL8110s", RTL_TD_0
, NULL
),
159 [RTL_GIGA_MAC_VER_04
] =
160 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
),
161 [RTL_GIGA_MAC_VER_05
] =
162 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
163 [RTL_GIGA_MAC_VER_06
] =
164 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
),
166 [RTL_GIGA_MAC_VER_07
] =
167 _R("RTL8102e", RTL_TD_1
, NULL
),
168 [RTL_GIGA_MAC_VER_08
] =
169 _R("RTL8102e", RTL_TD_1
, NULL
),
170 [RTL_GIGA_MAC_VER_09
] =
171 _R("RTL8102e", RTL_TD_1
, NULL
),
172 [RTL_GIGA_MAC_VER_10
] =
173 _R("RTL8101e", RTL_TD_0
, NULL
),
174 [RTL_GIGA_MAC_VER_11
] =
175 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
176 [RTL_GIGA_MAC_VER_12
] =
177 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
178 [RTL_GIGA_MAC_VER_13
] =
179 _R("RTL8101e", RTL_TD_0
, NULL
),
180 [RTL_GIGA_MAC_VER_14
] =
181 _R("RTL8100e", RTL_TD_0
, NULL
),
182 [RTL_GIGA_MAC_VER_15
] =
183 _R("RTL8100e", RTL_TD_0
, NULL
),
184 [RTL_GIGA_MAC_VER_16
] =
185 _R("RTL8101e", RTL_TD_0
, NULL
),
186 [RTL_GIGA_MAC_VER_17
] =
187 _R("RTL8168b/8111b", RTL_TD_0
, NULL
),
188 [RTL_GIGA_MAC_VER_18
] =
189 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
190 [RTL_GIGA_MAC_VER_19
] =
191 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
192 [RTL_GIGA_MAC_VER_20
] =
193 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
194 [RTL_GIGA_MAC_VER_21
] =
195 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
196 [RTL_GIGA_MAC_VER_22
] =
197 _R("RTL8168c/8111c", RTL_TD_1
, NULL
),
198 [RTL_GIGA_MAC_VER_23
] =
199 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
200 [RTL_GIGA_MAC_VER_24
] =
201 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
),
202 [RTL_GIGA_MAC_VER_25
] =
203 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
),
204 [RTL_GIGA_MAC_VER_26
] =
205 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
),
206 [RTL_GIGA_MAC_VER_27
] =
207 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
208 [RTL_GIGA_MAC_VER_28
] =
209 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
210 [RTL_GIGA_MAC_VER_29
] =
211 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
212 [RTL_GIGA_MAC_VER_30
] =
213 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
),
214 [RTL_GIGA_MAC_VER_31
] =
215 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
),
216 [RTL_GIGA_MAC_VER_32
] =
217 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
),
218 [RTL_GIGA_MAC_VER_33
] =
219 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
)
229 static void rtl_hw_start_8169(struct net_device
*);
230 static void rtl_hw_start_8168(struct net_device
*);
231 static void rtl_hw_start_8101(struct net_device
*);
233 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
234 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
235 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
239 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
240 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
241 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
242 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
243 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
245 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
249 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
251 static int rx_buf_sz
= 16383;
258 MAC0
= 0, /* Ethernet hardware address. */
260 MAR0
= 8, /* Multicast filter. */
261 CounterAddrLow
= 0x10,
262 CounterAddrHigh
= 0x14,
263 TxDescStartAddrLow
= 0x20,
264 TxDescStartAddrHigh
= 0x24,
265 TxHDescStartAddrLow
= 0x28,
266 TxHDescStartAddrHigh
= 0x2c,
276 #define RTL_RX_CONFIG_MASK 0xff7e1880u
292 RxDescAddrLow
= 0xe4,
293 RxDescAddrHigh
= 0xe8,
294 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
296 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
298 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
300 #define TxPacketMax (8064 >> 7)
303 FuncEventMask
= 0xf4,
304 FuncPresetState
= 0xf8,
305 FuncForceEvent
= 0xfc,
308 enum rtl8110_registers
{
314 enum rtl8168_8101_registers
{
317 #define CSIAR_FLAG 0x80000000
318 #define CSIAR_WRITE_CMD 0x80000000
319 #define CSIAR_BYTE_ENABLE 0x0f
320 #define CSIAR_BYTE_ENABLE_SHIFT 12
321 #define CSIAR_ADDR_MASK 0x0fff
324 #define EPHYAR_FLAG 0x80000000
325 #define EPHYAR_WRITE_CMD 0x80000000
326 #define EPHYAR_REG_MASK 0x1f
327 #define EPHYAR_REG_SHIFT 16
328 #define EPHYAR_DATA_MASK 0xffff
330 #define PM_SWITCH (1 << 6)
332 #define FIX_NAK_1 (1 << 4)
333 #define FIX_NAK_2 (1 << 3)
336 #define EN_NDP (1 << 3)
337 #define EN_OOB_RESET (1 << 2)
339 #define EFUSEAR_FLAG 0x80000000
340 #define EFUSEAR_WRITE_CMD 0x80000000
341 #define EFUSEAR_READ_CMD 0x00000000
342 #define EFUSEAR_REG_MASK 0x03ff
343 #define EFUSEAR_REG_SHIFT 8
344 #define EFUSEAR_DATA_MASK 0xff
347 enum rtl8168_registers
{
350 #define ERIAR_FLAG 0x80000000
351 #define ERIAR_WRITE_CMD 0x80000000
352 #define ERIAR_READ_CMD 0x00000000
353 #define ERIAR_ADDR_BYTE_ALIGN 4
354 #define ERIAR_EXGMAC 0
357 #define ERIAR_TYPE_SHIFT 16
358 #define ERIAR_BYTEEN 0x0f
359 #define ERIAR_BYTEEN_SHIFT 12
360 EPHY_RXER_NUM
= 0x7c,
361 OCPDR
= 0xb0, /* OCP GPHY access */
362 #define OCPDR_WRITE_CMD 0x80000000
363 #define OCPDR_READ_CMD 0x00000000
364 #define OCPDR_REG_MASK 0x7f
365 #define OCPDR_GPHY_REG_SHIFT 16
366 #define OCPDR_DATA_MASK 0xffff
368 #define OCPAR_FLAG 0x80000000
369 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
370 #define OCPAR_GPHY_READ_CMD 0x0000f060
371 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
372 MISC
= 0xf0, /* 8168e only. */
373 #define TXPLA_RST (1 << 29)
376 enum rtl_register_content
{
377 /* InterruptStatusBits */
381 TxDescUnavail
= 0x0080,
403 /* TXPoll register p.5 */
404 HPQ
= 0x80, /* Poll cmd on the high prio queue */
405 NPQ
= 0x40, /* Poll cmd on the low prio queue */
406 FSWInt
= 0x01, /* Forced software interrupt */
410 Cfg9346_Unlock
= 0xc0,
415 AcceptBroadcast
= 0x08,
416 AcceptMulticast
= 0x04,
418 AcceptAllPhys
= 0x01,
425 TxInterFrameGapShift
= 24,
426 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
428 /* Config1 register p.24 */
431 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
432 Speed_down
= (1 << 4),
436 PMEnable
= (1 << 0), /* Power Management Enable */
438 /* Config2 register p. 25 */
439 PCI_Clock_66MHz
= 0x01,
440 PCI_Clock_33MHz
= 0x00,
442 /* Config3 register p.25 */
443 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
444 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
445 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
447 /* Config5 register p.27 */
448 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
449 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
450 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
452 LanWake
= (1 << 1), /* LanWake enable/disable */
453 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
456 TBIReset
= 0x80000000,
457 TBILoopback
= 0x40000000,
458 TBINwEnable
= 0x20000000,
459 TBINwRestart
= 0x10000000,
460 TBILinkOk
= 0x02000000,
461 TBINwComplete
= 0x01000000,
464 EnableBist
= (1 << 15), // 8168 8101
465 Mac_dbgo_oe
= (1 << 14), // 8168 8101
466 Normal_mode
= (1 << 13), // unused
467 Force_half_dup
= (1 << 12), // 8168 8101
468 Force_rxflow_en
= (1 << 11), // 8168 8101
469 Force_txflow_en
= (1 << 10), // 8168 8101
470 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
471 ASF
= (1 << 8), // 8168 8101
472 PktCntrDisable
= (1 << 7), // 8168 8101
473 Mac_dbgo_sel
= 0x001c, // 8168
478 INTT_0
= 0x0000, // 8168
479 INTT_1
= 0x0001, // 8168
480 INTT_2
= 0x0002, // 8168
481 INTT_3
= 0x0003, // 8168
483 /* rtl8169_PHYstatus */
494 TBILinkOK
= 0x02000000,
496 /* DumpCounterCommand */
501 /* First doubleword. */
502 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
503 RingEnd
= (1 << 30), /* End of descriptor ring */
504 FirstFrag
= (1 << 29), /* First segment of a packet */
505 LastFrag
= (1 << 28), /* Final segment of a packet */
509 enum rtl_tx_desc_bit
{
510 /* First doubleword. */
511 TD_LSO
= (1 << 27), /* Large Send Offload */
512 #define TD_MSS_MAX 0x07ffu /* MSS value */
514 /* Second doubleword. */
515 TxVlanTag
= (1 << 17), /* Add VLAN tag */
518 /* 8169, 8168b and 810x except 8102e. */
519 enum rtl_tx_desc_bit_0
{
520 /* First doubleword. */
521 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
522 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
523 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
524 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
527 /* 8102e, 8168c and beyond. */
528 enum rtl_tx_desc_bit_1
{
529 /* Second doubleword. */
530 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
531 TD1_IP_CS
= (1 << 29), /* Calculate IP checksum */
532 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
533 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
536 static const struct rtl_tx_desc_info
{
543 } tx_desc_info
[] = {
546 .udp
= TD0_IP_CS
| TD0_UDP_CS
,
547 .tcp
= TD0_IP_CS
| TD0_TCP_CS
549 .mss_shift
= TD0_MSS_SHIFT
,
554 .udp
= TD1_IP_CS
| TD1_UDP_CS
,
555 .tcp
= TD1_IP_CS
| TD1_TCP_CS
557 .mss_shift
= TD1_MSS_SHIFT
,
562 enum rtl_rx_desc_bit
{
564 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
565 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
567 #define RxProtoUDP (PID1)
568 #define RxProtoTCP (PID0)
569 #define RxProtoIP (PID1 | PID0)
570 #define RxProtoMask RxProtoIP
572 IPFail
= (1 << 16), /* IP checksum failed */
573 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
574 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
575 RxVlanTag
= (1 << 16), /* VLAN tag available */
578 #define RsvdMask 0x3fffc000
595 u8 __pad
[sizeof(void *) - sizeof(u32
)];
599 RTL_FEATURE_WOL
= (1 << 0),
600 RTL_FEATURE_MSI
= (1 << 1),
601 RTL_FEATURE_GMII
= (1 << 2),
604 struct rtl8169_counters
{
611 __le32 tx_one_collision
;
612 __le32 tx_multi_collision
;
620 struct rtl8169_private
{
621 void __iomem
*mmio_addr
; /* memory map physical address */
622 struct pci_dev
*pci_dev
;
623 struct net_device
*dev
;
624 struct napi_struct napi
;
629 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
630 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
633 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
634 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
635 dma_addr_t TxPhyAddr
;
636 dma_addr_t RxPhyAddr
;
637 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
638 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
639 struct timer_list timer
;
646 void (*write
)(void __iomem
*, int, int);
647 int (*read
)(void __iomem
*, int);
650 struct pll_power_ops
{
651 void (*down
)(struct rtl8169_private
*);
652 void (*up
)(struct rtl8169_private
*);
655 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
656 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
657 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
658 void (*hw_start
)(struct net_device
*);
659 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
660 unsigned int (*link_ok
)(void __iomem
*);
661 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
662 struct delayed_work task
;
665 struct mii_if_info mii
;
666 struct rtl8169_counters counters
;
670 const struct firmware
*fw
;
672 #define RTL_VER_SIZE 32
674 char version
[RTL_VER_SIZE
];
676 struct rtl_fw_phy_action
{
681 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
684 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
685 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
686 module_param(use_dac
, int, 0);
687 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
688 module_param_named(debug
, debug
.msg_enable
, int, 0);
689 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
690 MODULE_LICENSE("GPL");
691 MODULE_VERSION(RTL8169_VERSION
);
692 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
693 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
694 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
695 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
696 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
698 static int rtl8169_open(struct net_device
*dev
);
699 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
700 struct net_device
*dev
);
701 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
702 static int rtl8169_init_ring(struct net_device
*dev
);
703 static void rtl_hw_start(struct net_device
*dev
);
704 static int rtl8169_close(struct net_device
*dev
);
705 static void rtl_set_rx_mode(struct net_device
*dev
);
706 static void rtl8169_tx_timeout(struct net_device
*dev
);
707 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
708 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
709 void __iomem
*, u32 budget
);
710 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
711 static void rtl8169_down(struct net_device
*dev
);
712 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
713 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
715 static const unsigned int rtl8169_rx_config
=
716 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
718 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
720 void __iomem
*ioaddr
= tp
->mmio_addr
;
723 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
724 for (i
= 0; i
< 20; i
++) {
726 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
729 return RTL_R32(OCPDR
);
732 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
734 void __iomem
*ioaddr
= tp
->mmio_addr
;
737 RTL_W32(OCPDR
, data
);
738 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
739 for (i
= 0; i
< 20; i
++) {
741 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
746 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
748 void __iomem
*ioaddr
= tp
->mmio_addr
;
752 RTL_W32(ERIAR
, 0x800010e8);
754 for (i
= 0; i
< 5; i
++) {
756 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
760 ocp_write(tp
, 0x1, 0x30, 0x00000001);
763 #define OOB_CMD_RESET 0x00
764 #define OOB_CMD_DRIVER_START 0x05
765 #define OOB_CMD_DRIVER_STOP 0x06
767 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
769 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
772 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
777 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
779 reg
= rtl8168_get_ocp_reg(tp
);
781 for (i
= 0; i
< 10; i
++) {
783 if (ocp_read(tp
, 0x0f, reg
) & 0x00000800)
788 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
793 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
795 reg
= rtl8168_get_ocp_reg(tp
);
797 for (i
= 0; i
< 10; i
++) {
799 if ((ocp_read(tp
, 0x0f, reg
) & 0x00000800) == 0)
804 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
806 u16 reg
= rtl8168_get_ocp_reg(tp
);
808 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
811 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
815 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
817 for (i
= 20; i
> 0; i
--) {
819 * Check if the RTL8169 has completed writing to the specified
822 if (!(RTL_R32(PHYAR
) & 0x80000000))
827 * According to hardware specs a 20us delay is required after write
828 * complete indication, but before sending next command.
833 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
837 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
839 for (i
= 20; i
> 0; i
--) {
841 * Check if the RTL8169 has completed retrieving data from
842 * the specified MII register.
844 if (RTL_R32(PHYAR
) & 0x80000000) {
845 value
= RTL_R32(PHYAR
) & 0xffff;
851 * According to hardware specs a 20us delay is required after read
852 * complete indication, but before sending next command.
859 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
863 RTL_W32(OCPDR
, data
|
864 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
865 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
866 RTL_W32(EPHY_RXER_NUM
, 0);
868 for (i
= 0; i
< 100; i
++) {
870 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
875 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
877 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
878 (value
& OCPDR_DATA_MASK
));
881 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
885 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
888 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
889 RTL_W32(EPHY_RXER_NUM
, 0);
891 for (i
= 0; i
< 100; i
++) {
893 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
897 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
900 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
902 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
904 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
907 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
909 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
912 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
914 r8168dp_2_mdio_start(ioaddr
);
916 r8169_mdio_write(ioaddr
, reg_addr
, value
);
918 r8168dp_2_mdio_stop(ioaddr
);
921 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
925 r8168dp_2_mdio_start(ioaddr
);
927 value
= r8169_mdio_read(ioaddr
, reg_addr
);
929 r8168dp_2_mdio_stop(ioaddr
);
934 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
936 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
939 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
941 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
944 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
946 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
949 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
953 val
= rtl_readphy(tp
, reg_addr
);
954 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
957 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
960 struct rtl8169_private
*tp
= netdev_priv(dev
);
962 rtl_writephy(tp
, location
, val
);
965 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
967 struct rtl8169_private
*tp
= netdev_priv(dev
);
969 return rtl_readphy(tp
, location
);
972 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
976 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
977 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
979 for (i
= 0; i
< 100; i
++) {
980 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
986 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
991 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
993 for (i
= 0; i
< 100; i
++) {
994 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
995 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
1004 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
1008 RTL_W32(CSIDR
, value
);
1009 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
1010 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1012 for (i
= 0; i
< 100; i
++) {
1013 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
1019 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
1024 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
1025 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
1027 for (i
= 0; i
< 100; i
++) {
1028 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
1029 value
= RTL_R32(CSIDR
);
1038 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
1043 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1045 for (i
= 0; i
< 300; i
++) {
1046 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
1047 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
1056 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
1058 RTL_W16(IntrMask
, 0x0000);
1060 RTL_W16(IntrStatus
, 0xffff);
1063 static void rtl8169_asic_down(void __iomem
*ioaddr
)
1065 RTL_W8(ChipCmd
, 0x00);
1066 rtl8169_irq_mask_and_ack(ioaddr
);
1070 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1072 void __iomem
*ioaddr
= tp
->mmio_addr
;
1074 return RTL_R32(TBICSR
) & TBIReset
;
1077 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1079 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1082 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1084 return RTL_R32(TBICSR
) & TBILinkOk
;
1087 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1089 return RTL_R8(PHYstatus
) & LinkStatus
;
1092 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1094 void __iomem
*ioaddr
= tp
->mmio_addr
;
1096 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1099 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1103 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1104 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1107 static void __rtl8169_check_link_status(struct net_device
*dev
,
1108 struct rtl8169_private
*tp
,
1109 void __iomem
*ioaddr
, bool pm
)
1111 unsigned long flags
;
1113 spin_lock_irqsave(&tp
->lock
, flags
);
1114 if (tp
->link_ok(ioaddr
)) {
1115 /* This is to cancel a scheduled suspend if there's one. */
1117 pm_request_resume(&tp
->pci_dev
->dev
);
1118 netif_carrier_on(dev
);
1119 if (net_ratelimit())
1120 netif_info(tp
, ifup
, dev
, "link up\n");
1122 netif_carrier_off(dev
);
1123 netif_info(tp
, ifdown
, dev
, "link down\n");
1125 pm_schedule_suspend(&tp
->pci_dev
->dev
, 100);
1127 spin_unlock_irqrestore(&tp
->lock
, flags
);
1130 static void rtl8169_check_link_status(struct net_device
*dev
,
1131 struct rtl8169_private
*tp
,
1132 void __iomem
*ioaddr
)
1134 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1137 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1139 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1141 void __iomem
*ioaddr
= tp
->mmio_addr
;
1145 options
= RTL_R8(Config1
);
1146 if (!(options
& PMEnable
))
1149 options
= RTL_R8(Config3
);
1150 if (options
& LinkUp
)
1151 wolopts
|= WAKE_PHY
;
1152 if (options
& MagicPacket
)
1153 wolopts
|= WAKE_MAGIC
;
1155 options
= RTL_R8(Config5
);
1157 wolopts
|= WAKE_UCAST
;
1159 wolopts
|= WAKE_BCAST
;
1161 wolopts
|= WAKE_MCAST
;
1166 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1168 struct rtl8169_private
*tp
= netdev_priv(dev
);
1170 spin_lock_irq(&tp
->lock
);
1172 wol
->supported
= WAKE_ANY
;
1173 wol
->wolopts
= __rtl8169_get_wol(tp
);
1175 spin_unlock_irq(&tp
->lock
);
1178 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1180 void __iomem
*ioaddr
= tp
->mmio_addr
;
1182 static const struct {
1187 { WAKE_ANY
, Config1
, PMEnable
},
1188 { WAKE_PHY
, Config3
, LinkUp
},
1189 { WAKE_MAGIC
, Config3
, MagicPacket
},
1190 { WAKE_UCAST
, Config5
, UWF
},
1191 { WAKE_BCAST
, Config5
, BWF
},
1192 { WAKE_MCAST
, Config5
, MWF
},
1193 { WAKE_ANY
, Config5
, LanWake
}
1196 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1198 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1199 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1200 if (wolopts
& cfg
[i
].opt
)
1201 options
|= cfg
[i
].mask
;
1202 RTL_W8(cfg
[i
].reg
, options
);
1205 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1208 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1210 struct rtl8169_private
*tp
= netdev_priv(dev
);
1212 spin_lock_irq(&tp
->lock
);
1215 tp
->features
|= RTL_FEATURE_WOL
;
1217 tp
->features
&= ~RTL_FEATURE_WOL
;
1218 __rtl8169_set_wol(tp
, wol
->wolopts
);
1219 spin_unlock_irq(&tp
->lock
);
1221 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1226 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1228 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1231 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1232 struct ethtool_drvinfo
*info
)
1234 struct rtl8169_private
*tp
= netdev_priv(dev
);
1235 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1237 strcpy(info
->driver
, MODULENAME
);
1238 strcpy(info
->version
, RTL8169_VERSION
);
1239 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
1240 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1241 strcpy(info
->fw_version
, IS_ERR_OR_NULL(rtl_fw
) ? "N/A" :
1245 static int rtl8169_get_regs_len(struct net_device
*dev
)
1247 return R8169_REGS_SIZE
;
1250 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1251 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1253 struct rtl8169_private
*tp
= netdev_priv(dev
);
1254 void __iomem
*ioaddr
= tp
->mmio_addr
;
1258 reg
= RTL_R32(TBICSR
);
1259 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1260 (duplex
== DUPLEX_FULL
)) {
1261 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1262 } else if (autoneg
== AUTONEG_ENABLE
)
1263 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1265 netif_warn(tp
, link
, dev
,
1266 "incorrect speed setting refused in TBI mode\n");
1273 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1274 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1276 struct rtl8169_private
*tp
= netdev_priv(dev
);
1277 int giga_ctrl
, bmcr
;
1280 rtl_writephy(tp
, 0x1f, 0x0000);
1282 if (autoneg
== AUTONEG_ENABLE
) {
1285 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1286 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1287 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1289 if (adv
& ADVERTISED_10baseT_Half
)
1290 auto_nego
|= ADVERTISE_10HALF
;
1291 if (adv
& ADVERTISED_10baseT_Full
)
1292 auto_nego
|= ADVERTISE_10FULL
;
1293 if (adv
& ADVERTISED_100baseT_Half
)
1294 auto_nego
|= ADVERTISE_100HALF
;
1295 if (adv
& ADVERTISED_100baseT_Full
)
1296 auto_nego
|= ADVERTISE_100FULL
;
1298 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1300 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1301 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1303 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1304 if (tp
->mii
.supports_gmii
) {
1305 if (adv
& ADVERTISED_1000baseT_Half
)
1306 giga_ctrl
|= ADVERTISE_1000HALF
;
1307 if (adv
& ADVERTISED_1000baseT_Full
)
1308 giga_ctrl
|= ADVERTISE_1000FULL
;
1309 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1310 ADVERTISED_1000baseT_Full
)) {
1311 netif_info(tp
, link
, dev
,
1312 "PHY does not support 1000Mbps\n");
1316 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1318 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1319 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1323 if (speed
== SPEED_10
)
1325 else if (speed
== SPEED_100
)
1326 bmcr
= BMCR_SPEED100
;
1330 if (duplex
== DUPLEX_FULL
)
1331 bmcr
|= BMCR_FULLDPLX
;
1334 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1336 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1337 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1338 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1339 rtl_writephy(tp
, 0x17, 0x2138);
1340 rtl_writephy(tp
, 0x0e, 0x0260);
1342 rtl_writephy(tp
, 0x17, 0x2108);
1343 rtl_writephy(tp
, 0x0e, 0x0000);
1352 static int rtl8169_set_speed(struct net_device
*dev
,
1353 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1355 struct rtl8169_private
*tp
= netdev_priv(dev
);
1358 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1362 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1363 (advertising
& ADVERTISED_1000baseT_Full
)) {
1364 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1370 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1372 struct rtl8169_private
*tp
= netdev_priv(dev
);
1373 unsigned long flags
;
1376 del_timer_sync(&tp
->timer
);
1378 spin_lock_irqsave(&tp
->lock
, flags
);
1379 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1380 cmd
->duplex
, cmd
->advertising
);
1381 spin_unlock_irqrestore(&tp
->lock
, flags
);
1386 static u32
rtl8169_fix_features(struct net_device
*dev
, u32 features
)
1388 if (dev
->mtu
> TD_MSS_MAX
)
1389 features
&= ~NETIF_F_ALL_TSO
;
1394 static int rtl8169_set_features(struct net_device
*dev
, u32 features
)
1396 struct rtl8169_private
*tp
= netdev_priv(dev
);
1397 void __iomem
*ioaddr
= tp
->mmio_addr
;
1398 unsigned long flags
;
1400 spin_lock_irqsave(&tp
->lock
, flags
);
1402 if (features
& NETIF_F_RXCSUM
)
1403 tp
->cp_cmd
|= RxChkSum
;
1405 tp
->cp_cmd
&= ~RxChkSum
;
1407 if (dev
->features
& NETIF_F_HW_VLAN_RX
)
1408 tp
->cp_cmd
|= RxVlan
;
1410 tp
->cp_cmd
&= ~RxVlan
;
1412 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1415 spin_unlock_irqrestore(&tp
->lock
, flags
);
1420 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1421 struct sk_buff
*skb
)
1423 return (vlan_tx_tag_present(skb
)) ?
1424 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1427 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1429 u32 opts2
= le32_to_cpu(desc
->opts2
);
1431 if (opts2
& RxVlanTag
)
1432 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
1437 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1439 struct rtl8169_private
*tp
= netdev_priv(dev
);
1440 void __iomem
*ioaddr
= tp
->mmio_addr
;
1444 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1445 cmd
->port
= PORT_FIBRE
;
1446 cmd
->transceiver
= XCVR_INTERNAL
;
1448 status
= RTL_R32(TBICSR
);
1449 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1450 cmd
->autoneg
= !!(status
& TBINwEnable
);
1452 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1453 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1458 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1460 struct rtl8169_private
*tp
= netdev_priv(dev
);
1462 return mii_ethtool_gset(&tp
->mii
, cmd
);
1465 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1467 struct rtl8169_private
*tp
= netdev_priv(dev
);
1468 unsigned long flags
;
1471 spin_lock_irqsave(&tp
->lock
, flags
);
1473 rc
= tp
->get_settings(dev
, cmd
);
1475 spin_unlock_irqrestore(&tp
->lock
, flags
);
1479 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1482 struct rtl8169_private
*tp
= netdev_priv(dev
);
1483 unsigned long flags
;
1485 if (regs
->len
> R8169_REGS_SIZE
)
1486 regs
->len
= R8169_REGS_SIZE
;
1488 spin_lock_irqsave(&tp
->lock
, flags
);
1489 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1490 spin_unlock_irqrestore(&tp
->lock
, flags
);
1493 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1495 struct rtl8169_private
*tp
= netdev_priv(dev
);
1497 return tp
->msg_enable
;
1500 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1502 struct rtl8169_private
*tp
= netdev_priv(dev
);
1504 tp
->msg_enable
= value
;
1507 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1514 "tx_single_collisions",
1515 "tx_multi_collisions",
1523 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1527 return ARRAY_SIZE(rtl8169_gstrings
);
1533 static void rtl8169_update_counters(struct net_device
*dev
)
1535 struct rtl8169_private
*tp
= netdev_priv(dev
);
1536 void __iomem
*ioaddr
= tp
->mmio_addr
;
1537 struct device
*d
= &tp
->pci_dev
->dev
;
1538 struct rtl8169_counters
*counters
;
1544 * Some chips are unable to dump tally counters when the receiver
1547 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1550 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1554 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1555 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1556 RTL_W32(CounterAddrLow
, cmd
);
1557 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1560 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1561 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1567 RTL_W32(CounterAddrLow
, 0);
1568 RTL_W32(CounterAddrHigh
, 0);
1570 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1573 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1574 struct ethtool_stats
*stats
, u64
*data
)
1576 struct rtl8169_private
*tp
= netdev_priv(dev
);
1580 rtl8169_update_counters(dev
);
1582 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1583 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1584 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1585 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1586 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1587 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1588 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1589 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1590 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1591 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1592 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1593 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1594 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1597 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1601 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1606 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1607 .get_drvinfo
= rtl8169_get_drvinfo
,
1608 .get_regs_len
= rtl8169_get_regs_len
,
1609 .get_link
= ethtool_op_get_link
,
1610 .get_settings
= rtl8169_get_settings
,
1611 .set_settings
= rtl8169_set_settings
,
1612 .get_msglevel
= rtl8169_get_msglevel
,
1613 .set_msglevel
= rtl8169_set_msglevel
,
1614 .get_regs
= rtl8169_get_regs
,
1615 .get_wol
= rtl8169_get_wol
,
1616 .set_wol
= rtl8169_set_wol
,
1617 .get_strings
= rtl8169_get_strings
,
1618 .get_sset_count
= rtl8169_get_sset_count
,
1619 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1622 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1623 struct net_device
*dev
, u8 default_version
)
1625 void __iomem
*ioaddr
= tp
->mmio_addr
;
1627 * The driver currently handles the 8168Bf and the 8168Be identically
1628 * but they can be identified more specifically through the test below
1631 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1633 * Same thing for the 8101Eb and the 8101Ec:
1635 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1637 static const struct rtl_mac_info
{
1643 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
1644 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
1645 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
1648 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1649 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1650 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1652 /* 8168DP family. */
1653 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1654 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1655 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
1658 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1659 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1660 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1661 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1662 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1663 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1664 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1665 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1666 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1669 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1670 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1671 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1672 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1675 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
1676 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
1677 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
1678 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
1679 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1680 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1681 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1682 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1683 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1684 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1685 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1686 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1687 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1688 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1689 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1690 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1691 /* FIXME: where did these entries come from ? -- FR */
1692 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1693 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1696 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1697 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1698 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1699 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1700 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1701 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1704 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1706 const struct rtl_mac_info
*p
= mac_info
;
1709 reg
= RTL_R32(TxConfig
);
1710 while ((reg
& p
->mask
) != p
->val
)
1712 tp
->mac_version
= p
->mac_version
;
1714 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
1715 netif_notice(tp
, probe
, dev
,
1716 "unknown MAC, using family default\n");
1717 tp
->mac_version
= default_version
;
1721 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1723 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1731 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1732 const struct phy_reg
*regs
, int len
)
1735 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1740 #define PHY_READ 0x00000000
1741 #define PHY_DATA_OR 0x10000000
1742 #define PHY_DATA_AND 0x20000000
1743 #define PHY_BJMPN 0x30000000
1744 #define PHY_READ_EFUSE 0x40000000
1745 #define PHY_READ_MAC_BYTE 0x50000000
1746 #define PHY_WRITE_MAC_BYTE 0x60000000
1747 #define PHY_CLEAR_READCOUNT 0x70000000
1748 #define PHY_WRITE 0x80000000
1749 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1750 #define PHY_COMP_EQ_SKIPN 0xa0000000
1751 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1752 #define PHY_WRITE_PREVIOUS 0xc0000000
1753 #define PHY_SKIPN 0xd0000000
1754 #define PHY_DELAY_MS 0xe0000000
1755 #define PHY_WRITE_ERI_WORD 0xf0000000
1759 char version
[RTL_VER_SIZE
];
1765 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1767 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1769 const struct firmware
*fw
= rtl_fw
->fw
;
1770 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
1771 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
1772 char *version
= rtl_fw
->version
;
1775 if (fw
->size
< FW_OPCODE_SIZE
)
1778 if (!fw_info
->magic
) {
1779 size_t i
, size
, start
;
1782 if (fw
->size
< sizeof(*fw_info
))
1785 for (i
= 0; i
< fw
->size
; i
++)
1786 checksum
+= fw
->data
[i
];
1790 start
= le32_to_cpu(fw_info
->fw_start
);
1791 if (start
> fw
->size
)
1794 size
= le32_to_cpu(fw_info
->fw_len
);
1795 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
1798 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
1800 pa
->code
= (__le32
*)(fw
->data
+ start
);
1803 if (fw
->size
% FW_OPCODE_SIZE
)
1806 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
1808 pa
->code
= (__le32
*)fw
->data
;
1809 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
1811 version
[RTL_VER_SIZE
- 1] = 0;
1818 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
1819 struct rtl_fw_phy_action
*pa
)
1824 for (index
= 0; index
< pa
->size
; index
++) {
1825 u32 action
= le32_to_cpu(pa
->code
[index
]);
1826 u32 regno
= (action
& 0x0fff0000) >> 16;
1828 switch(action
& 0xf0000000) {
1832 case PHY_READ_EFUSE
:
1833 case PHY_CLEAR_READCOUNT
:
1835 case PHY_WRITE_PREVIOUS
:
1840 if (regno
> index
) {
1841 netif_err(tp
, ifup
, tp
->dev
,
1842 "Out of range of firmware\n");
1846 case PHY_READCOUNT_EQ_SKIP
:
1847 if (index
+ 2 >= pa
->size
) {
1848 netif_err(tp
, ifup
, tp
->dev
,
1849 "Out of range of firmware\n");
1853 case PHY_COMP_EQ_SKIPN
:
1854 case PHY_COMP_NEQ_SKIPN
:
1856 if (index
+ 1 + regno
>= pa
->size
) {
1857 netif_err(tp
, ifup
, tp
->dev
,
1858 "Out of range of firmware\n");
1863 case PHY_READ_MAC_BYTE
:
1864 case PHY_WRITE_MAC_BYTE
:
1865 case PHY_WRITE_ERI_WORD
:
1867 netif_err(tp
, ifup
, tp
->dev
,
1868 "Invalid action 0x%08x\n", action
);
1877 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1879 struct net_device
*dev
= tp
->dev
;
1882 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
1883 netif_err(tp
, ifup
, dev
, "invalid firwmare\n");
1887 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
1893 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1895 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
1899 predata
= count
= 0;
1901 for (index
= 0; index
< pa
->size
; ) {
1902 u32 action
= le32_to_cpu(pa
->code
[index
]);
1903 u32 data
= action
& 0x0000ffff;
1904 u32 regno
= (action
& 0x0fff0000) >> 16;
1909 switch(action
& 0xf0000000) {
1911 predata
= rtl_readphy(tp
, regno
);
1926 case PHY_READ_EFUSE
:
1927 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
1930 case PHY_CLEAR_READCOUNT
:
1935 rtl_writephy(tp
, regno
, data
);
1938 case PHY_READCOUNT_EQ_SKIP
:
1939 index
+= (count
== data
) ? 2 : 1;
1941 case PHY_COMP_EQ_SKIPN
:
1942 if (predata
== data
)
1946 case PHY_COMP_NEQ_SKIPN
:
1947 if (predata
!= data
)
1951 case PHY_WRITE_PREVIOUS
:
1952 rtl_writephy(tp
, regno
, predata
);
1963 case PHY_READ_MAC_BYTE
:
1964 case PHY_WRITE_MAC_BYTE
:
1965 case PHY_WRITE_ERI_WORD
:
1972 static void rtl_release_firmware(struct rtl8169_private
*tp
)
1974 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
1975 release_firmware(tp
->rtl_fw
->fw
);
1978 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
1981 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
1983 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1985 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1986 if (!IS_ERR_OR_NULL(rtl_fw
))
1987 rtl_phy_write_fw(tp
, rtl_fw
);
1990 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
1992 if (rtl_readphy(tp
, reg
) != val
)
1993 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
1995 rtl_apply_firmware(tp
);
1998 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2000 static const struct phy_reg phy_reg_init
[] = {
2062 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2065 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2067 static const struct phy_reg phy_reg_init
[] = {
2073 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2076 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2078 struct pci_dev
*pdev
= tp
->pci_dev
;
2079 u16 vendor_id
, device_id
;
2081 pci_read_config_word(pdev
, PCI_SUBSYSTEM_VENDOR_ID
, &vendor_id
);
2082 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &device_id
);
2084 if ((vendor_id
!= PCI_VENDOR_ID_GIGABYTE
) || (device_id
!= 0xe000))
2087 rtl_writephy(tp
, 0x1f, 0x0001);
2088 rtl_writephy(tp
, 0x10, 0xf01b);
2089 rtl_writephy(tp
, 0x1f, 0x0000);
2092 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2094 static const struct phy_reg phy_reg_init
[] = {
2134 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2136 rtl8169scd_hw_phy_config_quirk(tp
);
2139 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2141 static const struct phy_reg phy_reg_init
[] = {
2189 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2192 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2194 static const struct phy_reg phy_reg_init
[] = {
2199 rtl_writephy(tp
, 0x1f, 0x0001);
2200 rtl_patchphy(tp
, 0x16, 1 << 0);
2202 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2205 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2207 static const struct phy_reg phy_reg_init
[] = {
2213 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2216 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2218 static const struct phy_reg phy_reg_init
[] = {
2226 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2229 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2231 static const struct phy_reg phy_reg_init
[] = {
2237 rtl_writephy(tp
, 0x1f, 0x0000);
2238 rtl_patchphy(tp
, 0x14, 1 << 5);
2239 rtl_patchphy(tp
, 0x0d, 1 << 5);
2241 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2244 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2246 static const struct phy_reg phy_reg_init
[] = {
2266 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2268 rtl_patchphy(tp
, 0x14, 1 << 5);
2269 rtl_patchphy(tp
, 0x0d, 1 << 5);
2270 rtl_writephy(tp
, 0x1f, 0x0000);
2273 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2275 static const struct phy_reg phy_reg_init
[] = {
2293 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2295 rtl_patchphy(tp
, 0x16, 1 << 0);
2296 rtl_patchphy(tp
, 0x14, 1 << 5);
2297 rtl_patchphy(tp
, 0x0d, 1 << 5);
2298 rtl_writephy(tp
, 0x1f, 0x0000);
2301 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2303 static const struct phy_reg phy_reg_init
[] = {
2315 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2317 rtl_patchphy(tp
, 0x16, 1 << 0);
2318 rtl_patchphy(tp
, 0x14, 1 << 5);
2319 rtl_patchphy(tp
, 0x0d, 1 << 5);
2320 rtl_writephy(tp
, 0x1f, 0x0000);
2323 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2325 rtl8168c_3_hw_phy_config(tp
);
2328 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2330 static const struct phy_reg phy_reg_init_0
[] = {
2331 /* Channel Estimation */
2352 * Enhance line driver power
2361 * Can not link to 1Gbps with bad cable
2362 * Decrease SNR threshold form 21.07dB to 19.04dB
2370 void __iomem
*ioaddr
= tp
->mmio_addr
;
2372 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2376 * Fine Tune Switching regulator parameter
2378 rtl_writephy(tp
, 0x1f, 0x0002);
2379 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2380 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2382 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2383 static const struct phy_reg phy_reg_init
[] = {
2393 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2395 val
= rtl_readphy(tp
, 0x0d);
2397 if ((val
& 0x00ff) != 0x006c) {
2398 static const u32 set
[] = {
2399 0x0065, 0x0066, 0x0067, 0x0068,
2400 0x0069, 0x006a, 0x006b, 0x006c
2404 rtl_writephy(tp
, 0x1f, 0x0002);
2407 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2408 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2411 static const struct phy_reg phy_reg_init
[] = {
2419 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2422 /* RSET couple improve */
2423 rtl_writephy(tp
, 0x1f, 0x0002);
2424 rtl_patchphy(tp
, 0x0d, 0x0300);
2425 rtl_patchphy(tp
, 0x0f, 0x0010);
2427 /* Fine tune PLL performance */
2428 rtl_writephy(tp
, 0x1f, 0x0002);
2429 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2430 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2432 rtl_writephy(tp
, 0x1f, 0x0005);
2433 rtl_writephy(tp
, 0x05, 0x001b);
2435 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2437 rtl_writephy(tp
, 0x1f, 0x0000);
2440 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2442 static const struct phy_reg phy_reg_init_0
[] = {
2443 /* Channel Estimation */
2464 * Enhance line driver power
2473 * Can not link to 1Gbps with bad cable
2474 * Decrease SNR threshold form 21.07dB to 19.04dB
2482 void __iomem
*ioaddr
= tp
->mmio_addr
;
2484 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2486 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2487 static const struct phy_reg phy_reg_init
[] = {
2498 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2500 val
= rtl_readphy(tp
, 0x0d);
2501 if ((val
& 0x00ff) != 0x006c) {
2502 static const u32 set
[] = {
2503 0x0065, 0x0066, 0x0067, 0x0068,
2504 0x0069, 0x006a, 0x006b, 0x006c
2508 rtl_writephy(tp
, 0x1f, 0x0002);
2511 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2512 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2515 static const struct phy_reg phy_reg_init
[] = {
2523 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2526 /* Fine tune PLL performance */
2527 rtl_writephy(tp
, 0x1f, 0x0002);
2528 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2529 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2531 /* Switching regulator Slew rate */
2532 rtl_writephy(tp
, 0x1f, 0x0002);
2533 rtl_patchphy(tp
, 0x0f, 0x0017);
2535 rtl_writephy(tp
, 0x1f, 0x0005);
2536 rtl_writephy(tp
, 0x05, 0x001b);
2538 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2540 rtl_writephy(tp
, 0x1f, 0x0000);
2543 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2545 static const struct phy_reg phy_reg_init
[] = {
2601 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2604 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2606 static const struct phy_reg phy_reg_init
[] = {
2616 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2617 rtl_patchphy(tp
, 0x0d, 1 << 5);
2620 static void rtl8168e_hw_phy_config(struct rtl8169_private
*tp
)
2622 static const struct phy_reg phy_reg_init
[] = {
2623 /* Enable Delay cap */
2629 /* Channel estimation fine tune */
2638 /* Update PFM & 10M TX idle timer */
2650 rtl_apply_firmware(tp
);
2652 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2654 /* DCO enable for 10M IDLE Power */
2655 rtl_writephy(tp
, 0x1f, 0x0007);
2656 rtl_writephy(tp
, 0x1e, 0x0023);
2657 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2658 rtl_writephy(tp
, 0x1f, 0x0000);
2660 /* For impedance matching */
2661 rtl_writephy(tp
, 0x1f, 0x0002);
2662 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
2663 rtl_writephy(tp
, 0x1f, 0x0000);
2665 /* PHY auto speed down */
2666 rtl_writephy(tp
, 0x1f, 0x0007);
2667 rtl_writephy(tp
, 0x1e, 0x002d);
2668 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
2669 rtl_writephy(tp
, 0x1f, 0x0000);
2670 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2672 rtl_writephy(tp
, 0x1f, 0x0005);
2673 rtl_writephy(tp
, 0x05, 0x8b86);
2674 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2675 rtl_writephy(tp
, 0x1f, 0x0000);
2677 rtl_writephy(tp
, 0x1f, 0x0005);
2678 rtl_writephy(tp
, 0x05, 0x8b85);
2679 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2680 rtl_writephy(tp
, 0x1f, 0x0007);
2681 rtl_writephy(tp
, 0x1e, 0x0020);
2682 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
2683 rtl_writephy(tp
, 0x1f, 0x0006);
2684 rtl_writephy(tp
, 0x00, 0x5a00);
2685 rtl_writephy(tp
, 0x1f, 0x0000);
2686 rtl_writephy(tp
, 0x0d, 0x0007);
2687 rtl_writephy(tp
, 0x0e, 0x003c);
2688 rtl_writephy(tp
, 0x0d, 0x4007);
2689 rtl_writephy(tp
, 0x0e, 0x0000);
2690 rtl_writephy(tp
, 0x0d, 0x0000);
2693 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
2695 static const struct phy_reg phy_reg_init
[] = {
2702 rtl_writephy(tp
, 0x1f, 0x0000);
2703 rtl_patchphy(tp
, 0x11, 1 << 12);
2704 rtl_patchphy(tp
, 0x19, 1 << 13);
2705 rtl_patchphy(tp
, 0x10, 1 << 15);
2707 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2710 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
2712 static const struct phy_reg phy_reg_init
[] = {
2726 /* Disable ALDPS before ram code */
2727 rtl_writephy(tp
, 0x1f, 0x0000);
2728 rtl_writephy(tp
, 0x18, 0x0310);
2731 rtl_apply_firmware(tp
);
2733 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2736 static void rtl_hw_phy_config(struct net_device
*dev
)
2738 struct rtl8169_private
*tp
= netdev_priv(dev
);
2740 rtl8169_print_mac_version(tp
);
2742 switch (tp
->mac_version
) {
2743 case RTL_GIGA_MAC_VER_01
:
2745 case RTL_GIGA_MAC_VER_02
:
2746 case RTL_GIGA_MAC_VER_03
:
2747 rtl8169s_hw_phy_config(tp
);
2749 case RTL_GIGA_MAC_VER_04
:
2750 rtl8169sb_hw_phy_config(tp
);
2752 case RTL_GIGA_MAC_VER_05
:
2753 rtl8169scd_hw_phy_config(tp
);
2755 case RTL_GIGA_MAC_VER_06
:
2756 rtl8169sce_hw_phy_config(tp
);
2758 case RTL_GIGA_MAC_VER_07
:
2759 case RTL_GIGA_MAC_VER_08
:
2760 case RTL_GIGA_MAC_VER_09
:
2761 rtl8102e_hw_phy_config(tp
);
2763 case RTL_GIGA_MAC_VER_11
:
2764 rtl8168bb_hw_phy_config(tp
);
2766 case RTL_GIGA_MAC_VER_12
:
2767 rtl8168bef_hw_phy_config(tp
);
2769 case RTL_GIGA_MAC_VER_17
:
2770 rtl8168bef_hw_phy_config(tp
);
2772 case RTL_GIGA_MAC_VER_18
:
2773 rtl8168cp_1_hw_phy_config(tp
);
2775 case RTL_GIGA_MAC_VER_19
:
2776 rtl8168c_1_hw_phy_config(tp
);
2778 case RTL_GIGA_MAC_VER_20
:
2779 rtl8168c_2_hw_phy_config(tp
);
2781 case RTL_GIGA_MAC_VER_21
:
2782 rtl8168c_3_hw_phy_config(tp
);
2784 case RTL_GIGA_MAC_VER_22
:
2785 rtl8168c_4_hw_phy_config(tp
);
2787 case RTL_GIGA_MAC_VER_23
:
2788 case RTL_GIGA_MAC_VER_24
:
2789 rtl8168cp_2_hw_phy_config(tp
);
2791 case RTL_GIGA_MAC_VER_25
:
2792 rtl8168d_1_hw_phy_config(tp
);
2794 case RTL_GIGA_MAC_VER_26
:
2795 rtl8168d_2_hw_phy_config(tp
);
2797 case RTL_GIGA_MAC_VER_27
:
2798 rtl8168d_3_hw_phy_config(tp
);
2800 case RTL_GIGA_MAC_VER_28
:
2801 rtl8168d_4_hw_phy_config(tp
);
2803 case RTL_GIGA_MAC_VER_29
:
2804 case RTL_GIGA_MAC_VER_30
:
2805 rtl8105e_hw_phy_config(tp
);
2807 case RTL_GIGA_MAC_VER_31
:
2810 case RTL_GIGA_MAC_VER_32
:
2811 case RTL_GIGA_MAC_VER_33
:
2812 rtl8168e_hw_phy_config(tp
);
2820 static void rtl8169_phy_timer(unsigned long __opaque
)
2822 struct net_device
*dev
= (struct net_device
*)__opaque
;
2823 struct rtl8169_private
*tp
= netdev_priv(dev
);
2824 struct timer_list
*timer
= &tp
->timer
;
2825 void __iomem
*ioaddr
= tp
->mmio_addr
;
2826 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2828 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
2830 spin_lock_irq(&tp
->lock
);
2832 if (tp
->phy_reset_pending(tp
)) {
2834 * A busy loop could burn quite a few cycles on nowadays CPU.
2835 * Let's delay the execution of the timer for a few ticks.
2841 if (tp
->link_ok(ioaddr
))
2844 netif_warn(tp
, link
, dev
, "PHY reset until link up\n");
2846 tp
->phy_reset_enable(tp
);
2849 mod_timer(timer
, jiffies
+ timeout
);
2851 spin_unlock_irq(&tp
->lock
);
2854 #ifdef CONFIG_NET_POLL_CONTROLLER
2856 * Polling 'interrupt' - used by things like netconsole to send skbs
2857 * without having to re-enable interrupts. It's not called while
2858 * the interrupt routine is executing.
2860 static void rtl8169_netpoll(struct net_device
*dev
)
2862 struct rtl8169_private
*tp
= netdev_priv(dev
);
2863 struct pci_dev
*pdev
= tp
->pci_dev
;
2865 disable_irq(pdev
->irq
);
2866 rtl8169_interrupt(pdev
->irq
, dev
);
2867 enable_irq(pdev
->irq
);
2871 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
2872 void __iomem
*ioaddr
)
2875 pci_release_regions(pdev
);
2876 pci_clear_mwi(pdev
);
2877 pci_disable_device(pdev
);
2881 static void rtl8169_phy_reset(struct net_device
*dev
,
2882 struct rtl8169_private
*tp
)
2886 tp
->phy_reset_enable(tp
);
2887 for (i
= 0; i
< 100; i
++) {
2888 if (!tp
->phy_reset_pending(tp
))
2892 netif_err(tp
, link
, dev
, "PHY reset failed\n");
2895 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
2897 void __iomem
*ioaddr
= tp
->mmio_addr
;
2899 rtl_hw_phy_config(dev
);
2901 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
2902 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2906 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
2908 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
2909 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
2911 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
2912 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2914 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2915 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
2918 rtl8169_phy_reset(dev
, tp
);
2920 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
2921 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
2922 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
2923 (tp
->mii
.supports_gmii
?
2924 ADVERTISED_1000baseT_Half
|
2925 ADVERTISED_1000baseT_Full
: 0));
2927 if (RTL_R8(PHYstatus
) & TBI_Enable
)
2928 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
2931 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
2933 void __iomem
*ioaddr
= tp
->mmio_addr
;
2937 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
2938 high
= addr
[4] | (addr
[5] << 8);
2940 spin_lock_irq(&tp
->lock
);
2942 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2944 RTL_W32(MAC4
, high
);
2950 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2952 spin_unlock_irq(&tp
->lock
);
2955 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
2957 struct rtl8169_private
*tp
= netdev_priv(dev
);
2958 struct sockaddr
*addr
= p
;
2960 if (!is_valid_ether_addr(addr
->sa_data
))
2961 return -EADDRNOTAVAIL
;
2963 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
2965 rtl_rar_set(tp
, dev
->dev_addr
);
2970 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2972 struct rtl8169_private
*tp
= netdev_priv(dev
);
2973 struct mii_ioctl_data
*data
= if_mii(ifr
);
2975 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
2978 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
2979 struct mii_ioctl_data
*data
, int cmd
)
2983 data
->phy_id
= 32; /* Internal PHY */
2987 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
2991 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
2997 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
3002 static const struct rtl_cfg_info
{
3003 void (*hw_start
)(struct net_device
*);
3004 unsigned int region
;
3010 } rtl_cfg_infos
[] = {
3012 .hw_start
= rtl_hw_start_8169
,
3015 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3016 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3017 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3018 .features
= RTL_FEATURE_GMII
,
3019 .default_ver
= RTL_GIGA_MAC_VER_01
,
3022 .hw_start
= rtl_hw_start_8168
,
3025 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
3026 TxErr
| TxOK
| RxOK
| RxErr
,
3027 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
3028 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
3029 .default_ver
= RTL_GIGA_MAC_VER_11
,
3032 .hw_start
= rtl_hw_start_8101
,
3035 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
3036 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
3037 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
3038 .features
= RTL_FEATURE_MSI
,
3039 .default_ver
= RTL_GIGA_MAC_VER_13
,
3043 /* Cfg9346_Unlock assumed. */
3044 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
3045 const struct rtl_cfg_info
*cfg
)
3050 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
3051 if (cfg
->features
& RTL_FEATURE_MSI
) {
3052 if (pci_enable_msi(pdev
)) {
3053 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
3056 msi
= RTL_FEATURE_MSI
;
3059 RTL_W8(Config2
, cfg2
);
3063 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
3065 if (tp
->features
& RTL_FEATURE_MSI
) {
3066 pci_disable_msi(pdev
);
3067 tp
->features
&= ~RTL_FEATURE_MSI
;
3071 static const struct net_device_ops rtl8169_netdev_ops
= {
3072 .ndo_open
= rtl8169_open
,
3073 .ndo_stop
= rtl8169_close
,
3074 .ndo_get_stats
= rtl8169_get_stats
,
3075 .ndo_start_xmit
= rtl8169_start_xmit
,
3076 .ndo_tx_timeout
= rtl8169_tx_timeout
,
3077 .ndo_validate_addr
= eth_validate_addr
,
3078 .ndo_change_mtu
= rtl8169_change_mtu
,
3079 .ndo_fix_features
= rtl8169_fix_features
,
3080 .ndo_set_features
= rtl8169_set_features
,
3081 .ndo_set_mac_address
= rtl_set_mac_address
,
3082 .ndo_do_ioctl
= rtl8169_ioctl
,
3083 .ndo_set_multicast_list
= rtl_set_rx_mode
,
3084 #ifdef CONFIG_NET_POLL_CONTROLLER
3085 .ndo_poll_controller
= rtl8169_netpoll
,
3090 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
3092 struct mdio_ops
*ops
= &tp
->mdio_ops
;
3094 switch (tp
->mac_version
) {
3095 case RTL_GIGA_MAC_VER_27
:
3096 ops
->write
= r8168dp_1_mdio_write
;
3097 ops
->read
= r8168dp_1_mdio_read
;
3099 case RTL_GIGA_MAC_VER_28
:
3100 case RTL_GIGA_MAC_VER_31
:
3101 ops
->write
= r8168dp_2_mdio_write
;
3102 ops
->read
= r8168dp_2_mdio_read
;
3105 ops
->write
= r8169_mdio_write
;
3106 ops
->read
= r8169_mdio_read
;
3111 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3113 rtl_writephy(tp
, 0x1f, 0x0000);
3114 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3117 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3119 rtl_writephy(tp
, 0x1f, 0x0000);
3120 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3123 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3125 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3126 rtl_writephy(tp
, 0x1f, 0x0000);
3127 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3131 r810x_phy_power_down(tp
);
3134 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3136 r810x_phy_power_up(tp
);
3139 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3141 rtl_writephy(tp
, 0x1f, 0x0000);
3142 switch (tp
->mac_version
) {
3143 case RTL_GIGA_MAC_VER_11
:
3144 case RTL_GIGA_MAC_VER_12
:
3145 case RTL_GIGA_MAC_VER_17
:
3146 case RTL_GIGA_MAC_VER_18
:
3147 case RTL_GIGA_MAC_VER_19
:
3148 case RTL_GIGA_MAC_VER_20
:
3149 case RTL_GIGA_MAC_VER_21
:
3150 case RTL_GIGA_MAC_VER_22
:
3151 case RTL_GIGA_MAC_VER_23
:
3152 case RTL_GIGA_MAC_VER_24
:
3153 case RTL_GIGA_MAC_VER_25
:
3154 case RTL_GIGA_MAC_VER_26
:
3155 case RTL_GIGA_MAC_VER_27
:
3156 case RTL_GIGA_MAC_VER_28
:
3157 case RTL_GIGA_MAC_VER_31
:
3158 rtl_writephy(tp
, 0x0e, 0x0000);
3163 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3166 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
3168 rtl_writephy(tp
, 0x1f, 0x0000);
3169 switch (tp
->mac_version
) {
3170 case RTL_GIGA_MAC_VER_32
:
3171 case RTL_GIGA_MAC_VER_33
:
3172 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
3175 case RTL_GIGA_MAC_VER_11
:
3176 case RTL_GIGA_MAC_VER_12
:
3177 case RTL_GIGA_MAC_VER_17
:
3178 case RTL_GIGA_MAC_VER_18
:
3179 case RTL_GIGA_MAC_VER_19
:
3180 case RTL_GIGA_MAC_VER_20
:
3181 case RTL_GIGA_MAC_VER_21
:
3182 case RTL_GIGA_MAC_VER_22
:
3183 case RTL_GIGA_MAC_VER_23
:
3184 case RTL_GIGA_MAC_VER_24
:
3185 case RTL_GIGA_MAC_VER_25
:
3186 case RTL_GIGA_MAC_VER_26
:
3187 case RTL_GIGA_MAC_VER_27
:
3188 case RTL_GIGA_MAC_VER_28
:
3189 case RTL_GIGA_MAC_VER_31
:
3190 rtl_writephy(tp
, 0x0e, 0x0200);
3192 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3197 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
3199 void __iomem
*ioaddr
= tp
->mmio_addr
;
3201 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3202 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3203 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3204 r8168dp_check_dash(tp
)) {
3208 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
3209 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
3210 (RTL_R16(CPlusCmd
) & ASF
)) {
3214 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3215 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3216 rtl_ephy_write(ioaddr
, 0x19, 0xff64);
3218 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
3219 rtl_writephy(tp
, 0x1f, 0x0000);
3220 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3222 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
3223 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
3227 r8168_phy_power_down(tp
);
3229 switch (tp
->mac_version
) {
3230 case RTL_GIGA_MAC_VER_25
:
3231 case RTL_GIGA_MAC_VER_26
:
3232 case RTL_GIGA_MAC_VER_27
:
3233 case RTL_GIGA_MAC_VER_28
:
3234 case RTL_GIGA_MAC_VER_31
:
3235 case RTL_GIGA_MAC_VER_32
:
3236 case RTL_GIGA_MAC_VER_33
:
3237 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3242 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
3244 void __iomem
*ioaddr
= tp
->mmio_addr
;
3246 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3247 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3248 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3249 r8168dp_check_dash(tp
)) {
3253 switch (tp
->mac_version
) {
3254 case RTL_GIGA_MAC_VER_25
:
3255 case RTL_GIGA_MAC_VER_26
:
3256 case RTL_GIGA_MAC_VER_27
:
3257 case RTL_GIGA_MAC_VER_28
:
3258 case RTL_GIGA_MAC_VER_31
:
3259 case RTL_GIGA_MAC_VER_32
:
3260 case RTL_GIGA_MAC_VER_33
:
3261 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3265 r8168_phy_power_up(tp
);
3268 static void rtl_pll_power_op(struct rtl8169_private
*tp
,
3269 void (*op
)(struct rtl8169_private
*))
3275 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3277 rtl_pll_power_op(tp
, tp
->pll_power_ops
.down
);
3280 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3282 rtl_pll_power_op(tp
, tp
->pll_power_ops
.up
);
3285 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
3287 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
3289 switch (tp
->mac_version
) {
3290 case RTL_GIGA_MAC_VER_07
:
3291 case RTL_GIGA_MAC_VER_08
:
3292 case RTL_GIGA_MAC_VER_09
:
3293 case RTL_GIGA_MAC_VER_10
:
3294 case RTL_GIGA_MAC_VER_16
:
3295 case RTL_GIGA_MAC_VER_29
:
3296 case RTL_GIGA_MAC_VER_30
:
3297 ops
->down
= r810x_pll_power_down
;
3298 ops
->up
= r810x_pll_power_up
;
3301 case RTL_GIGA_MAC_VER_11
:
3302 case RTL_GIGA_MAC_VER_12
:
3303 case RTL_GIGA_MAC_VER_17
:
3304 case RTL_GIGA_MAC_VER_18
:
3305 case RTL_GIGA_MAC_VER_19
:
3306 case RTL_GIGA_MAC_VER_20
:
3307 case RTL_GIGA_MAC_VER_21
:
3308 case RTL_GIGA_MAC_VER_22
:
3309 case RTL_GIGA_MAC_VER_23
:
3310 case RTL_GIGA_MAC_VER_24
:
3311 case RTL_GIGA_MAC_VER_25
:
3312 case RTL_GIGA_MAC_VER_26
:
3313 case RTL_GIGA_MAC_VER_27
:
3314 case RTL_GIGA_MAC_VER_28
:
3315 case RTL_GIGA_MAC_VER_31
:
3316 case RTL_GIGA_MAC_VER_32
:
3317 case RTL_GIGA_MAC_VER_33
:
3318 ops
->down
= r8168_pll_power_down
;
3319 ops
->up
= r8168_pll_power_up
;
3329 static void rtl_hw_reset(struct rtl8169_private
*tp
)
3331 void __iomem
*ioaddr
= tp
->mmio_addr
;
3334 /* Soft reset the chip. */
3335 RTL_W8(ChipCmd
, CmdReset
);
3337 /* Check that the chip has finished the reset. */
3338 for (i
= 0; i
< 100; i
++) {
3339 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3341 msleep_interruptible(1);
3345 static int __devinit
3346 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3348 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
3349 const unsigned int region
= cfg
->region
;
3350 struct rtl8169_private
*tp
;
3351 struct mii_if_info
*mii
;
3352 struct net_device
*dev
;
3353 void __iomem
*ioaddr
;
3357 if (netif_msg_drv(&debug
)) {
3358 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3359 MODULENAME
, RTL8169_VERSION
);
3362 dev
= alloc_etherdev(sizeof (*tp
));
3364 if (netif_msg_drv(&debug
))
3365 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3370 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3371 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3372 tp
= netdev_priv(dev
);
3375 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3379 mii
->mdio_read
= rtl_mdio_read
;
3380 mii
->mdio_write
= rtl_mdio_write
;
3381 mii
->phy_id_mask
= 0x1f;
3382 mii
->reg_num_mask
= 0x1f;
3383 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3385 /* disable ASPM completely as that cause random device stop working
3386 * problems as well as full system hangs for some PCIe devices users */
3387 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
3388 PCIE_LINK_STATE_CLKPM
);
3390 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3391 rc
= pci_enable_device(pdev
);
3393 netif_err(tp
, probe
, dev
, "enable failure\n");
3394 goto err_out_free_dev_1
;
3397 if (pci_set_mwi(pdev
) < 0)
3398 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
3400 /* make sure PCI base addr 1 is MMIO */
3401 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3402 netif_err(tp
, probe
, dev
,
3403 "region #%d not an MMIO resource, aborting\n",
3409 /* check for weird/broken PCI region reporting */
3410 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3411 netif_err(tp
, probe
, dev
,
3412 "Invalid PCI region size(s), aborting\n");
3417 rc
= pci_request_regions(pdev
, MODULENAME
);
3419 netif_err(tp
, probe
, dev
, "could not request regions\n");
3423 tp
->cp_cmd
= RxChkSum
;
3425 if ((sizeof(dma_addr_t
) > 4) &&
3426 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3427 tp
->cp_cmd
|= PCIDAC
;
3428 dev
->features
|= NETIF_F_HIGHDMA
;
3430 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3432 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
3433 goto err_out_free_res_3
;
3437 /* ioremap MMIO region */
3438 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3440 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
3442 goto err_out_free_res_3
;
3444 tp
->mmio_addr
= ioaddr
;
3446 if (!pci_is_pcie(pdev
))
3447 netif_info(tp
, probe
, dev
, "not PCI Express\n");
3449 RTL_W16(IntrMask
, 0x0000);
3453 RTL_W16(IntrStatus
, 0xffff);
3455 pci_set_master(pdev
);
3457 /* Identify chip attached to board */
3458 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
3461 * Pretend we are using VLANs; This bypasses a nasty bug where
3462 * Interrupts stop flowing on high load on 8110SCd controllers.
3464 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3465 tp
->cp_cmd
|= RxVlan
;
3467 rtl_init_mdio_ops(tp
);
3468 rtl_init_pll_power_ops(tp
);
3470 rtl8169_print_mac_version(tp
);
3472 chipset
= tp
->mac_version
;
3473 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
3475 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3476 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3477 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3478 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3479 tp
->features
|= RTL_FEATURE_WOL
;
3480 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3481 tp
->features
|= RTL_FEATURE_WOL
;
3482 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3483 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3485 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3486 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3487 tp
->set_speed
= rtl8169_set_speed_tbi
;
3488 tp
->get_settings
= rtl8169_gset_tbi
;
3489 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3490 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3491 tp
->link_ok
= rtl8169_tbi_link_ok
;
3492 tp
->do_ioctl
= rtl_tbi_ioctl
;
3494 tp
->set_speed
= rtl8169_set_speed_xmii
;
3495 tp
->get_settings
= rtl8169_gset_xmii
;
3496 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3497 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3498 tp
->link_ok
= rtl8169_xmii_link_ok
;
3499 tp
->do_ioctl
= rtl_xmii_ioctl
;
3502 spin_lock_init(&tp
->lock
);
3504 /* Get MAC address */
3505 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3506 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3507 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3509 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3510 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3511 dev
->irq
= pdev
->irq
;
3512 dev
->base_addr
= (unsigned long) ioaddr
;
3514 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3516 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3517 * properly for all devices */
3518 dev
->features
|= NETIF_F_RXCSUM
|
3519 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3521 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3522 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3523 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
3526 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3527 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3528 dev
->hw_features
&= ~NETIF_F_HW_VLAN_RX
;
3530 tp
->intr_mask
= 0xffff;
3531 tp
->hw_start
= cfg
->hw_start
;
3532 tp
->intr_event
= cfg
->intr_event
;
3533 tp
->napi_event
= cfg
->napi_event
;
3535 init_timer(&tp
->timer
);
3536 tp
->timer
.data
= (unsigned long) dev
;
3537 tp
->timer
.function
= rtl8169_phy_timer
;
3539 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
3541 rc
= register_netdev(dev
);
3545 pci_set_drvdata(pdev
, dev
);
3547 netif_info(tp
, probe
, dev
, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3548 rtl_chip_infos
[chipset
].name
, dev
->base_addr
, dev
->dev_addr
,
3549 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), dev
->irq
);
3551 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3552 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3553 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3554 rtl8168_driver_start(tp
);
3557 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3559 if (pci_dev_run_wake(pdev
))
3560 pm_runtime_put_noidle(&pdev
->dev
);
3562 netif_carrier_off(dev
);
3568 rtl_disable_msi(pdev
, tp
);
3571 pci_release_regions(pdev
);
3573 pci_clear_mwi(pdev
);
3574 pci_disable_device(pdev
);
3580 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3582 struct net_device
*dev
= pci_get_drvdata(pdev
);
3583 struct rtl8169_private
*tp
= netdev_priv(dev
);
3585 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3586 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3587 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3588 rtl8168_driver_stop(tp
);
3591 cancel_delayed_work_sync(&tp
->task
);
3593 unregister_netdev(dev
);
3595 rtl_release_firmware(tp
);
3597 if (pci_dev_run_wake(pdev
))
3598 pm_runtime_get_noresume(&pdev
->dev
);
3600 /* restore original MAC address */
3601 rtl_rar_set(tp
, dev
->perm_addr
);
3603 rtl_disable_msi(pdev
, tp
);
3604 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3605 pci_set_drvdata(pdev
, NULL
);
3608 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
3610 struct rtl_fw
*rtl_fw
;
3614 name
= rtl_lookup_firmware_name(tp
);
3616 goto out_no_firmware
;
3618 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
3622 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
3626 rc
= rtl_check_firmware(tp
, rtl_fw
);
3628 goto err_release_firmware
;
3630 tp
->rtl_fw
= rtl_fw
;
3634 err_release_firmware
:
3635 release_firmware(rtl_fw
->fw
);
3639 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
3646 static void rtl_request_firmware(struct rtl8169_private
*tp
)
3648 if (IS_ERR(tp
->rtl_fw
))
3649 rtl_request_uncached_firmware(tp
);
3652 static int rtl8169_open(struct net_device
*dev
)
3654 struct rtl8169_private
*tp
= netdev_priv(dev
);
3655 void __iomem
*ioaddr
= tp
->mmio_addr
;
3656 struct pci_dev
*pdev
= tp
->pci_dev
;
3657 int retval
= -ENOMEM
;
3659 pm_runtime_get_sync(&pdev
->dev
);
3662 * Rx and Tx desscriptors needs 256 bytes alignment.
3663 * dma_alloc_coherent provides more.
3665 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
3666 &tp
->TxPhyAddr
, GFP_KERNEL
);
3667 if (!tp
->TxDescArray
)
3668 goto err_pm_runtime_put
;
3670 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
3671 &tp
->RxPhyAddr
, GFP_KERNEL
);
3672 if (!tp
->RxDescArray
)
3675 retval
= rtl8169_init_ring(dev
);
3679 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3683 rtl_request_firmware(tp
);
3685 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3686 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3689 goto err_release_fw_2
;
3691 napi_enable(&tp
->napi
);
3693 rtl8169_init_phy(dev
, tp
);
3695 rtl8169_set_features(dev
, dev
->features
);
3697 rtl_pll_power_up(tp
);
3701 tp
->saved_wolopts
= 0;
3702 pm_runtime_put_noidle(&pdev
->dev
);
3704 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3709 rtl_release_firmware(tp
);
3710 rtl8169_rx_clear(tp
);
3712 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3714 tp
->RxDescArray
= NULL
;
3716 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3718 tp
->TxDescArray
= NULL
;
3720 pm_runtime_put_noidle(&pdev
->dev
);
3724 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
3726 void __iomem
*ioaddr
= tp
->mmio_addr
;
3728 /* Disable interrupts */
3729 rtl8169_irq_mask_and_ack(ioaddr
);
3731 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3732 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3733 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3734 while (RTL_R8(TxPoll
) & NPQ
)
3739 /* Reset the chipset */
3740 RTL_W8(ChipCmd
, CmdReset
);
3746 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3748 void __iomem
*ioaddr
= tp
->mmio_addr
;
3749 u32 cfg
= rtl8169_rx_config
;
3751 cfg
|= (RTL_R32(RxConfig
) & RTL_RX_CONFIG_MASK
);
3752 RTL_W32(RxConfig
, cfg
);
3754 /* Set DMA burst size and Interframe Gap Time */
3755 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3756 (InterFrameGap
<< TxInterFrameGapShift
));
3759 static void rtl_hw_start(struct net_device
*dev
)
3761 struct rtl8169_private
*tp
= netdev_priv(dev
);
3767 netif_start_queue(dev
);
3770 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3771 void __iomem
*ioaddr
)
3774 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3775 * register to be written before TxDescAddrLow to work.
3776 * Switching from MMIO to I/O access fixes the issue as well.
3778 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
3779 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
3780 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
3781 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
3784 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
3788 cmd
= RTL_R16(CPlusCmd
);
3789 RTL_W16(CPlusCmd
, cmd
);
3793 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
3795 /* Low hurts. Let's disable the filtering. */
3796 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
3799 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
3801 static const struct rtl_cfg2_info
{
3806 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
3807 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
3808 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
3809 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
3811 const struct rtl_cfg2_info
*p
= cfg2_info
;
3815 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
3816 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
3817 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
3818 RTL_W32(0x7c, p
->val
);
3824 static void rtl_hw_start_8169(struct net_device
*dev
)
3826 struct rtl8169_private
*tp
= netdev_priv(dev
);
3827 void __iomem
*ioaddr
= tp
->mmio_addr
;
3828 struct pci_dev
*pdev
= tp
->pci_dev
;
3830 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
3831 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
3832 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
3835 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3836 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
3837 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
3838 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
3839 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
3840 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3842 RTL_W8(EarlyTxThres
, NoEarlyTx
);
3844 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
3846 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
3847 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
3848 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
3849 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
3850 rtl_set_rx_tx_config_registers(tp
);
3852 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3854 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
3855 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
3856 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3857 "Bit-3 and bit-14 MUST be 1\n");
3858 tp
->cp_cmd
|= (1 << 14);
3861 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3863 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
3866 * Undocumented corner. Supposedly:
3867 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3869 RTL_W16(IntrMitigate
, 0x0000);
3871 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3873 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
3874 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
3875 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
3876 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
3877 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3878 rtl_set_rx_tx_config_registers(tp
);
3881 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3883 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3886 RTL_W32(RxMissed
, 0);
3888 rtl_set_rx_mode(dev
);
3890 /* no early-rx interrupts */
3891 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3893 /* Enable all known interrupts by setting the interrupt mask. */
3894 RTL_W16(IntrMask
, tp
->intr_event
);
3897 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
3899 int cap
= pci_pcie_cap(pdev
);
3904 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3905 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
3906 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3910 static void rtl_csi_access_enable(void __iomem
*ioaddr
, u32 bits
)
3914 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
3915 rtl_csi_write(ioaddr
, 0x070c, csi
| bits
);
3918 static void rtl_csi_access_enable_1(void __iomem
*ioaddr
)
3920 rtl_csi_access_enable(ioaddr
, 0x17000000);
3923 static void rtl_csi_access_enable_2(void __iomem
*ioaddr
)
3925 rtl_csi_access_enable(ioaddr
, 0x27000000);
3929 unsigned int offset
;
3934 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
3939 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
3940 rtl_ephy_write(ioaddr
, e
->offset
, w
);
3945 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
3947 int cap
= pci_pcie_cap(pdev
);
3952 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3953 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3954 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3958 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
3960 int cap
= pci_pcie_cap(pdev
);
3965 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3966 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
3967 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3971 #define R8168_CPCMD_QUIRK_MASK (\
3982 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3984 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3986 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3988 rtl_tx_performance_tweak(pdev
,
3989 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3992 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3994 rtl_hw_start_8168bb(ioaddr
, pdev
);
3996 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
3998 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4001 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4003 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
4005 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4007 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4009 rtl_disable_clock_request(pdev
);
4011 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4014 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4016 static const struct ephy_info e_info_8168cp
[] = {
4017 { 0x01, 0, 0x0001 },
4018 { 0x02, 0x0800, 0x1000 },
4019 { 0x03, 0, 0x0042 },
4020 { 0x06, 0x0080, 0x0000 },
4024 rtl_csi_access_enable_2(ioaddr
);
4026 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
4028 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4031 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4033 rtl_csi_access_enable_2(ioaddr
);
4035 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4037 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4039 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4042 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4044 rtl_csi_access_enable_2(ioaddr
);
4046 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4049 RTL_W8(DBG_REG
, 0x20);
4051 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4053 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4055 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4058 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4060 static const struct ephy_info e_info_8168c_1
[] = {
4061 { 0x02, 0x0800, 0x1000 },
4062 { 0x03, 0, 0x0002 },
4063 { 0x06, 0x0080, 0x0000 }
4066 rtl_csi_access_enable_2(ioaddr
);
4068 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
4070 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
4072 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4075 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4077 static const struct ephy_info e_info_8168c_2
[] = {
4078 { 0x01, 0, 0x0001 },
4079 { 0x03, 0x0400, 0x0220 }
4082 rtl_csi_access_enable_2(ioaddr
);
4084 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
4086 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4089 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4091 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4094 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4096 rtl_csi_access_enable_2(ioaddr
);
4098 __rtl_hw_start_8168cp(ioaddr
, pdev
);
4101 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4103 rtl_csi_access_enable_2(ioaddr
);
4105 rtl_disable_clock_request(pdev
);
4107 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4109 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4111 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4114 static void rtl_hw_start_8168dp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4116 rtl_csi_access_enable_1(ioaddr
);
4118 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4120 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4122 rtl_disable_clock_request(pdev
);
4125 static void rtl_hw_start_8168d_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4127 static const struct ephy_info e_info_8168d_4
[] = {
4129 { 0x19, 0x20, 0x50 },
4134 rtl_csi_access_enable_1(ioaddr
);
4136 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4138 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4140 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
4141 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
4144 w
= rtl_ephy_read(ioaddr
, e
->offset
);
4145 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
4148 rtl_enable_clock_request(pdev
);
4151 static void rtl_hw_start_8168e(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4153 static const struct ephy_info e_info_8168e
[] = {
4154 { 0x00, 0x0200, 0x0100 },
4155 { 0x00, 0x0000, 0x0004 },
4156 { 0x06, 0x0002, 0x0001 },
4157 { 0x06, 0x0000, 0x0030 },
4158 { 0x07, 0x0000, 0x2000 },
4159 { 0x00, 0x0000, 0x0020 },
4160 { 0x03, 0x5800, 0x2000 },
4161 { 0x03, 0x0000, 0x0001 },
4162 { 0x01, 0x0800, 0x1000 },
4163 { 0x07, 0x0000, 0x4000 },
4164 { 0x1e, 0x0000, 0x2000 },
4165 { 0x19, 0xffff, 0xfe6c },
4166 { 0x0a, 0x0000, 0x0040 }
4169 rtl_csi_access_enable_2(ioaddr
);
4171 rtl_ephy_init(ioaddr
, e_info_8168e
, ARRAY_SIZE(e_info_8168e
));
4173 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4175 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4177 rtl_disable_clock_request(pdev
);
4179 /* Reset tx FIFO pointer */
4180 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
4181 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
4183 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4186 static void rtl_hw_start_8168(struct net_device
*dev
)
4188 struct rtl8169_private
*tp
= netdev_priv(dev
);
4189 void __iomem
*ioaddr
= tp
->mmio_addr
;
4190 struct pci_dev
*pdev
= tp
->pci_dev
;
4192 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4194 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4196 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4198 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
4200 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4202 RTL_W16(IntrMitigate
, 0x5151);
4204 /* Work around for RxFIFO overflow. */
4205 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
||
4206 tp
->mac_version
== RTL_GIGA_MAC_VER_22
) {
4207 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
4208 tp
->intr_event
&= ~RxOverflow
;
4211 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4213 rtl_set_rx_mode(dev
);
4215 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4216 (InterFrameGap
<< TxInterFrameGapShift
));
4220 switch (tp
->mac_version
) {
4221 case RTL_GIGA_MAC_VER_11
:
4222 rtl_hw_start_8168bb(ioaddr
, pdev
);
4225 case RTL_GIGA_MAC_VER_12
:
4226 case RTL_GIGA_MAC_VER_17
:
4227 rtl_hw_start_8168bef(ioaddr
, pdev
);
4230 case RTL_GIGA_MAC_VER_18
:
4231 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
4234 case RTL_GIGA_MAC_VER_19
:
4235 rtl_hw_start_8168c_1(ioaddr
, pdev
);
4238 case RTL_GIGA_MAC_VER_20
:
4239 rtl_hw_start_8168c_2(ioaddr
, pdev
);
4242 case RTL_GIGA_MAC_VER_21
:
4243 rtl_hw_start_8168c_3(ioaddr
, pdev
);
4246 case RTL_GIGA_MAC_VER_22
:
4247 rtl_hw_start_8168c_4(ioaddr
, pdev
);
4250 case RTL_GIGA_MAC_VER_23
:
4251 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
4254 case RTL_GIGA_MAC_VER_24
:
4255 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
4258 case RTL_GIGA_MAC_VER_25
:
4259 case RTL_GIGA_MAC_VER_26
:
4260 case RTL_GIGA_MAC_VER_27
:
4261 rtl_hw_start_8168d(ioaddr
, pdev
);
4264 case RTL_GIGA_MAC_VER_28
:
4265 rtl_hw_start_8168d_4(ioaddr
, pdev
);
4268 case RTL_GIGA_MAC_VER_31
:
4269 rtl_hw_start_8168dp(ioaddr
, pdev
);
4272 case RTL_GIGA_MAC_VER_32
:
4273 case RTL_GIGA_MAC_VER_33
:
4274 rtl_hw_start_8168e(ioaddr
, pdev
);
4278 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
4279 dev
->name
, tp
->mac_version
);
4283 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4285 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4287 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4289 RTL_W16(IntrMask
, tp
->intr_event
);
4292 #define R810X_CPCMD_QUIRK_MASK (\
4303 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4305 static const struct ephy_info e_info_8102e_1
[] = {
4306 { 0x01, 0, 0x6e65 },
4307 { 0x02, 0, 0x091f },
4308 { 0x03, 0, 0xc2f9 },
4309 { 0x06, 0, 0xafb5 },
4310 { 0x07, 0, 0x0e00 },
4311 { 0x19, 0, 0xec80 },
4312 { 0x01, 0, 0x2e65 },
4317 rtl_csi_access_enable_2(ioaddr
);
4319 RTL_W8(DBG_REG
, FIX_NAK_1
);
4321 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4324 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
4325 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4327 cfg1
= RTL_R8(Config1
);
4328 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
4329 RTL_W8(Config1
, cfg1
& ~LEDS0
);
4331 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
4334 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4336 rtl_csi_access_enable_2(ioaddr
);
4338 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4340 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
4341 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4344 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4346 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4348 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
4351 static void rtl_hw_start_8105e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4353 static const struct ephy_info e_info_8105e_1
[] = {
4354 { 0x07, 0, 0x4000 },
4355 { 0x19, 0, 0x0200 },
4356 { 0x19, 0, 0x0020 },
4357 { 0x1e, 0, 0x2000 },
4358 { 0x03, 0, 0x0001 },
4359 { 0x19, 0, 0x0100 },
4360 { 0x19, 0, 0x0004 },
4364 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4365 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
4367 /* Disable Early Tally Counter */
4368 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
4370 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
4371 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PM_SWITCH
);
4373 rtl_ephy_init(ioaddr
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
4376 static void rtl_hw_start_8105e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
4378 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4379 rtl_ephy_write(ioaddr
, 0x1e, rtl_ephy_read(ioaddr
, 0x1e) | 0x8000);
4382 static void rtl_hw_start_8101(struct net_device
*dev
)
4384 struct rtl8169_private
*tp
= netdev_priv(dev
);
4385 void __iomem
*ioaddr
= tp
->mmio_addr
;
4386 struct pci_dev
*pdev
= tp
->pci_dev
;
4388 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
4389 tp
->mac_version
== RTL_GIGA_MAC_VER_16
) {
4390 int cap
= pci_pcie_cap(pdev
);
4393 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
4394 PCI_EXP_DEVCTL_NOSNOOP_EN
);
4398 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4400 switch (tp
->mac_version
) {
4401 case RTL_GIGA_MAC_VER_07
:
4402 rtl_hw_start_8102e_1(ioaddr
, pdev
);
4405 case RTL_GIGA_MAC_VER_08
:
4406 rtl_hw_start_8102e_3(ioaddr
, pdev
);
4409 case RTL_GIGA_MAC_VER_09
:
4410 rtl_hw_start_8102e_2(ioaddr
, pdev
);
4413 case RTL_GIGA_MAC_VER_29
:
4414 rtl_hw_start_8105e_1(ioaddr
, pdev
);
4416 case RTL_GIGA_MAC_VER_30
:
4417 rtl_hw_start_8105e_2(ioaddr
, pdev
);
4421 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4423 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4425 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4427 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
4428 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4430 RTL_W16(IntrMitigate
, 0x0000);
4432 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4434 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4435 rtl_set_rx_tx_config_registers(tp
);
4439 rtl_set_rx_mode(dev
);
4441 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
4443 RTL_W16(IntrMask
, tp
->intr_event
);
4446 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
4448 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
4452 netdev_update_features(dev
);
4457 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
4459 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
4460 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
4463 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
4464 void **data_buff
, struct RxDesc
*desc
)
4466 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
4471 rtl8169_make_unusable_by_asic(desc
);
4474 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
4476 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
4478 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
4481 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
4484 desc
->addr
= cpu_to_le64(mapping
);
4486 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4489 static inline void *rtl8169_align(void *data
)
4491 return (void *)ALIGN((long)data
, 16);
4494 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
4495 struct RxDesc
*desc
)
4499 struct device
*d
= &tp
->pci_dev
->dev
;
4500 struct net_device
*dev
= tp
->dev
;
4501 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
4503 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
4507 if (rtl8169_align(data
) != data
) {
4509 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
4514 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
4516 if (unlikely(dma_mapping_error(d
, mapping
))) {
4517 if (net_ratelimit())
4518 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
4522 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4530 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4534 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4535 if (tp
->Rx_databuff
[i
]) {
4536 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
4537 tp
->RxDescArray
+ i
);
4542 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4544 desc
->opts1
|= cpu_to_le32(RingEnd
);
4547 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
4551 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4554 if (tp
->Rx_databuff
[i
])
4557 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
4559 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
4562 tp
->Rx_databuff
[i
] = data
;
4565 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4569 rtl8169_rx_clear(tp
);
4573 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4575 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4578 static int rtl8169_init_ring(struct net_device
*dev
)
4580 struct rtl8169_private
*tp
= netdev_priv(dev
);
4582 rtl8169_init_ring_indexes(tp
);
4584 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4585 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
4587 return rtl8169_rx_fill(tp
);
4590 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
4591 struct TxDesc
*desc
)
4593 unsigned int len
= tx_skb
->len
;
4595 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
4603 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
4608 for (i
= 0; i
< n
; i
++) {
4609 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
4610 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4611 unsigned int len
= tx_skb
->len
;
4614 struct sk_buff
*skb
= tx_skb
->skb
;
4616 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4617 tp
->TxDescArray
+ entry
);
4619 tp
->dev
->stats
.tx_dropped
++;
4627 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4629 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
4630 tp
->cur_tx
= tp
->dirty_tx
= 0;
4633 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4635 struct rtl8169_private
*tp
= netdev_priv(dev
);
4637 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4638 schedule_delayed_work(&tp
->task
, 4);
4641 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4643 struct rtl8169_private
*tp
= netdev_priv(dev
);
4644 void __iomem
*ioaddr
= tp
->mmio_addr
;
4646 synchronize_irq(dev
->irq
);
4648 /* Wait for any pending NAPI task to complete */
4649 napi_disable(&tp
->napi
);
4651 rtl8169_irq_mask_and_ack(ioaddr
);
4653 tp
->intr_mask
= 0xffff;
4654 RTL_W16(IntrMask
, tp
->intr_event
);
4655 napi_enable(&tp
->napi
);
4658 static void rtl8169_reinit_task(struct work_struct
*work
)
4660 struct rtl8169_private
*tp
=
4661 container_of(work
, struct rtl8169_private
, task
.work
);
4662 struct net_device
*dev
= tp
->dev
;
4667 if (!netif_running(dev
))
4670 rtl8169_wait_for_quiescence(dev
);
4673 ret
= rtl8169_open(dev
);
4674 if (unlikely(ret
< 0)) {
4675 if (net_ratelimit())
4676 netif_err(tp
, drv
, dev
,
4677 "reinit failure (status = %d). Rescheduling\n",
4679 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4686 static void rtl8169_reset_task(struct work_struct
*work
)
4688 struct rtl8169_private
*tp
=
4689 container_of(work
, struct rtl8169_private
, task
.work
);
4690 struct net_device
*dev
= tp
->dev
;
4695 if (!netif_running(dev
))
4698 rtl8169_wait_for_quiescence(dev
);
4700 for (i
= 0; i
< NUM_RX_DESC
; i
++)
4701 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
4703 rtl8169_tx_clear(tp
);
4705 rtl8169_init_ring_indexes(tp
);
4707 netif_wake_queue(dev
);
4708 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4714 static void rtl8169_tx_timeout(struct net_device
*dev
)
4716 struct rtl8169_private
*tp
= netdev_priv(dev
);
4718 rtl8169_hw_reset(tp
);
4720 /* Let's wait a bit while any (async) irq lands on */
4721 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4724 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4727 struct skb_shared_info
*info
= skb_shinfo(skb
);
4728 unsigned int cur_frag
, entry
;
4729 struct TxDesc
* uninitialized_var(txd
);
4730 struct device
*d
= &tp
->pci_dev
->dev
;
4733 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4734 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4739 entry
= (entry
+ 1) % NUM_TX_DESC
;
4741 txd
= tp
->TxDescArray
+ entry
;
4743 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
4744 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
4745 if (unlikely(dma_mapping_error(d
, mapping
))) {
4746 if (net_ratelimit())
4747 netif_err(tp
, drv
, tp
->dev
,
4748 "Failed to map TX fragments DMA!\n");
4752 /* Anti gcc 2.95.3 bugware (sic) */
4753 status
= opts
[0] | len
|
4754 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4756 txd
->opts1
= cpu_to_le32(status
);
4757 txd
->opts2
= cpu_to_le32(opts
[1]);
4758 txd
->addr
= cpu_to_le64(mapping
);
4760 tp
->tx_skb
[entry
].len
= len
;
4764 tp
->tx_skb
[entry
].skb
= skb
;
4765 txd
->opts1
|= cpu_to_le32(LastFrag
);
4771 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
4775 static inline void rtl8169_tso_csum(struct rtl8169_private
*tp
,
4776 struct sk_buff
*skb
, u32
*opts
)
4778 const struct rtl_tx_desc_info
*info
= tx_desc_info
+ tp
->txd_version
;
4779 u32 mss
= skb_shinfo(skb
)->gso_size
;
4780 int offset
= info
->opts_offset
;
4784 opts
[offset
] |= min(mss
, TD_MSS_MAX
) << info
->mss_shift
;
4785 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4786 const struct iphdr
*ip
= ip_hdr(skb
);
4788 if (ip
->protocol
== IPPROTO_TCP
)
4789 opts
[offset
] |= info
->checksum
.tcp
;
4790 else if (ip
->protocol
== IPPROTO_UDP
)
4791 opts
[offset
] |= info
->checksum
.udp
;
4797 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
4798 struct net_device
*dev
)
4800 struct rtl8169_private
*tp
= netdev_priv(dev
);
4801 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
4802 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
4803 void __iomem
*ioaddr
= tp
->mmio_addr
;
4804 struct device
*d
= &tp
->pci_dev
->dev
;
4810 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
4811 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
4815 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
4818 len
= skb_headlen(skb
);
4819 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
4820 if (unlikely(dma_mapping_error(d
, mapping
))) {
4821 if (net_ratelimit())
4822 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
4826 tp
->tx_skb
[entry
].len
= len
;
4827 txd
->addr
= cpu_to_le64(mapping
);
4829 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
4832 rtl8169_tso_csum(tp
, skb
, opts
);
4834 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
4838 opts
[0] |= FirstFrag
;
4840 opts
[0] |= FirstFrag
| LastFrag
;
4841 tp
->tx_skb
[entry
].skb
= skb
;
4844 txd
->opts2
= cpu_to_le32(opts
[1]);
4848 /* Anti gcc 2.95.3 bugware (sic) */
4849 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4850 txd
->opts1
= cpu_to_le32(status
);
4852 tp
->cur_tx
+= frags
+ 1;
4856 RTL_W8(TxPoll
, NPQ
);
4858 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
4859 netif_stop_queue(dev
);
4861 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
4862 netif_wake_queue(dev
);
4865 return NETDEV_TX_OK
;
4868 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
4871 dev
->stats
.tx_dropped
++;
4872 return NETDEV_TX_OK
;
4875 netif_stop_queue(dev
);
4876 dev
->stats
.tx_dropped
++;
4877 return NETDEV_TX_BUSY
;
4880 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
4882 struct rtl8169_private
*tp
= netdev_priv(dev
);
4883 struct pci_dev
*pdev
= tp
->pci_dev
;
4884 u16 pci_status
, pci_cmd
;
4886 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4887 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
4889 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4890 pci_cmd
, pci_status
);
4893 * The recovery sequence below admits a very elaborated explanation:
4894 * - it seems to work;
4895 * - I did not see what else could be done;
4896 * - it makes iop3xx happy.
4898 * Feel free to adjust to your needs.
4900 if (pdev
->broken_parity_status
)
4901 pci_cmd
&= ~PCI_COMMAND_PARITY
;
4903 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
4905 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
4907 pci_write_config_word(pdev
, PCI_STATUS
,
4908 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
4909 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
4910 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
4912 /* The infamous DAC f*ckup only happens at boot time */
4913 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
4914 void __iomem
*ioaddr
= tp
->mmio_addr
;
4916 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
4917 tp
->cp_cmd
&= ~PCIDAC
;
4918 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4919 dev
->features
&= ~NETIF_F_HIGHDMA
;
4922 rtl8169_hw_reset(tp
);
4924 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4927 static void rtl8169_tx_interrupt(struct net_device
*dev
,
4928 struct rtl8169_private
*tp
,
4929 void __iomem
*ioaddr
)
4931 unsigned int dirty_tx
, tx_left
;
4933 dirty_tx
= tp
->dirty_tx
;
4935 tx_left
= tp
->cur_tx
- dirty_tx
;
4937 while (tx_left
> 0) {
4938 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
4939 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4943 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
4944 if (status
& DescOwn
)
4947 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
4948 tp
->TxDescArray
+ entry
);
4949 if (status
& LastFrag
) {
4950 dev
->stats
.tx_packets
++;
4951 dev
->stats
.tx_bytes
+= tx_skb
->skb
->len
;
4952 dev_kfree_skb(tx_skb
->skb
);
4959 if (tp
->dirty_tx
!= dirty_tx
) {
4960 tp
->dirty_tx
= dirty_tx
;
4962 if (netif_queue_stopped(dev
) &&
4963 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
4964 netif_wake_queue(dev
);
4967 * 8168 hack: TxPoll requests are lost when the Tx packets are
4968 * too close. Let's kick an extra TxPoll request when a burst
4969 * of start_xmit activity is detected (if it is not detected,
4970 * it is slow enough). -- FR
4973 if (tp
->cur_tx
!= dirty_tx
)
4974 RTL_W8(TxPoll
, NPQ
);
4978 static inline int rtl8169_fragmented_frame(u32 status
)
4980 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
4983 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
4985 u32 status
= opts1
& RxProtoMask
;
4987 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
4988 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
4989 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4991 skb_checksum_none_assert(skb
);
4994 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
4995 struct rtl8169_private
*tp
,
4999 struct sk_buff
*skb
;
5000 struct device
*d
= &tp
->pci_dev
->dev
;
5002 data
= rtl8169_align(data
);
5003 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5005 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
5007 memcpy(skb
->data
, data
, pkt_size
);
5008 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5013 static int rtl8169_rx_interrupt(struct net_device
*dev
,
5014 struct rtl8169_private
*tp
,
5015 void __iomem
*ioaddr
, u32 budget
)
5017 unsigned int cur_rx
, rx_left
;
5020 cur_rx
= tp
->cur_rx
;
5021 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
5022 rx_left
= min(rx_left
, budget
);
5024 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
5025 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
5026 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
5030 status
= le32_to_cpu(desc
->opts1
);
5032 if (status
& DescOwn
)
5034 if (unlikely(status
& RxRES
)) {
5035 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
5037 dev
->stats
.rx_errors
++;
5038 if (status
& (RxRWT
| RxRUNT
))
5039 dev
->stats
.rx_length_errors
++;
5041 dev
->stats
.rx_crc_errors
++;
5042 if (status
& RxFOVF
) {
5043 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5044 dev
->stats
.rx_fifo_errors
++;
5046 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5048 struct sk_buff
*skb
;
5049 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
5050 int pkt_size
= (status
& 0x00001FFF) - 4;
5053 * The driver does not support incoming fragmented
5054 * frames. They are seen as a symptom of over-mtu
5057 if (unlikely(rtl8169_fragmented_frame(status
))) {
5058 dev
->stats
.rx_dropped
++;
5059 dev
->stats
.rx_length_errors
++;
5060 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5064 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
5065 tp
, pkt_size
, addr
);
5066 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5068 dev
->stats
.rx_dropped
++;
5072 rtl8169_rx_csum(skb
, status
);
5073 skb_put(skb
, pkt_size
);
5074 skb
->protocol
= eth_type_trans(skb
, dev
);
5076 rtl8169_rx_vlan_tag(desc
, skb
);
5078 napi_gro_receive(&tp
->napi
, skb
);
5080 dev
->stats
.rx_bytes
+= pkt_size
;
5081 dev
->stats
.rx_packets
++;
5084 /* Work around for AMD plateform. */
5085 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
5086 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
5092 count
= cur_rx
- tp
->cur_rx
;
5093 tp
->cur_rx
= cur_rx
;
5095 tp
->dirty_rx
+= count
;
5100 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
5102 struct net_device
*dev
= dev_instance
;
5103 struct rtl8169_private
*tp
= netdev_priv(dev
);
5104 void __iomem
*ioaddr
= tp
->mmio_addr
;
5108 /* loop handling interrupts until we have no new ones or
5109 * we hit a invalid/hotplug case.
5111 status
= RTL_R16(IntrStatus
);
5112 while (status
&& status
!= 0xffff) {
5115 /* Handle all of the error cases first. These will reset
5116 * the chip, so just exit the loop.
5118 if (unlikely(!netif_running(dev
))) {
5119 rtl8169_asic_down(ioaddr
);
5123 if (unlikely(status
& RxFIFOOver
)) {
5124 switch (tp
->mac_version
) {
5125 /* Work around for rx fifo overflow */
5126 case RTL_GIGA_MAC_VER_11
:
5127 case RTL_GIGA_MAC_VER_22
:
5128 case RTL_GIGA_MAC_VER_26
:
5129 netif_stop_queue(dev
);
5130 rtl8169_tx_timeout(dev
);
5132 /* Testers needed. */
5133 case RTL_GIGA_MAC_VER_17
:
5134 case RTL_GIGA_MAC_VER_19
:
5135 case RTL_GIGA_MAC_VER_20
:
5136 case RTL_GIGA_MAC_VER_21
:
5137 case RTL_GIGA_MAC_VER_23
:
5138 case RTL_GIGA_MAC_VER_24
:
5139 case RTL_GIGA_MAC_VER_27
:
5140 case RTL_GIGA_MAC_VER_28
:
5141 case RTL_GIGA_MAC_VER_31
:
5142 /* Experimental science. Pktgen proof. */
5143 case RTL_GIGA_MAC_VER_12
:
5144 case RTL_GIGA_MAC_VER_25
:
5145 if (status
== RxFIFOOver
)
5153 if (unlikely(status
& SYSErr
)) {
5154 rtl8169_pcierr_interrupt(dev
);
5158 if (status
& LinkChg
)
5159 __rtl8169_check_link_status(dev
, tp
, ioaddr
, true);
5161 /* We need to see the lastest version of tp->intr_mask to
5162 * avoid ignoring an MSI interrupt and having to wait for
5163 * another event which may never come.
5166 if (status
& tp
->intr_mask
& tp
->napi_event
) {
5167 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
5168 tp
->intr_mask
= ~tp
->napi_event
;
5170 if (likely(napi_schedule_prep(&tp
->napi
)))
5171 __napi_schedule(&tp
->napi
);
5173 netif_info(tp
, intr
, dev
,
5174 "interrupt %04x in poll\n", status
);
5177 /* We only get a new MSI interrupt when all active irq
5178 * sources on the chip have been acknowledged. So, ack
5179 * everything we've seen and check if new sources have become
5180 * active to avoid blocking all interrupts from the chip.
5183 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
5184 status
= RTL_R16(IntrStatus
);
5187 return IRQ_RETVAL(handled
);
5190 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5192 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5193 struct net_device
*dev
= tp
->dev
;
5194 void __iomem
*ioaddr
= tp
->mmio_addr
;
5197 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
5198 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
5200 if (work_done
< budget
) {
5201 napi_complete(napi
);
5203 /* We need for force the visibility of tp->intr_mask
5204 * for other CPUs, as we can loose an MSI interrupt
5205 * and potentially wait for a retransmit timeout if we don't.
5206 * The posted write to IntrMask is safe, as it will
5207 * eventually make it to the chip and we won't loose anything
5210 tp
->intr_mask
= 0xffff;
5212 RTL_W16(IntrMask
, tp
->intr_event
);
5218 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
5220 struct rtl8169_private
*tp
= netdev_priv(dev
);
5222 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5225 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
5226 RTL_W32(RxMissed
, 0);
5229 static void rtl8169_down(struct net_device
*dev
)
5231 struct rtl8169_private
*tp
= netdev_priv(dev
);
5232 void __iomem
*ioaddr
= tp
->mmio_addr
;
5234 del_timer_sync(&tp
->timer
);
5236 netif_stop_queue(dev
);
5238 napi_disable(&tp
->napi
);
5240 spin_lock_irq(&tp
->lock
);
5242 rtl8169_asic_down(ioaddr
);
5244 * At this point device interrupts can not be enabled in any function,
5245 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5246 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5248 rtl8169_rx_missed(dev
, ioaddr
);
5250 spin_unlock_irq(&tp
->lock
);
5252 synchronize_irq(dev
->irq
);
5254 /* Give a racing hard_start_xmit a few cycles to complete. */
5255 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5257 rtl8169_tx_clear(tp
);
5259 rtl8169_rx_clear(tp
);
5261 rtl_pll_power_down(tp
);
5264 static int rtl8169_close(struct net_device
*dev
)
5266 struct rtl8169_private
*tp
= netdev_priv(dev
);
5267 struct pci_dev
*pdev
= tp
->pci_dev
;
5269 pm_runtime_get_sync(&pdev
->dev
);
5271 /* Update counters before going down */
5272 rtl8169_update_counters(dev
);
5276 free_irq(dev
->irq
, dev
);
5278 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5280 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5282 tp
->TxDescArray
= NULL
;
5283 tp
->RxDescArray
= NULL
;
5285 pm_runtime_put_sync(&pdev
->dev
);
5290 static void rtl_set_rx_mode(struct net_device
*dev
)
5292 struct rtl8169_private
*tp
= netdev_priv(dev
);
5293 void __iomem
*ioaddr
= tp
->mmio_addr
;
5294 unsigned long flags
;
5295 u32 mc_filter
[2]; /* Multicast hash filter */
5299 if (dev
->flags
& IFF_PROMISC
) {
5300 /* Unconditionally log net taps. */
5301 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
5303 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
5305 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5306 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
5307 (dev
->flags
& IFF_ALLMULTI
)) {
5308 /* Too many to filter perfectly -- accept all multicasts. */
5309 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
5310 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
5312 struct netdev_hw_addr
*ha
;
5314 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
5315 mc_filter
[1] = mc_filter
[0] = 0;
5316 netdev_for_each_mc_addr(ha
, dev
) {
5317 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
5318 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
5319 rx_mode
|= AcceptMulticast
;
5323 spin_lock_irqsave(&tp
->lock
, flags
);
5325 tmp
= rtl8169_rx_config
| rx_mode
|
5326 (RTL_R32(RxConfig
) & RTL_RX_CONFIG_MASK
);
5328 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
5329 u32 data
= mc_filter
[0];
5331 mc_filter
[0] = swab32(mc_filter
[1]);
5332 mc_filter
[1] = swab32(data
);
5335 RTL_W32(MAR0
+ 4, mc_filter
[1]);
5336 RTL_W32(MAR0
+ 0, mc_filter
[0]);
5338 RTL_W32(RxConfig
, tmp
);
5340 spin_unlock_irqrestore(&tp
->lock
, flags
);
5344 * rtl8169_get_stats - Get rtl8169 read/write statistics
5345 * @dev: The Ethernet Device to get statistics for
5347 * Get TX/RX statistics for rtl8169
5349 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
5351 struct rtl8169_private
*tp
= netdev_priv(dev
);
5352 void __iomem
*ioaddr
= tp
->mmio_addr
;
5353 unsigned long flags
;
5355 if (netif_running(dev
)) {
5356 spin_lock_irqsave(&tp
->lock
, flags
);
5357 rtl8169_rx_missed(dev
, ioaddr
);
5358 spin_unlock_irqrestore(&tp
->lock
, flags
);
5364 static void rtl8169_net_suspend(struct net_device
*dev
)
5366 struct rtl8169_private
*tp
= netdev_priv(dev
);
5368 if (!netif_running(dev
))
5371 rtl_pll_power_down(tp
);
5373 netif_device_detach(dev
);
5374 netif_stop_queue(dev
);
5379 static int rtl8169_suspend(struct device
*device
)
5381 struct pci_dev
*pdev
= to_pci_dev(device
);
5382 struct net_device
*dev
= pci_get_drvdata(pdev
);
5384 rtl8169_net_suspend(dev
);
5389 static void __rtl8169_resume(struct net_device
*dev
)
5391 struct rtl8169_private
*tp
= netdev_priv(dev
);
5393 netif_device_attach(dev
);
5395 rtl_pll_power_up(tp
);
5397 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
5400 static int rtl8169_resume(struct device
*device
)
5402 struct pci_dev
*pdev
= to_pci_dev(device
);
5403 struct net_device
*dev
= pci_get_drvdata(pdev
);
5404 struct rtl8169_private
*tp
= netdev_priv(dev
);
5406 rtl8169_init_phy(dev
, tp
);
5408 if (netif_running(dev
))
5409 __rtl8169_resume(dev
);
5414 static int rtl8169_runtime_suspend(struct device
*device
)
5416 struct pci_dev
*pdev
= to_pci_dev(device
);
5417 struct net_device
*dev
= pci_get_drvdata(pdev
);
5418 struct rtl8169_private
*tp
= netdev_priv(dev
);
5420 if (!tp
->TxDescArray
)
5423 spin_lock_irq(&tp
->lock
);
5424 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
5425 __rtl8169_set_wol(tp
, WAKE_ANY
);
5426 spin_unlock_irq(&tp
->lock
);
5428 rtl8169_net_suspend(dev
);
5433 static int rtl8169_runtime_resume(struct device
*device
)
5435 struct pci_dev
*pdev
= to_pci_dev(device
);
5436 struct net_device
*dev
= pci_get_drvdata(pdev
);
5437 struct rtl8169_private
*tp
= netdev_priv(dev
);
5439 if (!tp
->TxDescArray
)
5442 spin_lock_irq(&tp
->lock
);
5443 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
5444 tp
->saved_wolopts
= 0;
5445 spin_unlock_irq(&tp
->lock
);
5447 rtl8169_init_phy(dev
, tp
);
5449 __rtl8169_resume(dev
);
5454 static int rtl8169_runtime_idle(struct device
*device
)
5456 struct pci_dev
*pdev
= to_pci_dev(device
);
5457 struct net_device
*dev
= pci_get_drvdata(pdev
);
5458 struct rtl8169_private
*tp
= netdev_priv(dev
);
5460 return tp
->TxDescArray
? -EBUSY
: 0;
5463 static const struct dev_pm_ops rtl8169_pm_ops
= {
5464 .suspend
= rtl8169_suspend
,
5465 .resume
= rtl8169_resume
,
5466 .freeze
= rtl8169_suspend
,
5467 .thaw
= rtl8169_resume
,
5468 .poweroff
= rtl8169_suspend
,
5469 .restore
= rtl8169_resume
,
5470 .runtime_suspend
= rtl8169_runtime_suspend
,
5471 .runtime_resume
= rtl8169_runtime_resume
,
5472 .runtime_idle
= rtl8169_runtime_idle
,
5475 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5477 #else /* !CONFIG_PM */
5479 #define RTL8169_PM_OPS NULL
5481 #endif /* !CONFIG_PM */
5483 static void rtl_shutdown(struct pci_dev
*pdev
)
5485 struct net_device
*dev
= pci_get_drvdata(pdev
);
5486 struct rtl8169_private
*tp
= netdev_priv(dev
);
5487 void __iomem
*ioaddr
= tp
->mmio_addr
;
5489 rtl8169_net_suspend(dev
);
5491 /* Restore original MAC address */
5492 rtl_rar_set(tp
, dev
->perm_addr
);
5494 spin_lock_irq(&tp
->lock
);
5496 rtl8169_asic_down(ioaddr
);
5498 spin_unlock_irq(&tp
->lock
);
5500 if (system_state
== SYSTEM_POWER_OFF
) {
5501 /* WoL fails with some 8168 when the receiver is disabled. */
5502 if (tp
->features
& RTL_FEATURE_WOL
) {
5503 pci_clear_master(pdev
);
5505 RTL_W8(ChipCmd
, CmdRxEnb
);
5510 pci_wake_from_d3(pdev
, true);
5511 pci_set_power_state(pdev
, PCI_D3hot
);
5515 static struct pci_driver rtl8169_pci_driver
= {
5517 .id_table
= rtl8169_pci_tbl
,
5518 .probe
= rtl8169_init_one
,
5519 .remove
= __devexit_p(rtl8169_remove_one
),
5520 .shutdown
= rtl_shutdown
,
5521 .driver
.pm
= RTL8169_PM_OPS
,
5524 static int __init
rtl8169_init_module(void)
5526 return pci_register_driver(&rtl8169_pci_driver
);
5529 static void __exit
rtl8169_cleanup_module(void)
5531 pci_unregister_driver(&rtl8169_pci_driver
);
5534 module_init(rtl8169_init_module
);
5535 module_exit(rtl8169_cleanup_module
);