2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
41 #include <linux/firmware.h>
42 #include <linux/platform_device.h>
44 #include "r100_reg_safe.h"
45 #include "rn50_reg_safe.h"
48 #define FIRMWARE_R100 "radeon/R100_cp.bin"
49 #define FIRMWARE_R200 "radeon/R200_cp.bin"
50 #define FIRMWARE_R300 "radeon/R300_cp.bin"
51 #define FIRMWARE_R420 "radeon/R420_cp.bin"
52 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
53 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
54 #define FIRMWARE_R520 "radeon/R520_cp.bin"
56 MODULE_FIRMWARE(FIRMWARE_R100
);
57 MODULE_FIRMWARE(FIRMWARE_R200
);
58 MODULE_FIRMWARE(FIRMWARE_R300
);
59 MODULE_FIRMWARE(FIRMWARE_R420
);
60 MODULE_FIRMWARE(FIRMWARE_RS690
);
61 MODULE_FIRMWARE(FIRMWARE_RS600
);
62 MODULE_FIRMWARE(FIRMWARE_R520
);
64 #include "r100_track.h"
66 /* This files gather functions specifics to:
67 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
70 bool r100_gui_idle(struct radeon_device
*rdev
)
72 if (RREG32(RADEON_RBBM_STATUS
) & RADEON_RBBM_ACTIVE
)
78 /* hpd for digital panel detect/disconnect */
79 bool r100_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
)
81 bool connected
= false;
85 if (RREG32(RADEON_FP_GEN_CNTL
) & RADEON_FP_DETECT_SENSE
)
89 if (RREG32(RADEON_FP2_GEN_CNTL
) & RADEON_FP2_DETECT_SENSE
)
98 void r100_hpd_set_polarity(struct radeon_device
*rdev
,
99 enum radeon_hpd_id hpd
)
102 bool connected
= r100_hpd_sense(rdev
, hpd
);
106 tmp
= RREG32(RADEON_FP_GEN_CNTL
);
108 tmp
&= ~RADEON_FP_DETECT_INT_POL
;
110 tmp
|= RADEON_FP_DETECT_INT_POL
;
111 WREG32(RADEON_FP_GEN_CNTL
, tmp
);
114 tmp
= RREG32(RADEON_FP2_GEN_CNTL
);
116 tmp
&= ~RADEON_FP2_DETECT_INT_POL
;
118 tmp
|= RADEON_FP2_DETECT_INT_POL
;
119 WREG32(RADEON_FP2_GEN_CNTL
, tmp
);
126 void r100_hpd_init(struct radeon_device
*rdev
)
128 struct drm_device
*dev
= rdev
->ddev
;
129 struct drm_connector
*connector
;
131 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
132 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
133 switch (radeon_connector
->hpd
.hpd
) {
135 rdev
->irq
.hpd
[0] = true;
138 rdev
->irq
.hpd
[1] = true;
144 if (rdev
->irq
.installed
)
148 void r100_hpd_fini(struct radeon_device
*rdev
)
150 struct drm_device
*dev
= rdev
->ddev
;
151 struct drm_connector
*connector
;
153 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
154 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
155 switch (radeon_connector
->hpd
.hpd
) {
157 rdev
->irq
.hpd
[0] = false;
160 rdev
->irq
.hpd
[1] = false;
171 void r100_pci_gart_tlb_flush(struct radeon_device
*rdev
)
173 /* TODO: can we do somethings here ? */
174 /* It seems hw only cache one entry so we should discard this
175 * entry otherwise if first GPU GART read hit this entry it
176 * could end up in wrong address. */
179 int r100_pci_gart_init(struct radeon_device
*rdev
)
183 if (rdev
->gart
.table
.ram
.ptr
) {
184 WARN(1, "R100 PCI GART already initialized.\n");
187 /* Initialize common gart structure */
188 r
= radeon_gart_init(rdev
);
191 rdev
->gart
.table_size
= rdev
->gart
.num_gpu_pages
* 4;
192 rdev
->asic
->gart_tlb_flush
= &r100_pci_gart_tlb_flush
;
193 rdev
->asic
->gart_set_page
= &r100_pci_gart_set_page
;
194 return radeon_gart_table_ram_alloc(rdev
);
197 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
198 void r100_enable_bm(struct radeon_device
*rdev
)
201 /* Enable bus mastering */
202 tmp
= RREG32(RADEON_BUS_CNTL
) & ~RADEON_BUS_MASTER_DIS
;
203 WREG32(RADEON_BUS_CNTL
, tmp
);
206 int r100_pci_gart_enable(struct radeon_device
*rdev
)
210 radeon_gart_restore(rdev
);
211 /* discard memory request outside of configured range */
212 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS
;
213 WREG32(RADEON_AIC_CNTL
, tmp
);
214 /* set address range for PCI address translate */
215 WREG32(RADEON_AIC_LO_ADDR
, rdev
->mc
.gtt_start
);
216 WREG32(RADEON_AIC_HI_ADDR
, rdev
->mc
.gtt_end
);
217 /* set PCI GART page-table base address */
218 WREG32(RADEON_AIC_PT_BASE
, rdev
->gart
.table_addr
);
219 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_PCIGART_TRANSLATE_EN
;
220 WREG32(RADEON_AIC_CNTL
, tmp
);
221 r100_pci_gart_tlb_flush(rdev
);
222 rdev
->gart
.ready
= true;
226 void r100_pci_gart_disable(struct radeon_device
*rdev
)
230 /* discard memory request outside of configured range */
231 tmp
= RREG32(RADEON_AIC_CNTL
) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS
;
232 WREG32(RADEON_AIC_CNTL
, tmp
& ~RADEON_PCIGART_TRANSLATE_EN
);
233 WREG32(RADEON_AIC_LO_ADDR
, 0);
234 WREG32(RADEON_AIC_HI_ADDR
, 0);
237 int r100_pci_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
)
239 if (i
< 0 || i
> rdev
->gart
.num_gpu_pages
) {
242 rdev
->gart
.table
.ram
.ptr
[i
] = cpu_to_le32(lower_32_bits(addr
));
246 void r100_pci_gart_fini(struct radeon_device
*rdev
)
248 radeon_gart_fini(rdev
);
249 r100_pci_gart_disable(rdev
);
250 radeon_gart_table_ram_free(rdev
);
253 int r100_irq_set(struct radeon_device
*rdev
)
257 if (!rdev
->irq
.installed
) {
258 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
259 WREG32(R_000040_GEN_INT_CNTL
, 0);
262 if (rdev
->irq
.sw_int
) {
263 tmp
|= RADEON_SW_INT_ENABLE
;
265 if (rdev
->irq
.gui_idle
) {
266 tmp
|= RADEON_GUI_IDLE_MASK
;
268 if (rdev
->irq
.crtc_vblank_int
[0]) {
269 tmp
|= RADEON_CRTC_VBLANK_MASK
;
271 if (rdev
->irq
.crtc_vblank_int
[1]) {
272 tmp
|= RADEON_CRTC2_VBLANK_MASK
;
274 if (rdev
->irq
.hpd
[0]) {
275 tmp
|= RADEON_FP_DETECT_MASK
;
277 if (rdev
->irq
.hpd
[1]) {
278 tmp
|= RADEON_FP2_DETECT_MASK
;
280 WREG32(RADEON_GEN_INT_CNTL
, tmp
);
284 void r100_irq_disable(struct radeon_device
*rdev
)
288 WREG32(R_000040_GEN_INT_CNTL
, 0);
289 /* Wait and acknowledge irq */
291 tmp
= RREG32(R_000044_GEN_INT_STATUS
);
292 WREG32(R_000044_GEN_INT_STATUS
, tmp
);
295 static inline uint32_t r100_irq_ack(struct radeon_device
*rdev
)
297 uint32_t irqs
= RREG32(RADEON_GEN_INT_STATUS
);
298 uint32_t irq_mask
= RADEON_SW_INT_TEST
|
299 RADEON_CRTC_VBLANK_STAT
| RADEON_CRTC2_VBLANK_STAT
|
300 RADEON_FP_DETECT_STAT
| RADEON_FP2_DETECT_STAT
;
302 /* the interrupt works, but the status bit is permanently asserted */
303 if (rdev
->irq
.gui_idle
&& radeon_gui_idle(rdev
)) {
304 if (!rdev
->irq
.gui_idle_acked
)
305 irq_mask
|= RADEON_GUI_IDLE_STAT
;
309 WREG32(RADEON_GEN_INT_STATUS
, irqs
);
311 return irqs
& irq_mask
;
314 int r100_irq_process(struct radeon_device
*rdev
)
316 uint32_t status
, msi_rearm
;
317 bool queue_hotplug
= false;
319 /* reset gui idle ack. the status bit is broken */
320 rdev
->irq
.gui_idle_acked
= false;
322 status
= r100_irq_ack(rdev
);
326 if (rdev
->shutdown
) {
331 if (status
& RADEON_SW_INT_TEST
) {
332 radeon_fence_process(rdev
);
334 /* gui idle interrupt */
335 if (status
& RADEON_GUI_IDLE_STAT
) {
336 rdev
->irq
.gui_idle_acked
= true;
337 rdev
->pm
.gui_idle
= true;
338 wake_up(&rdev
->irq
.idle_queue
);
340 /* Vertical blank interrupts */
341 if (status
& RADEON_CRTC_VBLANK_STAT
) {
342 drm_handle_vblank(rdev
->ddev
, 0);
343 rdev
->pm
.vblank_sync
= true;
344 wake_up(&rdev
->irq
.vblank_queue
);
346 if (status
& RADEON_CRTC2_VBLANK_STAT
) {
347 drm_handle_vblank(rdev
->ddev
, 1);
348 rdev
->pm
.vblank_sync
= true;
349 wake_up(&rdev
->irq
.vblank_queue
);
351 if (status
& RADEON_FP_DETECT_STAT
) {
352 queue_hotplug
= true;
355 if (status
& RADEON_FP2_DETECT_STAT
) {
356 queue_hotplug
= true;
359 status
= r100_irq_ack(rdev
);
361 /* reset gui idle ack. the status bit is broken */
362 rdev
->irq
.gui_idle_acked
= false;
364 queue_work(rdev
->wq
, &rdev
->hotplug_work
);
365 if (rdev
->msi_enabled
) {
366 switch (rdev
->family
) {
369 msi_rearm
= RREG32(RADEON_AIC_CNTL
) & ~RS400_MSI_REARM
;
370 WREG32(RADEON_AIC_CNTL
, msi_rearm
);
371 WREG32(RADEON_AIC_CNTL
, msi_rearm
| RS400_MSI_REARM
);
374 msi_rearm
= RREG32(RADEON_MSI_REARM_EN
) & ~RV370_MSI_REARM_EN
;
375 WREG32(RADEON_MSI_REARM_EN
, msi_rearm
);
376 WREG32(RADEON_MSI_REARM_EN
, msi_rearm
| RV370_MSI_REARM_EN
);
383 u32
r100_get_vblank_counter(struct radeon_device
*rdev
, int crtc
)
386 return RREG32(RADEON_CRTC_CRNT_FRAME
);
388 return RREG32(RADEON_CRTC2_CRNT_FRAME
);
391 /* Who ever call radeon_fence_emit should call ring_lock and ask
392 * for enough space (today caller are ib schedule and buffer move) */
393 void r100_fence_ring_emit(struct radeon_device
*rdev
,
394 struct radeon_fence
*fence
)
396 /* We have to make sure that caches are flushed before
397 * CPU might read something from VRAM. */
398 radeon_ring_write(rdev
, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT
, 0));
399 radeon_ring_write(rdev
, RADEON_RB3D_DC_FLUSH_ALL
);
400 radeon_ring_write(rdev
, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT
, 0));
401 radeon_ring_write(rdev
, RADEON_RB3D_ZC_FLUSH_ALL
);
402 /* Wait until IDLE & CLEAN */
403 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
404 radeon_ring_write(rdev
, RADEON_WAIT_2D_IDLECLEAN
| RADEON_WAIT_3D_IDLECLEAN
);
405 radeon_ring_write(rdev
, PACKET0(RADEON_HOST_PATH_CNTL
, 0));
406 radeon_ring_write(rdev
, rdev
->config
.r100
.hdp_cntl
|
407 RADEON_HDP_READ_BUFFER_INVALIDATE
);
408 radeon_ring_write(rdev
, PACKET0(RADEON_HOST_PATH_CNTL
, 0));
409 radeon_ring_write(rdev
, rdev
->config
.r100
.hdp_cntl
);
410 /* Emit fence sequence & fire IRQ */
411 radeon_ring_write(rdev
, PACKET0(rdev
->fence_drv
.scratch_reg
, 0));
412 radeon_ring_write(rdev
, fence
->seq
);
413 radeon_ring_write(rdev
, PACKET0(RADEON_GEN_INT_STATUS
, 0));
414 radeon_ring_write(rdev
, RADEON_SW_INT_FIRE
);
417 int r100_wb_init(struct radeon_device
*rdev
)
421 if (rdev
->wb
.wb_obj
== NULL
) {
422 r
= radeon_bo_create(rdev
, NULL
, RADEON_GPU_PAGE_SIZE
, true,
423 RADEON_GEM_DOMAIN_GTT
,
426 dev_err(rdev
->dev
, "(%d) create WB buffer failed\n", r
);
429 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
430 if (unlikely(r
!= 0))
432 r
= radeon_bo_pin(rdev
->wb
.wb_obj
, RADEON_GEM_DOMAIN_GTT
,
435 dev_err(rdev
->dev
, "(%d) pin WB buffer failed\n", r
);
436 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
439 r
= radeon_bo_kmap(rdev
->wb
.wb_obj
, (void **)&rdev
->wb
.wb
);
440 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
442 dev_err(rdev
->dev
, "(%d) map WB buffer failed\n", r
);
446 WREG32(R_000774_SCRATCH_ADDR
, rdev
->wb
.gpu_addr
);
447 WREG32(R_00070C_CP_RB_RPTR_ADDR
,
448 S_00070C_RB_RPTR_ADDR((rdev
->wb
.gpu_addr
+ 1024) >> 2));
449 WREG32(R_000770_SCRATCH_UMSK
, 0xff);
453 void r100_wb_disable(struct radeon_device
*rdev
)
455 WREG32(R_000770_SCRATCH_UMSK
, 0);
458 void r100_wb_fini(struct radeon_device
*rdev
)
462 r100_wb_disable(rdev
);
463 if (rdev
->wb
.wb_obj
) {
464 r
= radeon_bo_reserve(rdev
->wb
.wb_obj
, false);
465 if (unlikely(r
!= 0)) {
466 dev_err(rdev
->dev
, "(%d) can't finish WB\n", r
);
469 radeon_bo_kunmap(rdev
->wb
.wb_obj
);
470 radeon_bo_unpin(rdev
->wb
.wb_obj
);
471 radeon_bo_unreserve(rdev
->wb
.wb_obj
);
472 radeon_bo_unref(&rdev
->wb
.wb_obj
);
474 rdev
->wb
.wb_obj
= NULL
;
478 int r100_copy_blit(struct radeon_device
*rdev
,
482 struct radeon_fence
*fence
)
485 uint32_t stride_bytes
= PAGE_SIZE
;
487 uint32_t stride_pixels
;
492 /* radeon limited to 16k stride */
493 stride_bytes
&= 0x3fff;
494 /* radeon pitch is /64 */
495 pitch
= stride_bytes
/ 64;
496 stride_pixels
= stride_bytes
/ 4;
497 num_loops
= DIV_ROUND_UP(num_pages
, 8191);
499 /* Ask for enough room for blit + flush + fence */
500 ndw
= 64 + (10 * num_loops
);
501 r
= radeon_ring_lock(rdev
, ndw
);
503 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r
, ndw
);
506 while (num_pages
> 0) {
507 cur_pages
= num_pages
;
508 if (cur_pages
> 8191) {
511 num_pages
-= cur_pages
;
513 /* pages are in Y direction - height
514 page width in X direction - width */
515 radeon_ring_write(rdev
, PACKET3(PACKET3_BITBLT_MULTI
, 8));
516 radeon_ring_write(rdev
,
517 RADEON_GMC_SRC_PITCH_OFFSET_CNTL
|
518 RADEON_GMC_DST_PITCH_OFFSET_CNTL
|
519 RADEON_GMC_SRC_CLIPPING
|
520 RADEON_GMC_DST_CLIPPING
|
521 RADEON_GMC_BRUSH_NONE
|
522 (RADEON_COLOR_FORMAT_ARGB8888
<< 8) |
523 RADEON_GMC_SRC_DATATYPE_COLOR
|
525 RADEON_DP_SRC_SOURCE_MEMORY
|
526 RADEON_GMC_CLR_CMP_CNTL_DIS
|
527 RADEON_GMC_WR_MSK_DIS
);
528 radeon_ring_write(rdev
, (pitch
<< 22) | (src_offset
>> 10));
529 radeon_ring_write(rdev
, (pitch
<< 22) | (dst_offset
>> 10));
530 radeon_ring_write(rdev
, (0x1fff) | (0x1fff << 16));
531 radeon_ring_write(rdev
, 0);
532 radeon_ring_write(rdev
, (0x1fff) | (0x1fff << 16));
533 radeon_ring_write(rdev
, num_pages
);
534 radeon_ring_write(rdev
, num_pages
);
535 radeon_ring_write(rdev
, cur_pages
| (stride_pixels
<< 16));
537 radeon_ring_write(rdev
, PACKET0(RADEON_DSTCACHE_CTLSTAT
, 0));
538 radeon_ring_write(rdev
, RADEON_RB2D_DC_FLUSH_ALL
);
539 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
540 radeon_ring_write(rdev
,
541 RADEON_WAIT_2D_IDLECLEAN
|
542 RADEON_WAIT_HOST_IDLECLEAN
|
543 RADEON_WAIT_DMA_GUI_IDLE
);
545 r
= radeon_fence_emit(rdev
, fence
);
547 radeon_ring_unlock_commit(rdev
);
551 static int r100_cp_wait_for_idle(struct radeon_device
*rdev
)
556 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
557 tmp
= RREG32(R_000E40_RBBM_STATUS
);
558 if (!G_000E40_CP_CMDSTRM_BUSY(tmp
)) {
566 void r100_ring_start(struct radeon_device
*rdev
)
570 r
= radeon_ring_lock(rdev
, 2);
574 radeon_ring_write(rdev
, PACKET0(RADEON_ISYNC_CNTL
, 0));
575 radeon_ring_write(rdev
,
576 RADEON_ISYNC_ANY2D_IDLE3D
|
577 RADEON_ISYNC_ANY3D_IDLE2D
|
578 RADEON_ISYNC_WAIT_IDLEGUI
|
579 RADEON_ISYNC_CPSCRATCH_IDLEGUI
);
580 radeon_ring_unlock_commit(rdev
);
584 /* Load the microcode for the CP */
585 static int r100_cp_init_microcode(struct radeon_device
*rdev
)
587 struct platform_device
*pdev
;
588 const char *fw_name
= NULL
;
593 pdev
= platform_device_register_simple("radeon_cp", 0, NULL
, 0);
596 printk(KERN_ERR
"radeon_cp: Failed to register firmware\n");
599 if ((rdev
->family
== CHIP_R100
) || (rdev
->family
== CHIP_RV100
) ||
600 (rdev
->family
== CHIP_RV200
) || (rdev
->family
== CHIP_RS100
) ||
601 (rdev
->family
== CHIP_RS200
)) {
602 DRM_INFO("Loading R100 Microcode\n");
603 fw_name
= FIRMWARE_R100
;
604 } else if ((rdev
->family
== CHIP_R200
) ||
605 (rdev
->family
== CHIP_RV250
) ||
606 (rdev
->family
== CHIP_RV280
) ||
607 (rdev
->family
== CHIP_RS300
)) {
608 DRM_INFO("Loading R200 Microcode\n");
609 fw_name
= FIRMWARE_R200
;
610 } else if ((rdev
->family
== CHIP_R300
) ||
611 (rdev
->family
== CHIP_R350
) ||
612 (rdev
->family
== CHIP_RV350
) ||
613 (rdev
->family
== CHIP_RV380
) ||
614 (rdev
->family
== CHIP_RS400
) ||
615 (rdev
->family
== CHIP_RS480
)) {
616 DRM_INFO("Loading R300 Microcode\n");
617 fw_name
= FIRMWARE_R300
;
618 } else if ((rdev
->family
== CHIP_R420
) ||
619 (rdev
->family
== CHIP_R423
) ||
620 (rdev
->family
== CHIP_RV410
)) {
621 DRM_INFO("Loading R400 Microcode\n");
622 fw_name
= FIRMWARE_R420
;
623 } else if ((rdev
->family
== CHIP_RS690
) ||
624 (rdev
->family
== CHIP_RS740
)) {
625 DRM_INFO("Loading RS690/RS740 Microcode\n");
626 fw_name
= FIRMWARE_RS690
;
627 } else if (rdev
->family
== CHIP_RS600
) {
628 DRM_INFO("Loading RS600 Microcode\n");
629 fw_name
= FIRMWARE_RS600
;
630 } else if ((rdev
->family
== CHIP_RV515
) ||
631 (rdev
->family
== CHIP_R520
) ||
632 (rdev
->family
== CHIP_RV530
) ||
633 (rdev
->family
== CHIP_R580
) ||
634 (rdev
->family
== CHIP_RV560
) ||
635 (rdev
->family
== CHIP_RV570
)) {
636 DRM_INFO("Loading R500 Microcode\n");
637 fw_name
= FIRMWARE_R520
;
640 err
= request_firmware(&rdev
->me_fw
, fw_name
, &pdev
->dev
);
641 platform_device_unregister(pdev
);
643 printk(KERN_ERR
"radeon_cp: Failed to load firmware \"%s\"\n",
645 } else if (rdev
->me_fw
->size
% 8) {
647 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
648 rdev
->me_fw
->size
, fw_name
);
650 release_firmware(rdev
->me_fw
);
656 static void r100_cp_load_microcode(struct radeon_device
*rdev
)
658 const __be32
*fw_data
;
661 if (r100_gui_wait_for_idle(rdev
)) {
662 printk(KERN_WARNING
"Failed to wait GUI idle while "
663 "programming pipes. Bad things might happen.\n");
667 size
= rdev
->me_fw
->size
/ 4;
668 fw_data
= (const __be32
*)&rdev
->me_fw
->data
[0];
669 WREG32(RADEON_CP_ME_RAM_ADDR
, 0);
670 for (i
= 0; i
< size
; i
+= 2) {
671 WREG32(RADEON_CP_ME_RAM_DATAH
,
672 be32_to_cpup(&fw_data
[i
]));
673 WREG32(RADEON_CP_ME_RAM_DATAL
,
674 be32_to_cpup(&fw_data
[i
+ 1]));
679 int r100_cp_init(struct radeon_device
*rdev
, unsigned ring_size
)
684 unsigned pre_write_timer
;
685 unsigned pre_write_limit
;
686 unsigned indirect2_start
;
687 unsigned indirect1_start
;
691 if (r100_debugfs_cp_init(rdev
)) {
692 DRM_ERROR("Failed to register debugfs file for CP !\n");
695 r
= r100_cp_init_microcode(rdev
);
697 DRM_ERROR("Failed to load firmware!\n");
702 /* Align ring size */
703 rb_bufsz
= drm_order(ring_size
/ 8);
704 ring_size
= (1 << (rb_bufsz
+ 1)) * 4;
705 r100_cp_load_microcode(rdev
);
706 r
= radeon_ring_init(rdev
, ring_size
);
710 /* Each time the cp read 1024 bytes (16 dword/quadword) update
711 * the rptr copy in system ram */
713 /* cp will read 128bytes at a time (4 dwords) */
715 rdev
->cp
.align_mask
= 16 - 1;
716 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
717 pre_write_timer
= 64;
718 /* Force CP_RB_WPTR write if written more than one time before the
722 /* Setup the cp cache like this (cache size is 96 dwords) :
726 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
727 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
728 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
729 * Idea being that most of the gpu cmd will be through indirect1 buffer
730 * so it gets the bigger cache.
732 indirect2_start
= 80;
733 indirect1_start
= 16;
735 WREG32(0x718, pre_write_timer
| (pre_write_limit
<< 28));
736 tmp
= (REG_SET(RADEON_RB_BUFSZ
, rb_bufsz
) |
737 REG_SET(RADEON_RB_BLKSZ
, rb_blksz
) |
738 REG_SET(RADEON_MAX_FETCH
, max_fetch
) |
739 RADEON_RB_NO_UPDATE
);
741 tmp
|= RADEON_BUF_SWAP_32BIT
;
743 WREG32(RADEON_CP_RB_CNTL
, tmp
);
745 /* Set ring address */
746 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev
->cp
.gpu_addr
);
747 WREG32(RADEON_CP_RB_BASE
, rdev
->cp
.gpu_addr
);
748 /* Force read & write ptr to 0 */
749 WREG32(RADEON_CP_RB_CNTL
, tmp
| RADEON_RB_RPTR_WR_ENA
);
750 WREG32(RADEON_CP_RB_RPTR_WR
, 0);
751 WREG32(RADEON_CP_RB_WPTR
, 0);
752 WREG32(RADEON_CP_RB_CNTL
, tmp
);
754 rdev
->cp
.rptr
= RREG32(RADEON_CP_RB_RPTR
);
755 rdev
->cp
.wptr
= RREG32(RADEON_CP_RB_WPTR
);
756 /* protect against crazy HW on resume */
757 rdev
->cp
.wptr
&= rdev
->cp
.ptr_mask
;
758 /* Set cp mode to bus mastering & enable cp*/
759 WREG32(RADEON_CP_CSQ_MODE
,
760 REG_SET(RADEON_INDIRECT2_START
, indirect2_start
) |
761 REG_SET(RADEON_INDIRECT1_START
, indirect1_start
));
763 WREG32(0x744, 0x00004D4D);
764 WREG32(RADEON_CP_CSQ_CNTL
, RADEON_CSQ_PRIBM_INDBM
);
765 radeon_ring_start(rdev
);
766 r
= radeon_ring_test(rdev
);
768 DRM_ERROR("radeon: cp isn't working (%d).\n", r
);
771 rdev
->cp
.ready
= true;
775 void r100_cp_fini(struct radeon_device
*rdev
)
777 if (r100_cp_wait_for_idle(rdev
)) {
778 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
781 r100_cp_disable(rdev
);
782 radeon_ring_fini(rdev
);
783 DRM_INFO("radeon: cp finalized\n");
786 void r100_cp_disable(struct radeon_device
*rdev
)
789 rdev
->cp
.ready
= false;
790 WREG32(RADEON_CP_CSQ_MODE
, 0);
791 WREG32(RADEON_CP_CSQ_CNTL
, 0);
792 if (r100_gui_wait_for_idle(rdev
)) {
793 printk(KERN_WARNING
"Failed to wait GUI idle while "
794 "programming pipes. Bad things might happen.\n");
798 void r100_cp_commit(struct radeon_device
*rdev
)
800 WREG32(RADEON_CP_RB_WPTR
, rdev
->cp
.wptr
);
801 (void)RREG32(RADEON_CP_RB_WPTR
);
808 int r100_cs_parse_packet0(struct radeon_cs_parser
*p
,
809 struct radeon_cs_packet
*pkt
,
810 const unsigned *auth
, unsigned n
,
811 radeon_packet0_check_t check
)
820 /* Check that register fall into register range
821 * determined by the number of entry (n) in the
822 * safe register bitmap.
824 if (pkt
->one_reg_wr
) {
825 if ((reg
>> 7) > n
) {
829 if (((reg
+ (pkt
->count
<< 2)) >> 7) > n
) {
833 for (i
= 0; i
<= pkt
->count
; i
++, idx
++) {
835 m
= 1 << ((reg
>> 2) & 31);
837 r
= check(p
, pkt
, idx
, reg
);
842 if (pkt
->one_reg_wr
) {
843 if (!(auth
[j
] & m
)) {
853 void r100_cs_dump_packet(struct radeon_cs_parser
*p
,
854 struct radeon_cs_packet
*pkt
)
856 volatile uint32_t *ib
;
862 for (i
= 0; i
<= (pkt
->count
+ 1); i
++, idx
++) {
863 DRM_INFO("ib[%d]=0x%08X\n", idx
, ib
[idx
]);
868 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
869 * @parser: parser structure holding parsing context.
870 * @pkt: where to store packet informations
872 * Assume that chunk_ib_index is properly set. Will return -EINVAL
873 * if packet is bigger than remaining ib size. or if packets is unknown.
875 int r100_cs_packet_parse(struct radeon_cs_parser
*p
,
876 struct radeon_cs_packet
*pkt
,
879 struct radeon_cs_chunk
*ib_chunk
= &p
->chunks
[p
->chunk_ib_idx
];
882 if (idx
>= ib_chunk
->length_dw
) {
883 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
884 idx
, ib_chunk
->length_dw
);
887 header
= radeon_get_ib_value(p
, idx
);
889 pkt
->type
= CP_PACKET_GET_TYPE(header
);
890 pkt
->count
= CP_PACKET_GET_COUNT(header
);
893 pkt
->reg
= CP_PACKET0_GET_REG(header
);
894 pkt
->one_reg_wr
= CP_PACKET0_GET_ONE_REG_WR(header
);
897 pkt
->opcode
= CP_PACKET3_GET_OPCODE(header
);
903 DRM_ERROR("Unknown packet type %d at %d !\n", pkt
->type
, idx
);
906 if ((pkt
->count
+ 1 + pkt
->idx
) >= ib_chunk
->length_dw
) {
907 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
908 pkt
->idx
, pkt
->type
, pkt
->count
, ib_chunk
->length_dw
);
915 * r100_cs_packet_next_vline() - parse userspace VLINE packet
916 * @parser: parser structure holding parsing context.
918 * Userspace sends a special sequence for VLINE waits.
919 * PACKET0 - VLINE_START_END + value
920 * PACKET0 - WAIT_UNTIL +_value
921 * RELOC (P3) - crtc_id in reloc.
923 * This function parses this and relocates the VLINE START END
924 * and WAIT UNTIL packets to the correct crtc.
925 * It also detects a switched off crtc and nulls out the
928 int r100_cs_packet_parse_vline(struct radeon_cs_parser
*p
)
930 struct drm_mode_object
*obj
;
931 struct drm_crtc
*crtc
;
932 struct radeon_crtc
*radeon_crtc
;
933 struct radeon_cs_packet p3reloc
, waitreloc
;
936 uint32_t header
, h_idx
, reg
;
937 volatile uint32_t *ib
;
941 /* parse the wait until */
942 r
= r100_cs_packet_parse(p
, &waitreloc
, p
->idx
);
946 /* check its a wait until and only 1 count */
947 if (waitreloc
.reg
!= RADEON_WAIT_UNTIL
||
948 waitreloc
.count
!= 0) {
949 DRM_ERROR("vline wait had illegal wait until segment\n");
954 if (radeon_get_ib_value(p
, waitreloc
.idx
+ 1) != RADEON_WAIT_CRTC_VLINE
) {
955 DRM_ERROR("vline wait had illegal wait until\n");
960 /* jump over the NOP */
961 r
= r100_cs_packet_parse(p
, &p3reloc
, p
->idx
+ waitreloc
.count
+ 2);
966 p
->idx
+= waitreloc
.count
+ 2;
967 p
->idx
+= p3reloc
.count
+ 2;
969 header
= radeon_get_ib_value(p
, h_idx
);
970 crtc_id
= radeon_get_ib_value(p
, h_idx
+ 5);
971 reg
= CP_PACKET0_GET_REG(header
);
972 mutex_lock(&p
->rdev
->ddev
->mode_config
.mutex
);
973 obj
= drm_mode_object_find(p
->rdev
->ddev
, crtc_id
, DRM_MODE_OBJECT_CRTC
);
975 DRM_ERROR("cannot find crtc %d\n", crtc_id
);
979 crtc
= obj_to_crtc(obj
);
980 radeon_crtc
= to_radeon_crtc(crtc
);
981 crtc_id
= radeon_crtc
->crtc_id
;
983 if (!crtc
->enabled
) {
984 /* if the CRTC isn't enabled - we need to nop out the wait until */
985 ib
[h_idx
+ 2] = PACKET2(0);
986 ib
[h_idx
+ 3] = PACKET2(0);
987 } else if (crtc_id
== 1) {
989 case AVIVO_D1MODE_VLINE_START_END
:
990 header
&= ~R300_CP_PACKET0_REG_MASK
;
991 header
|= AVIVO_D2MODE_VLINE_START_END
>> 2;
993 case RADEON_CRTC_GUI_TRIG_VLINE
:
994 header
&= ~R300_CP_PACKET0_REG_MASK
;
995 header
|= RADEON_CRTC2_GUI_TRIG_VLINE
>> 2;
998 DRM_ERROR("unknown crtc reloc\n");
1003 ib
[h_idx
+ 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1
;
1006 mutex_unlock(&p
->rdev
->ddev
->mode_config
.mutex
);
1011 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1012 * @parser: parser structure holding parsing context.
1013 * @data: pointer to relocation data
1014 * @offset_start: starting offset
1015 * @offset_mask: offset mask (to align start offset on)
1016 * @reloc: reloc informations
1018 * Check next packet is relocation packet3, do bo validation and compute
1019 * GPU offset using the provided start.
1021 int r100_cs_packet_next_reloc(struct radeon_cs_parser
*p
,
1022 struct radeon_cs_reloc
**cs_reloc
)
1024 struct radeon_cs_chunk
*relocs_chunk
;
1025 struct radeon_cs_packet p3reloc
;
1029 if (p
->chunk_relocs_idx
== -1) {
1030 DRM_ERROR("No relocation chunk !\n");
1034 relocs_chunk
= &p
->chunks
[p
->chunk_relocs_idx
];
1035 r
= r100_cs_packet_parse(p
, &p3reloc
, p
->idx
);
1039 p
->idx
+= p3reloc
.count
+ 2;
1040 if (p3reloc
.type
!= PACKET_TYPE3
|| p3reloc
.opcode
!= PACKET3_NOP
) {
1041 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1043 r100_cs_dump_packet(p
, &p3reloc
);
1046 idx
= radeon_get_ib_value(p
, p3reloc
.idx
+ 1);
1047 if (idx
>= relocs_chunk
->length_dw
) {
1048 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1049 idx
, relocs_chunk
->length_dw
);
1050 r100_cs_dump_packet(p
, &p3reloc
);
1053 /* FIXME: we assume reloc size is 4 dwords */
1054 *cs_reloc
= p
->relocs_ptr
[(idx
/ 4)];
1058 static int r100_get_vtx_size(uint32_t vtx_fmt
)
1062 /* ordered according to bits in spec */
1063 if (vtx_fmt
& RADEON_SE_VTX_FMT_W0
)
1065 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPCOLOR
)
1067 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPALPHA
)
1069 if (vtx_fmt
& RADEON_SE_VTX_FMT_PKCOLOR
)
1071 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPSPEC
)
1073 if (vtx_fmt
& RADEON_SE_VTX_FMT_FPFOG
)
1075 if (vtx_fmt
& RADEON_SE_VTX_FMT_PKSPEC
)
1077 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST0
)
1079 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST1
)
1081 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q1
)
1083 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST2
)
1085 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q2
)
1087 if (vtx_fmt
& RADEON_SE_VTX_FMT_ST3
)
1089 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q3
)
1091 if (vtx_fmt
& RADEON_SE_VTX_FMT_Q0
)
1094 if (vtx_fmt
& (0x7 << 15))
1095 vtx_size
+= (vtx_fmt
>> 15) & 0x7;
1096 if (vtx_fmt
& RADEON_SE_VTX_FMT_N0
)
1098 if (vtx_fmt
& RADEON_SE_VTX_FMT_XY1
)
1100 if (vtx_fmt
& RADEON_SE_VTX_FMT_Z1
)
1102 if (vtx_fmt
& RADEON_SE_VTX_FMT_W1
)
1104 if (vtx_fmt
& RADEON_SE_VTX_FMT_N1
)
1106 if (vtx_fmt
& RADEON_SE_VTX_FMT_Z
)
1111 static int r100_packet0_check(struct radeon_cs_parser
*p
,
1112 struct radeon_cs_packet
*pkt
,
1113 unsigned idx
, unsigned reg
)
1115 struct radeon_cs_reloc
*reloc
;
1116 struct r100_cs_track
*track
;
1117 volatile uint32_t *ib
;
1125 track
= (struct r100_cs_track
*)p
->track
;
1127 idx_value
= radeon_get_ib_value(p
, idx
);
1130 case RADEON_CRTC_GUI_TRIG_VLINE
:
1131 r
= r100_cs_packet_parse_vline(p
);
1133 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1135 r100_cs_dump_packet(p
, pkt
);
1139 /* FIXME: only allow PACKET3 blit? easier to check for out of
1141 case RADEON_DST_PITCH_OFFSET
:
1142 case RADEON_SRC_PITCH_OFFSET
:
1143 r
= r100_reloc_pitch_offset(p
, pkt
, idx
, reg
);
1147 case RADEON_RB3D_DEPTHOFFSET
:
1148 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1150 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1152 r100_cs_dump_packet(p
, pkt
);
1155 track
->zb
.robj
= reloc
->robj
;
1156 track
->zb
.offset
= idx_value
;
1157 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1159 case RADEON_RB3D_COLOROFFSET
:
1160 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1162 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1164 r100_cs_dump_packet(p
, pkt
);
1167 track
->cb
[0].robj
= reloc
->robj
;
1168 track
->cb
[0].offset
= idx_value
;
1169 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1171 case RADEON_PP_TXOFFSET_0
:
1172 case RADEON_PP_TXOFFSET_1
:
1173 case RADEON_PP_TXOFFSET_2
:
1174 i
= (reg
- RADEON_PP_TXOFFSET_0
) / 24;
1175 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1177 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1179 r100_cs_dump_packet(p
, pkt
);
1182 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1183 track
->textures
[i
].robj
= reloc
->robj
;
1185 case RADEON_PP_CUBIC_OFFSET_T0_0
:
1186 case RADEON_PP_CUBIC_OFFSET_T0_1
:
1187 case RADEON_PP_CUBIC_OFFSET_T0_2
:
1188 case RADEON_PP_CUBIC_OFFSET_T0_3
:
1189 case RADEON_PP_CUBIC_OFFSET_T0_4
:
1190 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T0_0
) / 4;
1191 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1193 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1195 r100_cs_dump_packet(p
, pkt
);
1198 track
->textures
[0].cube_info
[i
].offset
= idx_value
;
1199 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1200 track
->textures
[0].cube_info
[i
].robj
= reloc
->robj
;
1202 case RADEON_PP_CUBIC_OFFSET_T1_0
:
1203 case RADEON_PP_CUBIC_OFFSET_T1_1
:
1204 case RADEON_PP_CUBIC_OFFSET_T1_2
:
1205 case RADEON_PP_CUBIC_OFFSET_T1_3
:
1206 case RADEON_PP_CUBIC_OFFSET_T1_4
:
1207 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T1_0
) / 4;
1208 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1210 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1212 r100_cs_dump_packet(p
, pkt
);
1215 track
->textures
[1].cube_info
[i
].offset
= idx_value
;
1216 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1217 track
->textures
[1].cube_info
[i
].robj
= reloc
->robj
;
1219 case RADEON_PP_CUBIC_OFFSET_T2_0
:
1220 case RADEON_PP_CUBIC_OFFSET_T2_1
:
1221 case RADEON_PP_CUBIC_OFFSET_T2_2
:
1222 case RADEON_PP_CUBIC_OFFSET_T2_3
:
1223 case RADEON_PP_CUBIC_OFFSET_T2_4
:
1224 i
= (reg
- RADEON_PP_CUBIC_OFFSET_T2_0
) / 4;
1225 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1227 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1229 r100_cs_dump_packet(p
, pkt
);
1232 track
->textures
[2].cube_info
[i
].offset
= idx_value
;
1233 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1234 track
->textures
[2].cube_info
[i
].robj
= reloc
->robj
;
1236 case RADEON_RE_WIDTH_HEIGHT
:
1237 track
->maxy
= ((idx_value
>> 16) & 0x7FF);
1239 case RADEON_RB3D_COLORPITCH
:
1240 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1242 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1244 r100_cs_dump_packet(p
, pkt
);
1248 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
1249 tile_flags
|= RADEON_COLOR_TILE_ENABLE
;
1250 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
1251 tile_flags
|= RADEON_COLOR_MICROTILE_ENABLE
;
1253 tmp
= idx_value
& ~(0x7 << 16);
1257 track
->cb
[0].pitch
= idx_value
& RADEON_COLORPITCH_MASK
;
1259 case RADEON_RB3D_DEPTHPITCH
:
1260 track
->zb
.pitch
= idx_value
& RADEON_DEPTHPITCH_MASK
;
1262 case RADEON_RB3D_CNTL
:
1263 switch ((idx_value
>> RADEON_RB3D_COLOR_FORMAT_SHIFT
) & 0x1f) {
1269 track
->cb
[0].cpp
= 1;
1274 track
->cb
[0].cpp
= 2;
1277 track
->cb
[0].cpp
= 4;
1280 DRM_ERROR("Invalid color buffer format (%d) !\n",
1281 ((idx_value
>> RADEON_RB3D_COLOR_FORMAT_SHIFT
) & 0x1f));
1284 track
->z_enabled
= !!(idx_value
& RADEON_Z_ENABLE
);
1286 case RADEON_RB3D_ZSTENCILCNTL
:
1287 switch (idx_value
& 0xf) {
1303 case RADEON_RB3D_ZPASS_ADDR
:
1304 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1306 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1308 r100_cs_dump_packet(p
, pkt
);
1311 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
1313 case RADEON_PP_CNTL
:
1315 uint32_t temp
= idx_value
>> 4;
1316 for (i
= 0; i
< track
->num_texture
; i
++)
1317 track
->textures
[i
].enabled
= !!(temp
& (1 << i
));
1320 case RADEON_SE_VF_CNTL
:
1321 track
->vap_vf_cntl
= idx_value
;
1323 case RADEON_SE_VTX_FMT
:
1324 track
->vtx_size
= r100_get_vtx_size(idx_value
);
1326 case RADEON_PP_TEX_SIZE_0
:
1327 case RADEON_PP_TEX_SIZE_1
:
1328 case RADEON_PP_TEX_SIZE_2
:
1329 i
= (reg
- RADEON_PP_TEX_SIZE_0
) / 8;
1330 track
->textures
[i
].width
= (idx_value
& RADEON_TEX_USIZE_MASK
) + 1;
1331 track
->textures
[i
].height
= ((idx_value
& RADEON_TEX_VSIZE_MASK
) >> RADEON_TEX_VSIZE_SHIFT
) + 1;
1333 case RADEON_PP_TEX_PITCH_0
:
1334 case RADEON_PP_TEX_PITCH_1
:
1335 case RADEON_PP_TEX_PITCH_2
:
1336 i
= (reg
- RADEON_PP_TEX_PITCH_0
) / 8;
1337 track
->textures
[i
].pitch
= idx_value
+ 32;
1339 case RADEON_PP_TXFILTER_0
:
1340 case RADEON_PP_TXFILTER_1
:
1341 case RADEON_PP_TXFILTER_2
:
1342 i
= (reg
- RADEON_PP_TXFILTER_0
) / 24;
1343 track
->textures
[i
].num_levels
= ((idx_value
& RADEON_MAX_MIP_LEVEL_MASK
)
1344 >> RADEON_MAX_MIP_LEVEL_SHIFT
);
1345 tmp
= (idx_value
>> 23) & 0x7;
1346 if (tmp
== 2 || tmp
== 6)
1347 track
->textures
[i
].roundup_w
= false;
1348 tmp
= (idx_value
>> 27) & 0x7;
1349 if (tmp
== 2 || tmp
== 6)
1350 track
->textures
[i
].roundup_h
= false;
1352 case RADEON_PP_TXFORMAT_0
:
1353 case RADEON_PP_TXFORMAT_1
:
1354 case RADEON_PP_TXFORMAT_2
:
1355 i
= (reg
- RADEON_PP_TXFORMAT_0
) / 24;
1356 if (idx_value
& RADEON_TXFORMAT_NON_POWER2
) {
1357 track
->textures
[i
].use_pitch
= 1;
1359 track
->textures
[i
].use_pitch
= 0;
1360 track
->textures
[i
].width
= 1 << ((idx_value
>> RADEON_TXFORMAT_WIDTH_SHIFT
) & RADEON_TXFORMAT_WIDTH_MASK
);
1361 track
->textures
[i
].height
= 1 << ((idx_value
>> RADEON_TXFORMAT_HEIGHT_SHIFT
) & RADEON_TXFORMAT_HEIGHT_MASK
);
1363 if (idx_value
& RADEON_TXFORMAT_CUBIC_MAP_ENABLE
)
1364 track
->textures
[i
].tex_coord_type
= 2;
1365 switch ((idx_value
& RADEON_TXFORMAT_FORMAT_MASK
)) {
1366 case RADEON_TXFORMAT_I8
:
1367 case RADEON_TXFORMAT_RGB332
:
1368 case RADEON_TXFORMAT_Y8
:
1369 track
->textures
[i
].cpp
= 1;
1371 case RADEON_TXFORMAT_AI88
:
1372 case RADEON_TXFORMAT_ARGB1555
:
1373 case RADEON_TXFORMAT_RGB565
:
1374 case RADEON_TXFORMAT_ARGB4444
:
1375 case RADEON_TXFORMAT_VYUY422
:
1376 case RADEON_TXFORMAT_YVYU422
:
1377 case RADEON_TXFORMAT_SHADOW16
:
1378 case RADEON_TXFORMAT_LDUDV655
:
1379 case RADEON_TXFORMAT_DUDV88
:
1380 track
->textures
[i
].cpp
= 2;
1382 case RADEON_TXFORMAT_ARGB8888
:
1383 case RADEON_TXFORMAT_RGBA8888
:
1384 case RADEON_TXFORMAT_SHADOW32
:
1385 case RADEON_TXFORMAT_LDUDUV8888
:
1386 track
->textures
[i
].cpp
= 4;
1388 case RADEON_TXFORMAT_DXT1
:
1389 track
->textures
[i
].cpp
= 1;
1390 track
->textures
[i
].compress_format
= R100_TRACK_COMP_DXT1
;
1392 case RADEON_TXFORMAT_DXT23
:
1393 case RADEON_TXFORMAT_DXT45
:
1394 track
->textures
[i
].cpp
= 1;
1395 track
->textures
[i
].compress_format
= R100_TRACK_COMP_DXT35
;
1398 track
->textures
[i
].cube_info
[4].width
= 1 << ((idx_value
>> 16) & 0xf);
1399 track
->textures
[i
].cube_info
[4].height
= 1 << ((idx_value
>> 20) & 0xf);
1401 case RADEON_PP_CUBIC_FACES_0
:
1402 case RADEON_PP_CUBIC_FACES_1
:
1403 case RADEON_PP_CUBIC_FACES_2
:
1405 i
= (reg
- RADEON_PP_CUBIC_FACES_0
) / 4;
1406 for (face
= 0; face
< 4; face
++) {
1407 track
->textures
[i
].cube_info
[face
].width
= 1 << ((tmp
>> (face
* 8)) & 0xf);
1408 track
->textures
[i
].cube_info
[face
].height
= 1 << ((tmp
>> ((face
* 8) + 4)) & 0xf);
1412 printk(KERN_ERR
"Forbidden register 0x%04X in cs at %d\n",
1419 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser
*p
,
1420 struct radeon_cs_packet
*pkt
,
1421 struct radeon_bo
*robj
)
1426 value
= radeon_get_ib_value(p
, idx
+ 2);
1427 if ((value
+ 1) > radeon_bo_size(robj
)) {
1428 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1429 "(need %u have %lu) !\n",
1431 radeon_bo_size(robj
));
1437 static int r100_packet3_check(struct radeon_cs_parser
*p
,
1438 struct radeon_cs_packet
*pkt
)
1440 struct radeon_cs_reloc
*reloc
;
1441 struct r100_cs_track
*track
;
1443 volatile uint32_t *ib
;
1448 track
= (struct r100_cs_track
*)p
->track
;
1449 switch (pkt
->opcode
) {
1450 case PACKET3_3D_LOAD_VBPNTR
:
1451 r
= r100_packet3_load_vbpntr(p
, pkt
, idx
);
1455 case PACKET3_INDX_BUFFER
:
1456 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1458 DRM_ERROR("No reloc for packet3 %d\n", pkt
->opcode
);
1459 r100_cs_dump_packet(p
, pkt
);
1462 ib
[idx
+1] = radeon_get_ib_value(p
, idx
+1) + ((u32
)reloc
->lobj
.gpu_offset
);
1463 r
= r100_cs_track_check_pkt3_indx_buffer(p
, pkt
, reloc
->robj
);
1469 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1470 r
= r100_cs_packet_next_reloc(p
, &reloc
);
1472 DRM_ERROR("No reloc for packet3 %d\n", pkt
->opcode
);
1473 r100_cs_dump_packet(p
, pkt
);
1476 ib
[idx
] = radeon_get_ib_value(p
, idx
) + ((u32
)reloc
->lobj
.gpu_offset
);
1477 track
->num_arrays
= 1;
1478 track
->vtx_size
= r100_get_vtx_size(radeon_get_ib_value(p
, idx
+ 2));
1480 track
->arrays
[0].robj
= reloc
->robj
;
1481 track
->arrays
[0].esize
= track
->vtx_size
;
1483 track
->max_indx
= radeon_get_ib_value(p
, idx
+1);
1485 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+3);
1486 track
->immd_dwords
= pkt
->count
- 1;
1487 r
= r100_cs_track_check(p
->rdev
, track
);
1491 case PACKET3_3D_DRAW_IMMD
:
1492 if (((radeon_get_ib_value(p
, idx
+ 1) >> 4) & 0x3) != 3) {
1493 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1496 track
->vtx_size
= r100_get_vtx_size(radeon_get_ib_value(p
, idx
+ 0));
1497 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1498 track
->immd_dwords
= pkt
->count
- 1;
1499 r
= r100_cs_track_check(p
->rdev
, track
);
1503 /* triggers drawing using in-packet vertex data */
1504 case PACKET3_3D_DRAW_IMMD_2
:
1505 if (((radeon_get_ib_value(p
, idx
) >> 4) & 0x3) != 3) {
1506 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1509 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1510 track
->immd_dwords
= pkt
->count
;
1511 r
= r100_cs_track_check(p
->rdev
, track
);
1515 /* triggers drawing using in-packet vertex data */
1516 case PACKET3_3D_DRAW_VBUF_2
:
1517 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1518 r
= r100_cs_track_check(p
->rdev
, track
);
1522 /* triggers drawing of vertex buffers setup elsewhere */
1523 case PACKET3_3D_DRAW_INDX_2
:
1524 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
);
1525 r
= r100_cs_track_check(p
->rdev
, track
);
1529 /* triggers drawing using indices to vertex buffer */
1530 case PACKET3_3D_DRAW_VBUF
:
1531 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1532 r
= r100_cs_track_check(p
->rdev
, track
);
1536 /* triggers drawing of vertex buffers setup elsewhere */
1537 case PACKET3_3D_DRAW_INDX
:
1538 track
->vap_vf_cntl
= radeon_get_ib_value(p
, idx
+ 1);
1539 r
= r100_cs_track_check(p
->rdev
, track
);
1543 /* triggers drawing using indices to vertex buffer */
1547 DRM_ERROR("Packet3 opcode %x not supported\n", pkt
->opcode
);
1553 int r100_cs_parse(struct radeon_cs_parser
*p
)
1555 struct radeon_cs_packet pkt
;
1556 struct r100_cs_track
*track
;
1559 track
= kzalloc(sizeof(*track
), GFP_KERNEL
);
1560 r100_cs_track_clear(p
->rdev
, track
);
1563 r
= r100_cs_packet_parse(p
, &pkt
, p
->idx
);
1567 p
->idx
+= pkt
.count
+ 2;
1570 if (p
->rdev
->family
>= CHIP_R200
)
1571 r
= r100_cs_parse_packet0(p
, &pkt
,
1572 p
->rdev
->config
.r100
.reg_safe_bm
,
1573 p
->rdev
->config
.r100
.reg_safe_bm_size
,
1574 &r200_packet0_check
);
1576 r
= r100_cs_parse_packet0(p
, &pkt
,
1577 p
->rdev
->config
.r100
.reg_safe_bm
,
1578 p
->rdev
->config
.r100
.reg_safe_bm_size
,
1579 &r100_packet0_check
);
1584 r
= r100_packet3_check(p
, &pkt
);
1587 DRM_ERROR("Unknown packet type %d !\n",
1594 } while (p
->idx
< p
->chunks
[p
->chunk_ib_idx
].length_dw
);
1600 * Global GPU functions
1602 void r100_errata(struct radeon_device
*rdev
)
1604 rdev
->pll_errata
= 0;
1606 if (rdev
->family
== CHIP_RV200
|| rdev
->family
== CHIP_RS200
) {
1607 rdev
->pll_errata
|= CHIP_ERRATA_PLL_DUMMYREADS
;
1610 if (rdev
->family
== CHIP_RV100
||
1611 rdev
->family
== CHIP_RS100
||
1612 rdev
->family
== CHIP_RS200
) {
1613 rdev
->pll_errata
|= CHIP_ERRATA_PLL_DELAY
;
1617 /* Wait for vertical sync on primary CRTC */
1618 void r100_gpu_wait_for_vsync(struct radeon_device
*rdev
)
1620 uint32_t crtc_gen_cntl
, tmp
;
1623 crtc_gen_cntl
= RREG32(RADEON_CRTC_GEN_CNTL
);
1624 if ((crtc_gen_cntl
& RADEON_CRTC_DISP_REQ_EN_B
) ||
1625 !(crtc_gen_cntl
& RADEON_CRTC_EN
)) {
1628 /* Clear the CRTC_VBLANK_SAVE bit */
1629 WREG32(RADEON_CRTC_STATUS
, RADEON_CRTC_VBLANK_SAVE_CLEAR
);
1630 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1631 tmp
= RREG32(RADEON_CRTC_STATUS
);
1632 if (tmp
& RADEON_CRTC_VBLANK_SAVE
) {
1639 /* Wait for vertical sync on secondary CRTC */
1640 void r100_gpu_wait_for_vsync2(struct radeon_device
*rdev
)
1642 uint32_t crtc2_gen_cntl
, tmp
;
1645 crtc2_gen_cntl
= RREG32(RADEON_CRTC2_GEN_CNTL
);
1646 if ((crtc2_gen_cntl
& RADEON_CRTC2_DISP_REQ_EN_B
) ||
1647 !(crtc2_gen_cntl
& RADEON_CRTC2_EN
))
1650 /* Clear the CRTC_VBLANK_SAVE bit */
1651 WREG32(RADEON_CRTC2_STATUS
, RADEON_CRTC2_VBLANK_SAVE_CLEAR
);
1652 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1653 tmp
= RREG32(RADEON_CRTC2_STATUS
);
1654 if (tmp
& RADEON_CRTC2_VBLANK_SAVE
) {
1661 int r100_rbbm_fifo_wait_for_entry(struct radeon_device
*rdev
, unsigned n
)
1666 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1667 tmp
= RREG32(RADEON_RBBM_STATUS
) & RADEON_RBBM_FIFOCNT_MASK
;
1676 int r100_gui_wait_for_idle(struct radeon_device
*rdev
)
1681 if (r100_rbbm_fifo_wait_for_entry(rdev
, 64)) {
1682 printk(KERN_WARNING
"radeon: wait for empty RBBM fifo failed !"
1683 " Bad things might happen.\n");
1685 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1686 tmp
= RREG32(RADEON_RBBM_STATUS
);
1687 if (!(tmp
& RADEON_RBBM_ACTIVE
)) {
1695 int r100_mc_wait_for_idle(struct radeon_device
*rdev
)
1700 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
1701 /* read MC_STATUS */
1702 tmp
= RREG32(RADEON_MC_STATUS
);
1703 if (tmp
& RADEON_MC_IDLE
) {
1711 void r100_gpu_lockup_update(struct r100_gpu_lockup
*lockup
, struct radeon_cp
*cp
)
1713 lockup
->last_cp_rptr
= cp
->rptr
;
1714 lockup
->last_jiffies
= jiffies
;
1718 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1719 * @rdev: radeon device structure
1720 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
1721 * @cp: radeon_cp structure holding CP information
1723 * We don't need to initialize the lockup tracking information as we will either
1724 * have CP rptr to a different value of jiffies wrap around which will force
1725 * initialization of the lockup tracking informations.
1727 * A possible false positivie is if we get call after while and last_cp_rptr ==
1728 * the current CP rptr, even if it's unlikely it might happen. To avoid this
1729 * if the elapsed time since last call is bigger than 2 second than we return
1730 * false and update the tracking information. Due to this the caller must call
1731 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
1732 * the fencing code should be cautious about that.
1734 * Caller should write to the ring to force CP to do something so we don't get
1735 * false positive when CP is just gived nothing to do.
1738 bool r100_gpu_cp_is_lockup(struct radeon_device
*rdev
, struct r100_gpu_lockup
*lockup
, struct radeon_cp
*cp
)
1740 unsigned long cjiffies
, elapsed
;
1743 if (!time_after(cjiffies
, lockup
->last_jiffies
)) {
1744 /* likely a wrap around */
1745 lockup
->last_cp_rptr
= cp
->rptr
;
1746 lockup
->last_jiffies
= jiffies
;
1749 if (cp
->rptr
!= lockup
->last_cp_rptr
) {
1750 /* CP is still working no lockup */
1751 lockup
->last_cp_rptr
= cp
->rptr
;
1752 lockup
->last_jiffies
= jiffies
;
1755 elapsed
= jiffies_to_msecs(cjiffies
- lockup
->last_jiffies
);
1756 if (elapsed
>= 3000) {
1757 /* very likely the improbable case where current
1758 * rptr is equal to last recorded, a while ago, rptr
1759 * this is more likely a false positive update tracking
1760 * information which should force us to be recall at
1763 lockup
->last_cp_rptr
= cp
->rptr
;
1764 lockup
->last_jiffies
= jiffies
;
1767 if (elapsed
>= 1000) {
1768 dev_err(rdev
->dev
, "GPU lockup CP stall for more than %lumsec\n", elapsed
);
1771 /* give a chance to the GPU ... */
1775 bool r100_gpu_is_lockup(struct radeon_device
*rdev
)
1780 rbbm_status
= RREG32(R_000E40_RBBM_STATUS
);
1781 if (!G_000E40_GUI_ACTIVE(rbbm_status
)) {
1782 r100_gpu_lockup_update(&rdev
->config
.r100
.lockup
, &rdev
->cp
);
1785 /* force CP activities */
1786 r
= radeon_ring_lock(rdev
, 2);
1789 radeon_ring_write(rdev
, 0x80000000);
1790 radeon_ring_write(rdev
, 0x80000000);
1791 radeon_ring_unlock_commit(rdev
);
1793 rdev
->cp
.rptr
= RREG32(RADEON_CP_RB_RPTR
);
1794 return r100_gpu_cp_is_lockup(rdev
, &rdev
->config
.r100
.lockup
, &rdev
->cp
);
1797 void r100_bm_disable(struct radeon_device
*rdev
)
1801 /* disable bus mastering */
1802 tmp
= RREG32(R_000030_BUS_CNTL
);
1803 WREG32(R_000030_BUS_CNTL
, (tmp
& 0xFFFFFFFF) | 0x00000044);
1805 WREG32(R_000030_BUS_CNTL
, (tmp
& 0xFFFFFFFF) | 0x00000042);
1807 WREG32(R_000030_BUS_CNTL
, (tmp
& 0xFFFFFFFF) | 0x00000040);
1808 tmp
= RREG32(RADEON_BUS_CNTL
);
1810 pci_read_config_word(rdev
->pdev
, 0x4, (u16
*)&tmp
);
1811 pci_write_config_word(rdev
->pdev
, 0x4, tmp
& 0xFFFB);
1815 int r100_asic_reset(struct radeon_device
*rdev
)
1817 struct r100_mc_save save
;
1820 r100_mc_stop(rdev
, &save
);
1821 status
= RREG32(R_000E40_RBBM_STATUS
);
1822 if (!G_000E40_GUI_ACTIVE(status
)) {
1825 status
= RREG32(R_000E40_RBBM_STATUS
);
1826 dev_info(rdev
->dev
, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__
, __LINE__
, status
);
1828 WREG32(RADEON_CP_CSQ_CNTL
, 0);
1829 tmp
= RREG32(RADEON_CP_RB_CNTL
);
1830 WREG32(RADEON_CP_RB_CNTL
, tmp
| RADEON_RB_RPTR_WR_ENA
);
1831 WREG32(RADEON_CP_RB_RPTR_WR
, 0);
1832 WREG32(RADEON_CP_RB_WPTR
, 0);
1833 WREG32(RADEON_CP_RB_CNTL
, tmp
);
1834 /* save PCI state */
1835 pci_save_state(rdev
->pdev
);
1836 /* disable bus mastering */
1837 r100_bm_disable(rdev
);
1838 WREG32(R_0000F0_RBBM_SOFT_RESET
, S_0000F0_SOFT_RESET_SE(1) |
1839 S_0000F0_SOFT_RESET_RE(1) |
1840 S_0000F0_SOFT_RESET_PP(1) |
1841 S_0000F0_SOFT_RESET_RB(1));
1842 RREG32(R_0000F0_RBBM_SOFT_RESET
);
1844 WREG32(R_0000F0_RBBM_SOFT_RESET
, 0);
1846 status
= RREG32(R_000E40_RBBM_STATUS
);
1847 dev_info(rdev
->dev
, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__
, __LINE__
, status
);
1849 WREG32(R_0000F0_RBBM_SOFT_RESET
, S_0000F0_SOFT_RESET_CP(1));
1850 RREG32(R_0000F0_RBBM_SOFT_RESET
);
1852 WREG32(R_0000F0_RBBM_SOFT_RESET
, 0);
1854 status
= RREG32(R_000E40_RBBM_STATUS
);
1855 dev_info(rdev
->dev
, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__
, __LINE__
, status
);
1856 /* restore PCI & busmastering */
1857 pci_restore_state(rdev
->pdev
);
1858 r100_enable_bm(rdev
);
1859 /* Check if GPU is idle */
1860 if (G_000E40_SE_BUSY(status
) || G_000E40_RE_BUSY(status
) ||
1861 G_000E40_TAM_BUSY(status
) || G_000E40_PB_BUSY(status
)) {
1862 dev_err(rdev
->dev
, "failed to reset GPU\n");
1863 rdev
->gpu_lockup
= true;
1866 r100_mc_resume(rdev
, &save
);
1867 dev_info(rdev
->dev
, "GPU reset succeed\n");
1871 void r100_set_common_regs(struct radeon_device
*rdev
)
1873 struct drm_device
*dev
= rdev
->ddev
;
1874 bool force_dac2
= false;
1877 /* set these so they don't interfere with anything */
1878 WREG32(RADEON_OV0_SCALE_CNTL
, 0);
1879 WREG32(RADEON_SUBPIC_CNTL
, 0);
1880 WREG32(RADEON_VIPH_CONTROL
, 0);
1881 WREG32(RADEON_I2C_CNTL_1
, 0);
1882 WREG32(RADEON_DVI_I2C_CNTL_1
, 0);
1883 WREG32(RADEON_CAP0_TRIG_CNTL
, 0);
1884 WREG32(RADEON_CAP1_TRIG_CNTL
, 0);
1886 /* always set up dac2 on rn50 and some rv100 as lots
1887 * of servers seem to wire it up to a VGA port but
1888 * don't report it in the bios connector
1891 switch (dev
->pdev
->device
) {
1900 /* DELL triple head servers */
1901 if ((dev
->pdev
->subsystem_vendor
== 0x1028 /* DELL */) &&
1902 ((dev
->pdev
->subsystem_device
== 0x016c) ||
1903 (dev
->pdev
->subsystem_device
== 0x016d) ||
1904 (dev
->pdev
->subsystem_device
== 0x016e) ||
1905 (dev
->pdev
->subsystem_device
== 0x016f) ||
1906 (dev
->pdev
->subsystem_device
== 0x0170) ||
1907 (dev
->pdev
->subsystem_device
== 0x017d) ||
1908 (dev
->pdev
->subsystem_device
== 0x017e) ||
1909 (dev
->pdev
->subsystem_device
== 0x0183) ||
1910 (dev
->pdev
->subsystem_device
== 0x018a) ||
1911 (dev
->pdev
->subsystem_device
== 0x019a)))
1917 u32 disp_hw_debug
= RREG32(RADEON_DISP_HW_DEBUG
);
1918 u32 tv_dac_cntl
= RREG32(RADEON_TV_DAC_CNTL
);
1919 u32 dac2_cntl
= RREG32(RADEON_DAC_CNTL2
);
1921 /* For CRT on DAC2, don't turn it on if BIOS didn't
1922 enable it, even it's detected.
1925 /* force it to crtc0 */
1926 dac2_cntl
&= ~RADEON_DAC2_DAC_CLK_SEL
;
1927 dac2_cntl
|= RADEON_DAC2_DAC2_CLK_SEL
;
1928 disp_hw_debug
|= RADEON_CRT2_DISP1_SEL
;
1930 /* set up the TV DAC */
1931 tv_dac_cntl
&= ~(RADEON_TV_DAC_PEDESTAL
|
1932 RADEON_TV_DAC_STD_MASK
|
1933 RADEON_TV_DAC_RDACPD
|
1934 RADEON_TV_DAC_GDACPD
|
1935 RADEON_TV_DAC_BDACPD
|
1936 RADEON_TV_DAC_BGADJ_MASK
|
1937 RADEON_TV_DAC_DACADJ_MASK
);
1938 tv_dac_cntl
|= (RADEON_TV_DAC_NBLANK
|
1939 RADEON_TV_DAC_NHOLD
|
1940 RADEON_TV_DAC_STD_PS2
|
1943 WREG32(RADEON_TV_DAC_CNTL
, tv_dac_cntl
);
1944 WREG32(RADEON_DISP_HW_DEBUG
, disp_hw_debug
);
1945 WREG32(RADEON_DAC_CNTL2
, dac2_cntl
);
1948 /* switch PM block to ACPI mode */
1949 tmp
= RREG32_PLL(RADEON_PLL_PWRMGT_CNTL
);
1950 tmp
&= ~RADEON_PM_MODE_SEL
;
1951 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL
, tmp
);
1958 static void r100_vram_get_type(struct radeon_device
*rdev
)
1962 rdev
->mc
.vram_is_ddr
= false;
1963 if (rdev
->flags
& RADEON_IS_IGP
)
1964 rdev
->mc
.vram_is_ddr
= true;
1965 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG
) & RADEON_MEM_CFG_TYPE_DDR
)
1966 rdev
->mc
.vram_is_ddr
= true;
1967 if ((rdev
->family
== CHIP_RV100
) ||
1968 (rdev
->family
== CHIP_RS100
) ||
1969 (rdev
->family
== CHIP_RS200
)) {
1970 tmp
= RREG32(RADEON_MEM_CNTL
);
1971 if (tmp
& RV100_HALF_MODE
) {
1972 rdev
->mc
.vram_width
= 32;
1974 rdev
->mc
.vram_width
= 64;
1976 if (rdev
->flags
& RADEON_SINGLE_CRTC
) {
1977 rdev
->mc
.vram_width
/= 4;
1978 rdev
->mc
.vram_is_ddr
= true;
1980 } else if (rdev
->family
<= CHIP_RV280
) {
1981 tmp
= RREG32(RADEON_MEM_CNTL
);
1982 if (tmp
& RADEON_MEM_NUM_CHANNELS_MASK
) {
1983 rdev
->mc
.vram_width
= 128;
1985 rdev
->mc
.vram_width
= 64;
1989 rdev
->mc
.vram_width
= 128;
1993 static u32
r100_get_accessible_vram(struct radeon_device
*rdev
)
1998 aper_size
= RREG32(RADEON_CONFIG_APER_SIZE
);
2000 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2001 * that is has the 2nd generation multifunction PCI interface
2003 if (rdev
->family
== CHIP_RV280
||
2004 rdev
->family
>= CHIP_RV350
) {
2005 WREG32_P(RADEON_HOST_PATH_CNTL
, RADEON_HDP_APER_CNTL
,
2006 ~RADEON_HDP_APER_CNTL
);
2007 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2008 return aper_size
* 2;
2011 /* Older cards have all sorts of funny issues to deal with. First
2012 * check if it's a multifunction card by reading the PCI config
2013 * header type... Limit those to one aperture size
2015 pci_read_config_byte(rdev
->pdev
, 0xe, &byte
);
2017 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2018 DRM_INFO("Limiting VRAM to one aperture\n");
2022 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2023 * have set it up. We don't write this as it's broken on some ASICs but
2024 * we expect the BIOS to have done the right thing (might be too optimistic...)
2026 if (RREG32(RADEON_HOST_PATH_CNTL
) & RADEON_HDP_APER_CNTL
)
2027 return aper_size
* 2;
2031 void r100_vram_init_sizes(struct radeon_device
*rdev
)
2033 u64 config_aper_size
;
2035 /* work out accessible VRAM */
2036 rdev
->mc
.aper_base
= drm_get_resource_start(rdev
->ddev
, 0);
2037 rdev
->mc
.aper_size
= drm_get_resource_len(rdev
->ddev
, 0);
2038 rdev
->mc
.visible_vram_size
= r100_get_accessible_vram(rdev
);
2039 /* FIXME we don't use the second aperture yet when we could use it */
2040 if (rdev
->mc
.visible_vram_size
> rdev
->mc
.aper_size
)
2041 rdev
->mc
.visible_vram_size
= rdev
->mc
.aper_size
;
2042 config_aper_size
= RREG32(RADEON_CONFIG_APER_SIZE
);
2043 if (rdev
->flags
& RADEON_IS_IGP
) {
2045 /* read NB_TOM to get the amount of ram stolen for the GPU */
2046 tom
= RREG32(RADEON_NB_TOM
);
2047 rdev
->mc
.real_vram_size
= (((tom
>> 16) - (tom
& 0xffff) + 1) << 16);
2048 WREG32(RADEON_CONFIG_MEMSIZE
, rdev
->mc
.real_vram_size
);
2049 rdev
->mc
.mc_vram_size
= rdev
->mc
.real_vram_size
;
2051 rdev
->mc
.real_vram_size
= RREG32(RADEON_CONFIG_MEMSIZE
);
2052 /* Some production boards of m6 will report 0
2055 if (rdev
->mc
.real_vram_size
== 0) {
2056 rdev
->mc
.real_vram_size
= 8192 * 1024;
2057 WREG32(RADEON_CONFIG_MEMSIZE
, rdev
->mc
.real_vram_size
);
2059 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2060 * Novell bug 204882 + along with lots of ubuntu ones
2062 if (config_aper_size
> rdev
->mc
.real_vram_size
)
2063 rdev
->mc
.mc_vram_size
= config_aper_size
;
2065 rdev
->mc
.mc_vram_size
= rdev
->mc
.real_vram_size
;
2069 void r100_vga_set_state(struct radeon_device
*rdev
, bool state
)
2073 temp
= RREG32(RADEON_CONFIG_CNTL
);
2074 if (state
== false) {
2080 WREG32(RADEON_CONFIG_CNTL
, temp
);
2083 void r100_mc_init(struct radeon_device
*rdev
)
2087 r100_vram_get_type(rdev
);
2088 r100_vram_init_sizes(rdev
);
2089 base
= rdev
->mc
.aper_base
;
2090 if (rdev
->flags
& RADEON_IS_IGP
)
2091 base
= (RREG32(RADEON_NB_TOM
) & 0xffff) << 16;
2092 radeon_vram_location(rdev
, &rdev
->mc
, base
);
2093 if (!(rdev
->flags
& RADEON_IS_AGP
))
2094 radeon_gtt_location(rdev
, &rdev
->mc
);
2095 radeon_update_bandwidth_info(rdev
);
2100 * Indirect registers accessor
2102 void r100_pll_errata_after_index(struct radeon_device
*rdev
)
2104 if (!(rdev
->pll_errata
& CHIP_ERRATA_PLL_DUMMYREADS
)) {
2107 (void)RREG32(RADEON_CLOCK_CNTL_DATA
);
2108 (void)RREG32(RADEON_CRTC_GEN_CNTL
);
2111 static void r100_pll_errata_after_data(struct radeon_device
*rdev
)
2113 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2114 * or the chip could hang on a subsequent access
2116 if (rdev
->pll_errata
& CHIP_ERRATA_PLL_DELAY
) {
2120 /* This function is required to workaround a hardware bug in some (all?)
2121 * revisions of the R300. This workaround should be called after every
2122 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2123 * may not be correct.
2125 if (rdev
->pll_errata
& CHIP_ERRATA_R300_CG
) {
2128 save
= RREG32(RADEON_CLOCK_CNTL_INDEX
);
2129 tmp
= save
& ~(0x3f | RADEON_PLL_WR_EN
);
2130 WREG32(RADEON_CLOCK_CNTL_INDEX
, tmp
);
2131 tmp
= RREG32(RADEON_CLOCK_CNTL_DATA
);
2132 WREG32(RADEON_CLOCK_CNTL_INDEX
, save
);
2136 uint32_t r100_pll_rreg(struct radeon_device
*rdev
, uint32_t reg
)
2140 WREG8(RADEON_CLOCK_CNTL_INDEX
, reg
& 0x3f);
2141 r100_pll_errata_after_index(rdev
);
2142 data
= RREG32(RADEON_CLOCK_CNTL_DATA
);
2143 r100_pll_errata_after_data(rdev
);
2147 void r100_pll_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
)
2149 WREG8(RADEON_CLOCK_CNTL_INDEX
, ((reg
& 0x3f) | RADEON_PLL_WR_EN
));
2150 r100_pll_errata_after_index(rdev
);
2151 WREG32(RADEON_CLOCK_CNTL_DATA
, v
);
2152 r100_pll_errata_after_data(rdev
);
2155 void r100_set_safe_registers(struct radeon_device
*rdev
)
2157 if (ASIC_IS_RN50(rdev
)) {
2158 rdev
->config
.r100
.reg_safe_bm
= rn50_reg_safe_bm
;
2159 rdev
->config
.r100
.reg_safe_bm_size
= ARRAY_SIZE(rn50_reg_safe_bm
);
2160 } else if (rdev
->family
< CHIP_R200
) {
2161 rdev
->config
.r100
.reg_safe_bm
= r100_reg_safe_bm
;
2162 rdev
->config
.r100
.reg_safe_bm_size
= ARRAY_SIZE(r100_reg_safe_bm
);
2164 r200_set_safe_registers(rdev
);
2171 #if defined(CONFIG_DEBUG_FS)
2172 static int r100_debugfs_rbbm_info(struct seq_file
*m
, void *data
)
2174 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2175 struct drm_device
*dev
= node
->minor
->dev
;
2176 struct radeon_device
*rdev
= dev
->dev_private
;
2177 uint32_t reg
, value
;
2180 seq_printf(m
, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS
));
2181 seq_printf(m
, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2182 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
2183 for (i
= 0; i
< 64; i
++) {
2184 WREG32(RADEON_RBBM_CMDFIFO_ADDR
, i
| 0x100);
2185 reg
= (RREG32(RADEON_RBBM_CMDFIFO_DATA
) - 1) >> 2;
2186 WREG32(RADEON_RBBM_CMDFIFO_ADDR
, i
);
2187 value
= RREG32(RADEON_RBBM_CMDFIFO_DATA
);
2188 seq_printf(m
, "[0x%03X] 0x%04X=0x%08X\n", i
, reg
, value
);
2193 static int r100_debugfs_cp_ring_info(struct seq_file
*m
, void *data
)
2195 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2196 struct drm_device
*dev
= node
->minor
->dev
;
2197 struct radeon_device
*rdev
= dev
->dev_private
;
2199 unsigned count
, i
, j
;
2201 radeon_ring_free_size(rdev
);
2202 rdp
= RREG32(RADEON_CP_RB_RPTR
);
2203 wdp
= RREG32(RADEON_CP_RB_WPTR
);
2204 count
= (rdp
+ rdev
->cp
.ring_size
- wdp
) & rdev
->cp
.ptr_mask
;
2205 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
2206 seq_printf(m
, "CP_RB_WPTR 0x%08x\n", wdp
);
2207 seq_printf(m
, "CP_RB_RPTR 0x%08x\n", rdp
);
2208 seq_printf(m
, "%u free dwords in ring\n", rdev
->cp
.ring_free_dw
);
2209 seq_printf(m
, "%u dwords in ring\n", count
);
2210 for (j
= 0; j
<= count
; j
++) {
2211 i
= (rdp
+ j
) & rdev
->cp
.ptr_mask
;
2212 seq_printf(m
, "r[%04d]=0x%08x\n", i
, rdev
->cp
.ring
[i
]);
2218 static int r100_debugfs_cp_csq_fifo(struct seq_file
*m
, void *data
)
2220 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2221 struct drm_device
*dev
= node
->minor
->dev
;
2222 struct radeon_device
*rdev
= dev
->dev_private
;
2223 uint32_t csq_stat
, csq2_stat
, tmp
;
2224 unsigned r_rptr
, r_wptr
, ib1_rptr
, ib1_wptr
, ib2_rptr
, ib2_wptr
;
2227 seq_printf(m
, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT
));
2228 seq_printf(m
, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE
));
2229 csq_stat
= RREG32(RADEON_CP_CSQ_STAT
);
2230 csq2_stat
= RREG32(RADEON_CP_CSQ2_STAT
);
2231 r_rptr
= (csq_stat
>> 0) & 0x3ff;
2232 r_wptr
= (csq_stat
>> 10) & 0x3ff;
2233 ib1_rptr
= (csq_stat
>> 20) & 0x3ff;
2234 ib1_wptr
= (csq2_stat
>> 0) & 0x3ff;
2235 ib2_rptr
= (csq2_stat
>> 10) & 0x3ff;
2236 ib2_wptr
= (csq2_stat
>> 20) & 0x3ff;
2237 seq_printf(m
, "CP_CSQ_STAT 0x%08x\n", csq_stat
);
2238 seq_printf(m
, "CP_CSQ2_STAT 0x%08x\n", csq2_stat
);
2239 seq_printf(m
, "Ring rptr %u\n", r_rptr
);
2240 seq_printf(m
, "Ring wptr %u\n", r_wptr
);
2241 seq_printf(m
, "Indirect1 rptr %u\n", ib1_rptr
);
2242 seq_printf(m
, "Indirect1 wptr %u\n", ib1_wptr
);
2243 seq_printf(m
, "Indirect2 rptr %u\n", ib2_rptr
);
2244 seq_printf(m
, "Indirect2 wptr %u\n", ib2_wptr
);
2245 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2246 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2247 seq_printf(m
, "Ring fifo:\n");
2248 for (i
= 0; i
< 256; i
++) {
2249 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
2250 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
2251 seq_printf(m
, "rfifo[%04d]=0x%08X\n", i
, tmp
);
2253 seq_printf(m
, "Indirect1 fifo:\n");
2254 for (i
= 256; i
<= 512; i
++) {
2255 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
2256 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
2257 seq_printf(m
, "ib1fifo[%04d]=0x%08X\n", i
, tmp
);
2259 seq_printf(m
, "Indirect2 fifo:\n");
2260 for (i
= 640; i
< ib1_wptr
; i
++) {
2261 WREG32(RADEON_CP_CSQ_ADDR
, i
<< 2);
2262 tmp
= RREG32(RADEON_CP_CSQ_DATA
);
2263 seq_printf(m
, "ib2fifo[%04d]=0x%08X\n", i
, tmp
);
2268 static int r100_debugfs_mc_info(struct seq_file
*m
, void *data
)
2270 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2271 struct drm_device
*dev
= node
->minor
->dev
;
2272 struct radeon_device
*rdev
= dev
->dev_private
;
2275 tmp
= RREG32(RADEON_CONFIG_MEMSIZE
);
2276 seq_printf(m
, "CONFIG_MEMSIZE 0x%08x\n", tmp
);
2277 tmp
= RREG32(RADEON_MC_FB_LOCATION
);
2278 seq_printf(m
, "MC_FB_LOCATION 0x%08x\n", tmp
);
2279 tmp
= RREG32(RADEON_BUS_CNTL
);
2280 seq_printf(m
, "BUS_CNTL 0x%08x\n", tmp
);
2281 tmp
= RREG32(RADEON_MC_AGP_LOCATION
);
2282 seq_printf(m
, "MC_AGP_LOCATION 0x%08x\n", tmp
);
2283 tmp
= RREG32(RADEON_AGP_BASE
);
2284 seq_printf(m
, "AGP_BASE 0x%08x\n", tmp
);
2285 tmp
= RREG32(RADEON_HOST_PATH_CNTL
);
2286 seq_printf(m
, "HOST_PATH_CNTL 0x%08x\n", tmp
);
2287 tmp
= RREG32(0x01D0);
2288 seq_printf(m
, "AIC_CTRL 0x%08x\n", tmp
);
2289 tmp
= RREG32(RADEON_AIC_LO_ADDR
);
2290 seq_printf(m
, "AIC_LO_ADDR 0x%08x\n", tmp
);
2291 tmp
= RREG32(RADEON_AIC_HI_ADDR
);
2292 seq_printf(m
, "AIC_HI_ADDR 0x%08x\n", tmp
);
2293 tmp
= RREG32(0x01E4);
2294 seq_printf(m
, "AIC_TLB_ADDR 0x%08x\n", tmp
);
2298 static struct drm_info_list r100_debugfs_rbbm_list
[] = {
2299 {"r100_rbbm_info", r100_debugfs_rbbm_info
, 0, NULL
},
2302 static struct drm_info_list r100_debugfs_cp_list
[] = {
2303 {"r100_cp_ring_info", r100_debugfs_cp_ring_info
, 0, NULL
},
2304 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo
, 0, NULL
},
2307 static struct drm_info_list r100_debugfs_mc_info_list
[] = {
2308 {"r100_mc_info", r100_debugfs_mc_info
, 0, NULL
},
2312 int r100_debugfs_rbbm_init(struct radeon_device
*rdev
)
2314 #if defined(CONFIG_DEBUG_FS)
2315 return radeon_debugfs_add_files(rdev
, r100_debugfs_rbbm_list
, 1);
2321 int r100_debugfs_cp_init(struct radeon_device
*rdev
)
2323 #if defined(CONFIG_DEBUG_FS)
2324 return radeon_debugfs_add_files(rdev
, r100_debugfs_cp_list
, 2);
2330 int r100_debugfs_mc_info_init(struct radeon_device
*rdev
)
2332 #if defined(CONFIG_DEBUG_FS)
2333 return radeon_debugfs_add_files(rdev
, r100_debugfs_mc_info_list
, 1);
2339 int r100_set_surface_reg(struct radeon_device
*rdev
, int reg
,
2340 uint32_t tiling_flags
, uint32_t pitch
,
2341 uint32_t offset
, uint32_t obj_size
)
2343 int surf_index
= reg
* 16;
2346 /* r100/r200 divide by 16 */
2347 if (rdev
->family
< CHIP_R300
)
2352 if (rdev
->family
<= CHIP_RS200
) {
2353 if ((tiling_flags
& (RADEON_TILING_MACRO
|RADEON_TILING_MICRO
))
2354 == (RADEON_TILING_MACRO
|RADEON_TILING_MICRO
))
2355 flags
|= RADEON_SURF_TILE_COLOR_BOTH
;
2356 if (tiling_flags
& RADEON_TILING_MACRO
)
2357 flags
|= RADEON_SURF_TILE_COLOR_MACRO
;
2358 } else if (rdev
->family
<= CHIP_RV280
) {
2359 if (tiling_flags
& (RADEON_TILING_MACRO
))
2360 flags
|= R200_SURF_TILE_COLOR_MACRO
;
2361 if (tiling_flags
& RADEON_TILING_MICRO
)
2362 flags
|= R200_SURF_TILE_COLOR_MICRO
;
2364 if (tiling_flags
& RADEON_TILING_MACRO
)
2365 flags
|= R300_SURF_TILE_MACRO
;
2366 if (tiling_flags
& RADEON_TILING_MICRO
)
2367 flags
|= R300_SURF_TILE_MICRO
;
2370 if (tiling_flags
& RADEON_TILING_SWAP_16BIT
)
2371 flags
|= RADEON_SURF_AP0_SWP_16BPP
| RADEON_SURF_AP1_SWP_16BPP
;
2372 if (tiling_flags
& RADEON_TILING_SWAP_32BIT
)
2373 flags
|= RADEON_SURF_AP0_SWP_32BPP
| RADEON_SURF_AP1_SWP_32BPP
;
2375 DRM_DEBUG("writing surface %d %d %x %x\n", reg
, flags
, offset
, offset
+obj_size
-1);
2376 WREG32(RADEON_SURFACE0_INFO
+ surf_index
, flags
);
2377 WREG32(RADEON_SURFACE0_LOWER_BOUND
+ surf_index
, offset
);
2378 WREG32(RADEON_SURFACE0_UPPER_BOUND
+ surf_index
, offset
+ obj_size
- 1);
2382 void r100_clear_surface_reg(struct radeon_device
*rdev
, int reg
)
2384 int surf_index
= reg
* 16;
2385 WREG32(RADEON_SURFACE0_INFO
+ surf_index
, 0);
2388 void r100_bandwidth_update(struct radeon_device
*rdev
)
2390 fixed20_12 trcd_ff
, trp_ff
, tras_ff
, trbs_ff
, tcas_ff
;
2391 fixed20_12 sclk_ff
, mclk_ff
, sclk_eff_ff
, sclk_delay_ff
;
2392 fixed20_12 peak_disp_bw
, mem_bw
, pix_clk
, pix_clk2
, temp_ff
, crit_point_ff
;
2393 uint32_t temp
, data
, mem_trcd
, mem_trp
, mem_tras
;
2394 fixed20_12 memtcas_ff
[8] = {
2403 fixed20_12 memtcas_rs480_ff
[8] = {
2413 fixed20_12 memtcas2_ff
[8] = {
2423 fixed20_12 memtrbs
[8] = {
2433 fixed20_12 memtrbs_r4xx
[8] = {
2443 fixed20_12 min_mem_eff
;
2444 fixed20_12 mc_latency_sclk
, mc_latency_mclk
, k1
;
2445 fixed20_12 cur_latency_mclk
, cur_latency_sclk
;
2446 fixed20_12 disp_latency
, disp_latency_overhead
, disp_drain_rate
,
2447 disp_drain_rate2
, read_return_rate
;
2448 fixed20_12 time_disp1_drop_priority
;
2450 int cur_size
= 16; /* in octawords */
2451 int critical_point
= 0, critical_point2
;
2452 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2453 int stop_req
, max_stop_req
;
2454 struct drm_display_mode
*mode1
= NULL
;
2455 struct drm_display_mode
*mode2
= NULL
;
2456 uint32_t pixel_bytes1
= 0;
2457 uint32_t pixel_bytes2
= 0;
2459 radeon_update_display_priority(rdev
);
2461 if (rdev
->mode_info
.crtcs
[0]->base
.enabled
) {
2462 mode1
= &rdev
->mode_info
.crtcs
[0]->base
.mode
;
2463 pixel_bytes1
= rdev
->mode_info
.crtcs
[0]->base
.fb
->bits_per_pixel
/ 8;
2465 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
2466 if (rdev
->mode_info
.crtcs
[1]->base
.enabled
) {
2467 mode2
= &rdev
->mode_info
.crtcs
[1]->base
.mode
;
2468 pixel_bytes2
= rdev
->mode_info
.crtcs
[1]->base
.fb
->bits_per_pixel
/ 8;
2472 min_mem_eff
.full
= rfixed_const_8(0);
2474 if ((rdev
->disp_priority
== 2) && ASIC_IS_R300(rdev
)) {
2475 uint32_t mc_init_misc_lat_timer
= RREG32(R300_MC_INIT_MISC_LAT_TIMER
);
2476 mc_init_misc_lat_timer
&= ~(R300_MC_DISP1R_INIT_LAT_MASK
<< R300_MC_DISP1R_INIT_LAT_SHIFT
);
2477 mc_init_misc_lat_timer
&= ~(R300_MC_DISP0R_INIT_LAT_MASK
<< R300_MC_DISP0R_INIT_LAT_SHIFT
);
2478 /* check crtc enables */
2480 mc_init_misc_lat_timer
|= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT
);
2482 mc_init_misc_lat_timer
|= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT
);
2483 WREG32(R300_MC_INIT_MISC_LAT_TIMER
, mc_init_misc_lat_timer
);
2487 * determine is there is enough bw for current mode
2489 sclk_ff
= rdev
->pm
.sclk
;
2490 mclk_ff
= rdev
->pm
.mclk
;
2492 temp
= (rdev
->mc
.vram_width
/ 8) * (rdev
->mc
.vram_is_ddr
? 2 : 1);
2493 temp_ff
.full
= rfixed_const(temp
);
2494 mem_bw
.full
= rfixed_mul(mclk_ff
, temp_ff
);
2498 peak_disp_bw
.full
= 0;
2500 temp_ff
.full
= rfixed_const(1000);
2501 pix_clk
.full
= rfixed_const(mode1
->clock
); /* convert to fixed point */
2502 pix_clk
.full
= rfixed_div(pix_clk
, temp_ff
);
2503 temp_ff
.full
= rfixed_const(pixel_bytes1
);
2504 peak_disp_bw
.full
+= rfixed_mul(pix_clk
, temp_ff
);
2507 temp_ff
.full
= rfixed_const(1000);
2508 pix_clk2
.full
= rfixed_const(mode2
->clock
); /* convert to fixed point */
2509 pix_clk2
.full
= rfixed_div(pix_clk2
, temp_ff
);
2510 temp_ff
.full
= rfixed_const(pixel_bytes2
);
2511 peak_disp_bw
.full
+= rfixed_mul(pix_clk2
, temp_ff
);
2514 mem_bw
.full
= rfixed_mul(mem_bw
, min_mem_eff
);
2515 if (peak_disp_bw
.full
>= mem_bw
.full
) {
2516 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2517 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2520 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2521 temp
= RREG32(RADEON_MEM_TIMING_CNTL
);
2522 if ((rdev
->family
== CHIP_RV100
) || (rdev
->flags
& RADEON_IS_IGP
)) { /* RV100, M6, IGPs */
2523 mem_trcd
= ((temp
>> 2) & 0x3) + 1;
2524 mem_trp
= ((temp
& 0x3)) + 1;
2525 mem_tras
= ((temp
& 0x70) >> 4) + 1;
2526 } else if (rdev
->family
== CHIP_R300
||
2527 rdev
->family
== CHIP_R350
) { /* r300, r350 */
2528 mem_trcd
= (temp
& 0x7) + 1;
2529 mem_trp
= ((temp
>> 8) & 0x7) + 1;
2530 mem_tras
= ((temp
>> 11) & 0xf) + 4;
2531 } else if (rdev
->family
== CHIP_RV350
||
2532 rdev
->family
<= CHIP_RV380
) {
2534 mem_trcd
= (temp
& 0x7) + 3;
2535 mem_trp
= ((temp
>> 8) & 0x7) + 3;
2536 mem_tras
= ((temp
>> 11) & 0xf) + 6;
2537 } else if (rdev
->family
== CHIP_R420
||
2538 rdev
->family
== CHIP_R423
||
2539 rdev
->family
== CHIP_RV410
) {
2541 mem_trcd
= (temp
& 0xf) + 3;
2544 mem_trp
= ((temp
>> 8) & 0xf) + 3;
2547 mem_tras
= ((temp
>> 12) & 0x1f) + 6;
2550 } else { /* RV200, R200 */
2551 mem_trcd
= (temp
& 0x7) + 1;
2552 mem_trp
= ((temp
>> 8) & 0x7) + 1;
2553 mem_tras
= ((temp
>> 12) & 0xf) + 4;
2556 trcd_ff
.full
= rfixed_const(mem_trcd
);
2557 trp_ff
.full
= rfixed_const(mem_trp
);
2558 tras_ff
.full
= rfixed_const(mem_tras
);
2560 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2561 temp
= RREG32(RADEON_MEM_SDRAM_MODE_REG
);
2562 data
= (temp
& (7 << 20)) >> 20;
2563 if ((rdev
->family
== CHIP_RV100
) || rdev
->flags
& RADEON_IS_IGP
) {
2564 if (rdev
->family
== CHIP_RS480
) /* don't think rs400 */
2565 tcas_ff
= memtcas_rs480_ff
[data
];
2567 tcas_ff
= memtcas_ff
[data
];
2569 tcas_ff
= memtcas2_ff
[data
];
2571 if (rdev
->family
== CHIP_RS400
||
2572 rdev
->family
== CHIP_RS480
) {
2573 /* extra cas latency stored in bits 23-25 0-4 clocks */
2574 data
= (temp
>> 23) & 0x7;
2576 tcas_ff
.full
+= rfixed_const(data
);
2579 if (ASIC_IS_R300(rdev
) && !(rdev
->flags
& RADEON_IS_IGP
)) {
2580 /* on the R300, Tcas is included in Trbs.
2582 temp
= RREG32(RADEON_MEM_CNTL
);
2583 data
= (R300_MEM_NUM_CHANNELS_MASK
& temp
);
2585 if (R300_MEM_USE_CD_CH_ONLY
& temp
) {
2586 temp
= RREG32(R300_MC_IND_INDEX
);
2587 temp
&= ~R300_MC_IND_ADDR_MASK
;
2588 temp
|= R300_MC_READ_CNTL_CD_mcind
;
2589 WREG32(R300_MC_IND_INDEX
, temp
);
2590 temp
= RREG32(R300_MC_IND_DATA
);
2591 data
= (R300_MEM_RBS_POSITION_C_MASK
& temp
);
2593 temp
= RREG32(R300_MC_READ_CNTL_AB
);
2594 data
= (R300_MEM_RBS_POSITION_A_MASK
& temp
);
2597 temp
= RREG32(R300_MC_READ_CNTL_AB
);
2598 data
= (R300_MEM_RBS_POSITION_A_MASK
& temp
);
2600 if (rdev
->family
== CHIP_RV410
||
2601 rdev
->family
== CHIP_R420
||
2602 rdev
->family
== CHIP_R423
)
2603 trbs_ff
= memtrbs_r4xx
[data
];
2605 trbs_ff
= memtrbs
[data
];
2606 tcas_ff
.full
+= trbs_ff
.full
;
2609 sclk_eff_ff
.full
= sclk_ff
.full
;
2611 if (rdev
->flags
& RADEON_IS_AGP
) {
2612 fixed20_12 agpmode_ff
;
2613 agpmode_ff
.full
= rfixed_const(radeon_agpmode
);
2614 temp_ff
.full
= rfixed_const_666(16);
2615 sclk_eff_ff
.full
-= rfixed_mul(agpmode_ff
, temp_ff
);
2617 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2619 if (ASIC_IS_R300(rdev
)) {
2620 sclk_delay_ff
.full
= rfixed_const(250);
2622 if ((rdev
->family
== CHIP_RV100
) ||
2623 rdev
->flags
& RADEON_IS_IGP
) {
2624 if (rdev
->mc
.vram_is_ddr
)
2625 sclk_delay_ff
.full
= rfixed_const(41);
2627 sclk_delay_ff
.full
= rfixed_const(33);
2629 if (rdev
->mc
.vram_width
== 128)
2630 sclk_delay_ff
.full
= rfixed_const(57);
2632 sclk_delay_ff
.full
= rfixed_const(41);
2636 mc_latency_sclk
.full
= rfixed_div(sclk_delay_ff
, sclk_eff_ff
);
2638 if (rdev
->mc
.vram_is_ddr
) {
2639 if (rdev
->mc
.vram_width
== 32) {
2640 k1
.full
= rfixed_const(40);
2643 k1
.full
= rfixed_const(20);
2647 k1
.full
= rfixed_const(40);
2651 temp_ff
.full
= rfixed_const(2);
2652 mc_latency_mclk
.full
= rfixed_mul(trcd_ff
, temp_ff
);
2653 temp_ff
.full
= rfixed_const(c
);
2654 mc_latency_mclk
.full
+= rfixed_mul(tcas_ff
, temp_ff
);
2655 temp_ff
.full
= rfixed_const(4);
2656 mc_latency_mclk
.full
+= rfixed_mul(tras_ff
, temp_ff
);
2657 mc_latency_mclk
.full
+= rfixed_mul(trp_ff
, temp_ff
);
2658 mc_latency_mclk
.full
+= k1
.full
;
2660 mc_latency_mclk
.full
= rfixed_div(mc_latency_mclk
, mclk_ff
);
2661 mc_latency_mclk
.full
+= rfixed_div(temp_ff
, sclk_eff_ff
);
2664 HW cursor time assuming worst case of full size colour cursor.
2666 temp_ff
.full
= rfixed_const((2 * (cur_size
- (rdev
->mc
.vram_is_ddr
+ 1))));
2667 temp_ff
.full
+= trcd_ff
.full
;
2668 if (temp_ff
.full
< tras_ff
.full
)
2669 temp_ff
.full
= tras_ff
.full
;
2670 cur_latency_mclk
.full
= rfixed_div(temp_ff
, mclk_ff
);
2672 temp_ff
.full
= rfixed_const(cur_size
);
2673 cur_latency_sclk
.full
= rfixed_div(temp_ff
, sclk_eff_ff
);
2675 Find the total latency for the display data.
2677 disp_latency_overhead
.full
= rfixed_const(8);
2678 disp_latency_overhead
.full
= rfixed_div(disp_latency_overhead
, sclk_ff
);
2679 mc_latency_mclk
.full
+= disp_latency_overhead
.full
+ cur_latency_mclk
.full
;
2680 mc_latency_sclk
.full
+= disp_latency_overhead
.full
+ cur_latency_sclk
.full
;
2682 if (mc_latency_mclk
.full
> mc_latency_sclk
.full
)
2683 disp_latency
.full
= mc_latency_mclk
.full
;
2685 disp_latency
.full
= mc_latency_sclk
.full
;
2687 /* setup Max GRPH_STOP_REQ default value */
2688 if (ASIC_IS_RV100(rdev
))
2689 max_stop_req
= 0x5c;
2691 max_stop_req
= 0x7c;
2695 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2696 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2698 stop_req
= mode1
->hdisplay
* pixel_bytes1
/ 16;
2700 if (stop_req
> max_stop_req
)
2701 stop_req
= max_stop_req
;
2704 Find the drain rate of the display buffer.
2706 temp_ff
.full
= rfixed_const((16/pixel_bytes1
));
2707 disp_drain_rate
.full
= rfixed_div(pix_clk
, temp_ff
);
2710 Find the critical point of the display buffer.
2712 crit_point_ff
.full
= rfixed_mul(disp_drain_rate
, disp_latency
);
2713 crit_point_ff
.full
+= rfixed_const_half(0);
2715 critical_point
= rfixed_trunc(crit_point_ff
);
2717 if (rdev
->disp_priority
== 2) {
2722 The critical point should never be above max_stop_req-4. Setting
2723 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2725 if (max_stop_req
- critical_point
< 4)
2728 if (critical_point
== 0 && mode2
&& rdev
->family
== CHIP_R300
) {
2729 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2730 critical_point
= 0x10;
2733 temp
= RREG32(RADEON_GRPH_BUFFER_CNTL
);
2734 temp
&= ~(RADEON_GRPH_STOP_REQ_MASK
);
2735 temp
|= (stop_req
<< RADEON_GRPH_STOP_REQ_SHIFT
);
2736 temp
&= ~(RADEON_GRPH_START_REQ_MASK
);
2737 if ((rdev
->family
== CHIP_R350
) &&
2738 (stop_req
> 0x15)) {
2741 temp
|= (stop_req
<< RADEON_GRPH_START_REQ_SHIFT
);
2742 temp
|= RADEON_GRPH_BUFFER_SIZE
;
2743 temp
&= ~(RADEON_GRPH_CRITICAL_CNTL
|
2744 RADEON_GRPH_CRITICAL_AT_SOF
|
2745 RADEON_GRPH_STOP_CNTL
);
2747 Write the result into the register.
2749 WREG32(RADEON_GRPH_BUFFER_CNTL
, ((temp
& ~RADEON_GRPH_CRITICAL_POINT_MASK
) |
2750 (critical_point
<< RADEON_GRPH_CRITICAL_POINT_SHIFT
)));
2753 if ((rdev
->family
== CHIP_RS400
) ||
2754 (rdev
->family
== CHIP_RS480
)) {
2755 /* attempt to program RS400 disp regs correctly ??? */
2756 temp
= RREG32(RS400_DISP1_REG_CNTL
);
2757 temp
&= ~(RS400_DISP1_START_REQ_LEVEL_MASK
|
2758 RS400_DISP1_STOP_REQ_LEVEL_MASK
);
2759 WREG32(RS400_DISP1_REQ_CNTL1
, (temp
|
2760 (critical_point
<< RS400_DISP1_START_REQ_LEVEL_SHIFT
) |
2761 (critical_point
<< RS400_DISP1_STOP_REQ_LEVEL_SHIFT
)));
2762 temp
= RREG32(RS400_DMIF_MEM_CNTL1
);
2763 temp
&= ~(RS400_DISP1_CRITICAL_POINT_START_MASK
|
2764 RS400_DISP1_CRITICAL_POINT_STOP_MASK
);
2765 WREG32(RS400_DMIF_MEM_CNTL1
, (temp
|
2766 (critical_point
<< RS400_DISP1_CRITICAL_POINT_START_SHIFT
) |
2767 (critical_point
<< RS400_DISP1_CRITICAL_POINT_STOP_SHIFT
)));
2771 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2772 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2773 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL
));
2778 stop_req
= mode2
->hdisplay
* pixel_bytes2
/ 16;
2780 if (stop_req
> max_stop_req
)
2781 stop_req
= max_stop_req
;
2784 Find the drain rate of the display buffer.
2786 temp_ff
.full
= rfixed_const((16/pixel_bytes2
));
2787 disp_drain_rate2
.full
= rfixed_div(pix_clk2
, temp_ff
);
2789 grph2_cntl
= RREG32(RADEON_GRPH2_BUFFER_CNTL
);
2790 grph2_cntl
&= ~(RADEON_GRPH_STOP_REQ_MASK
);
2791 grph2_cntl
|= (stop_req
<< RADEON_GRPH_STOP_REQ_SHIFT
);
2792 grph2_cntl
&= ~(RADEON_GRPH_START_REQ_MASK
);
2793 if ((rdev
->family
== CHIP_R350
) &&
2794 (stop_req
> 0x15)) {
2797 grph2_cntl
|= (stop_req
<< RADEON_GRPH_START_REQ_SHIFT
);
2798 grph2_cntl
|= RADEON_GRPH_BUFFER_SIZE
;
2799 grph2_cntl
&= ~(RADEON_GRPH_CRITICAL_CNTL
|
2800 RADEON_GRPH_CRITICAL_AT_SOF
|
2801 RADEON_GRPH_STOP_CNTL
);
2803 if ((rdev
->family
== CHIP_RS100
) ||
2804 (rdev
->family
== CHIP_RS200
))
2805 critical_point2
= 0;
2807 temp
= (rdev
->mc
.vram_width
* rdev
->mc
.vram_is_ddr
+ 1)/128;
2808 temp_ff
.full
= rfixed_const(temp
);
2809 temp_ff
.full
= rfixed_mul(mclk_ff
, temp_ff
);
2810 if (sclk_ff
.full
< temp_ff
.full
)
2811 temp_ff
.full
= sclk_ff
.full
;
2813 read_return_rate
.full
= temp_ff
.full
;
2816 temp_ff
.full
= read_return_rate
.full
- disp_drain_rate
.full
;
2817 time_disp1_drop_priority
.full
= rfixed_div(crit_point_ff
, temp_ff
);
2819 time_disp1_drop_priority
.full
= 0;
2821 crit_point_ff
.full
= disp_latency
.full
+ time_disp1_drop_priority
.full
+ disp_latency
.full
;
2822 crit_point_ff
.full
= rfixed_mul(crit_point_ff
, disp_drain_rate2
);
2823 crit_point_ff
.full
+= rfixed_const_half(0);
2825 critical_point2
= rfixed_trunc(crit_point_ff
);
2827 if (rdev
->disp_priority
== 2) {
2828 critical_point2
= 0;
2831 if (max_stop_req
- critical_point2
< 4)
2832 critical_point2
= 0;
2836 if (critical_point2
== 0 && rdev
->family
== CHIP_R300
) {
2837 /* some R300 cards have problem with this set to 0 */
2838 critical_point2
= 0x10;
2841 WREG32(RADEON_GRPH2_BUFFER_CNTL
, ((grph2_cntl
& ~RADEON_GRPH_CRITICAL_POINT_MASK
) |
2842 (critical_point2
<< RADEON_GRPH_CRITICAL_POINT_SHIFT
)));
2844 if ((rdev
->family
== CHIP_RS400
) ||
2845 (rdev
->family
== CHIP_RS480
)) {
2847 /* attempt to program RS400 disp2 regs correctly ??? */
2848 temp
= RREG32(RS400_DISP2_REQ_CNTL1
);
2849 temp
&= ~(RS400_DISP2_START_REQ_LEVEL_MASK
|
2850 RS400_DISP2_STOP_REQ_LEVEL_MASK
);
2851 WREG32(RS400_DISP2_REQ_CNTL1
, (temp
|
2852 (critical_point2
<< RS400_DISP1_START_REQ_LEVEL_SHIFT
) |
2853 (critical_point2
<< RS400_DISP1_STOP_REQ_LEVEL_SHIFT
)));
2854 temp
= RREG32(RS400_DISP2_REQ_CNTL2
);
2855 temp
&= ~(RS400_DISP2_CRITICAL_POINT_START_MASK
|
2856 RS400_DISP2_CRITICAL_POINT_STOP_MASK
);
2857 WREG32(RS400_DISP2_REQ_CNTL2
, (temp
|
2858 (critical_point2
<< RS400_DISP2_CRITICAL_POINT_START_SHIFT
) |
2859 (critical_point2
<< RS400_DISP2_CRITICAL_POINT_STOP_SHIFT
)));
2861 WREG32(RS400_DISP2_REQ_CNTL1
, 0x105DC1CC);
2862 WREG32(RS400_DISP2_REQ_CNTL2
, 0x2749D000);
2863 WREG32(RS400_DMIF_MEM_CNTL1
, 0x29CA71DC);
2864 WREG32(RS400_DISP1_REQ_CNTL1
, 0x28FBC3AC);
2867 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2868 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL
));
2872 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture
*t
)
2874 DRM_ERROR("pitch %d\n", t
->pitch
);
2875 DRM_ERROR("use_pitch %d\n", t
->use_pitch
);
2876 DRM_ERROR("width %d\n", t
->width
);
2877 DRM_ERROR("width_11 %d\n", t
->width_11
);
2878 DRM_ERROR("height %d\n", t
->height
);
2879 DRM_ERROR("height_11 %d\n", t
->height_11
);
2880 DRM_ERROR("num levels %d\n", t
->num_levels
);
2881 DRM_ERROR("depth %d\n", t
->txdepth
);
2882 DRM_ERROR("bpp %d\n", t
->cpp
);
2883 DRM_ERROR("coordinate type %d\n", t
->tex_coord_type
);
2884 DRM_ERROR("width round to power of 2 %d\n", t
->roundup_w
);
2885 DRM_ERROR("height round to power of 2 %d\n", t
->roundup_h
);
2886 DRM_ERROR("compress format %d\n", t
->compress_format
);
2889 static int r100_cs_track_cube(struct radeon_device
*rdev
,
2890 struct r100_cs_track
*track
, unsigned idx
)
2892 unsigned face
, w
, h
;
2893 struct radeon_bo
*cube_robj
;
2896 for (face
= 0; face
< 5; face
++) {
2897 cube_robj
= track
->textures
[idx
].cube_info
[face
].robj
;
2898 w
= track
->textures
[idx
].cube_info
[face
].width
;
2899 h
= track
->textures
[idx
].cube_info
[face
].height
;
2902 size
*= track
->textures
[idx
].cpp
;
2904 size
+= track
->textures
[idx
].cube_info
[face
].offset
;
2906 if (size
> radeon_bo_size(cube_robj
)) {
2907 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2908 size
, radeon_bo_size(cube_robj
));
2909 r100_cs_track_texture_print(&track
->textures
[idx
]);
2916 static int r100_track_compress_size(int compress_format
, int w
, int h
)
2918 int block_width
, block_height
, block_bytes
;
2919 int wblocks
, hblocks
;
2926 switch (compress_format
) {
2927 case R100_TRACK_COMP_DXT1
:
2932 case R100_TRACK_COMP_DXT35
:
2938 hblocks
= (h
+ block_height
- 1) / block_height
;
2939 wblocks
= (w
+ block_width
- 1) / block_width
;
2940 if (wblocks
< min_wblocks
)
2941 wblocks
= min_wblocks
;
2942 sz
= wblocks
* hblocks
* block_bytes
;
2946 static int r100_cs_track_texture_check(struct radeon_device
*rdev
,
2947 struct r100_cs_track
*track
)
2949 struct radeon_bo
*robj
;
2951 unsigned u
, i
, w
, h
, d
;
2954 for (u
= 0; u
< track
->num_texture
; u
++) {
2955 if (!track
->textures
[u
].enabled
)
2957 robj
= track
->textures
[u
].robj
;
2959 DRM_ERROR("No texture bound to unit %u\n", u
);
2963 for (i
= 0; i
<= track
->textures
[u
].num_levels
; i
++) {
2964 if (track
->textures
[u
].use_pitch
) {
2965 if (rdev
->family
< CHIP_R300
)
2966 w
= (track
->textures
[u
].pitch
/ track
->textures
[u
].cpp
) / (1 << i
);
2968 w
= track
->textures
[u
].pitch
/ (1 << i
);
2970 w
= track
->textures
[u
].width
;
2971 if (rdev
->family
>= CHIP_RV515
)
2972 w
|= track
->textures
[u
].width_11
;
2974 if (track
->textures
[u
].roundup_w
)
2975 w
= roundup_pow_of_two(w
);
2977 h
= track
->textures
[u
].height
;
2978 if (rdev
->family
>= CHIP_RV515
)
2979 h
|= track
->textures
[u
].height_11
;
2981 if (track
->textures
[u
].roundup_h
)
2982 h
= roundup_pow_of_two(h
);
2983 if (track
->textures
[u
].tex_coord_type
== 1) {
2984 d
= (1 << track
->textures
[u
].txdepth
) / (1 << i
);
2990 if (track
->textures
[u
].compress_format
) {
2992 size
+= r100_track_compress_size(track
->textures
[u
].compress_format
, w
, h
) * d
;
2993 /* compressed textures are block based */
2997 size
*= track
->textures
[u
].cpp
;
2999 switch (track
->textures
[u
].tex_coord_type
) {
3004 if (track
->separate_cube
) {
3005 ret
= r100_cs_track_cube(rdev
, track
, u
);
3012 DRM_ERROR("Invalid texture coordinate type %u for unit "
3013 "%u\n", track
->textures
[u
].tex_coord_type
, u
);
3016 if (size
> radeon_bo_size(robj
)) {
3017 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3018 "%lu\n", u
, size
, radeon_bo_size(robj
));
3019 r100_cs_track_texture_print(&track
->textures
[u
]);
3026 int r100_cs_track_check(struct radeon_device
*rdev
, struct r100_cs_track
*track
)
3033 for (i
= 0; i
< track
->num_cb
; i
++) {
3034 if (track
->cb
[i
].robj
== NULL
) {
3035 if (!(track
->fastfill
|| track
->color_channel_mask
||
3036 track
->blend_read_enable
)) {
3039 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i
);
3042 size
= track
->cb
[i
].pitch
* track
->cb
[i
].cpp
* track
->maxy
;
3043 size
+= track
->cb
[i
].offset
;
3044 if (size
> radeon_bo_size(track
->cb
[i
].robj
)) {
3045 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3046 "(need %lu have %lu) !\n", i
, size
,
3047 radeon_bo_size(track
->cb
[i
].robj
));
3048 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3049 i
, track
->cb
[i
].pitch
, track
->cb
[i
].cpp
,
3050 track
->cb
[i
].offset
, track
->maxy
);
3054 if (track
->z_enabled
) {
3055 if (track
->zb
.robj
== NULL
) {
3056 DRM_ERROR("[drm] No buffer for z buffer !\n");
3059 size
= track
->zb
.pitch
* track
->zb
.cpp
* track
->maxy
;
3060 size
+= track
->zb
.offset
;
3061 if (size
> radeon_bo_size(track
->zb
.robj
)) {
3062 DRM_ERROR("[drm] Buffer too small for z buffer "
3063 "(need %lu have %lu) !\n", size
,
3064 radeon_bo_size(track
->zb
.robj
));
3065 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3066 track
->zb
.pitch
, track
->zb
.cpp
,
3067 track
->zb
.offset
, track
->maxy
);
3071 prim_walk
= (track
->vap_vf_cntl
>> 4) & 0x3;
3072 if (track
->vap_vf_cntl
& (1 << 14)) {
3073 nverts
= track
->vap_alt_nverts
;
3075 nverts
= (track
->vap_vf_cntl
>> 16) & 0xFFFF;
3077 switch (prim_walk
) {
3079 for (i
= 0; i
< track
->num_arrays
; i
++) {
3080 size
= track
->arrays
[i
].esize
* track
->max_indx
* 4;
3081 if (track
->arrays
[i
].robj
== NULL
) {
3082 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3083 "bound\n", prim_walk
, i
);
3086 if (size
> radeon_bo_size(track
->arrays
[i
].robj
)) {
3087 dev_err(rdev
->dev
, "(PW %u) Vertex array %u "
3088 "need %lu dwords have %lu dwords\n",
3089 prim_walk
, i
, size
>> 2,
3090 radeon_bo_size(track
->arrays
[i
].robj
)
3092 DRM_ERROR("Max indices %u\n", track
->max_indx
);
3098 for (i
= 0; i
< track
->num_arrays
; i
++) {
3099 size
= track
->arrays
[i
].esize
* (nverts
- 1) * 4;
3100 if (track
->arrays
[i
].robj
== NULL
) {
3101 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3102 "bound\n", prim_walk
, i
);
3105 if (size
> radeon_bo_size(track
->arrays
[i
].robj
)) {
3106 dev_err(rdev
->dev
, "(PW %u) Vertex array %u "
3107 "need %lu dwords have %lu dwords\n",
3108 prim_walk
, i
, size
>> 2,
3109 radeon_bo_size(track
->arrays
[i
].robj
)
3116 size
= track
->vtx_size
* nverts
;
3117 if (size
!= track
->immd_dwords
) {
3118 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3119 track
->immd_dwords
, size
);
3120 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3121 nverts
, track
->vtx_size
);
3126 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3130 return r100_cs_track_texture_check(rdev
, track
);
3133 void r100_cs_track_clear(struct radeon_device
*rdev
, struct r100_cs_track
*track
)
3137 if (rdev
->family
< CHIP_R300
) {
3139 if (rdev
->family
<= CHIP_RS200
)
3140 track
->num_texture
= 3;
3142 track
->num_texture
= 6;
3144 track
->separate_cube
= 1;
3147 track
->num_texture
= 16;
3149 track
->separate_cube
= 0;
3152 for (i
= 0; i
< track
->num_cb
; i
++) {
3153 track
->cb
[i
].robj
= NULL
;
3154 track
->cb
[i
].pitch
= 8192;
3155 track
->cb
[i
].cpp
= 16;
3156 track
->cb
[i
].offset
= 0;
3158 track
->z_enabled
= true;
3159 track
->zb
.robj
= NULL
;
3160 track
->zb
.pitch
= 8192;
3162 track
->zb
.offset
= 0;
3163 track
->vtx_size
= 0x7F;
3164 track
->immd_dwords
= 0xFFFFFFFFUL
;
3165 track
->num_arrays
= 11;
3166 track
->max_indx
= 0x00FFFFFFUL
;
3167 for (i
= 0; i
< track
->num_arrays
; i
++) {
3168 track
->arrays
[i
].robj
= NULL
;
3169 track
->arrays
[i
].esize
= 0x7F;
3171 for (i
= 0; i
< track
->num_texture
; i
++) {
3172 track
->textures
[i
].compress_format
= R100_TRACK_COMP_NONE
;
3173 track
->textures
[i
].pitch
= 16536;
3174 track
->textures
[i
].width
= 16536;
3175 track
->textures
[i
].height
= 16536;
3176 track
->textures
[i
].width_11
= 1 << 11;
3177 track
->textures
[i
].height_11
= 1 << 11;
3178 track
->textures
[i
].num_levels
= 12;
3179 if (rdev
->family
<= CHIP_RS200
) {
3180 track
->textures
[i
].tex_coord_type
= 0;
3181 track
->textures
[i
].txdepth
= 0;
3183 track
->textures
[i
].txdepth
= 16;
3184 track
->textures
[i
].tex_coord_type
= 1;
3186 track
->textures
[i
].cpp
= 64;
3187 track
->textures
[i
].robj
= NULL
;
3188 /* CS IB emission code makes sure texture unit are disabled */
3189 track
->textures
[i
].enabled
= false;
3190 track
->textures
[i
].roundup_w
= true;
3191 track
->textures
[i
].roundup_h
= true;
3192 if (track
->separate_cube
)
3193 for (face
= 0; face
< 5; face
++) {
3194 track
->textures
[i
].cube_info
[face
].robj
= NULL
;
3195 track
->textures
[i
].cube_info
[face
].width
= 16536;
3196 track
->textures
[i
].cube_info
[face
].height
= 16536;
3197 track
->textures
[i
].cube_info
[face
].offset
= 0;
3202 int r100_ring_test(struct radeon_device
*rdev
)
3209 r
= radeon_scratch_get(rdev
, &scratch
);
3211 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r
);
3214 WREG32(scratch
, 0xCAFEDEAD);
3215 r
= radeon_ring_lock(rdev
, 2);
3217 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r
);
3218 radeon_scratch_free(rdev
, scratch
);
3221 radeon_ring_write(rdev
, PACKET0(scratch
, 0));
3222 radeon_ring_write(rdev
, 0xDEADBEEF);
3223 radeon_ring_unlock_commit(rdev
);
3224 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3225 tmp
= RREG32(scratch
);
3226 if (tmp
== 0xDEADBEEF) {
3231 if (i
< rdev
->usec_timeout
) {
3232 DRM_INFO("ring test succeeded in %d usecs\n", i
);
3234 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3238 radeon_scratch_free(rdev
, scratch
);
3242 void r100_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
)
3244 radeon_ring_write(rdev
, PACKET0(RADEON_CP_IB_BASE
, 1));
3245 radeon_ring_write(rdev
, ib
->gpu_addr
);
3246 radeon_ring_write(rdev
, ib
->length_dw
);
3249 int r100_ib_test(struct radeon_device
*rdev
)
3251 struct radeon_ib
*ib
;
3257 r
= radeon_scratch_get(rdev
, &scratch
);
3259 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r
);
3262 WREG32(scratch
, 0xCAFEDEAD);
3263 r
= radeon_ib_get(rdev
, &ib
);
3267 ib
->ptr
[0] = PACKET0(scratch
, 0);
3268 ib
->ptr
[1] = 0xDEADBEEF;
3269 ib
->ptr
[2] = PACKET2(0);
3270 ib
->ptr
[3] = PACKET2(0);
3271 ib
->ptr
[4] = PACKET2(0);
3272 ib
->ptr
[5] = PACKET2(0);
3273 ib
->ptr
[6] = PACKET2(0);
3274 ib
->ptr
[7] = PACKET2(0);
3276 r
= radeon_ib_schedule(rdev
, ib
);
3278 radeon_scratch_free(rdev
, scratch
);
3279 radeon_ib_free(rdev
, &ib
);
3282 r
= radeon_fence_wait(ib
->fence
, false);
3286 for (i
= 0; i
< rdev
->usec_timeout
; i
++) {
3287 tmp
= RREG32(scratch
);
3288 if (tmp
== 0xDEADBEEF) {
3293 if (i
< rdev
->usec_timeout
) {
3294 DRM_INFO("ib test succeeded in %u usecs\n", i
);
3296 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3300 radeon_scratch_free(rdev
, scratch
);
3301 radeon_ib_free(rdev
, &ib
);
3305 void r100_ib_fini(struct radeon_device
*rdev
)
3307 radeon_ib_pool_fini(rdev
);
3310 int r100_ib_init(struct radeon_device
*rdev
)
3314 r
= radeon_ib_pool_init(rdev
);
3316 dev_err(rdev
->dev
, "failled initializing IB pool (%d).\n", r
);
3320 r
= r100_ib_test(rdev
);
3322 dev_err(rdev
->dev
, "failled testing IB (%d).\n", r
);
3329 void r100_mc_stop(struct radeon_device
*rdev
, struct r100_mc_save
*save
)
3331 /* Shutdown CP we shouldn't need to do that but better be safe than
3334 rdev
->cp
.ready
= false;
3335 WREG32(R_000740_CP_CSQ_CNTL
, 0);
3337 /* Save few CRTC registers */
3338 save
->GENMO_WT
= RREG8(R_0003C2_GENMO_WT
);
3339 save
->CRTC_EXT_CNTL
= RREG32(R_000054_CRTC_EXT_CNTL
);
3340 save
->CRTC_GEN_CNTL
= RREG32(R_000050_CRTC_GEN_CNTL
);
3341 save
->CUR_OFFSET
= RREG32(R_000260_CUR_OFFSET
);
3342 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3343 save
->CRTC2_GEN_CNTL
= RREG32(R_0003F8_CRTC2_GEN_CNTL
);
3344 save
->CUR2_OFFSET
= RREG32(R_000360_CUR2_OFFSET
);
3347 /* Disable VGA aperture access */
3348 WREG8(R_0003C2_GENMO_WT
, C_0003C2_VGA_RAM_EN
& save
->GENMO_WT
);
3349 /* Disable cursor, overlay, crtc */
3350 WREG32(R_000260_CUR_OFFSET
, save
->CUR_OFFSET
| S_000260_CUR_LOCK(1));
3351 WREG32(R_000054_CRTC_EXT_CNTL
, save
->CRTC_EXT_CNTL
|
3352 S_000054_CRTC_DISPLAY_DIS(1));
3353 WREG32(R_000050_CRTC_GEN_CNTL
,
3354 (C_000050_CRTC_CUR_EN
& save
->CRTC_GEN_CNTL
) |
3355 S_000050_CRTC_DISP_REQ_EN_B(1));
3356 WREG32(R_000420_OV0_SCALE_CNTL
,
3357 C_000420_OV0_OVERLAY_EN
& RREG32(R_000420_OV0_SCALE_CNTL
));
3358 WREG32(R_000260_CUR_OFFSET
, C_000260_CUR_LOCK
& save
->CUR_OFFSET
);
3359 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3360 WREG32(R_000360_CUR2_OFFSET
, save
->CUR2_OFFSET
|
3361 S_000360_CUR2_LOCK(1));
3362 WREG32(R_0003F8_CRTC2_GEN_CNTL
,
3363 (C_0003F8_CRTC2_CUR_EN
& save
->CRTC2_GEN_CNTL
) |
3364 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3365 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3366 WREG32(R_000360_CUR2_OFFSET
,
3367 C_000360_CUR2_LOCK
& save
->CUR2_OFFSET
);
3371 void r100_mc_resume(struct radeon_device
*rdev
, struct r100_mc_save
*save
)
3373 /* Update base address for crtc */
3374 WREG32(R_00023C_DISPLAY_BASE_ADDR
, rdev
->mc
.vram_start
);
3375 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3376 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR
, rdev
->mc
.vram_start
);
3378 /* Restore CRTC registers */
3379 WREG8(R_0003C2_GENMO_WT
, save
->GENMO_WT
);
3380 WREG32(R_000054_CRTC_EXT_CNTL
, save
->CRTC_EXT_CNTL
);
3381 WREG32(R_000050_CRTC_GEN_CNTL
, save
->CRTC_GEN_CNTL
);
3382 if (!(rdev
->flags
& RADEON_SINGLE_CRTC
)) {
3383 WREG32(R_0003F8_CRTC2_GEN_CNTL
, save
->CRTC2_GEN_CNTL
);
3387 void r100_vga_render_disable(struct radeon_device
*rdev
)
3391 tmp
= RREG8(R_0003C2_GENMO_WT
);
3392 WREG8(R_0003C2_GENMO_WT
, C_0003C2_VGA_RAM_EN
& tmp
);
3395 static void r100_debugfs(struct radeon_device
*rdev
)
3399 r
= r100_debugfs_mc_info_init(rdev
);
3401 dev_warn(rdev
->dev
, "Failed to create r100_mc debugfs file.\n");
3404 static void r100_mc_program(struct radeon_device
*rdev
)
3406 struct r100_mc_save save
;
3408 /* Stops all mc clients */
3409 r100_mc_stop(rdev
, &save
);
3410 if (rdev
->flags
& RADEON_IS_AGP
) {
3411 WREG32(R_00014C_MC_AGP_LOCATION
,
3412 S_00014C_MC_AGP_START(rdev
->mc
.gtt_start
>> 16) |
3413 S_00014C_MC_AGP_TOP(rdev
->mc
.gtt_end
>> 16));
3414 WREG32(R_000170_AGP_BASE
, lower_32_bits(rdev
->mc
.agp_base
));
3415 if (rdev
->family
> CHIP_RV200
)
3416 WREG32(R_00015C_AGP_BASE_2
,
3417 upper_32_bits(rdev
->mc
.agp_base
) & 0xff);
3419 WREG32(R_00014C_MC_AGP_LOCATION
, 0x0FFFFFFF);
3420 WREG32(R_000170_AGP_BASE
, 0);
3421 if (rdev
->family
> CHIP_RV200
)
3422 WREG32(R_00015C_AGP_BASE_2
, 0);
3424 /* Wait for mc idle */
3425 if (r100_mc_wait_for_idle(rdev
))
3426 dev_warn(rdev
->dev
, "Wait for MC idle timeout.\n");
3427 /* Program MC, should be a 32bits limited address space */
3428 WREG32(R_000148_MC_FB_LOCATION
,
3429 S_000148_MC_FB_START(rdev
->mc
.vram_start
>> 16) |
3430 S_000148_MC_FB_TOP(rdev
->mc
.vram_end
>> 16));
3431 r100_mc_resume(rdev
, &save
);
3434 void r100_clock_startup(struct radeon_device
*rdev
)
3438 if (radeon_dynclks
!= -1 && radeon_dynclks
)
3439 radeon_legacy_set_clock_gating(rdev
, 1);
3440 /* We need to force on some of the block */
3441 tmp
= RREG32_PLL(R_00000D_SCLK_CNTL
);
3442 tmp
|= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3443 if ((rdev
->family
== CHIP_RV250
) || (rdev
->family
== CHIP_RV280
))
3444 tmp
|= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3445 WREG32_PLL(R_00000D_SCLK_CNTL
, tmp
);
3448 static int r100_startup(struct radeon_device
*rdev
)
3452 /* set common regs */
3453 r100_set_common_regs(rdev
);
3455 r100_mc_program(rdev
);
3457 r100_clock_startup(rdev
);
3458 /* Initialize GPU configuration (# pipes, ...) */
3459 // r100_gpu_init(rdev);
3460 /* Initialize GART (initialize after TTM so we can allocate
3461 * memory through TTM but finalize after TTM) */
3462 r100_enable_bm(rdev
);
3463 if (rdev
->flags
& RADEON_IS_PCI
) {
3464 r
= r100_pci_gart_enable(rdev
);
3470 rdev
->config
.r100
.hdp_cntl
= RREG32(RADEON_HOST_PATH_CNTL
);
3471 /* 1M ring buffer */
3472 r
= r100_cp_init(rdev
, 1024 * 1024);
3474 dev_err(rdev
->dev
, "failled initializing CP (%d).\n", r
);
3477 r
= r100_wb_init(rdev
);
3479 dev_err(rdev
->dev
, "failled initializing WB (%d).\n", r
);
3480 r
= r100_ib_init(rdev
);
3482 dev_err(rdev
->dev
, "failled initializing IB (%d).\n", r
);
3488 int r100_resume(struct radeon_device
*rdev
)
3490 /* Make sur GART are not working */
3491 if (rdev
->flags
& RADEON_IS_PCI
)
3492 r100_pci_gart_disable(rdev
);
3493 /* Resume clock before doing reset */
3494 r100_clock_startup(rdev
);
3495 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3496 if (radeon_asic_reset(rdev
)) {
3497 dev_warn(rdev
->dev
, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3498 RREG32(R_000E40_RBBM_STATUS
),
3499 RREG32(R_0007C0_CP_STAT
));
3502 radeon_combios_asic_init(rdev
->ddev
);
3503 /* Resume clock after posting */
3504 r100_clock_startup(rdev
);
3505 /* Initialize surface registers */
3506 radeon_surface_init(rdev
);
3507 return r100_startup(rdev
);
3510 int r100_suspend(struct radeon_device
*rdev
)
3512 r100_cp_disable(rdev
);
3513 r100_wb_disable(rdev
);
3514 r100_irq_disable(rdev
);
3515 if (rdev
->flags
& RADEON_IS_PCI
)
3516 r100_pci_gart_disable(rdev
);
3520 void r100_fini(struct radeon_device
*rdev
)
3522 radeon_pm_fini(rdev
);
3526 radeon_gem_fini(rdev
);
3527 if (rdev
->flags
& RADEON_IS_PCI
)
3528 r100_pci_gart_fini(rdev
);
3529 radeon_agp_fini(rdev
);
3530 radeon_irq_kms_fini(rdev
);
3531 radeon_fence_driver_fini(rdev
);
3532 radeon_bo_fini(rdev
);
3533 radeon_atombios_fini(rdev
);
3538 int r100_init(struct radeon_device
*rdev
)
3542 /* Register debugfs file specific to this group of asics */
3545 r100_vga_render_disable(rdev
);
3546 /* Initialize scratch registers */
3547 radeon_scratch_init(rdev
);
3548 /* Initialize surface registers */
3549 radeon_surface_init(rdev
);
3550 /* TODO: disable VGA need to use VGA request */
3552 if (!radeon_get_bios(rdev
)) {
3553 if (ASIC_IS_AVIVO(rdev
))
3556 if (rdev
->is_atom_bios
) {
3557 dev_err(rdev
->dev
, "Expecting combios for RS400/RS480 GPU\n");
3560 r
= radeon_combios_init(rdev
);
3564 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3565 if (radeon_asic_reset(rdev
)) {
3567 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3568 RREG32(R_000E40_RBBM_STATUS
),
3569 RREG32(R_0007C0_CP_STAT
));
3571 /* check if cards are posted or not */
3572 if (radeon_boot_test_post_card(rdev
) == false)
3574 /* Set asic errata */
3576 /* Initialize clocks */
3577 radeon_get_clock_info(rdev
->ddev
);
3578 /* Initialize power management */
3579 radeon_pm_init(rdev
);
3580 /* initialize AGP */
3581 if (rdev
->flags
& RADEON_IS_AGP
) {
3582 r
= radeon_agp_init(rdev
);
3584 radeon_agp_disable(rdev
);
3587 /* initialize VRAM */
3590 r
= radeon_fence_driver_init(rdev
);
3593 r
= radeon_irq_kms_init(rdev
);
3596 /* Memory manager */
3597 r
= radeon_bo_init(rdev
);
3600 if (rdev
->flags
& RADEON_IS_PCI
) {
3601 r
= r100_pci_gart_init(rdev
);
3605 r100_set_safe_registers(rdev
);
3606 rdev
->accel_working
= true;
3607 r
= r100_startup(rdev
);
3609 /* Somethings want wront with the accel init stop accel */
3610 dev_err(rdev
->dev
, "Disabling GPU acceleration\n");
3614 radeon_irq_kms_fini(rdev
);
3615 if (rdev
->flags
& RADEON_IS_PCI
)
3616 r100_pci_gart_fini(rdev
);
3617 rdev
->accel_working
= false;