2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
55 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
56 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
57 struct drm_i915_gem_pwrite
*args
,
58 struct drm_file
*file_priv
);
59 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
62 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
66 i915_gem_object_put_pages(struct drm_gem_object
*obj
);
68 static LIST_HEAD(shrink_list
);
69 static DEFINE_SPINLOCK(shrink_list_lock
);
71 /* some bookkeeping */
72 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
75 dev_priv
->mm
.object_count
++;
76 dev_priv
->mm
.object_memory
+= size
;
79 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
82 dev_priv
->mm
.object_count
--;
83 dev_priv
->mm
.object_memory
-= size
;
86 static void i915_gem_info_add_gtt(struct drm_i915_private
*dev_priv
,
89 dev_priv
->mm
.gtt_count
++;
90 dev_priv
->mm
.gtt_memory
+= size
;
93 static void i915_gem_info_remove_gtt(struct drm_i915_private
*dev_priv
,
96 dev_priv
->mm
.gtt_count
--;
97 dev_priv
->mm
.gtt_memory
-= size
;
100 static void i915_gem_info_add_pin(struct drm_i915_private
*dev_priv
,
103 dev_priv
->mm
.pin_count
++;
104 dev_priv
->mm
.pin_memory
+= size
;
107 static void i915_gem_info_remove_pin(struct drm_i915_private
*dev_priv
,
110 dev_priv
->mm
.pin_count
--;
111 dev_priv
->mm
.pin_memory
-= size
;
115 i915_gem_check_is_wedged(struct drm_device
*dev
)
117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
118 struct completion
*x
= &dev_priv
->error_completion
;
122 if (!atomic_read(&dev_priv
->mm
.wedged
))
125 ret
= wait_for_completion_interruptible(x
);
129 /* Success, we reset the GPU! */
130 if (!atomic_read(&dev_priv
->mm
.wedged
))
133 /* GPU is hung, bump the completion count to account for
134 * the token we just consumed so that we never hit zero and
135 * end up waiting upon a subsequent completion event that
138 spin_lock_irqsave(&x
->wait
.lock
, flags
);
140 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
144 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 ret
= i915_gem_check_is_wedged(dev
);
153 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
157 if (atomic_read(&dev_priv
->mm
.wedged
)) {
158 mutex_unlock(&dev
->struct_mutex
);
162 WARN_ON(i915_verify_lists(dev
));
167 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
169 return obj_priv
->gtt_space
&&
171 obj_priv
->pin_count
== 0;
174 int i915_gem_do_init(struct drm_device
*dev
,
178 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
181 (start
& (PAGE_SIZE
- 1)) != 0 ||
182 (end
& (PAGE_SIZE
- 1)) != 0) {
186 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
189 dev_priv
->mm
.gtt_total
= end
- start
;
195 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
196 struct drm_file
*file_priv
)
198 struct drm_i915_gem_init
*args
= data
;
201 mutex_lock(&dev
->struct_mutex
);
202 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
203 mutex_unlock(&dev
->struct_mutex
);
209 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
210 struct drm_file
*file_priv
)
212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
213 struct drm_i915_gem_get_aperture
*args
= data
;
215 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
218 mutex_lock(&dev
->struct_mutex
);
219 args
->aper_size
= dev_priv
->mm
.gtt_total
;
220 args
->aper_available_size
= args
->aper_size
- dev_priv
->mm
.pin_memory
;
221 mutex_unlock(&dev
->struct_mutex
);
228 * Creates a new mm object and returns a handle to it.
231 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
232 struct drm_file
*file_priv
)
234 struct drm_i915_gem_create
*args
= data
;
235 struct drm_gem_object
*obj
;
239 args
->size
= roundup(args
->size
, PAGE_SIZE
);
241 /* Allocate the new object */
242 obj
= i915_gem_alloc_object(dev
, args
->size
);
246 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
248 drm_gem_object_release(obj
);
249 i915_gem_info_remove_obj(dev
->dev_private
, obj
->size
);
254 /* drop reference from allocate - handle holds it now */
255 drm_gem_object_unreference(obj
);
256 trace_i915_gem_object_create(obj
);
258 args
->handle
= handle
;
263 fast_shmem_read(struct page
**pages
,
264 loff_t page_base
, int page_offset
,
271 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
274 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
275 kunmap_atomic(vaddr
, KM_USER0
);
283 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
285 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
286 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
288 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
289 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
293 slow_shmem_copy(struct page
*dst_page
,
295 struct page
*src_page
,
299 char *dst_vaddr
, *src_vaddr
;
301 dst_vaddr
= kmap(dst_page
);
302 src_vaddr
= kmap(src_page
);
304 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
311 slow_shmem_bit17_copy(struct page
*gpu_page
,
313 struct page
*cpu_page
,
318 char *gpu_vaddr
, *cpu_vaddr
;
320 /* Use the unswizzled path if this page isn't affected. */
321 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
323 return slow_shmem_copy(cpu_page
, cpu_offset
,
324 gpu_page
, gpu_offset
, length
);
326 return slow_shmem_copy(gpu_page
, gpu_offset
,
327 cpu_page
, cpu_offset
, length
);
330 gpu_vaddr
= kmap(gpu_page
);
331 cpu_vaddr
= kmap(cpu_page
);
333 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
334 * XORing with the other bits (A9 for Y, A9 and A10 for X)
337 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
338 int this_length
= min(cacheline_end
- gpu_offset
, length
);
339 int swizzled_gpu_offset
= gpu_offset
^ 64;
342 memcpy(cpu_vaddr
+ cpu_offset
,
343 gpu_vaddr
+ swizzled_gpu_offset
,
346 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
347 cpu_vaddr
+ cpu_offset
,
350 cpu_offset
+= this_length
;
351 gpu_offset
+= this_length
;
352 length
-= this_length
;
360 * This is the fast shmem pread path, which attempts to copy_from_user directly
361 * from the backing pages of the object to the user's address space. On a
362 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
365 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
366 struct drm_i915_gem_pread
*args
,
367 struct drm_file
*file_priv
)
369 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
371 loff_t offset
, page_base
;
372 char __user
*user_data
;
373 int page_offset
, page_length
;
376 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
379 ret
= i915_mutex_lock_interruptible(dev
);
383 ret
= i915_gem_object_get_pages(obj
, 0);
387 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
392 obj_priv
= to_intel_bo(obj
);
393 offset
= args
->offset
;
396 /* Operation in this page
398 * page_base = page offset within aperture
399 * page_offset = offset within page
400 * page_length = bytes to copy for this page
402 page_base
= (offset
& ~(PAGE_SIZE
-1));
403 page_offset
= offset
& (PAGE_SIZE
-1);
404 page_length
= remain
;
405 if ((page_offset
+ remain
) > PAGE_SIZE
)
406 page_length
= PAGE_SIZE
- page_offset
;
408 ret
= fast_shmem_read(obj_priv
->pages
,
409 page_base
, page_offset
,
410 user_data
, page_length
);
414 remain
-= page_length
;
415 user_data
+= page_length
;
416 offset
+= page_length
;
420 i915_gem_object_put_pages(obj
);
422 mutex_unlock(&dev
->struct_mutex
);
428 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
432 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
434 /* If we've insufficient memory to map in the pages, attempt
435 * to make some space by throwing out some old buffers.
437 if (ret
== -ENOMEM
) {
438 struct drm_device
*dev
= obj
->dev
;
440 ret
= i915_gem_evict_something(dev
, obj
->size
,
441 i915_gem_get_gtt_alignment(obj
));
445 ret
= i915_gem_object_get_pages(obj
, 0);
452 * This is the fallback shmem pread path, which allocates temporary storage
453 * in kernel space to copy_to_user into outside of the struct_mutex, so we
454 * can copy out of the object's backing pages while holding the struct mutex
455 * and not take page faults.
458 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
459 struct drm_i915_gem_pread
*args
,
460 struct drm_file
*file_priv
)
462 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
463 struct mm_struct
*mm
= current
->mm
;
464 struct page
**user_pages
;
466 loff_t offset
, pinned_pages
, i
;
467 loff_t first_data_page
, last_data_page
, num_pages
;
468 int shmem_page_index
, shmem_page_offset
;
469 int data_page_index
, data_page_offset
;
472 uint64_t data_ptr
= args
->data_ptr
;
473 int do_bit17_swizzling
;
477 /* Pin the user pages containing the data. We can't fault while
478 * holding the struct mutex, yet we want to hold it while
479 * dereferencing the user data.
481 first_data_page
= data_ptr
/ PAGE_SIZE
;
482 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
483 num_pages
= last_data_page
- first_data_page
+ 1;
485 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
486 if (user_pages
== NULL
)
489 down_read(&mm
->mmap_sem
);
490 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
491 num_pages
, 1, 0, user_pages
, NULL
);
492 up_read(&mm
->mmap_sem
);
493 if (pinned_pages
< num_pages
) {
495 goto fail_put_user_pages
;
498 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
500 ret
= i915_mutex_lock_interruptible(dev
);
502 goto fail_put_user_pages
;
504 ret
= i915_gem_object_get_pages_or_evict(obj
);
508 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
513 obj_priv
= to_intel_bo(obj
);
514 offset
= args
->offset
;
517 /* Operation in this page
519 * shmem_page_index = page number within shmem file
520 * shmem_page_offset = offset within page in shmem file
521 * data_page_index = page number in get_user_pages return
522 * data_page_offset = offset with data_page_index page.
523 * page_length = bytes to copy for this page
525 shmem_page_index
= offset
/ PAGE_SIZE
;
526 shmem_page_offset
= offset
& ~PAGE_MASK
;
527 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
528 data_page_offset
= data_ptr
& ~PAGE_MASK
;
530 page_length
= remain
;
531 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
532 page_length
= PAGE_SIZE
- shmem_page_offset
;
533 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
534 page_length
= PAGE_SIZE
- data_page_offset
;
536 if (do_bit17_swizzling
) {
537 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
539 user_pages
[data_page_index
],
544 slow_shmem_copy(user_pages
[data_page_index
],
546 obj_priv
->pages
[shmem_page_index
],
551 remain
-= page_length
;
552 data_ptr
+= page_length
;
553 offset
+= page_length
;
557 i915_gem_object_put_pages(obj
);
559 mutex_unlock(&dev
->struct_mutex
);
561 for (i
= 0; i
< pinned_pages
; i
++) {
562 SetPageDirty(user_pages
[i
]);
563 page_cache_release(user_pages
[i
]);
565 drm_free_large(user_pages
);
571 * Reads data from the object referenced by handle.
573 * On error, the contents of *data are undefined.
576 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
577 struct drm_file
*file_priv
)
579 struct drm_i915_gem_pread
*args
= data
;
580 struct drm_gem_object
*obj
;
581 struct drm_i915_gem_object
*obj_priv
;
584 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
587 obj_priv
= to_intel_bo(obj
);
589 /* Bounds check source. */
590 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
598 if (!access_ok(VERIFY_WRITE
,
599 (char __user
*)(uintptr_t)args
->data_ptr
,
605 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
606 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
608 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
610 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
615 drm_gem_object_unreference_unlocked(obj
);
619 /* This is the fast write path which cannot handle
620 * page faults in the source data
624 fast_user_write(struct io_mapping
*mapping
,
625 loff_t page_base
, int page_offset
,
626 char __user
*user_data
,
630 unsigned long unwritten
;
632 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
633 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
635 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
641 /* Here's the write path which can sleep for
646 slow_kernel_write(struct io_mapping
*mapping
,
647 loff_t gtt_base
, int gtt_offset
,
648 struct page
*user_page
, int user_offset
,
651 char __iomem
*dst_vaddr
;
654 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
655 src_vaddr
= kmap(user_page
);
657 memcpy_toio(dst_vaddr
+ gtt_offset
,
658 src_vaddr
+ user_offset
,
662 io_mapping_unmap(dst_vaddr
);
666 fast_shmem_write(struct page
**pages
,
667 loff_t page_base
, int page_offset
,
672 unsigned long unwritten
;
674 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
677 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
678 kunmap_atomic(vaddr
, KM_USER0
);
686 * This is the fast pwrite path, where we copy the data directly from the
687 * user into the GTT, uncached.
690 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
691 struct drm_i915_gem_pwrite
*args
,
692 struct drm_file
*file_priv
)
694 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
695 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
697 loff_t offset
, page_base
;
698 char __user
*user_data
;
699 int page_offset
, page_length
;
702 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
705 ret
= i915_mutex_lock_interruptible(dev
);
709 ret
= i915_gem_object_pin(obj
, 0);
711 mutex_unlock(&dev
->struct_mutex
);
714 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
718 obj_priv
= to_intel_bo(obj
);
719 offset
= obj_priv
->gtt_offset
+ args
->offset
;
722 /* Operation in this page
724 * page_base = page offset within aperture
725 * page_offset = offset within page
726 * page_length = bytes to copy for this page
728 page_base
= (offset
& ~(PAGE_SIZE
-1));
729 page_offset
= offset
& (PAGE_SIZE
-1);
730 page_length
= remain
;
731 if ((page_offset
+ remain
) > PAGE_SIZE
)
732 page_length
= PAGE_SIZE
- page_offset
;
734 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
735 page_offset
, user_data
, page_length
);
737 /* If we get a fault while copying data, then (presumably) our
738 * source page isn't available. Return the error and we'll
739 * retry in the slow path.
744 remain
-= page_length
;
745 user_data
+= page_length
;
746 offset
+= page_length
;
750 i915_gem_object_unpin(obj
);
751 mutex_unlock(&dev
->struct_mutex
);
757 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
758 * the memory and maps it using kmap_atomic for copying.
760 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
761 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
764 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
765 struct drm_i915_gem_pwrite
*args
,
766 struct drm_file
*file_priv
)
768 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
769 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
771 loff_t gtt_page_base
, offset
;
772 loff_t first_data_page
, last_data_page
, num_pages
;
773 loff_t pinned_pages
, i
;
774 struct page
**user_pages
;
775 struct mm_struct
*mm
= current
->mm
;
776 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
778 uint64_t data_ptr
= args
->data_ptr
;
782 /* Pin the user pages containing the data. We can't fault while
783 * holding the struct mutex, and all of the pwrite implementations
784 * want to hold it while dereferencing the user data.
786 first_data_page
= data_ptr
/ PAGE_SIZE
;
787 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
788 num_pages
= last_data_page
- first_data_page
+ 1;
790 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
791 if (user_pages
== NULL
)
794 down_read(&mm
->mmap_sem
);
795 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
796 num_pages
, 0, 0, user_pages
, NULL
);
797 up_read(&mm
->mmap_sem
);
798 if (pinned_pages
< num_pages
) {
800 goto out_unpin_pages
;
803 ret
= i915_mutex_lock_interruptible(dev
);
805 goto out_unpin_pages
;
807 ret
= i915_gem_object_pin(obj
, 0);
811 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
813 goto out_unpin_object
;
815 obj_priv
= to_intel_bo(obj
);
816 offset
= obj_priv
->gtt_offset
+ args
->offset
;
819 /* Operation in this page
821 * gtt_page_base = page offset within aperture
822 * gtt_page_offset = offset within page in aperture
823 * data_page_index = page number in get_user_pages return
824 * data_page_offset = offset with data_page_index page.
825 * page_length = bytes to copy for this page
827 gtt_page_base
= offset
& PAGE_MASK
;
828 gtt_page_offset
= offset
& ~PAGE_MASK
;
829 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
830 data_page_offset
= data_ptr
& ~PAGE_MASK
;
832 page_length
= remain
;
833 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
834 page_length
= PAGE_SIZE
- gtt_page_offset
;
835 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
836 page_length
= PAGE_SIZE
- data_page_offset
;
838 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
839 gtt_page_base
, gtt_page_offset
,
840 user_pages
[data_page_index
],
844 remain
-= page_length
;
845 offset
+= page_length
;
846 data_ptr
+= page_length
;
850 i915_gem_object_unpin(obj
);
852 mutex_unlock(&dev
->struct_mutex
);
854 for (i
= 0; i
< pinned_pages
; i
++)
855 page_cache_release(user_pages
[i
]);
856 drm_free_large(user_pages
);
862 * This is the fast shmem pwrite path, which attempts to directly
863 * copy_from_user into the kmapped pages backing the object.
866 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
867 struct drm_i915_gem_pwrite
*args
,
868 struct drm_file
*file_priv
)
870 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
872 loff_t offset
, page_base
;
873 char __user
*user_data
;
874 int page_offset
, page_length
;
877 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
880 ret
= i915_mutex_lock_interruptible(dev
);
884 ret
= i915_gem_object_get_pages(obj
, 0);
888 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
892 obj_priv
= to_intel_bo(obj
);
893 offset
= args
->offset
;
897 /* Operation in this page
899 * page_base = page offset within aperture
900 * page_offset = offset within page
901 * page_length = bytes to copy for this page
903 page_base
= (offset
& ~(PAGE_SIZE
-1));
904 page_offset
= offset
& (PAGE_SIZE
-1);
905 page_length
= remain
;
906 if ((page_offset
+ remain
) > PAGE_SIZE
)
907 page_length
= PAGE_SIZE
- page_offset
;
909 ret
= fast_shmem_write(obj_priv
->pages
,
910 page_base
, page_offset
,
911 user_data
, page_length
);
915 remain
-= page_length
;
916 user_data
+= page_length
;
917 offset
+= page_length
;
921 i915_gem_object_put_pages(obj
);
923 mutex_unlock(&dev
->struct_mutex
);
929 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
930 * the memory and maps it using kmap_atomic for copying.
932 * This avoids taking mmap_sem for faulting on the user's address while the
933 * struct_mutex is held.
936 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
937 struct drm_i915_gem_pwrite
*args
,
938 struct drm_file
*file_priv
)
940 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
941 struct mm_struct
*mm
= current
->mm
;
942 struct page
**user_pages
;
944 loff_t offset
, pinned_pages
, i
;
945 loff_t first_data_page
, last_data_page
, num_pages
;
946 int shmem_page_index
, shmem_page_offset
;
947 int data_page_index
, data_page_offset
;
950 uint64_t data_ptr
= args
->data_ptr
;
951 int do_bit17_swizzling
;
955 /* Pin the user pages containing the data. We can't fault while
956 * holding the struct mutex, and all of the pwrite implementations
957 * want to hold it while dereferencing the user data.
959 first_data_page
= data_ptr
/ PAGE_SIZE
;
960 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
961 num_pages
= last_data_page
- first_data_page
+ 1;
963 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
964 if (user_pages
== NULL
)
967 down_read(&mm
->mmap_sem
);
968 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
969 num_pages
, 0, 0, user_pages
, NULL
);
970 up_read(&mm
->mmap_sem
);
971 if (pinned_pages
< num_pages
) {
973 goto fail_put_user_pages
;
976 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
978 ret
= i915_mutex_lock_interruptible(dev
);
980 goto fail_put_user_pages
;
982 ret
= i915_gem_object_get_pages_or_evict(obj
);
986 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
990 obj_priv
= to_intel_bo(obj
);
991 offset
= args
->offset
;
995 /* Operation in this page
997 * shmem_page_index = page number within shmem file
998 * shmem_page_offset = offset within page in shmem file
999 * data_page_index = page number in get_user_pages return
1000 * data_page_offset = offset with data_page_index page.
1001 * page_length = bytes to copy for this page
1003 shmem_page_index
= offset
/ PAGE_SIZE
;
1004 shmem_page_offset
= offset
& ~PAGE_MASK
;
1005 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
1006 data_page_offset
= data_ptr
& ~PAGE_MASK
;
1008 page_length
= remain
;
1009 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
1010 page_length
= PAGE_SIZE
- shmem_page_offset
;
1011 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
1012 page_length
= PAGE_SIZE
- data_page_offset
;
1014 if (do_bit17_swizzling
) {
1015 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
1017 user_pages
[data_page_index
],
1022 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
1024 user_pages
[data_page_index
],
1029 remain
-= page_length
;
1030 data_ptr
+= page_length
;
1031 offset
+= page_length
;
1035 i915_gem_object_put_pages(obj
);
1037 mutex_unlock(&dev
->struct_mutex
);
1038 fail_put_user_pages
:
1039 for (i
= 0; i
< pinned_pages
; i
++)
1040 page_cache_release(user_pages
[i
]);
1041 drm_free_large(user_pages
);
1047 * Writes data to the object referenced by handle.
1049 * On error, the contents of the buffer that were to be modified are undefined.
1052 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1053 struct drm_file
*file_priv
)
1055 struct drm_i915_gem_pwrite
*args
= data
;
1056 struct drm_gem_object
*obj
;
1057 struct drm_i915_gem_object
*obj_priv
;
1060 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1063 obj_priv
= to_intel_bo(obj
);
1065 /* Bounds check destination. */
1066 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
1071 if (args
->size
== 0)
1074 if (!access_ok(VERIFY_READ
,
1075 (char __user
*)(uintptr_t)args
->data_ptr
,
1081 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1082 * it would end up going through the fenced access, and we'll get
1083 * different detiling behavior between reading and writing.
1084 * pread/pwrite currently are reading and writing from the CPU
1085 * perspective, requiring manual detiling by the client.
1087 if (obj_priv
->phys_obj
)
1088 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
1089 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1090 obj_priv
->gtt_space
&&
1091 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1092 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
1093 if (ret
== -EFAULT
) {
1094 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
1097 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
1098 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
1100 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
1101 if (ret
== -EFAULT
) {
1102 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
1109 DRM_INFO("pwrite failed %d\n", ret
);
1113 drm_gem_object_unreference_unlocked(obj
);
1118 * Called when user space prepares to use an object with the CPU, either
1119 * through the mmap ioctl's mapping or a GTT mapping.
1122 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1123 struct drm_file
*file_priv
)
1125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1126 struct drm_i915_gem_set_domain
*args
= data
;
1127 struct drm_gem_object
*obj
;
1128 struct drm_i915_gem_object
*obj_priv
;
1129 uint32_t read_domains
= args
->read_domains
;
1130 uint32_t write_domain
= args
->write_domain
;
1133 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1136 /* Only handle setting domains to types used by the CPU. */
1137 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1140 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1143 /* Having something in the write domain implies it's in the read
1144 * domain, and only that read domain. Enforce that in the request.
1146 if (write_domain
!= 0 && read_domains
!= write_domain
)
1149 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1152 obj_priv
= to_intel_bo(obj
);
1154 ret
= i915_mutex_lock_interruptible(dev
);
1156 drm_gem_object_unreference_unlocked(obj
);
1160 intel_mark_busy(dev
, obj
);
1162 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1163 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1165 /* Update the LRU on the fence for the CPU access that's
1168 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1169 struct drm_i915_fence_reg
*reg
=
1170 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1171 list_move_tail(®
->lru_list
,
1172 &dev_priv
->mm
.fence_list
);
1175 /* Silently promote "you're not bound, there was nothing to do"
1176 * to success, since the client was just asking us to
1177 * make sure everything was done.
1182 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1185 /* Maintain LRU order of "inactive" objects */
1186 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1187 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1189 drm_gem_object_unreference(obj
);
1190 mutex_unlock(&dev
->struct_mutex
);
1195 * Called when user space has done writes to this buffer
1198 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1199 struct drm_file
*file_priv
)
1201 struct drm_i915_gem_sw_finish
*args
= data
;
1202 struct drm_gem_object
*obj
;
1205 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1208 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1212 ret
= i915_mutex_lock_interruptible(dev
);
1214 drm_gem_object_unreference_unlocked(obj
);
1218 /* Pinned buffers may be scanout, so flush the cache */
1219 if (to_intel_bo(obj
)->pin_count
)
1220 i915_gem_object_flush_cpu_write_domain(obj
);
1222 drm_gem_object_unreference(obj
);
1223 mutex_unlock(&dev
->struct_mutex
);
1228 * Maps the contents of an object, returning the address it is mapped
1231 * While the mapping holds a reference on the contents of the object, it doesn't
1232 * imply a ref on the object itself.
1235 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1236 struct drm_file
*file_priv
)
1238 struct drm_i915_gem_mmap
*args
= data
;
1239 struct drm_gem_object
*obj
;
1243 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1246 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1250 offset
= args
->offset
;
1252 down_write(¤t
->mm
->mmap_sem
);
1253 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1254 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1256 up_write(¤t
->mm
->mmap_sem
);
1257 drm_gem_object_unreference_unlocked(obj
);
1258 if (IS_ERR((void *)addr
))
1261 args
->addr_ptr
= (uint64_t) addr
;
1267 * i915_gem_fault - fault a page into the GTT
1268 * vma: VMA in question
1271 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1272 * from userspace. The fault handler takes care of binding the object to
1273 * the GTT (if needed), allocating and programming a fence register (again,
1274 * only if needed based on whether the old reg is still valid or the object
1275 * is tiled) and inserting a new PTE into the faulting process.
1277 * Note that the faulting process may involve evicting existing objects
1278 * from the GTT and/or fence registers to make room. So performance may
1279 * suffer if the GTT working set is large or there are few fence registers
1282 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1284 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1285 struct drm_device
*dev
= obj
->dev
;
1286 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1287 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1288 pgoff_t page_offset
;
1291 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1293 /* We don't use vmf->pgoff since that has the fake offset */
1294 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1297 /* Now bind it into the GTT if needed */
1298 mutex_lock(&dev
->struct_mutex
);
1299 if (!obj_priv
->gtt_space
) {
1300 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1304 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1309 /* Need a new fence register? */
1310 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1311 ret
= i915_gem_object_get_fence_reg(obj
, true);
1316 if (i915_gem_object_is_inactive(obj_priv
))
1317 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1319 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1322 /* Finally, remap it using the new GTT offset */
1323 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1325 mutex_unlock(&dev
->struct_mutex
);
1330 return VM_FAULT_NOPAGE
;
1333 return VM_FAULT_OOM
;
1335 return VM_FAULT_SIGBUS
;
1340 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1341 * @obj: obj in question
1343 * GEM memory mapping works by handing back to userspace a fake mmap offset
1344 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1345 * up the object based on the offset and sets up the various memory mapping
1348 * This routine allocates and attaches a fake offset for @obj.
1351 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1353 struct drm_device
*dev
= obj
->dev
;
1354 struct drm_gem_mm
*mm
= dev
->mm_private
;
1355 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1356 struct drm_map_list
*list
;
1357 struct drm_local_map
*map
;
1360 /* Set the object up for mmap'ing */
1361 list
= &obj
->map_list
;
1362 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1367 map
->type
= _DRM_GEM
;
1368 map
->size
= obj
->size
;
1371 /* Get a DRM GEM mmap offset allocated... */
1372 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1373 obj
->size
/ PAGE_SIZE
, 0, 0);
1374 if (!list
->file_offset_node
) {
1375 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1380 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1381 obj
->size
/ PAGE_SIZE
, 0);
1382 if (!list
->file_offset_node
) {
1387 list
->hash
.key
= list
->file_offset_node
->start
;
1388 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1390 DRM_ERROR("failed to add to map hash\n");
1394 /* By now we should be all set, any drm_mmap request on the offset
1395 * below will get to our mmap & fault handler */
1396 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1401 drm_mm_put_block(list
->file_offset_node
);
1409 * i915_gem_release_mmap - remove physical page mappings
1410 * @obj: obj in question
1412 * Preserve the reservation of the mmapping with the DRM core code, but
1413 * relinquish ownership of the pages back to the system.
1415 * It is vital that we remove the page mapping if we have mapped a tiled
1416 * object through the GTT and then lose the fence register due to
1417 * resource pressure. Similarly if the object has been moved out of the
1418 * aperture, than pages mapped into userspace must be revoked. Removing the
1419 * mapping will then trigger a page fault on the next user access, allowing
1420 * fixup by i915_gem_fault().
1423 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1425 struct drm_device
*dev
= obj
->dev
;
1426 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1428 if (dev
->dev_mapping
)
1429 unmap_mapping_range(dev
->dev_mapping
,
1430 obj_priv
->mmap_offset
, obj
->size
, 1);
1434 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1436 struct drm_device
*dev
= obj
->dev
;
1437 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1438 struct drm_gem_mm
*mm
= dev
->mm_private
;
1439 struct drm_map_list
*list
;
1441 list
= &obj
->map_list
;
1442 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1444 if (list
->file_offset_node
) {
1445 drm_mm_put_block(list
->file_offset_node
);
1446 list
->file_offset_node
= NULL
;
1454 obj_priv
->mmap_offset
= 0;
1458 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1459 * @obj: object to check
1461 * Return the required GTT alignment for an object, taking into account
1462 * potential fence register mapping if needed.
1465 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1467 struct drm_device
*dev
= obj
->dev
;
1468 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1472 * Minimum alignment is 4k (GTT page size), but might be greater
1473 * if a fence register is needed for the object.
1475 if (INTEL_INFO(dev
)->gen
>= 4 || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1479 * Previous chips need to be aligned to the size of the smallest
1480 * fence register that can contain the object.
1482 if (INTEL_INFO(dev
)->gen
== 3)
1487 for (i
= start
; i
< obj
->size
; i
<<= 1)
1494 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1496 * @data: GTT mapping ioctl data
1497 * @file_priv: GEM object info
1499 * Simply returns the fake offset to userspace so it can mmap it.
1500 * The mmap call will end up in drm_gem_mmap(), which will set things
1501 * up so we can get faults in the handler above.
1503 * The fault handler will take care of binding the object into the GTT
1504 * (since it may have been evicted to make room for something), allocating
1505 * a fence register, and mapping the appropriate aperture address into
1509 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1510 struct drm_file
*file_priv
)
1512 struct drm_i915_gem_mmap_gtt
*args
= data
;
1513 struct drm_gem_object
*obj
;
1514 struct drm_i915_gem_object
*obj_priv
;
1517 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1520 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1524 ret
= i915_mutex_lock_interruptible(dev
);
1526 drm_gem_object_unreference_unlocked(obj
);
1530 obj_priv
= to_intel_bo(obj
);
1532 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1533 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1534 drm_gem_object_unreference(obj
);
1535 mutex_unlock(&dev
->struct_mutex
);
1540 if (!obj_priv
->mmap_offset
) {
1541 ret
= i915_gem_create_mmap_offset(obj
);
1543 drm_gem_object_unreference(obj
);
1544 mutex_unlock(&dev
->struct_mutex
);
1549 args
->offset
= obj_priv
->mmap_offset
;
1552 * Pull it into the GTT so that we have a page list (makes the
1553 * initial fault faster and any subsequent flushing possible).
1555 if (!obj_priv
->agp_mem
) {
1556 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1558 drm_gem_object_unreference(obj
);
1559 mutex_unlock(&dev
->struct_mutex
);
1564 drm_gem_object_unreference(obj
);
1565 mutex_unlock(&dev
->struct_mutex
);
1571 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1573 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1574 int page_count
= obj
->size
/ PAGE_SIZE
;
1577 BUG_ON(obj_priv
->pages_refcount
== 0);
1578 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1580 if (--obj_priv
->pages_refcount
!= 0)
1583 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1584 i915_gem_object_save_bit_17_swizzle(obj
);
1586 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1587 obj_priv
->dirty
= 0;
1589 for (i
= 0; i
< page_count
; i
++) {
1590 if (obj_priv
->dirty
)
1591 set_page_dirty(obj_priv
->pages
[i
]);
1593 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1594 mark_page_accessed(obj_priv
->pages
[i
]);
1596 page_cache_release(obj_priv
->pages
[i
]);
1598 obj_priv
->dirty
= 0;
1600 drm_free_large(obj_priv
->pages
);
1601 obj_priv
->pages
= NULL
;
1605 i915_gem_next_request_seqno(struct drm_device
*dev
,
1606 struct intel_ring_buffer
*ring
)
1608 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1610 ring
->outstanding_lazy_request
= true;
1611 return dev_priv
->next_seqno
;
1615 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1616 struct intel_ring_buffer
*ring
)
1618 struct drm_device
*dev
= obj
->dev
;
1619 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1620 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1622 BUG_ON(ring
== NULL
);
1623 obj_priv
->ring
= ring
;
1625 /* Add a reference if we're newly entering the active list. */
1626 if (!obj_priv
->active
) {
1627 drm_gem_object_reference(obj
);
1628 obj_priv
->active
= 1;
1631 /* Move from whatever list we were on to the tail of execution. */
1632 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1633 obj_priv
->last_rendering_seqno
= seqno
;
1637 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1639 struct drm_device
*dev
= obj
->dev
;
1640 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1641 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1643 BUG_ON(!obj_priv
->active
);
1644 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1645 obj_priv
->last_rendering_seqno
= 0;
1648 /* Immediately discard the backing storage */
1650 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1652 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1653 struct inode
*inode
;
1655 /* Our goal here is to return as much of the memory as
1656 * is possible back to the system as we are called from OOM.
1657 * To do this we must instruct the shmfs to drop all of its
1658 * backing pages, *now*. Here we mirror the actions taken
1659 * when by shmem_delete_inode() to release the backing store.
1661 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1662 truncate_inode_pages(inode
->i_mapping
, 0);
1663 if (inode
->i_op
->truncate_range
)
1664 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1666 obj_priv
->madv
= __I915_MADV_PURGED
;
1670 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1672 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1676 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1678 struct drm_device
*dev
= obj
->dev
;
1679 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1680 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1682 if (obj_priv
->pin_count
!= 0)
1683 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.pinned_list
);
1685 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1687 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1689 obj_priv
->last_rendering_seqno
= 0;
1690 obj_priv
->ring
= NULL
;
1691 if (obj_priv
->active
) {
1692 obj_priv
->active
= 0;
1693 drm_gem_object_unreference(obj
);
1695 WARN_ON(i915_verify_lists(dev
));
1699 i915_gem_process_flushing_list(struct drm_device
*dev
,
1700 uint32_t flush_domains
,
1701 struct intel_ring_buffer
*ring
)
1703 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1704 struct drm_i915_gem_object
*obj_priv
, *next
;
1706 list_for_each_entry_safe(obj_priv
, next
,
1707 &dev_priv
->mm
.gpu_write_list
,
1709 struct drm_gem_object
*obj
= &obj_priv
->base
;
1711 if (obj
->write_domain
& flush_domains
&&
1712 obj_priv
->ring
== ring
) {
1713 uint32_t old_write_domain
= obj
->write_domain
;
1715 obj
->write_domain
= 0;
1716 list_del_init(&obj_priv
->gpu_write_list
);
1717 i915_gem_object_move_to_active(obj
, ring
);
1719 /* update the fence lru list */
1720 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1721 struct drm_i915_fence_reg
*reg
=
1722 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1723 list_move_tail(®
->lru_list
,
1724 &dev_priv
->mm
.fence_list
);
1727 trace_i915_gem_object_change_domain(obj
,
1735 i915_add_request(struct drm_device
*dev
,
1736 struct drm_file
*file
,
1737 struct drm_i915_gem_request
*request
,
1738 struct intel_ring_buffer
*ring
)
1740 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1741 struct drm_i915_file_private
*file_priv
= NULL
;
1746 file_priv
= file
->driver_priv
;
1748 if (request
== NULL
) {
1749 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1750 if (request
== NULL
)
1754 seqno
= ring
->add_request(dev
, ring
, 0);
1755 ring
->outstanding_lazy_request
= false;
1757 request
->seqno
= seqno
;
1758 request
->ring
= ring
;
1759 request
->emitted_jiffies
= jiffies
;
1760 was_empty
= list_empty(&ring
->request_list
);
1761 list_add_tail(&request
->list
, &ring
->request_list
);
1764 spin_lock(&file_priv
->mm
.lock
);
1765 request
->file_priv
= file_priv
;
1766 list_add_tail(&request
->client_list
,
1767 &file_priv
->mm
.request_list
);
1768 spin_unlock(&file_priv
->mm
.lock
);
1771 if (!dev_priv
->mm
.suspended
) {
1772 mod_timer(&dev_priv
->hangcheck_timer
,
1773 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1775 queue_delayed_work(dev_priv
->wq
,
1776 &dev_priv
->mm
.retire_work
, HZ
);
1782 * Command execution barrier
1784 * Ensures that all commands in the ring are finished
1785 * before signalling the CPU
1788 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1790 uint32_t flush_domains
= 0;
1792 /* The sampler always gets flushed on i965 (sigh) */
1793 if (INTEL_INFO(dev
)->gen
>= 4)
1794 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1796 ring
->flush(dev
, ring
,
1797 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1801 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1803 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1808 spin_lock(&file_priv
->mm
.lock
);
1809 list_del(&request
->client_list
);
1810 request
->file_priv
= NULL
;
1811 spin_unlock(&file_priv
->mm
.lock
);
1814 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1815 struct intel_ring_buffer
*ring
)
1817 while (!list_empty(&ring
->request_list
)) {
1818 struct drm_i915_gem_request
*request
;
1820 request
= list_first_entry(&ring
->request_list
,
1821 struct drm_i915_gem_request
,
1824 list_del(&request
->list
);
1825 i915_gem_request_remove_from_client(request
);
1829 while (!list_empty(&ring
->active_list
)) {
1830 struct drm_i915_gem_object
*obj_priv
;
1832 obj_priv
= list_first_entry(&ring
->active_list
,
1833 struct drm_i915_gem_object
,
1836 obj_priv
->base
.write_domain
= 0;
1837 list_del_init(&obj_priv
->gpu_write_list
);
1838 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1842 void i915_gem_reset(struct drm_device
*dev
)
1844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1845 struct drm_i915_gem_object
*obj_priv
;
1848 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1850 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1852 /* Remove anything from the flushing lists. The GPU cache is likely
1853 * to be lost on reset along with the data, so simply move the
1854 * lost bo to the inactive list.
1856 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1857 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1858 struct drm_i915_gem_object
,
1861 obj_priv
->base
.write_domain
= 0;
1862 list_del_init(&obj_priv
->gpu_write_list
);
1863 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1866 /* Move everything out of the GPU domains to ensure we do any
1867 * necessary invalidation upon reuse.
1869 list_for_each_entry(obj_priv
,
1870 &dev_priv
->mm
.inactive_list
,
1873 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1876 /* The fence registers are invalidated so clear them out */
1877 for (i
= 0; i
< 16; i
++) {
1878 struct drm_i915_fence_reg
*reg
;
1880 reg
= &dev_priv
->fence_regs
[i
];
1884 i915_gem_clear_fence_reg(reg
->obj
);
1889 * This function clears the request list as sequence numbers are passed.
1892 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1893 struct intel_ring_buffer
*ring
)
1895 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1898 if (!ring
->status_page
.page_addr
||
1899 list_empty(&ring
->request_list
))
1902 WARN_ON(i915_verify_lists(dev
));
1904 seqno
= ring
->get_seqno(dev
, ring
);
1905 while (!list_empty(&ring
->request_list
)) {
1906 struct drm_i915_gem_request
*request
;
1908 request
= list_first_entry(&ring
->request_list
,
1909 struct drm_i915_gem_request
,
1912 if (!i915_seqno_passed(seqno
, request
->seqno
))
1915 trace_i915_gem_request_retire(dev
, request
->seqno
);
1917 list_del(&request
->list
);
1918 i915_gem_request_remove_from_client(request
);
1922 /* Move any buffers on the active list that are no longer referenced
1923 * by the ringbuffer to the flushing/inactive lists as appropriate.
1925 while (!list_empty(&ring
->active_list
)) {
1926 struct drm_gem_object
*obj
;
1927 struct drm_i915_gem_object
*obj_priv
;
1929 obj_priv
= list_first_entry(&ring
->active_list
,
1930 struct drm_i915_gem_object
,
1933 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
1936 obj
= &obj_priv
->base
;
1937 if (obj
->write_domain
!= 0)
1938 i915_gem_object_move_to_flushing(obj
);
1940 i915_gem_object_move_to_inactive(obj
);
1943 if (unlikely (dev_priv
->trace_irq_seqno
&&
1944 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1945 ring
->user_irq_put(dev
, ring
);
1946 dev_priv
->trace_irq_seqno
= 0;
1949 WARN_ON(i915_verify_lists(dev
));
1953 i915_gem_retire_requests(struct drm_device
*dev
)
1955 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1957 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1958 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1960 /* We must be careful that during unbind() we do not
1961 * accidentally infinitely recurse into retire requests.
1963 * retire -> free -> unbind -> wait -> retire_ring
1965 list_for_each_entry_safe(obj_priv
, tmp
,
1966 &dev_priv
->mm
.deferred_free_list
,
1968 i915_gem_free_object_tail(&obj_priv
->base
);
1971 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1973 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1977 i915_gem_retire_work_handler(struct work_struct
*work
)
1979 drm_i915_private_t
*dev_priv
;
1980 struct drm_device
*dev
;
1982 dev_priv
= container_of(work
, drm_i915_private_t
,
1983 mm
.retire_work
.work
);
1984 dev
= dev_priv
->dev
;
1986 /* Come back later if the device is busy... */
1987 if (!mutex_trylock(&dev
->struct_mutex
)) {
1988 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1992 i915_gem_retire_requests(dev
);
1994 if (!dev_priv
->mm
.suspended
&&
1995 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1997 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1998 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1999 mutex_unlock(&dev
->struct_mutex
);
2003 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2004 bool interruptible
, struct intel_ring_buffer
*ring
)
2006 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2012 if (atomic_read(&dev_priv
->mm
.wedged
))
2015 if (ring
->outstanding_lazy_request
) {
2016 seqno
= i915_add_request(dev
, NULL
, NULL
, ring
);
2020 BUG_ON(seqno
== dev_priv
->next_seqno
);
2022 if (!i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)) {
2023 if (HAS_PCH_SPLIT(dev
))
2024 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
2026 ier
= I915_READ(IER
);
2028 DRM_ERROR("something (likely vbetool) disabled "
2029 "interrupts, re-enabling\n");
2030 i915_driver_irq_preinstall(dev
);
2031 i915_driver_irq_postinstall(dev
);
2034 trace_i915_gem_request_wait_begin(dev
, seqno
);
2036 ring
->waiting_gem_seqno
= seqno
;
2037 ring
->user_irq_get(dev
, ring
);
2039 ret
= wait_event_interruptible(ring
->irq_queue
,
2041 ring
->get_seqno(dev
, ring
), seqno
)
2042 || atomic_read(&dev_priv
->mm
.wedged
));
2044 wait_event(ring
->irq_queue
,
2046 ring
->get_seqno(dev
, ring
), seqno
)
2047 || atomic_read(&dev_priv
->mm
.wedged
));
2049 ring
->user_irq_put(dev
, ring
);
2050 ring
->waiting_gem_seqno
= 0;
2052 trace_i915_gem_request_wait_end(dev
, seqno
);
2054 if (atomic_read(&dev_priv
->mm
.wedged
))
2057 if (ret
&& ret
!= -ERESTARTSYS
)
2058 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2059 __func__
, ret
, seqno
, ring
->get_seqno(dev
, ring
),
2060 dev_priv
->next_seqno
);
2062 /* Directly dispatch request retiring. While we have the work queue
2063 * to handle this, the waiter on a request often wants an associated
2064 * buffer to have made it to the inactive list, and we would need
2065 * a separate wait queue to handle that.
2068 i915_gem_retire_requests_ring(dev
, ring
);
2074 * Waits for a sequence number to be signaled, and cleans up the
2075 * request and object lists appropriately for that event.
2078 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2079 struct intel_ring_buffer
*ring
)
2081 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2085 i915_gem_flush_ring(struct drm_device
*dev
,
2086 struct drm_file
*file_priv
,
2087 struct intel_ring_buffer
*ring
,
2088 uint32_t invalidate_domains
,
2089 uint32_t flush_domains
)
2091 ring
->flush(dev
, ring
, invalidate_domains
, flush_domains
);
2092 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2096 i915_gem_flush(struct drm_device
*dev
,
2097 struct drm_file
*file_priv
,
2098 uint32_t invalidate_domains
,
2099 uint32_t flush_domains
,
2100 uint32_t flush_rings
)
2102 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2104 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2105 drm_agp_chipset_flush(dev
);
2107 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2108 if (flush_rings
& RING_RENDER
)
2109 i915_gem_flush_ring(dev
, file_priv
,
2110 &dev_priv
->render_ring
,
2111 invalidate_domains
, flush_domains
);
2112 if (flush_rings
& RING_BSD
)
2113 i915_gem_flush_ring(dev
, file_priv
,
2114 &dev_priv
->bsd_ring
,
2115 invalidate_domains
, flush_domains
);
2120 * Ensures that all rendering to the object has completed and the object is
2121 * safe to unbind from the GTT or access from the CPU.
2124 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2127 struct drm_device
*dev
= obj
->dev
;
2128 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2131 /* This function only exists to support waiting for existing rendering,
2132 * not for emitting required flushes.
2134 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2136 /* If there is rendering queued on the buffer being evicted, wait for
2139 if (obj_priv
->active
) {
2140 ret
= i915_do_wait_request(dev
,
2141 obj_priv
->last_rendering_seqno
,
2152 * Unbinds an object from the GTT aperture.
2155 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2157 struct drm_device
*dev
= obj
->dev
;
2158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2159 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2162 if (obj_priv
->gtt_space
== NULL
)
2165 if (obj_priv
->pin_count
!= 0) {
2166 DRM_ERROR("Attempting to unbind pinned buffer\n");
2170 /* blow away mappings if mapped through GTT */
2171 i915_gem_release_mmap(obj
);
2173 /* Move the object to the CPU domain to ensure that
2174 * any possible CPU writes while it's not in the GTT
2175 * are flushed when we go to remap it. This will
2176 * also ensure that all pending GPU writes are finished
2179 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2180 if (ret
== -ERESTARTSYS
)
2182 /* Continue on if we fail due to EIO, the GPU is hung so we
2183 * should be safe and we need to cleanup or else we might
2184 * cause memory corruption through use-after-free.
2187 i915_gem_clflush_object(obj
);
2188 obj
->read_domains
= obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2191 /* release the fence reg _after_ flushing */
2192 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2193 i915_gem_clear_fence_reg(obj
);
2195 drm_unbind_agp(obj_priv
->agp_mem
);
2196 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2198 i915_gem_object_put_pages(obj
);
2199 BUG_ON(obj_priv
->pages_refcount
);
2201 i915_gem_info_remove_gtt(dev_priv
, obj
->size
);
2202 list_del_init(&obj_priv
->list
);
2204 drm_mm_put_block(obj_priv
->gtt_space
);
2205 obj_priv
->gtt_space
= NULL
;
2207 if (i915_gem_object_is_purgeable(obj_priv
))
2208 i915_gem_object_truncate(obj
);
2210 trace_i915_gem_object_unbind(obj
);
2215 static int i915_ring_idle(struct drm_device
*dev
,
2216 struct intel_ring_buffer
*ring
)
2218 i915_gem_flush_ring(dev
, NULL
, ring
,
2219 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2220 return i915_wait_request(dev
,
2221 i915_gem_next_request_seqno(dev
, ring
),
2226 i915_gpu_idle(struct drm_device
*dev
)
2228 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2232 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2233 list_empty(&dev_priv
->render_ring
.active_list
) &&
2235 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2239 /* Flush everything onto the inactive list. */
2240 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2245 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2254 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2257 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2259 struct address_space
*mapping
;
2260 struct inode
*inode
;
2263 BUG_ON(obj_priv
->pages_refcount
2264 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2266 if (obj_priv
->pages_refcount
++ != 0)
2269 /* Get the list of pages out of our struct file. They'll be pinned
2270 * at this point until we release them.
2272 page_count
= obj
->size
/ PAGE_SIZE
;
2273 BUG_ON(obj_priv
->pages
!= NULL
);
2274 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2275 if (obj_priv
->pages
== NULL
) {
2276 obj_priv
->pages_refcount
--;
2280 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2281 mapping
= inode
->i_mapping
;
2282 for (i
= 0; i
< page_count
; i
++) {
2283 page
= read_cache_page_gfp(mapping
, i
,
2291 obj_priv
->pages
[i
] = page
;
2294 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2295 i915_gem_object_do_bit_17_swizzle(obj
);
2301 page_cache_release(obj_priv
->pages
[i
]);
2303 drm_free_large(obj_priv
->pages
);
2304 obj_priv
->pages
= NULL
;
2305 obj_priv
->pages_refcount
--;
2306 return PTR_ERR(page
);
2309 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2311 struct drm_gem_object
*obj
= reg
->obj
;
2312 struct drm_device
*dev
= obj
->dev
;
2313 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2314 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2315 int regnum
= obj_priv
->fence_reg
;
2318 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2320 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2321 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2322 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2324 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2325 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2326 val
|= I965_FENCE_REG_VALID
;
2328 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2331 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2333 struct drm_gem_object
*obj
= reg
->obj
;
2334 struct drm_device
*dev
= obj
->dev
;
2335 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2336 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2337 int regnum
= obj_priv
->fence_reg
;
2340 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2342 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2343 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2344 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2345 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2346 val
|= I965_FENCE_REG_VALID
;
2348 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2351 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2353 struct drm_gem_object
*obj
= reg
->obj
;
2354 struct drm_device
*dev
= obj
->dev
;
2355 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2356 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2357 int regnum
= obj_priv
->fence_reg
;
2359 uint32_t fence_reg
, val
;
2362 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2363 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2364 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2365 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2369 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2370 HAS_128_BYTE_Y_TILING(dev
))
2375 /* Note: pitch better be a power of two tile widths */
2376 pitch_val
= obj_priv
->stride
/ tile_width
;
2377 pitch_val
= ffs(pitch_val
) - 1;
2379 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2380 HAS_128_BYTE_Y_TILING(dev
))
2381 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2383 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2385 val
= obj_priv
->gtt_offset
;
2386 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2387 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2388 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2389 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2390 val
|= I830_FENCE_REG_VALID
;
2393 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2395 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2396 I915_WRITE(fence_reg
, val
);
2399 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2401 struct drm_gem_object
*obj
= reg
->obj
;
2402 struct drm_device
*dev
= obj
->dev
;
2403 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2404 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2405 int regnum
= obj_priv
->fence_reg
;
2408 uint32_t fence_size_bits
;
2410 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2411 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2412 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2413 __func__
, obj_priv
->gtt_offset
);
2417 pitch_val
= obj_priv
->stride
/ 128;
2418 pitch_val
= ffs(pitch_val
) - 1;
2419 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2421 val
= obj_priv
->gtt_offset
;
2422 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2423 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2424 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2425 WARN_ON(fence_size_bits
& ~0x00000f00);
2426 val
|= fence_size_bits
;
2427 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2428 val
|= I830_FENCE_REG_VALID
;
2430 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2433 static int i915_find_fence_reg(struct drm_device
*dev
,
2436 struct drm_i915_fence_reg
*reg
= NULL
;
2437 struct drm_i915_gem_object
*obj_priv
= NULL
;
2438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2439 struct drm_gem_object
*obj
= NULL
;
2442 /* First try to find a free reg */
2444 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2445 reg
= &dev_priv
->fence_regs
[i
];
2449 obj_priv
= to_intel_bo(reg
->obj
);
2450 if (!obj_priv
->pin_count
)
2457 /* None available, try to steal one or wait for a user to finish */
2458 i
= I915_FENCE_REG_NONE
;
2459 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2462 obj_priv
= to_intel_bo(obj
);
2464 if (obj_priv
->pin_count
)
2468 i
= obj_priv
->fence_reg
;
2472 BUG_ON(i
== I915_FENCE_REG_NONE
);
2474 /* We only have a reference on obj from the active list. put_fence_reg
2475 * might drop that one, causing a use-after-free in it. So hold a
2476 * private reference to obj like the other callers of put_fence_reg
2477 * (set_tiling ioctl) do. */
2478 drm_gem_object_reference(obj
);
2479 ret
= i915_gem_object_put_fence_reg(obj
, interruptible
);
2480 drm_gem_object_unreference(obj
);
2488 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2489 * @obj: object to map through a fence reg
2491 * When mapping objects through the GTT, userspace wants to be able to write
2492 * to them without having to worry about swizzling if the object is tiled.
2494 * This function walks the fence regs looking for a free one for @obj,
2495 * stealing one if it can't find any.
2497 * It then sets up the reg based on the object's properties: address, pitch
2498 * and tiling format.
2501 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2504 struct drm_device
*dev
= obj
->dev
;
2505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2506 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2507 struct drm_i915_fence_reg
*reg
= NULL
;
2510 /* Just update our place in the LRU if our fence is getting used. */
2511 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2512 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2513 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2517 switch (obj_priv
->tiling_mode
) {
2518 case I915_TILING_NONE
:
2519 WARN(1, "allocating a fence for non-tiled object?\n");
2522 if (!obj_priv
->stride
)
2524 WARN((obj_priv
->stride
& (512 - 1)),
2525 "object 0x%08x is X tiled but has non-512B pitch\n",
2526 obj_priv
->gtt_offset
);
2529 if (!obj_priv
->stride
)
2531 WARN((obj_priv
->stride
& (128 - 1)),
2532 "object 0x%08x is Y tiled but has non-128B pitch\n",
2533 obj_priv
->gtt_offset
);
2537 ret
= i915_find_fence_reg(dev
, interruptible
);
2541 obj_priv
->fence_reg
= ret
;
2542 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2543 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2547 switch (INTEL_INFO(dev
)->gen
) {
2549 sandybridge_write_fence_reg(reg
);
2553 i965_write_fence_reg(reg
);
2556 i915_write_fence_reg(reg
);
2559 i830_write_fence_reg(reg
);
2563 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2564 obj_priv
->tiling_mode
);
2570 * i915_gem_clear_fence_reg - clear out fence register info
2571 * @obj: object to clear
2573 * Zeroes out the fence register itself and clears out the associated
2574 * data structures in dev_priv and obj_priv.
2577 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2579 struct drm_device
*dev
= obj
->dev
;
2580 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2581 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2582 struct drm_i915_fence_reg
*reg
=
2583 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2586 switch (INTEL_INFO(dev
)->gen
) {
2588 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2589 (obj_priv
->fence_reg
* 8), 0);
2593 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2596 if (obj_priv
->fence_reg
>= 8)
2597 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2600 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2602 I915_WRITE(fence_reg
, 0);
2607 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2608 list_del_init(®
->lru_list
);
2612 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2613 * to the buffer to finish, and then resets the fence register.
2614 * @obj: tiled object holding a fence register.
2615 * @bool: whether the wait upon the fence is interruptible
2617 * Zeroes out the fence register itself and clears out the associated
2618 * data structures in dev_priv and obj_priv.
2621 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2624 struct drm_device
*dev
= obj
->dev
;
2625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2626 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2627 struct drm_i915_fence_reg
*reg
;
2629 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2632 /* If we've changed tiling, GTT-mappings of the object
2633 * need to re-fault to ensure that the correct fence register
2634 * setup is in place.
2636 i915_gem_release_mmap(obj
);
2638 /* On the i915, GPU access to tiled buffers is via a fence,
2639 * therefore we must wait for any outstanding access to complete
2640 * before clearing the fence.
2642 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2646 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2650 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2657 i915_gem_object_flush_gtt_write_domain(obj
);
2658 i915_gem_clear_fence_reg(obj
);
2664 * Finds free space in the GTT aperture and binds the object there.
2667 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2669 struct drm_device
*dev
= obj
->dev
;
2670 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2671 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2672 struct drm_mm_node
*free_space
;
2673 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2676 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2677 DRM_ERROR("Attempting to bind a purgeable object\n");
2682 alignment
= i915_gem_get_gtt_alignment(obj
);
2683 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2684 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2688 /* If the object is bigger than the entire aperture, reject it early
2689 * before evicting everything in a vain attempt to find space.
2691 if (obj
->size
> dev_priv
->mm
.gtt_total
) {
2692 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2697 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2698 obj
->size
, alignment
, 0);
2699 if (free_space
!= NULL
) {
2700 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2702 if (obj_priv
->gtt_space
!= NULL
)
2703 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2705 if (obj_priv
->gtt_space
== NULL
) {
2706 /* If the gtt is empty and we're still having trouble
2707 * fitting our object in, we're out of memory.
2709 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2716 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2718 drm_mm_put_block(obj_priv
->gtt_space
);
2719 obj_priv
->gtt_space
= NULL
;
2721 if (ret
== -ENOMEM
) {
2722 /* first try to clear up some space from the GTT */
2723 ret
= i915_gem_evict_something(dev
, obj
->size
,
2726 /* now try to shrink everyone else */
2741 /* Create an AGP memory structure pointing at our pages, and bind it
2744 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2746 obj
->size
>> PAGE_SHIFT
,
2747 obj_priv
->gtt_offset
,
2748 obj_priv
->agp_type
);
2749 if (obj_priv
->agp_mem
== NULL
) {
2750 i915_gem_object_put_pages(obj
);
2751 drm_mm_put_block(obj_priv
->gtt_space
);
2752 obj_priv
->gtt_space
= NULL
;
2754 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2761 /* keep track of bounds object by adding it to the inactive list */
2762 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
2763 i915_gem_info_add_gtt(dev_priv
, obj
->size
);
2765 /* Assert that the object is not currently in any GPU domain. As it
2766 * wasn't in the GTT, there shouldn't be any way it could have been in
2769 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2770 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2772 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2778 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2780 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2782 /* If we don't have a page list set up, then we're not pinned
2783 * to GPU, and we can ignore the cache flush because it'll happen
2784 * again at bind time.
2786 if (obj_priv
->pages
== NULL
)
2789 trace_i915_gem_object_clflush(obj
);
2791 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2794 /** Flushes any GPU write domain for the object if it's dirty. */
2796 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2799 struct drm_device
*dev
= obj
->dev
;
2800 uint32_t old_write_domain
;
2802 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2805 /* Queue the GPU write cache flushing we need. */
2806 old_write_domain
= obj
->write_domain
;
2807 i915_gem_flush_ring(dev
, NULL
,
2808 to_intel_bo(obj
)->ring
,
2809 0, obj
->write_domain
);
2810 BUG_ON(obj
->write_domain
);
2812 trace_i915_gem_object_change_domain(obj
,
2819 return i915_gem_object_wait_rendering(obj
, true);
2822 /** Flushes the GTT write domain for the object if it's dirty. */
2824 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2826 uint32_t old_write_domain
;
2828 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2831 /* No actual flushing is required for the GTT write domain. Writes
2832 * to it immediately go to main memory as far as we know, so there's
2833 * no chipset flush. It also doesn't land in render cache.
2835 old_write_domain
= obj
->write_domain
;
2836 obj
->write_domain
= 0;
2838 trace_i915_gem_object_change_domain(obj
,
2843 /** Flushes the CPU write domain for the object if it's dirty. */
2845 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2847 struct drm_device
*dev
= obj
->dev
;
2848 uint32_t old_write_domain
;
2850 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2853 i915_gem_clflush_object(obj
);
2854 drm_agp_chipset_flush(dev
);
2855 old_write_domain
= obj
->write_domain
;
2856 obj
->write_domain
= 0;
2858 trace_i915_gem_object_change_domain(obj
,
2864 * Moves a single object to the GTT read, and possibly write domain.
2866 * This function returns when the move is complete, including waiting on
2870 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2872 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2873 uint32_t old_write_domain
, old_read_domains
;
2876 /* Not valid to be called on unbound objects. */
2877 if (obj_priv
->gtt_space
== NULL
)
2880 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2884 i915_gem_object_flush_cpu_write_domain(obj
);
2887 ret
= i915_gem_object_wait_rendering(obj
, true);
2892 old_write_domain
= obj
->write_domain
;
2893 old_read_domains
= obj
->read_domains
;
2895 /* It should now be out of any other write domains, and we can update
2896 * the domain values for our changes.
2898 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2899 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2901 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2902 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2903 obj_priv
->dirty
= 1;
2906 trace_i915_gem_object_change_domain(obj
,
2914 * Prepare buffer for display plane. Use uninterruptible for possible flush
2915 * wait, as in modesetting process we're not supposed to be interrupted.
2918 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2921 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2922 uint32_t old_read_domains
;
2925 /* Not valid to be called on unbound objects. */
2926 if (obj_priv
->gtt_space
== NULL
)
2929 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2933 /* Currently, we are always called from an non-interruptible context. */
2935 ret
= i915_gem_object_wait_rendering(obj
, false);
2940 i915_gem_object_flush_cpu_write_domain(obj
);
2942 old_read_domains
= obj
->read_domains
;
2943 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2945 trace_i915_gem_object_change_domain(obj
,
2953 * Moves a single object to the CPU read, and possibly write domain.
2955 * This function returns when the move is complete, including waiting on
2959 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2961 uint32_t old_write_domain
, old_read_domains
;
2964 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2968 i915_gem_object_flush_gtt_write_domain(obj
);
2970 /* If we have a partially-valid cache of the object in the CPU,
2971 * finish invalidating it and free the per-page flags.
2973 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2976 ret
= i915_gem_object_wait_rendering(obj
, true);
2981 old_write_domain
= obj
->write_domain
;
2982 old_read_domains
= obj
->read_domains
;
2984 /* Flush the CPU cache if it's still invalid. */
2985 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2986 i915_gem_clflush_object(obj
);
2988 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2991 /* It should now be out of any other write domains, and we can update
2992 * the domain values for our changes.
2994 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2996 /* If we're writing through the CPU, then the GPU read domains will
2997 * need to be invalidated at next use.
3000 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
3001 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
3004 trace_i915_gem_object_change_domain(obj
,
3012 * Set the next domain for the specified object. This
3013 * may not actually perform the necessary flushing/invaliding though,
3014 * as that may want to be batched with other set_domain operations
3016 * This is (we hope) the only really tricky part of gem. The goal
3017 * is fairly simple -- track which caches hold bits of the object
3018 * and make sure they remain coherent. A few concrete examples may
3019 * help to explain how it works. For shorthand, we use the notation
3020 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3021 * a pair of read and write domain masks.
3023 * Case 1: the batch buffer
3029 * 5. Unmapped from GTT
3032 * Let's take these a step at a time
3035 * Pages allocated from the kernel may still have
3036 * cache contents, so we set them to (CPU, CPU) always.
3037 * 2. Written by CPU (using pwrite)
3038 * The pwrite function calls set_domain (CPU, CPU) and
3039 * this function does nothing (as nothing changes)
3041 * This function asserts that the object is not
3042 * currently in any GPU-based read or write domains
3044 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3045 * As write_domain is zero, this function adds in the
3046 * current read domains (CPU+COMMAND, 0).
3047 * flush_domains is set to CPU.
3048 * invalidate_domains is set to COMMAND
3049 * clflush is run to get data out of the CPU caches
3050 * then i915_dev_set_domain calls i915_gem_flush to
3051 * emit an MI_FLUSH and drm_agp_chipset_flush
3052 * 5. Unmapped from GTT
3053 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3054 * flush_domains and invalidate_domains end up both zero
3055 * so no flushing/invalidating happens
3059 * Case 2: The shared render buffer
3063 * 3. Read/written by GPU
3064 * 4. set_domain to (CPU,CPU)
3065 * 5. Read/written by CPU
3066 * 6. Read/written by GPU
3069 * Same as last example, (CPU, CPU)
3071 * Nothing changes (assertions find that it is not in the GPU)
3072 * 3. Read/written by GPU
3073 * execbuffer calls set_domain (RENDER, RENDER)
3074 * flush_domains gets CPU
3075 * invalidate_domains gets GPU
3077 * MI_FLUSH and drm_agp_chipset_flush
3078 * 4. set_domain (CPU, CPU)
3079 * flush_domains gets GPU
3080 * invalidate_domains gets CPU
3081 * wait_rendering (obj) to make sure all drawing is complete.
3082 * This will include an MI_FLUSH to get the data from GPU
3084 * clflush (obj) to invalidate the CPU cache
3085 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3086 * 5. Read/written by CPU
3087 * cache lines are loaded and dirtied
3088 * 6. Read written by GPU
3089 * Same as last GPU access
3091 * Case 3: The constant buffer
3096 * 4. Updated (written) by CPU again
3105 * flush_domains = CPU
3106 * invalidate_domains = RENDER
3109 * drm_agp_chipset_flush
3110 * 4. Updated (written) by CPU again
3112 * flush_domains = 0 (no previous write domain)
3113 * invalidate_domains = 0 (no new read domains)
3116 * flush_domains = CPU
3117 * invalidate_domains = RENDER
3120 * drm_agp_chipset_flush
3123 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3125 struct drm_device
*dev
= obj
->dev
;
3126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3127 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3128 uint32_t invalidate_domains
= 0;
3129 uint32_t flush_domains
= 0;
3130 uint32_t old_read_domains
;
3132 intel_mark_busy(dev
, obj
);
3135 * If the object isn't moving to a new write domain,
3136 * let the object stay in multiple read domains
3138 if (obj
->pending_write_domain
== 0)
3139 obj
->pending_read_domains
|= obj
->read_domains
;
3141 obj_priv
->dirty
= 1;
3144 * Flush the current write domain if
3145 * the new read domains don't match. Invalidate
3146 * any read domains which differ from the old
3149 if (obj
->write_domain
&&
3150 obj
->write_domain
!= obj
->pending_read_domains
) {
3151 flush_domains
|= obj
->write_domain
;
3152 invalidate_domains
|=
3153 obj
->pending_read_domains
& ~obj
->write_domain
;
3156 * Invalidate any read caches which may have
3157 * stale data. That is, any new read domains.
3159 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3160 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3161 i915_gem_clflush_object(obj
);
3163 old_read_domains
= obj
->read_domains
;
3165 /* The actual obj->write_domain will be updated with
3166 * pending_write_domain after we emit the accumulated flush for all
3167 * of our domain changes in execbuffers (which clears objects'
3168 * write_domains). So if we have a current write domain that we
3169 * aren't changing, set pending_write_domain to that.
3171 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3172 obj
->pending_write_domain
= obj
->write_domain
;
3173 obj
->read_domains
= obj
->pending_read_domains
;
3175 dev
->invalidate_domains
|= invalidate_domains
;
3176 dev
->flush_domains
|= flush_domains
;
3178 dev_priv
->mm
.flush_rings
|= obj_priv
->ring
->id
;
3180 trace_i915_gem_object_change_domain(obj
,
3186 * Moves the object from a partially CPU read to a full one.
3188 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3189 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3192 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3194 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3196 if (!obj_priv
->page_cpu_valid
)
3199 /* If we're partially in the CPU read domain, finish moving it in.
3201 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3204 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3205 if (obj_priv
->page_cpu_valid
[i
])
3207 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3211 /* Free the page_cpu_valid mappings which are now stale, whether
3212 * or not we've got I915_GEM_DOMAIN_CPU.
3214 kfree(obj_priv
->page_cpu_valid
);
3215 obj_priv
->page_cpu_valid
= NULL
;
3219 * Set the CPU read domain on a range of the object.
3221 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3222 * not entirely valid. The page_cpu_valid member of the object flags which
3223 * pages have been flushed, and will be respected by
3224 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3225 * of the whole object.
3227 * This function returns when the move is complete, including waiting on
3231 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3232 uint64_t offset
, uint64_t size
)
3234 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3235 uint32_t old_read_domains
;
3238 if (offset
== 0 && size
== obj
->size
)
3239 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3241 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3244 i915_gem_object_flush_gtt_write_domain(obj
);
3246 /* If we're already fully in the CPU read domain, we're done. */
3247 if (obj_priv
->page_cpu_valid
== NULL
&&
3248 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3251 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3252 * newly adding I915_GEM_DOMAIN_CPU
3254 if (obj_priv
->page_cpu_valid
== NULL
) {
3255 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3257 if (obj_priv
->page_cpu_valid
== NULL
)
3259 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3260 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3262 /* Flush the cache on any pages that are still invalid from the CPU's
3265 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3267 if (obj_priv
->page_cpu_valid
[i
])
3270 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3272 obj_priv
->page_cpu_valid
[i
] = 1;
3275 /* It should now be out of any other write domains, and we can update
3276 * the domain values for our changes.
3278 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3280 old_read_domains
= obj
->read_domains
;
3281 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3283 trace_i915_gem_object_change_domain(obj
,
3291 * Pin an object to the GTT and evaluate the relocations landing in it.
3294 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3295 struct drm_file
*file_priv
,
3296 struct drm_i915_gem_exec_object2
*entry
)
3298 struct drm_device
*dev
= obj
->dev
;
3299 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3300 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3301 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3305 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3306 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3308 /* Check fence reg constraints and rebind if necessary */
3310 !i915_gem_object_fence_offset_ok(obj
,
3311 obj_priv
->tiling_mode
)) {
3312 ret
= i915_gem_object_unbind(obj
);
3317 /* Choose the GTT offset for our buffer and put it there. */
3318 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3323 * Pre-965 chips need a fence register set up in order to
3324 * properly handle blits to/from tiled surfaces.
3327 ret
= i915_gem_object_get_fence_reg(obj
, true);
3329 i915_gem_object_unpin(obj
);
3333 dev_priv
->fence_regs
[obj_priv
->fence_reg
].gpu
= true;
3336 entry
->offset
= obj_priv
->gtt_offset
;
3338 /* Apply the relocations, using the GTT aperture to avoid cache
3339 * flushing requirements.
3341 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
3342 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3343 struct drm_i915_gem_relocation_entry reloc
;
3344 struct drm_gem_object
*target_obj
;
3345 struct drm_i915_gem_object
*target_obj_priv
;
3347 ret
= __copy_from_user_inatomic(&reloc
,
3351 i915_gem_object_unpin(obj
);
3355 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3356 reloc
.target_handle
);
3357 if (target_obj
== NULL
) {
3358 i915_gem_object_unpin(obj
);
3361 target_obj_priv
= to_intel_bo(target_obj
);
3364 DRM_INFO("%s: obj %p offset %08x target %d "
3365 "read %08x write %08x gtt %08x "
3366 "presumed %08x delta %08x\n",
3370 (int) reloc
.target_handle
,
3371 (int) reloc
.read_domains
,
3372 (int) reloc
.write_domain
,
3373 (int) target_obj_priv
->gtt_offset
,
3374 (int) reloc
.presumed_offset
,
3378 /* The target buffer should have appeared before us in the
3379 * exec_object list, so it should have a GTT space bound by now.
3381 if (target_obj_priv
->gtt_space
== NULL
) {
3382 DRM_ERROR("No GTT space found for object %d\n",
3383 reloc
.target_handle
);
3384 drm_gem_object_unreference(target_obj
);
3385 i915_gem_object_unpin(obj
);
3389 /* Validate that the target is in a valid r/w GPU domain */
3390 if (reloc
.write_domain
& (reloc
.write_domain
- 1)) {
3391 DRM_ERROR("reloc with multiple write domains: "
3392 "obj %p target %d offset %d "
3393 "read %08x write %08x",
3394 obj
, reloc
.target_handle
,
3397 reloc
.write_domain
);
3398 drm_gem_object_unreference(target_obj
);
3399 i915_gem_object_unpin(obj
);
3402 if (reloc
.write_domain
& I915_GEM_DOMAIN_CPU
||
3403 reloc
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3404 DRM_ERROR("reloc with read/write CPU domains: "
3405 "obj %p target %d offset %d "
3406 "read %08x write %08x",
3407 obj
, reloc
.target_handle
,
3410 reloc
.write_domain
);
3411 drm_gem_object_unreference(target_obj
);
3412 i915_gem_object_unpin(obj
);
3415 if (reloc
.write_domain
&& target_obj
->pending_write_domain
&&
3416 reloc
.write_domain
!= target_obj
->pending_write_domain
) {
3417 DRM_ERROR("Write domain conflict: "
3418 "obj %p target %d offset %d "
3419 "new %08x old %08x\n",
3420 obj
, reloc
.target_handle
,
3423 target_obj
->pending_write_domain
);
3424 drm_gem_object_unreference(target_obj
);
3425 i915_gem_object_unpin(obj
);
3429 target_obj
->pending_read_domains
|= reloc
.read_domains
;
3430 target_obj
->pending_write_domain
|= reloc
.write_domain
;
3432 /* If the relocation already has the right value in it, no
3433 * more work needs to be done.
3435 if (target_obj_priv
->gtt_offset
== reloc
.presumed_offset
) {
3436 drm_gem_object_unreference(target_obj
);
3440 /* Check that the relocation address is valid... */
3441 if (reloc
.offset
> obj
->size
- 4) {
3442 DRM_ERROR("Relocation beyond object bounds: "
3443 "obj %p target %d offset %d size %d.\n",
3444 obj
, reloc
.target_handle
,
3445 (int) reloc
.offset
, (int) obj
->size
);
3446 drm_gem_object_unreference(target_obj
);
3447 i915_gem_object_unpin(obj
);
3450 if (reloc
.offset
& 3) {
3451 DRM_ERROR("Relocation not 4-byte aligned: "
3452 "obj %p target %d offset %d.\n",
3453 obj
, reloc
.target_handle
,
3454 (int) reloc
.offset
);
3455 drm_gem_object_unreference(target_obj
);
3456 i915_gem_object_unpin(obj
);
3460 /* and points to somewhere within the target object. */
3461 if (reloc
.delta
>= target_obj
->size
) {
3462 DRM_ERROR("Relocation beyond target object bounds: "
3463 "obj %p target %d delta %d size %d.\n",
3464 obj
, reloc
.target_handle
,
3465 (int) reloc
.delta
, (int) target_obj
->size
);
3466 drm_gem_object_unreference(target_obj
);
3467 i915_gem_object_unpin(obj
);
3471 reloc
.delta
+= target_obj_priv
->gtt_offset
;
3472 if (obj
->write_domain
== I915_GEM_DOMAIN_CPU
) {
3473 uint32_t page_offset
= reloc
.offset
& ~PAGE_MASK
;
3476 vaddr
= kmap_atomic(obj_priv
->pages
[reloc
.offset
>> PAGE_SHIFT
], KM_USER0
);
3477 *(uint32_t *)(vaddr
+ page_offset
) = reloc
.delta
;
3478 kunmap_atomic(vaddr
, KM_USER0
);
3480 uint32_t __iomem
*reloc_entry
;
3481 void __iomem
*reloc_page
;
3484 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3486 drm_gem_object_unreference(target_obj
);
3487 i915_gem_object_unpin(obj
);
3491 /* Map the page containing the relocation we're going to perform. */
3492 reloc
.offset
+= obj_priv
->gtt_offset
;
3493 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3494 reloc
.offset
& PAGE_MASK
,
3496 reloc_entry
= (uint32_t __iomem
*)
3497 (reloc_page
+ (reloc
.offset
& ~PAGE_MASK
));
3498 iowrite32(reloc
.delta
, reloc_entry
);
3499 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3502 drm_gem_object_unreference(target_obj
);
3508 /* Throttle our rendering by waiting until the ring has completed our requests
3509 * emitted over 20 msec ago.
3511 * Note that if we were to use the current jiffies each time around the loop,
3512 * we wouldn't escape the function with any frames outstanding if the time to
3513 * render a frame was over 20ms.
3515 * This should get us reasonable parallelism between CPU and GPU but also
3516 * relatively low latency when blocking on a particular request to finish.
3519 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3522 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3523 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3524 struct drm_i915_gem_request
*request
;
3525 struct intel_ring_buffer
*ring
= NULL
;
3529 spin_lock(&file_priv
->mm
.lock
);
3530 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3531 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3534 ring
= request
->ring
;
3535 seqno
= request
->seqno
;
3537 spin_unlock(&file_priv
->mm
.lock
);
3543 if (!i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)) {
3544 /* And wait for the seqno passing without holding any locks and
3545 * causing extra latency for others. This is safe as the irq
3546 * generation is designed to be run atomically and so is
3549 ring
->user_irq_get(dev
, ring
);
3550 ret
= wait_event_interruptible(ring
->irq_queue
,
3551 i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)
3552 || atomic_read(&dev_priv
->mm
.wedged
));
3553 ring
->user_irq_put(dev
, ring
);
3555 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3560 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3566 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
,
3567 uint64_t exec_offset
)
3569 uint32_t exec_start
, exec_len
;
3571 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3572 exec_len
= (uint32_t) exec
->batch_len
;
3574 if ((exec_start
| exec_len
) & 0x7)
3584 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
3589 for (i
= 0; i
< count
; i
++) {
3590 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
3591 size_t length
= exec
[i
].relocation_count
* sizeof(struct drm_i915_gem_relocation_entry
);
3593 if (!access_ok(VERIFY_READ
, ptr
, length
))
3596 if (fault_in_pages_readable(ptr
, length
))
3604 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3605 struct drm_file
*file_priv
,
3606 struct drm_i915_gem_execbuffer2
*args
,
3607 struct drm_i915_gem_exec_object2
*exec_list
)
3609 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3610 struct drm_gem_object
**object_list
= NULL
;
3611 struct drm_gem_object
*batch_obj
;
3612 struct drm_i915_gem_object
*obj_priv
;
3613 struct drm_clip_rect
*cliprects
= NULL
;
3614 struct drm_i915_gem_request
*request
= NULL
;
3615 int ret
, i
, pinned
= 0;
3616 uint64_t exec_offset
;
3617 int pin_tries
, flips
;
3619 struct intel_ring_buffer
*ring
= NULL
;
3621 ret
= i915_gem_check_is_wedged(dev
);
3625 ret
= validate_exec_list(exec_list
, args
->buffer_count
);
3630 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3631 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3633 if (args
->flags
& I915_EXEC_BSD
) {
3634 if (!HAS_BSD(dev
)) {
3635 DRM_ERROR("execbuf with wrong flag\n");
3638 ring
= &dev_priv
->bsd_ring
;
3640 ring
= &dev_priv
->render_ring
;
3643 if (args
->buffer_count
< 1) {
3644 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3647 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3648 if (object_list
== NULL
) {
3649 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3650 args
->buffer_count
);
3655 if (args
->num_cliprects
!= 0) {
3656 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3658 if (cliprects
== NULL
) {
3663 ret
= copy_from_user(cliprects
,
3664 (struct drm_clip_rect __user
*)
3665 (uintptr_t) args
->cliprects_ptr
,
3666 sizeof(*cliprects
) * args
->num_cliprects
);
3668 DRM_ERROR("copy %d cliprects failed: %d\n",
3669 args
->num_cliprects
, ret
);
3675 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3676 if (request
== NULL
) {
3681 ret
= i915_mutex_lock_interruptible(dev
);
3685 if (dev_priv
->mm
.suspended
) {
3686 mutex_unlock(&dev
->struct_mutex
);
3691 /* Look up object handles */
3692 for (i
= 0; i
< args
->buffer_count
; i
++) {
3693 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3694 exec_list
[i
].handle
);
3695 if (object_list
[i
] == NULL
) {
3696 DRM_ERROR("Invalid object handle %d at index %d\n",
3697 exec_list
[i
].handle
, i
);
3698 /* prevent error path from reading uninitialized data */
3699 args
->buffer_count
= i
+ 1;
3704 obj_priv
= to_intel_bo(object_list
[i
]);
3705 if (obj_priv
->in_execbuffer
) {
3706 DRM_ERROR("Object %p appears more than once in object list\n",
3708 /* prevent error path from reading uninitialized data */
3709 args
->buffer_count
= i
+ 1;
3713 obj_priv
->in_execbuffer
= true;
3716 /* Pin and relocate */
3717 for (pin_tries
= 0; ; pin_tries
++) {
3720 for (i
= 0; i
< args
->buffer_count
; i
++) {
3721 object_list
[i
]->pending_read_domains
= 0;
3722 object_list
[i
]->pending_write_domain
= 0;
3723 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3734 /* error other than GTT full, or we've already tried again */
3735 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3736 if (ret
!= -ERESTARTSYS
) {
3737 unsigned long long total_size
= 0;
3739 for (i
= 0; i
< args
->buffer_count
; i
++) {
3740 obj_priv
= to_intel_bo(object_list
[i
]);
3742 total_size
+= object_list
[i
]->size
;
3744 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3745 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3747 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3748 pinned
+1, args
->buffer_count
,
3749 total_size
, num_fences
,
3751 DRM_ERROR("%u objects [%u pinned, %u GTT], "
3752 "%zu object bytes [%zu pinned], "
3753 "%zu /%zu gtt bytes\n",
3754 dev_priv
->mm
.object_count
,
3755 dev_priv
->mm
.pin_count
,
3756 dev_priv
->mm
.gtt_count
,
3757 dev_priv
->mm
.object_memory
,
3758 dev_priv
->mm
.pin_memory
,
3759 dev_priv
->mm
.gtt_memory
,
3760 dev_priv
->mm
.gtt_total
);
3765 /* unpin all of our buffers */
3766 for (i
= 0; i
< pinned
; i
++)
3767 i915_gem_object_unpin(object_list
[i
]);
3770 /* evict everyone we can from the aperture */
3771 ret
= i915_gem_evict_everything(dev
);
3772 if (ret
&& ret
!= -ENOSPC
)
3776 /* Set the pending read domains for the batch buffer to COMMAND */
3777 batch_obj
= object_list
[args
->buffer_count
-1];
3778 if (batch_obj
->pending_write_domain
) {
3779 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3783 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3785 /* Sanity check the batch buffer, prior to moving objects */
3786 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3787 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3789 DRM_ERROR("execbuf with invalid offset/length\n");
3793 /* Zero the global flush/invalidate flags. These
3794 * will be modified as new domains are computed
3797 dev
->invalidate_domains
= 0;
3798 dev
->flush_domains
= 0;
3799 dev_priv
->mm
.flush_rings
= 0;
3801 for (i
= 0; i
< args
->buffer_count
; i
++) {
3802 struct drm_gem_object
*obj
= object_list
[i
];
3804 /* Compute new gpu domains and update invalidate/flush */
3805 i915_gem_object_set_to_gpu_domain(obj
);
3808 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3810 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3812 dev
->invalidate_domains
,
3813 dev
->flush_domains
);
3815 i915_gem_flush(dev
, file_priv
,
3816 dev
->invalidate_domains
,
3818 dev_priv
->mm
.flush_rings
);
3821 for (i
= 0; i
< args
->buffer_count
; i
++) {
3822 struct drm_gem_object
*obj
= object_list
[i
];
3823 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3824 uint32_t old_write_domain
= obj
->write_domain
;
3826 obj
->write_domain
= obj
->pending_write_domain
;
3827 if (obj
->write_domain
)
3828 list_move_tail(&obj_priv
->gpu_write_list
,
3829 &dev_priv
->mm
.gpu_write_list
);
3831 trace_i915_gem_object_change_domain(obj
,
3837 for (i
= 0; i
< args
->buffer_count
; i
++) {
3838 i915_gem_object_check_coherency(object_list
[i
],
3839 exec_list
[i
].handle
);
3844 i915_gem_dump_object(batch_obj
,
3850 /* Check for any pending flips. As we only maintain a flip queue depth
3851 * of 1, we can simply insert a WAIT for the next display flip prior
3852 * to executing the batch and avoid stalling the CPU.
3855 for (i
= 0; i
< args
->buffer_count
; i
++) {
3856 if (object_list
[i
]->write_domain
)
3857 flips
|= atomic_read(&to_intel_bo(object_list
[i
])->pending_flip
);
3860 int plane
, flip_mask
;
3862 for (plane
= 0; flips
>> plane
; plane
++) {
3863 if (((flips
>> plane
) & 1) == 0)
3867 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
3869 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
3871 intel_ring_begin(dev
, ring
, 2);
3872 intel_ring_emit(dev
, ring
,
3873 MI_WAIT_FOR_EVENT
| flip_mask
);
3874 intel_ring_emit(dev
, ring
, MI_NOOP
);
3875 intel_ring_advance(dev
, ring
);
3879 /* Exec the batchbuffer */
3880 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3881 cliprects
, exec_offset
);
3883 DRM_ERROR("dispatch failed %d\n", ret
);
3888 * Ensure that the commands in the batch buffer are
3889 * finished before the interrupt fires
3891 i915_retire_commands(dev
, ring
);
3893 for (i
= 0; i
< args
->buffer_count
; i
++) {
3894 struct drm_gem_object
*obj
= object_list
[i
];
3895 obj_priv
= to_intel_bo(obj
);
3897 i915_gem_object_move_to_active(obj
, ring
);
3900 i915_add_request(dev
, file_priv
, request
, ring
);
3904 for (i
= 0; i
< pinned
; i
++)
3905 i915_gem_object_unpin(object_list
[i
]);
3907 for (i
= 0; i
< args
->buffer_count
; i
++) {
3908 if (object_list
[i
]) {
3909 obj_priv
= to_intel_bo(object_list
[i
]);
3910 obj_priv
->in_execbuffer
= false;
3912 drm_gem_object_unreference(object_list
[i
]);
3915 mutex_unlock(&dev
->struct_mutex
);
3918 drm_free_large(object_list
);
3926 * Legacy execbuffer just creates an exec2 list from the original exec object
3927 * list array and passes it to the real function.
3930 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3931 struct drm_file
*file_priv
)
3933 struct drm_i915_gem_execbuffer
*args
= data
;
3934 struct drm_i915_gem_execbuffer2 exec2
;
3935 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3936 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3940 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3941 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3944 if (args
->buffer_count
< 1) {
3945 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3949 /* Copy in the exec list from userland */
3950 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3951 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3952 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3953 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3954 args
->buffer_count
);
3955 drm_free_large(exec_list
);
3956 drm_free_large(exec2_list
);
3959 ret
= copy_from_user(exec_list
,
3960 (struct drm_i915_relocation_entry __user
*)
3961 (uintptr_t) args
->buffers_ptr
,
3962 sizeof(*exec_list
) * args
->buffer_count
);
3964 DRM_ERROR("copy %d exec entries failed %d\n",
3965 args
->buffer_count
, ret
);
3966 drm_free_large(exec_list
);
3967 drm_free_large(exec2_list
);
3971 for (i
= 0; i
< args
->buffer_count
; i
++) {
3972 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3973 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3974 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3975 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3976 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3977 if (INTEL_INFO(dev
)->gen
< 4)
3978 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3980 exec2_list
[i
].flags
= 0;
3983 exec2
.buffers_ptr
= args
->buffers_ptr
;
3984 exec2
.buffer_count
= args
->buffer_count
;
3985 exec2
.batch_start_offset
= args
->batch_start_offset
;
3986 exec2
.batch_len
= args
->batch_len
;
3987 exec2
.DR1
= args
->DR1
;
3988 exec2
.DR4
= args
->DR4
;
3989 exec2
.num_cliprects
= args
->num_cliprects
;
3990 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3991 exec2
.flags
= I915_EXEC_RENDER
;
3993 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3995 /* Copy the new buffer offsets back to the user's exec list. */
3996 for (i
= 0; i
< args
->buffer_count
; i
++)
3997 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3998 /* ... and back out to userspace */
3999 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4000 (uintptr_t) args
->buffers_ptr
,
4002 sizeof(*exec_list
) * args
->buffer_count
);
4005 DRM_ERROR("failed to copy %d exec entries "
4006 "back to user (%d)\n",
4007 args
->buffer_count
, ret
);
4011 drm_free_large(exec_list
);
4012 drm_free_large(exec2_list
);
4017 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4018 struct drm_file
*file_priv
)
4020 struct drm_i915_gem_execbuffer2
*args
= data
;
4021 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4025 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4026 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4029 if (args
->buffer_count
< 1) {
4030 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4034 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4035 if (exec2_list
== NULL
) {
4036 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4037 args
->buffer_count
);
4040 ret
= copy_from_user(exec2_list
,
4041 (struct drm_i915_relocation_entry __user
*)
4042 (uintptr_t) args
->buffers_ptr
,
4043 sizeof(*exec2_list
) * args
->buffer_count
);
4045 DRM_ERROR("copy %d exec entries failed %d\n",
4046 args
->buffer_count
, ret
);
4047 drm_free_large(exec2_list
);
4051 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4053 /* Copy the new buffer offsets back to the user's exec list. */
4054 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4055 (uintptr_t) args
->buffers_ptr
,
4057 sizeof(*exec2_list
) * args
->buffer_count
);
4060 DRM_ERROR("failed to copy %d exec entries "
4061 "back to user (%d)\n",
4062 args
->buffer_count
, ret
);
4066 drm_free_large(exec2_list
);
4071 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4073 struct drm_device
*dev
= obj
->dev
;
4074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4075 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4078 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4079 WARN_ON(i915_verify_lists(dev
));
4081 if (obj_priv
->gtt_space
!= NULL
) {
4083 alignment
= i915_gem_get_gtt_alignment(obj
);
4084 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4085 WARN(obj_priv
->pin_count
,
4086 "bo is already pinned with incorrect alignment:"
4087 " offset=%x, req.alignment=%x\n",
4088 obj_priv
->gtt_offset
, alignment
);
4089 ret
= i915_gem_object_unbind(obj
);
4095 if (obj_priv
->gtt_space
== NULL
) {
4096 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4101 obj_priv
->pin_count
++;
4103 /* If the object is not active and not pending a flush,
4104 * remove it from the inactive list
4106 if (obj_priv
->pin_count
== 1) {
4107 i915_gem_info_add_pin(dev_priv
, obj
->size
);
4108 if (!obj_priv
->active
)
4109 list_move_tail(&obj_priv
->list
,
4110 &dev_priv
->mm
.pinned_list
);
4113 WARN_ON(i915_verify_lists(dev
));
4118 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4120 struct drm_device
*dev
= obj
->dev
;
4121 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4122 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4124 WARN_ON(i915_verify_lists(dev
));
4125 obj_priv
->pin_count
--;
4126 BUG_ON(obj_priv
->pin_count
< 0);
4127 BUG_ON(obj_priv
->gtt_space
== NULL
);
4129 /* If the object is no longer pinned, and is
4130 * neither active nor being flushed, then stick it on
4133 if (obj_priv
->pin_count
== 0) {
4134 if (!obj_priv
->active
)
4135 list_move_tail(&obj_priv
->list
,
4136 &dev_priv
->mm
.inactive_list
);
4137 i915_gem_info_remove_pin(dev_priv
, obj
->size
);
4139 WARN_ON(i915_verify_lists(dev
));
4143 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4144 struct drm_file
*file_priv
)
4146 struct drm_i915_gem_pin
*args
= data
;
4147 struct drm_gem_object
*obj
;
4148 struct drm_i915_gem_object
*obj_priv
;
4151 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4153 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4157 obj_priv
= to_intel_bo(obj
);
4159 ret
= i915_mutex_lock_interruptible(dev
);
4161 drm_gem_object_unreference_unlocked(obj
);
4165 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4166 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4167 drm_gem_object_unreference(obj
);
4168 mutex_unlock(&dev
->struct_mutex
);
4172 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4173 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4175 drm_gem_object_unreference(obj
);
4176 mutex_unlock(&dev
->struct_mutex
);
4180 obj_priv
->user_pin_count
++;
4181 obj_priv
->pin_filp
= file_priv
;
4182 if (obj_priv
->user_pin_count
== 1) {
4183 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4185 drm_gem_object_unreference(obj
);
4186 mutex_unlock(&dev
->struct_mutex
);
4191 /* XXX - flush the CPU caches for pinned objects
4192 * as the X server doesn't manage domains yet
4194 i915_gem_object_flush_cpu_write_domain(obj
);
4195 args
->offset
= obj_priv
->gtt_offset
;
4196 drm_gem_object_unreference(obj
);
4197 mutex_unlock(&dev
->struct_mutex
);
4203 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4204 struct drm_file
*file_priv
)
4206 struct drm_i915_gem_pin
*args
= data
;
4207 struct drm_gem_object
*obj
;
4208 struct drm_i915_gem_object
*obj_priv
;
4211 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4213 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4218 obj_priv
= to_intel_bo(obj
);
4220 ret
= i915_mutex_lock_interruptible(dev
);
4222 drm_gem_object_unreference_unlocked(obj
);
4226 if (obj_priv
->pin_filp
!= file_priv
) {
4227 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4229 drm_gem_object_unreference(obj
);
4230 mutex_unlock(&dev
->struct_mutex
);
4233 obj_priv
->user_pin_count
--;
4234 if (obj_priv
->user_pin_count
== 0) {
4235 obj_priv
->pin_filp
= NULL
;
4236 i915_gem_object_unpin(obj
);
4239 drm_gem_object_unreference(obj
);
4240 mutex_unlock(&dev
->struct_mutex
);
4245 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4246 struct drm_file
*file_priv
)
4248 struct drm_i915_gem_busy
*args
= data
;
4249 struct drm_gem_object
*obj
;
4250 struct drm_i915_gem_object
*obj_priv
;
4253 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4255 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4260 ret
= i915_mutex_lock_interruptible(dev
);
4262 drm_gem_object_unreference_unlocked(obj
);
4266 /* Count all active objects as busy, even if they are currently not used
4267 * by the gpu. Users of this interface expect objects to eventually
4268 * become non-busy without any further actions, therefore emit any
4269 * necessary flushes here.
4271 obj_priv
= to_intel_bo(obj
);
4272 args
->busy
= obj_priv
->active
;
4274 /* Unconditionally flush objects, even when the gpu still uses this
4275 * object. Userspace calling this function indicates that it wants to
4276 * use this buffer rather sooner than later, so issuing the required
4277 * flush earlier is beneficial.
4279 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4280 i915_gem_flush_ring(dev
, file_priv
,
4282 0, obj
->write_domain
);
4284 /* Update the active list for the hardware's current position.
4285 * Otherwise this only updates on a delayed timer or when irqs
4286 * are actually unmasked, and our working set ends up being
4287 * larger than required.
4289 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4291 args
->busy
= obj_priv
->active
;
4294 drm_gem_object_unreference(obj
);
4295 mutex_unlock(&dev
->struct_mutex
);
4300 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4301 struct drm_file
*file_priv
)
4303 return i915_gem_ring_throttle(dev
, file_priv
);
4307 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4308 struct drm_file
*file_priv
)
4310 struct drm_i915_gem_madvise
*args
= data
;
4311 struct drm_gem_object
*obj
;
4312 struct drm_i915_gem_object
*obj_priv
;
4315 switch (args
->madv
) {
4316 case I915_MADV_DONTNEED
:
4317 case I915_MADV_WILLNEED
:
4323 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4325 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4329 obj_priv
= to_intel_bo(obj
);
4331 ret
= i915_mutex_lock_interruptible(dev
);
4333 drm_gem_object_unreference_unlocked(obj
);
4337 if (obj_priv
->pin_count
) {
4338 drm_gem_object_unreference(obj
);
4339 mutex_unlock(&dev
->struct_mutex
);
4341 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4345 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4346 obj_priv
->madv
= args
->madv
;
4348 /* if the object is no longer bound, discard its backing storage */
4349 if (i915_gem_object_is_purgeable(obj_priv
) &&
4350 obj_priv
->gtt_space
== NULL
)
4351 i915_gem_object_truncate(obj
);
4353 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4355 drm_gem_object_unreference(obj
);
4356 mutex_unlock(&dev
->struct_mutex
);
4361 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4365 struct drm_i915_gem_object
*obj
;
4367 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4371 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4376 i915_gem_info_add_obj(dev_priv
, size
);
4378 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4379 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4381 obj
->agp_type
= AGP_USER_MEMORY
;
4382 obj
->base
.driver_private
= NULL
;
4383 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4384 INIT_LIST_HEAD(&obj
->list
);
4385 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4386 obj
->madv
= I915_MADV_WILLNEED
;
4391 int i915_gem_init_object(struct drm_gem_object
*obj
)
4398 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4400 struct drm_device
*dev
= obj
->dev
;
4401 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4402 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4405 ret
= i915_gem_object_unbind(obj
);
4406 if (ret
== -ERESTARTSYS
) {
4407 list_move(&obj_priv
->list
,
4408 &dev_priv
->mm
.deferred_free_list
);
4412 if (obj_priv
->mmap_offset
)
4413 i915_gem_free_mmap_offset(obj
);
4415 drm_gem_object_release(obj
);
4416 i915_gem_info_remove_obj(dev_priv
, obj
->size
);
4418 kfree(obj_priv
->page_cpu_valid
);
4419 kfree(obj_priv
->bit_17
);
4423 void i915_gem_free_object(struct drm_gem_object
*obj
)
4425 struct drm_device
*dev
= obj
->dev
;
4426 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4428 trace_i915_gem_object_destroy(obj
);
4430 while (obj_priv
->pin_count
> 0)
4431 i915_gem_object_unpin(obj
);
4433 if (obj_priv
->phys_obj
)
4434 i915_gem_detach_phys_object(dev
, obj
);
4436 i915_gem_free_object_tail(obj
);
4440 i915_gem_idle(struct drm_device
*dev
)
4442 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4445 mutex_lock(&dev
->struct_mutex
);
4447 if (dev_priv
->mm
.suspended
||
4448 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4450 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4451 mutex_unlock(&dev
->struct_mutex
);
4455 ret
= i915_gpu_idle(dev
);
4457 mutex_unlock(&dev
->struct_mutex
);
4461 /* Under UMS, be paranoid and evict. */
4462 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4463 ret
= i915_gem_evict_inactive(dev
);
4465 mutex_unlock(&dev
->struct_mutex
);
4470 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4471 * We need to replace this with a semaphore, or something.
4472 * And not confound mm.suspended!
4474 dev_priv
->mm
.suspended
= 1;
4475 del_timer_sync(&dev_priv
->hangcheck_timer
);
4477 i915_kernel_lost_context(dev
);
4478 i915_gem_cleanup_ringbuffer(dev
);
4480 mutex_unlock(&dev
->struct_mutex
);
4482 /* Cancel the retire work handler, which should be idle now. */
4483 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4489 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4490 * over cache flushing.
4493 i915_gem_init_pipe_control(struct drm_device
*dev
)
4495 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4496 struct drm_gem_object
*obj
;
4497 struct drm_i915_gem_object
*obj_priv
;
4500 obj
= i915_gem_alloc_object(dev
, 4096);
4502 DRM_ERROR("Failed to allocate seqno page\n");
4506 obj_priv
= to_intel_bo(obj
);
4507 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4509 ret
= i915_gem_object_pin(obj
, 4096);
4513 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4514 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4515 if (dev_priv
->seqno_page
== NULL
)
4518 dev_priv
->seqno_obj
= obj
;
4519 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4524 i915_gem_object_unpin(obj
);
4526 drm_gem_object_unreference(obj
);
4533 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4535 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4536 struct drm_gem_object
*obj
;
4537 struct drm_i915_gem_object
*obj_priv
;
4539 obj
= dev_priv
->seqno_obj
;
4540 obj_priv
= to_intel_bo(obj
);
4541 kunmap(obj_priv
->pages
[0]);
4542 i915_gem_object_unpin(obj
);
4543 drm_gem_object_unreference(obj
);
4544 dev_priv
->seqno_obj
= NULL
;
4546 dev_priv
->seqno_page
= NULL
;
4550 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4552 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4555 if (HAS_PIPE_CONTROL(dev
)) {
4556 ret
= i915_gem_init_pipe_control(dev
);
4561 ret
= intel_init_render_ring_buffer(dev
);
4563 goto cleanup_pipe_control
;
4566 ret
= intel_init_bsd_ring_buffer(dev
);
4568 goto cleanup_render_ring
;
4571 dev_priv
->next_seqno
= 1;
4575 cleanup_render_ring
:
4576 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4577 cleanup_pipe_control
:
4578 if (HAS_PIPE_CONTROL(dev
))
4579 i915_gem_cleanup_pipe_control(dev
);
4584 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4586 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4588 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4590 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4591 if (HAS_PIPE_CONTROL(dev
))
4592 i915_gem_cleanup_pipe_control(dev
);
4596 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4597 struct drm_file
*file_priv
)
4599 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4602 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4605 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4606 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4607 atomic_set(&dev_priv
->mm
.wedged
, 0);
4610 mutex_lock(&dev
->struct_mutex
);
4611 dev_priv
->mm
.suspended
= 0;
4613 ret
= i915_gem_init_ringbuffer(dev
);
4615 mutex_unlock(&dev
->struct_mutex
);
4619 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4620 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4621 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4622 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4623 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4624 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4625 mutex_unlock(&dev
->struct_mutex
);
4627 ret
= drm_irq_install(dev
);
4629 goto cleanup_ringbuffer
;
4634 mutex_lock(&dev
->struct_mutex
);
4635 i915_gem_cleanup_ringbuffer(dev
);
4636 dev_priv
->mm
.suspended
= 1;
4637 mutex_unlock(&dev
->struct_mutex
);
4643 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4644 struct drm_file
*file_priv
)
4646 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4649 drm_irq_uninstall(dev
);
4650 return i915_gem_idle(dev
);
4654 i915_gem_lastclose(struct drm_device
*dev
)
4658 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4661 ret
= i915_gem_idle(dev
);
4663 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4667 i915_gem_load(struct drm_device
*dev
)
4670 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4672 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4673 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4674 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4675 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4676 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4677 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4678 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4679 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4681 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4682 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4684 for (i
= 0; i
< 16; i
++)
4685 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4686 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4687 i915_gem_retire_work_handler
);
4688 init_completion(&dev_priv
->error_completion
);
4689 spin_lock(&shrink_list_lock
);
4690 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4691 spin_unlock(&shrink_list_lock
);
4693 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4695 u32 tmp
= I915_READ(MI_ARB_STATE
);
4696 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4697 /* arb state is a masked write, so set bit + bit in mask */
4698 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4699 I915_WRITE(MI_ARB_STATE
, tmp
);
4703 /* Old X drivers will take 0-2 for front, back, depth buffers */
4704 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4705 dev_priv
->fence_reg_start
= 3;
4707 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4708 dev_priv
->num_fence_regs
= 16;
4710 dev_priv
->num_fence_regs
= 8;
4712 /* Initialize fence registers to zero */
4713 switch (INTEL_INFO(dev
)->gen
) {
4715 for (i
= 0; i
< 16; i
++)
4716 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4720 for (i
= 0; i
< 16; i
++)
4721 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4724 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4725 for (i
= 0; i
< 8; i
++)
4726 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4728 for (i
= 0; i
< 8; i
++)
4729 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4732 i915_gem_detect_bit_6_swizzle(dev
);
4733 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4737 * Create a physically contiguous memory object for this object
4738 * e.g. for cursor + overlay regs
4740 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4741 int id
, int size
, int align
)
4743 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4744 struct drm_i915_gem_phys_object
*phys_obj
;
4747 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4750 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4756 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4757 if (!phys_obj
->handle
) {
4762 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4765 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4773 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4775 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4776 struct drm_i915_gem_phys_object
*phys_obj
;
4778 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4781 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4782 if (phys_obj
->cur_obj
) {
4783 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4787 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4789 drm_pci_free(dev
, phys_obj
->handle
);
4791 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4794 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4798 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4799 i915_gem_free_phys_object(dev
, i
);
4802 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4803 struct drm_gem_object
*obj
)
4805 struct drm_i915_gem_object
*obj_priv
;
4810 obj_priv
= to_intel_bo(obj
);
4811 if (!obj_priv
->phys_obj
)
4814 ret
= i915_gem_object_get_pages(obj
, 0);
4818 page_count
= obj
->size
/ PAGE_SIZE
;
4820 for (i
= 0; i
< page_count
; i
++) {
4821 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4822 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4824 memcpy(dst
, src
, PAGE_SIZE
);
4825 kunmap_atomic(dst
, KM_USER0
);
4827 drm_clflush_pages(obj_priv
->pages
, page_count
);
4828 drm_agp_chipset_flush(dev
);
4830 i915_gem_object_put_pages(obj
);
4832 obj_priv
->phys_obj
->cur_obj
= NULL
;
4833 obj_priv
->phys_obj
= NULL
;
4837 i915_gem_attach_phys_object(struct drm_device
*dev
,
4838 struct drm_gem_object
*obj
,
4842 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4843 struct drm_i915_gem_object
*obj_priv
;
4848 if (id
> I915_MAX_PHYS_OBJECT
)
4851 obj_priv
= to_intel_bo(obj
);
4853 if (obj_priv
->phys_obj
) {
4854 if (obj_priv
->phys_obj
->id
== id
)
4856 i915_gem_detach_phys_object(dev
, obj
);
4859 /* create a new object */
4860 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4861 ret
= i915_gem_init_phys_object(dev
, id
,
4864 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4869 /* bind to the object */
4870 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4871 obj_priv
->phys_obj
->cur_obj
= obj
;
4873 ret
= i915_gem_object_get_pages(obj
, 0);
4875 DRM_ERROR("failed to get page list\n");
4879 page_count
= obj
->size
/ PAGE_SIZE
;
4881 for (i
= 0; i
< page_count
; i
++) {
4882 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4883 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4885 memcpy(dst
, src
, PAGE_SIZE
);
4886 kunmap_atomic(src
, KM_USER0
);
4889 i915_gem_object_put_pages(obj
);
4897 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4898 struct drm_i915_gem_pwrite
*args
,
4899 struct drm_file
*file_priv
)
4901 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4904 char __user
*user_data
;
4906 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4907 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4909 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4910 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4914 drm_agp_chipset_flush(dev
);
4918 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4920 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4922 /* Clean up our request list when the client is going away, so that
4923 * later retire_requests won't dereference our soon-to-be-gone
4926 spin_lock(&file_priv
->mm
.lock
);
4927 while (!list_empty(&file_priv
->mm
.request_list
)) {
4928 struct drm_i915_gem_request
*request
;
4930 request
= list_first_entry(&file_priv
->mm
.request_list
,
4931 struct drm_i915_gem_request
,
4933 list_del(&request
->client_list
);
4934 request
->file_priv
= NULL
;
4936 spin_unlock(&file_priv
->mm
.lock
);
4940 i915_gpu_is_active(struct drm_device
*dev
)
4942 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4945 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4946 list_empty(&dev_priv
->render_ring
.active_list
);
4948 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
4950 return !lists_empty
;
4954 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4956 drm_i915_private_t
*dev_priv
, *next_dev
;
4957 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4959 int would_deadlock
= 1;
4961 /* "fast-path" to count number of available objects */
4962 if (nr_to_scan
== 0) {
4963 spin_lock(&shrink_list_lock
);
4964 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4965 struct drm_device
*dev
= dev_priv
->dev
;
4967 if (mutex_trylock(&dev
->struct_mutex
)) {
4968 list_for_each_entry(obj_priv
,
4969 &dev_priv
->mm
.inactive_list
,
4972 mutex_unlock(&dev
->struct_mutex
);
4975 spin_unlock(&shrink_list_lock
);
4977 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4980 spin_lock(&shrink_list_lock
);
4983 /* first scan for clean buffers */
4984 list_for_each_entry_safe(dev_priv
, next_dev
,
4985 &shrink_list
, mm
.shrink_list
) {
4986 struct drm_device
*dev
= dev_priv
->dev
;
4988 if (! mutex_trylock(&dev
->struct_mutex
))
4991 spin_unlock(&shrink_list_lock
);
4992 i915_gem_retire_requests(dev
);
4994 list_for_each_entry_safe(obj_priv
, next_obj
,
4995 &dev_priv
->mm
.inactive_list
,
4997 if (i915_gem_object_is_purgeable(obj_priv
)) {
4998 i915_gem_object_unbind(&obj_priv
->base
);
4999 if (--nr_to_scan
<= 0)
5004 spin_lock(&shrink_list_lock
);
5005 mutex_unlock(&dev
->struct_mutex
);
5009 if (nr_to_scan
<= 0)
5013 /* second pass, evict/count anything still on the inactive list */
5014 list_for_each_entry_safe(dev_priv
, next_dev
,
5015 &shrink_list
, mm
.shrink_list
) {
5016 struct drm_device
*dev
= dev_priv
->dev
;
5018 if (! mutex_trylock(&dev
->struct_mutex
))
5021 spin_unlock(&shrink_list_lock
);
5023 list_for_each_entry_safe(obj_priv
, next_obj
,
5024 &dev_priv
->mm
.inactive_list
,
5026 if (nr_to_scan
> 0) {
5027 i915_gem_object_unbind(&obj_priv
->base
);
5033 spin_lock(&shrink_list_lock
);
5034 mutex_unlock(&dev
->struct_mutex
);
5043 * We are desperate for pages, so as a last resort, wait
5044 * for the GPU to finish and discard whatever we can.
5045 * This has a dramatic impact to reduce the number of
5046 * OOM-killer events whilst running the GPU aggressively.
5048 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5049 struct drm_device
*dev
= dev_priv
->dev
;
5051 if (!mutex_trylock(&dev
->struct_mutex
))
5054 spin_unlock(&shrink_list_lock
);
5056 if (i915_gpu_is_active(dev
)) {
5061 spin_lock(&shrink_list_lock
);
5062 mutex_unlock(&dev
->struct_mutex
);
5069 spin_unlock(&shrink_list_lock
);
5074 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5079 static struct shrinker shrinker
= {
5080 .shrink
= i915_gem_shrink
,
5081 .seeks
= DEFAULT_SEEKS
,
5085 i915_gem_shrinker_init(void)
5087 register_shrinker(&shrinker
);
5091 i915_gem_shrinker_exit(void)
5093 unregister_shrinker(&shrinker
);