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ath9k: Do not try to calibrate radio when in sleep mode
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / main.c
blobdd54fa727a613252eec16b1b6b39965439c020ef
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19
20 #define ATH_PCI_VERSION "0.1"
21
22 static char *dev_info = "ath9k";
23
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
28
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
33 /* We use the hw_value as an index into our private channel structure */
34
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39 }
40
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46 }
47
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67 };
68
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102 };
103
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
106 {
107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
118 else
119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
135 break;
136 default:
137 BUG_ON(1);
138 break;
139 }
140 }
141
142 static void ath_update_txpow(struct ath_softc *sc)
143 {
144 struct ath_hw *ah = sc->sc_ah;
145 u32 txpow;
146
147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151 sc->curtxpow = txpow;
152 }
153 }
154
155 static u8 parse_mpdudensity(u8 mpdudensity)
156 {
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188 }
189
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191 {
192 const struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
227 sband->n_bitrates++;
228
229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
231 }
232 }
233
234 /*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238 */
239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
241 {
242 struct ath_hw *ah = sc->sc_ah;
243 bool fastcc = true, stopped;
244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
250 ath9k_ps_wakeup(sc);
251
252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
262 ath_drain_all_txq(sc, false);
263 stopped = ath_stoprecv(sc);
264
265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
268
269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
274 sc->sc_ah->curchan->channel,
275 channel->center_freq, sc->tx_chan_width);
276
277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
283 "reset status %d\n",
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
287 }
288 spin_unlock_bh(&sc->sc_resetlock);
289
290 sc->sc_flags &= ~SC_OP_FULL_RESET;
291
292 if (ath_startrecv(sc) != 0) {
293 DPRINTF(sc, ATH_DBG_FATAL,
294 "Unable to restart recv logic\n");
295 return -EIO;
296 }
297
298 ath_cache_conf_rate(sc, &hw->conf);
299 ath_update_txpow(sc);
300 ath9k_hw_set_interrupts(ah, sc->imask);
301 ath9k_ps_restore(sc);
302 return 0;
303 }
304
305 /*
306 * This routine performs the periodic noise floor calibration function
307 * that is used to adjust and optimize the chip performance. This
308 * takes environmental changes (location, temperature) into account.
309 * When the task is complete, it reschedules itself depending on the
310 * appropriate interval that was calculated.
311 */
312 static void ath_ani_calibrate(unsigned long data)
313 {
314 struct ath_softc *sc = (struct ath_softc *)data;
315 struct ath_hw *ah = sc->sc_ah;
316 bool longcal = false;
317 bool shortcal = false;
318 bool aniflag = false;
319 unsigned int timestamp = jiffies_to_msecs(jiffies);
320 u32 cal_interval, short_cal_interval;
321
322 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
323 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
324
325 /*
326 * don't calibrate when we're scanning.
327 * we are most likely not on our home channel.
328 */
329 if (sc->sc_flags & SC_OP_SCANNING)
330 goto set_timer;
331
332 /* Only calibrate if awake */
333 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
334 goto set_timer;
335
336 ath9k_ps_wakeup(sc);
337
338 /* Long calibration runs independently of short calibration. */
339 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
340 longcal = true;
341 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
342 sc->ani.longcal_timer = timestamp;
343 }
344
345 /* Short calibration applies only while caldone is false */
346 if (!sc->ani.caldone) {
347 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
348 shortcal = true;
349 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
350 sc->ani.shortcal_timer = timestamp;
351 sc->ani.resetcal_timer = timestamp;
352 }
353 } else {
354 if ((timestamp - sc->ani.resetcal_timer) >=
355 ATH_RESTART_CALINTERVAL) {
356 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
357 if (sc->ani.caldone)
358 sc->ani.resetcal_timer = timestamp;
359 }
360 }
361
362 /* Verify whether we must check ANI */
363 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
364 aniflag = true;
365 sc->ani.checkani_timer = timestamp;
366 }
367
368 /* Skip all processing if there's nothing to do. */
369 if (longcal || shortcal || aniflag) {
370 /* Call ANI routine if necessary */
371 if (aniflag)
372 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
373
374 /* Perform calibration if necessary */
375 if (longcal || shortcal) {
376 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
377 sc->rx_chainmask, longcal);
378
379 if (longcal)
380 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
381 ah->curchan);
382
383 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
384 ah->curchan->channel, ah->curchan->channelFlags,
385 sc->ani.noise_floor);
386 }
387 }
388
389 ath9k_ps_restore(sc);
390
391 set_timer:
392 /*
393 * Set timer interval based on previous results.
394 * The interval must be the shortest necessary to satisfy ANI,
395 * short calibration and long calibration.
396 */
397 cal_interval = ATH_LONG_CALINTERVAL;
398 if (sc->sc_ah->config.enable_ani)
399 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
400 if (!sc->ani.caldone)
401 cal_interval = min(cal_interval, (u32)short_cal_interval);
402
403 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
404 }
405
406 static void ath_start_ani(struct ath_softc *sc)
407 {
408 unsigned long timestamp = jiffies_to_msecs(jiffies);
409
410 sc->ani.longcal_timer = timestamp;
411 sc->ani.shortcal_timer = timestamp;
412 sc->ani.checkani_timer = timestamp;
413
414 mod_timer(&sc->ani.timer,
415 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
416 }
417
418 /*
419 * Update tx/rx chainmask. For legacy association,
420 * hard code chainmask to 1x1, for 11n association, use
421 * the chainmask configuration, for bt coexistence, use
422 * the chainmask configuration even in legacy mode.
423 */
424 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
425 {
426 if (is_ht ||
427 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
428 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
429 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
430 } else {
431 sc->tx_chainmask = 1;
432 sc->rx_chainmask = 1;
433 }
434
435 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
436 sc->tx_chainmask, sc->rx_chainmask);
437 }
438
439 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
440 {
441 struct ath_node *an;
442
443 an = (struct ath_node *)sta->drv_priv;
444
445 if (sc->sc_flags & SC_OP_TXAGGR) {
446 ath_tx_node_init(sc, an);
447 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
448 sta->ht_cap.ampdu_factor);
449 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
450 }
451 }
452
453 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
454 {
455 struct ath_node *an = (struct ath_node *)sta->drv_priv;
456
457 if (sc->sc_flags & SC_OP_TXAGGR)
458 ath_tx_node_cleanup(sc, an);
459 }
460
461 static void ath9k_tasklet(unsigned long data)
462 {
463 struct ath_softc *sc = (struct ath_softc *)data;
464 u32 status = sc->intrstatus;
465
466 ath9k_ps_wakeup(sc);
467
468 if (status & ATH9K_INT_FATAL) {
469 ath_reset(sc, false);
470 ath9k_ps_restore(sc);
471 return;
472 }
473
474 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
475 spin_lock_bh(&sc->rx.rxflushlock);
476 ath_rx_tasklet(sc, 0);
477 spin_unlock_bh(&sc->rx.rxflushlock);
478 }
479
480 if (status & ATH9K_INT_TX)
481 ath_tx_tasklet(sc);
482
483 /* re-enable hardware interrupt */
484 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
485 ath9k_ps_restore(sc);
486 }
487
488 irqreturn_t ath_isr(int irq, void *dev)
489 {
490 #define SCHED_INTR ( \
491 ATH9K_INT_FATAL | \
492 ATH9K_INT_RXORN | \
493 ATH9K_INT_RXEOL | \
494 ATH9K_INT_RX | \
495 ATH9K_INT_TX | \
496 ATH9K_INT_BMISS | \
497 ATH9K_INT_CST | \
498 ATH9K_INT_TSFOOR)
499
500 struct ath_softc *sc = dev;
501 struct ath_hw *ah = sc->sc_ah;
502 enum ath9k_int status;
503 bool sched = false;
504
505 /*
506 * The hardware is not ready/present, don't
507 * touch anything. Note this can happen early
508 * on if the IRQ is shared.
509 */
510 if (sc->sc_flags & SC_OP_INVALID)
511 return IRQ_NONE;
512
513
514 /* shared irq, not for us */
515
516 if (!ath9k_hw_intrpend(ah))
517 return IRQ_NONE;
518
519 /*
520 * Figure out the reason(s) for the interrupt. Note
521 * that the hal returns a pseudo-ISR that may include
522 * bits we haven't explicitly enabled so we mask the
523 * value to insure we only process bits we requested.
524 */
525 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
526 status &= sc->imask; /* discard unasked-for bits */
527
528 /*
529 * If there are no status bits set, then this interrupt was not
530 * for me (should have been caught above).
531 */
532 if (!status)
533 return IRQ_NONE;
534
535 /* Cache the status */
536 sc->intrstatus = status;
537
538 if (status & SCHED_INTR)
539 sched = true;
540
541 /*
542 * If a FATAL or RXORN interrupt is received, we have to reset the
543 * chip immediately.
544 */
545 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
546 goto chip_reset;
547
548 if (status & ATH9K_INT_SWBA)
549 tasklet_schedule(&sc->bcon_tasklet);
550
551 if (status & ATH9K_INT_TXURN)
552 ath9k_hw_updatetxtriglevel(ah, true);
553
554 if (status & ATH9K_INT_MIB) {
555 /*
556 * Disable interrupts until we service the MIB
557 * interrupt; otherwise it will continue to
558 * fire.
559 */
560 ath9k_hw_set_interrupts(ah, 0);
561 /*
562 * Let the hal handle the event. We assume
563 * it will clear whatever condition caused
564 * the interrupt.
565 */
566 ath9k_hw_procmibevent(ah, &sc->nodestats);
567 ath9k_hw_set_interrupts(ah, sc->imask);
568 }
569
570 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
571 if (status & ATH9K_INT_TIM_TIMER) {
572 /* Clear RxAbort bit so that we can
573 * receive frames */
574 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
575 ath9k_hw_setrxabort(sc->sc_ah, 0);
576 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
577 }
578
579 chip_reset:
580
581 ath_debug_stat_interrupt(sc, status);
582
583 if (sched) {
584 /* turn off every interrupt except SWBA */
585 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
586 tasklet_schedule(&sc->intr_tq);
587 }
588
589 return IRQ_HANDLED;
590
591 #undef SCHED_INTR
592 }
593
594 static u32 ath_get_extchanmode(struct ath_softc *sc,
595 struct ieee80211_channel *chan,
596 enum nl80211_channel_type channel_type)
597 {
598 u32 chanmode = 0;
599
600 switch (chan->band) {
601 case IEEE80211_BAND_2GHZ:
602 switch(channel_type) {
603 case NL80211_CHAN_NO_HT:
604 case NL80211_CHAN_HT20:
605 chanmode = CHANNEL_G_HT20;
606 break;
607 case NL80211_CHAN_HT40PLUS:
608 chanmode = CHANNEL_G_HT40PLUS;
609 break;
610 case NL80211_CHAN_HT40MINUS:
611 chanmode = CHANNEL_G_HT40MINUS;
612 break;
613 }
614 break;
615 case IEEE80211_BAND_5GHZ:
616 switch(channel_type) {
617 case NL80211_CHAN_NO_HT:
618 case NL80211_CHAN_HT20:
619 chanmode = CHANNEL_A_HT20;
620 break;
621 case NL80211_CHAN_HT40PLUS:
622 chanmode = CHANNEL_A_HT40PLUS;
623 break;
624 case NL80211_CHAN_HT40MINUS:
625 chanmode = CHANNEL_A_HT40MINUS;
626 break;
627 }
628 break;
629 default:
630 break;
631 }
632
633 return chanmode;
634 }
635
636 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
637 struct ath9k_keyval *hk, const u8 *addr,
638 bool authenticator)
639 {
640 const u8 *key_rxmic;
641 const u8 *key_txmic;
642
643 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
644 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
645
646 if (addr == NULL) {
647 /*
648 * Group key installation - only two key cache entries are used
649 * regardless of splitmic capability since group key is only
650 * used either for TX or RX.
651 */
652 if (authenticator) {
653 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
654 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
655 } else {
656 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
657 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
658 }
659 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
660 }
661 if (!sc->splitmic) {
662 /* TX and RX keys share the same key cache entry. */
663 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
664 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
665 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
666 }
667
668 /* Separate key cache entries for TX and RX */
669
670 /* TX key goes at first index, RX key at +32. */
671 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
672 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
673 /* TX MIC entry failed. No need to proceed further */
674 DPRINTF(sc, ATH_DBG_FATAL,
675 "Setting TX MIC Key Failed\n");
676 return 0;
677 }
678
679 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
680 /* XXX delete tx key on failure? */
681 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
682 }
683
684 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
685 {
686 int i;
687
688 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
689 if (test_bit(i, sc->keymap) ||
690 test_bit(i + 64, sc->keymap))
691 continue; /* At least one part of TKIP key allocated */
692 if (sc->splitmic &&
693 (test_bit(i + 32, sc->keymap) ||
694 test_bit(i + 64 + 32, sc->keymap)))
695 continue; /* At least one part of TKIP key allocated */
696
697 /* Found a free slot for a TKIP key */
698 return i;
699 }
700 return -1;
701 }
702
703 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
704 {
705 int i;
706
707 /* First, try to find slots that would not be available for TKIP. */
708 if (sc->splitmic) {
709 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
710 if (!test_bit(i, sc->keymap) &&
711 (test_bit(i + 32, sc->keymap) ||
712 test_bit(i + 64, sc->keymap) ||
713 test_bit(i + 64 + 32, sc->keymap)))
714 return i;
715 if (!test_bit(i + 32, sc->keymap) &&
716 (test_bit(i, sc->keymap) ||
717 test_bit(i + 64, sc->keymap) ||
718 test_bit(i + 64 + 32, sc->keymap)))
719 return i + 32;
720 if (!test_bit(i + 64, sc->keymap) &&
721 (test_bit(i , sc->keymap) ||
722 test_bit(i + 32, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
724 return i + 64;
725 if (!test_bit(i + 64 + 32, sc->keymap) &&
726 (test_bit(i, sc->keymap) ||
727 test_bit(i + 32, sc->keymap) ||
728 test_bit(i + 64, sc->keymap)))
729 return i + 64 + 32;
730 }
731 } else {
732 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
733 if (!test_bit(i, sc->keymap) &&
734 test_bit(i + 64, sc->keymap))
735 return i;
736 if (test_bit(i, sc->keymap) &&
737 !test_bit(i + 64, sc->keymap))
738 return i + 64;
739 }
740 }
741
742 /* No partially used TKIP slots, pick any available slot */
743 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
744 /* Do not allow slots that could be needed for TKIP group keys
745 * to be used. This limitation could be removed if we know that
746 * TKIP will not be used. */
747 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
748 continue;
749 if (sc->splitmic) {
750 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
751 continue;
752 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
753 continue;
754 }
755
756 if (!test_bit(i, sc->keymap))
757 return i; /* Found a free slot for a key */
758 }
759
760 /* No free slot found */
761 return -1;
762 }
763
764 static int ath_key_config(struct ath_softc *sc,
765 struct ieee80211_vif *vif,
766 struct ieee80211_sta *sta,
767 struct ieee80211_key_conf *key)
768 {
769 struct ath9k_keyval hk;
770 const u8 *mac = NULL;
771 int ret = 0;
772 int idx;
773
774 memset(&hk, 0, sizeof(hk));
775
776 switch (key->alg) {
777 case ALG_WEP:
778 hk.kv_type = ATH9K_CIPHER_WEP;
779 break;
780 case ALG_TKIP:
781 hk.kv_type = ATH9K_CIPHER_TKIP;
782 break;
783 case ALG_CCMP:
784 hk.kv_type = ATH9K_CIPHER_AES_CCM;
785 break;
786 default:
787 return -EOPNOTSUPP;
788 }
789
790 hk.kv_len = key->keylen;
791 memcpy(hk.kv_val, key->key, key->keylen);
792
793 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
794 /* For now, use the default keys for broadcast keys. This may
795 * need to change with virtual interfaces. */
796 idx = key->keyidx;
797 } else if (key->keyidx) {
798 if (WARN_ON(!sta))
799 return -EOPNOTSUPP;
800 mac = sta->addr;
801
802 if (vif->type != NL80211_IFTYPE_AP) {
803 /* Only keyidx 0 should be used with unicast key, but
804 * allow this for client mode for now. */
805 idx = key->keyidx;
806 } else
807 return -EIO;
808 } else {
809 if (WARN_ON(!sta))
810 return -EOPNOTSUPP;
811 mac = sta->addr;
812
813 if (key->alg == ALG_TKIP)
814 idx = ath_reserve_key_cache_slot_tkip(sc);
815 else
816 idx = ath_reserve_key_cache_slot(sc);
817 if (idx < 0)
818 return -ENOSPC; /* no free key cache entries */
819 }
820
821 if (key->alg == ALG_TKIP)
822 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
823 vif->type == NL80211_IFTYPE_AP);
824 else
825 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
826
827 if (!ret)
828 return -EIO;
829
830 set_bit(idx, sc->keymap);
831 if (key->alg == ALG_TKIP) {
832 set_bit(idx + 64, sc->keymap);
833 if (sc->splitmic) {
834 set_bit(idx + 32, sc->keymap);
835 set_bit(idx + 64 + 32, sc->keymap);
836 }
837 }
838
839 return idx;
840 }
841
842 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
843 {
844 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
845 if (key->hw_key_idx < IEEE80211_WEP_NKID)
846 return;
847
848 clear_bit(key->hw_key_idx, sc->keymap);
849 if (key->alg != ALG_TKIP)
850 return;
851
852 clear_bit(key->hw_key_idx + 64, sc->keymap);
853 if (sc->splitmic) {
854 clear_bit(key->hw_key_idx + 32, sc->keymap);
855 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
856 }
857 }
858
859 static void setup_ht_cap(struct ath_softc *sc,
860 struct ieee80211_sta_ht_cap *ht_info)
861 {
862 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
863 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
864
865 ht_info->ht_supported = true;
866 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
867 IEEE80211_HT_CAP_SM_PS |
868 IEEE80211_HT_CAP_SGI_40 |
869 IEEE80211_HT_CAP_DSSSCCK40;
870
871 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
872 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
873
874 /* set up supported mcs set */
875 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
876
877 switch(sc->rx_chainmask) {
878 case 1:
879 ht_info->mcs.rx_mask[0] = 0xff;
880 break;
881 case 3:
882 case 5:
883 case 7:
884 default:
885 ht_info->mcs.rx_mask[0] = 0xff;
886 ht_info->mcs.rx_mask[1] = 0xff;
887 break;
888 }
889
890 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
891 }
892
893 static void ath9k_bss_assoc_info(struct ath_softc *sc,
894 struct ieee80211_vif *vif,
895 struct ieee80211_bss_conf *bss_conf)
896 {
897 struct ath_vif *avp = (void *)vif->drv_priv;
898
899 if (bss_conf->assoc) {
900 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
901 bss_conf->aid, sc->curbssid);
902
903 /* New association, store aid */
904 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
905 sc->curaid = bss_conf->aid;
906 ath9k_hw_write_associd(sc);
907 }
908
909 /* Configure the beacon */
910 ath_beacon_config(sc, vif);
911
912 /* Reset rssi stats */
913 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
914 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
915 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
916 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
917
918 ath_start_ani(sc);
919 } else {
920 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
921 sc->curaid = 0;
922 }
923 }
924
925 /********************************/
926 /* LED functions */
927 /********************************/
928
929 static void ath_led_blink_work(struct work_struct *work)
930 {
931 struct ath_softc *sc = container_of(work, struct ath_softc,
932 ath_led_blink_work.work);
933
934 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
935 return;
936
937 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
938 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
939 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
940 else
941 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
942 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
943
944 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
945 (sc->sc_flags & SC_OP_LED_ON) ?
946 msecs_to_jiffies(sc->led_off_duration) :
947 msecs_to_jiffies(sc->led_on_duration));
948
949 sc->led_on_duration = sc->led_on_cnt ?
950 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
951 ATH_LED_ON_DURATION_IDLE;
952 sc->led_off_duration = sc->led_off_cnt ?
953 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
954 ATH_LED_OFF_DURATION_IDLE;
955 sc->led_on_cnt = sc->led_off_cnt = 0;
956 if (sc->sc_flags & SC_OP_LED_ON)
957 sc->sc_flags &= ~SC_OP_LED_ON;
958 else
959 sc->sc_flags |= SC_OP_LED_ON;
960 }
961
962 static void ath_led_brightness(struct led_classdev *led_cdev,
963 enum led_brightness brightness)
964 {
965 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
966 struct ath_softc *sc = led->sc;
967
968 switch (brightness) {
969 case LED_OFF:
970 if (led->led_type == ATH_LED_ASSOC ||
971 led->led_type == ATH_LED_RADIO) {
972 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
973 (led->led_type == ATH_LED_RADIO));
974 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
975 if (led->led_type == ATH_LED_RADIO)
976 sc->sc_flags &= ~SC_OP_LED_ON;
977 } else {
978 sc->led_off_cnt++;
979 }
980 break;
981 case LED_FULL:
982 if (led->led_type == ATH_LED_ASSOC) {
983 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
984 queue_delayed_work(sc->hw->workqueue,
985 &sc->ath_led_blink_work, 0);
986 } else if (led->led_type == ATH_LED_RADIO) {
987 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
988 sc->sc_flags |= SC_OP_LED_ON;
989 } else {
990 sc->led_on_cnt++;
991 }
992 break;
993 default:
994 break;
995 }
996 }
997
998 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
999 char *trigger)
1000 {
1001 int ret;
1002
1003 led->sc = sc;
1004 led->led_cdev.name = led->name;
1005 led->led_cdev.default_trigger = trigger;
1006 led->led_cdev.brightness_set = ath_led_brightness;
1007
1008 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1009 if (ret)
1010 DPRINTF(sc, ATH_DBG_FATAL,
1011 "Failed to register led:%s", led->name);
1012 else
1013 led->registered = 1;
1014 return ret;
1015 }
1016
1017 static void ath_unregister_led(struct ath_led *led)
1018 {
1019 if (led->registered) {
1020 led_classdev_unregister(&led->led_cdev);
1021 led->registered = 0;
1022 }
1023 }
1024
1025 static void ath_deinit_leds(struct ath_softc *sc)
1026 {
1027 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1028 ath_unregister_led(&sc->assoc_led);
1029 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1030 ath_unregister_led(&sc->tx_led);
1031 ath_unregister_led(&sc->rx_led);
1032 ath_unregister_led(&sc->radio_led);
1033 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1034 }
1035
1036 static void ath_init_leds(struct ath_softc *sc)
1037 {
1038 char *trigger;
1039 int ret;
1040
1041 /* Configure gpio 1 for output */
1042 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1043 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1044 /* LED off, active low */
1045 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1046
1047 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1048
1049 trigger = ieee80211_get_radio_led_name(sc->hw);
1050 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1051 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1052 ret = ath_register_led(sc, &sc->radio_led, trigger);
1053 sc->radio_led.led_type = ATH_LED_RADIO;
1054 if (ret)
1055 goto fail;
1056
1057 trigger = ieee80211_get_assoc_led_name(sc->hw);
1058 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1059 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1060 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1061 sc->assoc_led.led_type = ATH_LED_ASSOC;
1062 if (ret)
1063 goto fail;
1064
1065 trigger = ieee80211_get_tx_led_name(sc->hw);
1066 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1067 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1068 ret = ath_register_led(sc, &sc->tx_led, trigger);
1069 sc->tx_led.led_type = ATH_LED_TX;
1070 if (ret)
1071 goto fail;
1072
1073 trigger = ieee80211_get_rx_led_name(sc->hw);
1074 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1075 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1076 ret = ath_register_led(sc, &sc->rx_led, trigger);
1077 sc->rx_led.led_type = ATH_LED_RX;
1078 if (ret)
1079 goto fail;
1080
1081 return;
1082
1083 fail:
1084 ath_deinit_leds(sc);
1085 }
1086
1087 void ath_radio_enable(struct ath_softc *sc)
1088 {
1089 struct ath_hw *ah = sc->sc_ah;
1090 struct ieee80211_channel *channel = sc->hw->conf.channel;
1091 int r;
1092
1093 ath9k_ps_wakeup(sc);
1094 ath9k_hw_configpcipowersave(ah, 0);
1095
1096 spin_lock_bh(&sc->sc_resetlock);
1097 r = ath9k_hw_reset(ah, ah->curchan, false);
1098 if (r) {
1099 DPRINTF(sc, ATH_DBG_FATAL,
1100 "Unable to reset channel %u (%uMhz) ",
1101 "reset status %d\n",
1102 channel->center_freq, r);
1103 }
1104 spin_unlock_bh(&sc->sc_resetlock);
1105
1106 ath_update_txpow(sc);
1107 if (ath_startrecv(sc) != 0) {
1108 DPRINTF(sc, ATH_DBG_FATAL,
1109 "Unable to restart recv logic\n");
1110 return;
1111 }
1112
1113 if (sc->sc_flags & SC_OP_BEACONS)
1114 ath_beacon_config(sc, NULL); /* restart beacons */
1115
1116 /* Re-Enable interrupts */
1117 ath9k_hw_set_interrupts(ah, sc->imask);
1118
1119 /* Enable LED */
1120 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1121 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1122 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1123
1124 ieee80211_wake_queues(sc->hw);
1125 ath9k_ps_restore(sc);
1126 }
1127
1128 void ath_radio_disable(struct ath_softc *sc)
1129 {
1130 struct ath_hw *ah = sc->sc_ah;
1131 struct ieee80211_channel *channel = sc->hw->conf.channel;
1132 int r;
1133
1134 ath9k_ps_wakeup(sc);
1135 ieee80211_stop_queues(sc->hw);
1136
1137 /* Disable LED */
1138 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1139 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1140
1141 /* Disable interrupts */
1142 ath9k_hw_set_interrupts(ah, 0);
1143
1144 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1145 ath_stoprecv(sc); /* turn off frame recv */
1146 ath_flushrecv(sc); /* flush recv queue */
1147
1148 spin_lock_bh(&sc->sc_resetlock);
1149 r = ath9k_hw_reset(ah, ah->curchan, false);
1150 if (r) {
1151 DPRINTF(sc, ATH_DBG_FATAL,
1152 "Unable to reset channel %u (%uMhz) "
1153 "reset status %d\n",
1154 channel->center_freq, r);
1155 }
1156 spin_unlock_bh(&sc->sc_resetlock);
1157
1158 ath9k_hw_phy_disable(ah);
1159 ath9k_hw_configpcipowersave(ah, 1);
1160 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1161 ath9k_ps_restore(sc);
1162 }
1163
1164 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1165
1166 /*******************/
1167 /* Rfkill */
1168 /*******************/
1169
1170 static bool ath_is_rfkill_set(struct ath_softc *sc)
1171 {
1172 struct ath_hw *ah = sc->sc_ah;
1173
1174 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1175 ah->rfkill_polarity;
1176 }
1177
1178 /* h/w rfkill poll function */
1179 static void ath_rfkill_poll(struct work_struct *work)
1180 {
1181 struct ath_softc *sc = container_of(work, struct ath_softc,
1182 rf_kill.rfkill_poll.work);
1183 bool radio_on;
1184
1185 if (sc->sc_flags & SC_OP_INVALID)
1186 return;
1187
1188 radio_on = !ath_is_rfkill_set(sc);
1189
1190 /*
1191 * enable/disable radio only when there is a
1192 * state change in RF switch
1193 */
1194 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1195 enum rfkill_state state;
1196
1197 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1198 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1199 : RFKILL_STATE_HARD_BLOCKED;
1200 } else if (radio_on) {
1201 ath_radio_enable(sc);
1202 state = RFKILL_STATE_UNBLOCKED;
1203 } else {
1204 ath_radio_disable(sc);
1205 state = RFKILL_STATE_HARD_BLOCKED;
1206 }
1207
1208 if (state == RFKILL_STATE_HARD_BLOCKED)
1209 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1210 else
1211 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1212
1213 rfkill_force_state(sc->rf_kill.rfkill, state);
1214 }
1215
1216 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1217 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1218 }
1219
1220 /* s/w rfkill handler */
1221 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1222 {
1223 struct ath_softc *sc = data;
1224
1225 switch (state) {
1226 case RFKILL_STATE_SOFT_BLOCKED:
1227 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1228 SC_OP_RFKILL_SW_BLOCKED)))
1229 ath_radio_disable(sc);
1230 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1231 return 0;
1232 case RFKILL_STATE_UNBLOCKED:
1233 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1234 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1235 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1236 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1237 "radio as it is disabled by h/w\n");
1238 return -EPERM;
1239 }
1240 ath_radio_enable(sc);
1241 }
1242 return 0;
1243 default:
1244 return -EINVAL;
1245 }
1246 }
1247
1248 /* Init s/w rfkill */
1249 static int ath_init_sw_rfkill(struct ath_softc *sc)
1250 {
1251 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1252 RFKILL_TYPE_WLAN);
1253 if (!sc->rf_kill.rfkill) {
1254 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1255 return -ENOMEM;
1256 }
1257
1258 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1259 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1260 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1261 sc->rf_kill.rfkill->data = sc;
1262 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1263 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1264
1265 return 0;
1266 }
1267
1268 /* Deinitialize rfkill */
1269 static void ath_deinit_rfkill(struct ath_softc *sc)
1270 {
1271 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1272 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1273
1274 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1275 rfkill_unregister(sc->rf_kill.rfkill);
1276 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1277 sc->rf_kill.rfkill = NULL;
1278 }
1279 }
1280
1281 static int ath_start_rfkill_poll(struct ath_softc *sc)
1282 {
1283 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1284 queue_delayed_work(sc->hw->workqueue,
1285 &sc->rf_kill.rfkill_poll, 0);
1286
1287 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1288 if (rfkill_register(sc->rf_kill.rfkill)) {
1289 DPRINTF(sc, ATH_DBG_FATAL,
1290 "Unable to register rfkill\n");
1291 rfkill_free(sc->rf_kill.rfkill);
1292
1293 /* Deinitialize the device */
1294 ath_cleanup(sc);
1295 return -EIO;
1296 } else {
1297 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1298 }
1299 }
1300
1301 return 0;
1302 }
1303 #endif /* CONFIG_RFKILL */
1304
1305 void ath_cleanup(struct ath_softc *sc)
1306 {
1307 ath_detach(sc);
1308 free_irq(sc->irq, sc);
1309 ath_bus_cleanup(sc);
1310 kfree(sc->sec_wiphy);
1311 ieee80211_free_hw(sc->hw);
1312 }
1313
1314 void ath_detach(struct ath_softc *sc)
1315 {
1316 struct ieee80211_hw *hw = sc->hw;
1317 int i = 0;
1318
1319 ath9k_ps_wakeup(sc);
1320
1321 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1322
1323 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1324 ath_deinit_rfkill(sc);
1325 #endif
1326 ath_deinit_leds(sc);
1327 cancel_work_sync(&sc->chan_work);
1328 cancel_delayed_work_sync(&sc->wiphy_work);
1329
1330 for (i = 0; i < sc->num_sec_wiphy; i++) {
1331 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1332 if (aphy == NULL)
1333 continue;
1334 sc->sec_wiphy[i] = NULL;
1335 ieee80211_unregister_hw(aphy->hw);
1336 ieee80211_free_hw(aphy->hw);
1337 }
1338 ieee80211_unregister_hw(hw);
1339 ath_rx_cleanup(sc);
1340 ath_tx_cleanup(sc);
1341
1342 tasklet_kill(&sc->intr_tq);
1343 tasklet_kill(&sc->bcon_tasklet);
1344
1345 if (!(sc->sc_flags & SC_OP_INVALID))
1346 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1347
1348 /* cleanup tx queues */
1349 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1350 if (ATH_TXQ_SETUP(sc, i))
1351 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1352
1353 ath9k_hw_detach(sc->sc_ah);
1354 ath9k_exit_debug(sc);
1355 ath9k_ps_restore(sc);
1356 }
1357
1358 static int ath9k_reg_notifier(struct wiphy *wiphy,
1359 struct regulatory_request *request)
1360 {
1361 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1362 struct ath_wiphy *aphy = hw->priv;
1363 struct ath_softc *sc = aphy->sc;
1364 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1365
1366 return ath_reg_notifier_apply(wiphy, request, reg);
1367 }
1368
1369 static int ath_init(u16 devid, struct ath_softc *sc)
1370 {
1371 struct ath_hw *ah = NULL;
1372 int status;
1373 int error = 0, i;
1374 int csz = 0;
1375
1376 /* XXX: hardware will not be ready until ath_open() being called */
1377 sc->sc_flags |= SC_OP_INVALID;
1378
1379 if (ath9k_init_debug(sc) < 0)
1380 printk(KERN_ERR "Unable to create debugfs files\n");
1381
1382 spin_lock_init(&sc->wiphy_lock);
1383 spin_lock_init(&sc->sc_resetlock);
1384 spin_lock_init(&sc->sc_serial_rw);
1385 mutex_init(&sc->mutex);
1386 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1387 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1388 (unsigned long)sc);
1389
1390 /*
1391 * Cache line size is used to size and align various
1392 * structures used to communicate with the hardware.
1393 */
1394 ath_read_cachesize(sc, &csz);
1395 /* XXX assert csz is non-zero */
1396 sc->cachelsz = csz << 2; /* convert to bytes */
1397
1398 ah = ath9k_hw_attach(devid, sc, &status);
1399 if (ah == NULL) {
1400 DPRINTF(sc, ATH_DBG_FATAL,
1401 "Unable to attach hardware; HAL status %d\n", status);
1402 error = -ENXIO;
1403 goto bad;
1404 }
1405 sc->sc_ah = ah;
1406
1407 /* Get the hardware key cache size. */
1408 sc->keymax = ah->caps.keycache_size;
1409 if (sc->keymax > ATH_KEYMAX) {
1410 DPRINTF(sc, ATH_DBG_ANY,
1411 "Warning, using only %u entries in %u key cache\n",
1412 ATH_KEYMAX, sc->keymax);
1413 sc->keymax = ATH_KEYMAX;
1414 }
1415
1416 /*
1417 * Reset the key cache since some parts do not
1418 * reset the contents on initial power up.
1419 */
1420 for (i = 0; i < sc->keymax; i++)
1421 ath9k_hw_keyreset(ah, (u16) i);
1422
1423 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1424 ath9k_reg_notifier);
1425 if (error)
1426 goto bad;
1427
1428 /* default to MONITOR mode */
1429 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1430
1431 /* Setup rate tables */
1432
1433 ath_rate_attach(sc);
1434 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1435 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1436
1437 /*
1438 * Allocate hardware transmit queues: one queue for
1439 * beacon frames and one data queue for each QoS
1440 * priority. Note that the hal handles reseting
1441 * these queues at the needed time.
1442 */
1443 sc->beacon.beaconq = ath_beaconq_setup(ah);
1444 if (sc->beacon.beaconq == -1) {
1445 DPRINTF(sc, ATH_DBG_FATAL,
1446 "Unable to setup a beacon xmit queue\n");
1447 error = -EIO;
1448 goto bad2;
1449 }
1450 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1451 if (sc->beacon.cabq == NULL) {
1452 DPRINTF(sc, ATH_DBG_FATAL,
1453 "Unable to setup CAB xmit queue\n");
1454 error = -EIO;
1455 goto bad2;
1456 }
1457
1458 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1459 ath_cabq_update(sc);
1460
1461 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1462 sc->tx.hwq_map[i] = -1;
1463
1464 /* Setup data queues */
1465 /* NB: ensure BK queue is the lowest priority h/w queue */
1466 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1467 DPRINTF(sc, ATH_DBG_FATAL,
1468 "Unable to setup xmit queue for BK traffic\n");
1469 error = -EIO;
1470 goto bad2;
1471 }
1472
1473 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1474 DPRINTF(sc, ATH_DBG_FATAL,
1475 "Unable to setup xmit queue for BE traffic\n");
1476 error = -EIO;
1477 goto bad2;
1478 }
1479 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1480 DPRINTF(sc, ATH_DBG_FATAL,
1481 "Unable to setup xmit queue for VI traffic\n");
1482 error = -EIO;
1483 goto bad2;
1484 }
1485 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1486 DPRINTF(sc, ATH_DBG_FATAL,
1487 "Unable to setup xmit queue for VO traffic\n");
1488 error = -EIO;
1489 goto bad2;
1490 }
1491
1492 /* Initializes the noise floor to a reasonable default value.
1493 * Later on this will be updated during ANI processing. */
1494
1495 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1496 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1497
1498 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1499 ATH9K_CIPHER_TKIP, NULL)) {
1500 /*
1501 * Whether we should enable h/w TKIP MIC.
1502 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1503 * report WMM capable, so it's always safe to turn on
1504 * TKIP MIC in this case.
1505 */
1506 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1507 0, 1, NULL);
1508 }
1509
1510 /*
1511 * Check whether the separate key cache entries
1512 * are required to handle both tx+rx MIC keys.
1513 * With split mic keys the number of stations is limited
1514 * to 27 otherwise 59.
1515 */
1516 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1517 ATH9K_CIPHER_TKIP, NULL)
1518 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1519 ATH9K_CIPHER_MIC, NULL)
1520 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1521 0, NULL))
1522 sc->splitmic = 1;
1523
1524 /* turn on mcast key search if possible */
1525 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1526 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1527 1, NULL);
1528
1529 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1530
1531 /* 11n Capabilities */
1532 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1533 sc->sc_flags |= SC_OP_TXAGGR;
1534 sc->sc_flags |= SC_OP_RXAGGR;
1535 }
1536
1537 sc->tx_chainmask = ah->caps.tx_chainmask;
1538 sc->rx_chainmask = ah->caps.rx_chainmask;
1539
1540 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1541 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1542
1543 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1544 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1545
1546 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1547
1548 /* initialize beacon slots */
1549 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1550 sc->beacon.bslot[i] = NULL;
1551 sc->beacon.bslot_aphy[i] = NULL;
1552 }
1553
1554 /* setup channels and rates */
1555
1556 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1557 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1558 sc->rates[IEEE80211_BAND_2GHZ];
1559 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1560 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1561 ARRAY_SIZE(ath9k_2ghz_chantable);
1562
1563 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1564 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1565 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1566 sc->rates[IEEE80211_BAND_5GHZ];
1567 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1568 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1569 ARRAY_SIZE(ath9k_5ghz_chantable);
1570 }
1571
1572 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1573 ath9k_hw_btcoex_enable(sc->sc_ah);
1574
1575 return 0;
1576 bad2:
1577 /* cleanup tx queues */
1578 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1579 if (ATH_TXQ_SETUP(sc, i))
1580 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1581 bad:
1582 if (ah)
1583 ath9k_hw_detach(ah);
1584 ath9k_exit_debug(sc);
1585
1586 return error;
1587 }
1588
1589 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1590 {
1591 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1592 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1593 IEEE80211_HW_SIGNAL_DBM |
1594 IEEE80211_HW_AMPDU_AGGREGATION |
1595 IEEE80211_HW_SUPPORTS_PS |
1596 IEEE80211_HW_PS_NULLFUNC_STACK |
1597 IEEE80211_HW_SPECTRUM_MGMT;
1598
1599 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1600 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1601
1602 hw->wiphy->interface_modes =
1603 BIT(NL80211_IFTYPE_AP) |
1604 BIT(NL80211_IFTYPE_STATION) |
1605 BIT(NL80211_IFTYPE_ADHOC) |
1606 BIT(NL80211_IFTYPE_MESH_POINT);
1607
1608 hw->queues = 4;
1609 hw->max_rates = 4;
1610 hw->channel_change_time = 5000;
1611 hw->max_listen_interval = 10;
1612 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1613 hw->sta_data_size = sizeof(struct ath_node);
1614 hw->vif_data_size = sizeof(struct ath_vif);
1615
1616 hw->rate_control_algorithm = "ath9k_rate_control";
1617
1618 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1619 &sc->sbands[IEEE80211_BAND_2GHZ];
1620 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1621 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1622 &sc->sbands[IEEE80211_BAND_5GHZ];
1623 }
1624
1625 int ath_attach(u16 devid, struct ath_softc *sc)
1626 {
1627 struct ieee80211_hw *hw = sc->hw;
1628 int error = 0, i;
1629 struct ath_regulatory *reg;
1630
1631 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1632
1633 error = ath_init(devid, sc);
1634 if (error != 0)
1635 return error;
1636
1637 reg = &sc->sc_ah->regulatory;
1638
1639 /* get mac address from hardware and set in mac80211 */
1640
1641 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1642
1643 ath_set_hw_capab(sc, hw);
1644
1645 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1646 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1647 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1648 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1649 }
1650
1651 /* initialize tx/rx engine */
1652 error = ath_tx_init(sc, ATH_TXBUF);
1653 if (error != 0)
1654 goto error_attach;
1655
1656 error = ath_rx_init(sc, ATH_RXBUF);
1657 if (error != 0)
1658 goto error_attach;
1659
1660 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1661 /* Initialze h/w Rfkill */
1662 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1663 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1664
1665 /* Initialize s/w rfkill */
1666 error = ath_init_sw_rfkill(sc);
1667 if (error)
1668 goto error_attach;
1669 #endif
1670
1671 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1672 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1673 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1674
1675 error = ieee80211_register_hw(hw);
1676
1677 if (!ath_is_world_regd(reg)) {
1678 error = regulatory_hint(hw->wiphy, reg->alpha2);
1679 if (error)
1680 goto error_attach;
1681 }
1682
1683 /* Initialize LED control */
1684 ath_init_leds(sc);
1685
1686
1687 return 0;
1688
1689 error_attach:
1690 /* cleanup tx queues */
1691 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1692 if (ATH_TXQ_SETUP(sc, i))
1693 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1694
1695 ath9k_hw_detach(sc->sc_ah);
1696 ath9k_exit_debug(sc);
1697
1698 return error;
1699 }
1700
1701 int ath_reset(struct ath_softc *sc, bool retry_tx)
1702 {
1703 struct ath_hw *ah = sc->sc_ah;
1704 struct ieee80211_hw *hw = sc->hw;
1705 int r;
1706
1707 ath9k_hw_set_interrupts(ah, 0);
1708 ath_drain_all_txq(sc, retry_tx);
1709 ath_stoprecv(sc);
1710 ath_flushrecv(sc);
1711
1712 spin_lock_bh(&sc->sc_resetlock);
1713 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1714 if (r)
1715 DPRINTF(sc, ATH_DBG_FATAL,
1716 "Unable to reset hardware; reset status %d\n", r);
1717 spin_unlock_bh(&sc->sc_resetlock);
1718
1719 if (ath_startrecv(sc) != 0)
1720 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1721
1722 /*
1723 * We may be doing a reset in response to a request
1724 * that changes the channel so update any state that
1725 * might change as a result.
1726 */
1727 ath_cache_conf_rate(sc, &hw->conf);
1728
1729 ath_update_txpow(sc);
1730
1731 if (sc->sc_flags & SC_OP_BEACONS)
1732 ath_beacon_config(sc, NULL); /* restart beacons */
1733
1734 ath9k_hw_set_interrupts(ah, sc->imask);
1735
1736 if (retry_tx) {
1737 int i;
1738 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1739 if (ATH_TXQ_SETUP(sc, i)) {
1740 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1741 ath_txq_schedule(sc, &sc->tx.txq[i]);
1742 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1743 }
1744 }
1745 }
1746
1747 return r;
1748 }
1749
1750 /*
1751 * This function will allocate both the DMA descriptor structure, and the
1752 * buffers it contains. These are used to contain the descriptors used
1753 * by the system.
1754 */
1755 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1756 struct list_head *head, const char *name,
1757 int nbuf, int ndesc)
1758 {
1759 #define DS2PHYS(_dd, _ds) \
1760 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1761 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1762 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1763
1764 struct ath_desc *ds;
1765 struct ath_buf *bf;
1766 int i, bsize, error;
1767
1768 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1769 name, nbuf, ndesc);
1770
1771 INIT_LIST_HEAD(head);
1772 /* ath_desc must be a multiple of DWORDs */
1773 if ((sizeof(struct ath_desc) % 4) != 0) {
1774 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1775 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1776 error = -ENOMEM;
1777 goto fail;
1778 }
1779
1780 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1781
1782 /*
1783 * Need additional DMA memory because we can't use
1784 * descriptors that cross the 4K page boundary. Assume
1785 * one skipped descriptor per 4K page.
1786 */
1787 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1788 u32 ndesc_skipped =
1789 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1790 u32 dma_len;
1791
1792 while (ndesc_skipped) {
1793 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1794 dd->dd_desc_len += dma_len;
1795
1796 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1797 };
1798 }
1799
1800 /* allocate descriptors */
1801 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1802 &dd->dd_desc_paddr, GFP_KERNEL);
1803 if (dd->dd_desc == NULL) {
1804 error = -ENOMEM;
1805 goto fail;
1806 }
1807 ds = dd->dd_desc;
1808 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1809 name, ds, (u32) dd->dd_desc_len,
1810 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1811
1812 /* allocate buffers */
1813 bsize = sizeof(struct ath_buf) * nbuf;
1814 bf = kzalloc(bsize, GFP_KERNEL);
1815 if (bf == NULL) {
1816 error = -ENOMEM;
1817 goto fail2;
1818 }
1819 dd->dd_bufptr = bf;
1820
1821 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1822 bf->bf_desc = ds;
1823 bf->bf_daddr = DS2PHYS(dd, ds);
1824
1825 if (!(sc->sc_ah->caps.hw_caps &
1826 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1827 /*
1828 * Skip descriptor addresses which can cause 4KB
1829 * boundary crossing (addr + length) with a 32 dword
1830 * descriptor fetch.
1831 */
1832 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1833 ASSERT((caddr_t) bf->bf_desc <
1834 ((caddr_t) dd->dd_desc +
1835 dd->dd_desc_len));
1836
1837 ds += ndesc;
1838 bf->bf_desc = ds;
1839 bf->bf_daddr = DS2PHYS(dd, ds);
1840 }
1841 }
1842 list_add_tail(&bf->list, head);
1843 }
1844 return 0;
1845 fail2:
1846 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1847 dd->dd_desc_paddr);
1848 fail:
1849 memset(dd, 0, sizeof(*dd));
1850 return error;
1851 #undef ATH_DESC_4KB_BOUND_CHECK
1852 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1853 #undef DS2PHYS
1854 }
1855
1856 void ath_descdma_cleanup(struct ath_softc *sc,
1857 struct ath_descdma *dd,
1858 struct list_head *head)
1859 {
1860 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1861 dd->dd_desc_paddr);
1862
1863 INIT_LIST_HEAD(head);
1864 kfree(dd->dd_bufptr);
1865 memset(dd, 0, sizeof(*dd));
1866 }
1867
1868 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1869 {
1870 int qnum;
1871
1872 switch (queue) {
1873 case 0:
1874 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1875 break;
1876 case 1:
1877 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1878 break;
1879 case 2:
1880 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1881 break;
1882 case 3:
1883 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1884 break;
1885 default:
1886 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1887 break;
1888 }
1889
1890 return qnum;
1891 }
1892
1893 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1894 {
1895 int qnum;
1896
1897 switch (queue) {
1898 case ATH9K_WME_AC_VO:
1899 qnum = 0;
1900 break;
1901 case ATH9K_WME_AC_VI:
1902 qnum = 1;
1903 break;
1904 case ATH9K_WME_AC_BE:
1905 qnum = 2;
1906 break;
1907 case ATH9K_WME_AC_BK:
1908 qnum = 3;
1909 break;
1910 default:
1911 qnum = -1;
1912 break;
1913 }
1914
1915 return qnum;
1916 }
1917
1918 /* XXX: Remove me once we don't depend on ath9k_channel for all
1919 * this redundant data */
1920 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1921 struct ath9k_channel *ichan)
1922 {
1923 struct ieee80211_channel *chan = hw->conf.channel;
1924 struct ieee80211_conf *conf = &hw->conf;
1925
1926 ichan->channel = chan->center_freq;
1927 ichan->chan = chan;
1928
1929 if (chan->band == IEEE80211_BAND_2GHZ) {
1930 ichan->chanmode = CHANNEL_G;
1931 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1932 } else {
1933 ichan->chanmode = CHANNEL_A;
1934 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1935 }
1936
1937 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1938
1939 if (conf_is_ht(conf)) {
1940 if (conf_is_ht40(conf))
1941 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1942
1943 ichan->chanmode = ath_get_extchanmode(sc, chan,
1944 conf->channel_type);
1945 }
1946 }
1947
1948 /**********************/
1949 /* mac80211 callbacks */
1950 /**********************/
1951
1952 static int ath9k_start(struct ieee80211_hw *hw)
1953 {
1954 struct ath_wiphy *aphy = hw->priv;
1955 struct ath_softc *sc = aphy->sc;
1956 struct ieee80211_channel *curchan = hw->conf.channel;
1957 struct ath9k_channel *init_channel;
1958 int r, pos;
1959
1960 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1961 "initial channel: %d MHz\n", curchan->center_freq);
1962
1963 mutex_lock(&sc->mutex);
1964
1965 if (ath9k_wiphy_started(sc)) {
1966 if (sc->chan_idx == curchan->hw_value) {
1967 /*
1968 * Already on the operational channel, the new wiphy
1969 * can be marked active.
1970 */
1971 aphy->state = ATH_WIPHY_ACTIVE;
1972 ieee80211_wake_queues(hw);
1973 } else {
1974 /*
1975 * Another wiphy is on another channel, start the new
1976 * wiphy in paused state.
1977 */
1978 aphy->state = ATH_WIPHY_PAUSED;
1979 ieee80211_stop_queues(hw);
1980 }
1981 mutex_unlock(&sc->mutex);
1982 return 0;
1983 }
1984 aphy->state = ATH_WIPHY_ACTIVE;
1985
1986 /* setup initial channel */
1987
1988 pos = curchan->hw_value;
1989
1990 sc->chan_idx = pos;
1991 init_channel = &sc->sc_ah->channels[pos];
1992 ath9k_update_ichannel(sc, hw, init_channel);
1993
1994 /* Reset SERDES registers */
1995 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1996
1997 /*
1998 * The basic interface to setting the hardware in a good
1999 * state is ``reset''. On return the hardware is known to
2000 * be powered up and with interrupts disabled. This must
2001 * be followed by initialization of the appropriate bits
2002 * and then setup of the interrupt mask.
2003 */
2004 spin_lock_bh(&sc->sc_resetlock);
2005 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2006 if (r) {
2007 DPRINTF(sc, ATH_DBG_FATAL,
2008 "Unable to reset hardware; reset status %d "
2009 "(freq %u MHz)\n", r,
2010 curchan->center_freq);
2011 spin_unlock_bh(&sc->sc_resetlock);
2012 goto mutex_unlock;
2013 }
2014 spin_unlock_bh(&sc->sc_resetlock);
2015
2016 /*
2017 * This is needed only to setup initial state
2018 * but it's best done after a reset.
2019 */
2020 ath_update_txpow(sc);
2021
2022 /*
2023 * Setup the hardware after reset:
2024 * The receive engine is set going.
2025 * Frame transmit is handled entirely
2026 * in the frame output path; there's nothing to do
2027 * here except setup the interrupt mask.
2028 */
2029 if (ath_startrecv(sc) != 0) {
2030 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
2031 r = -EIO;
2032 goto mutex_unlock;
2033 }
2034
2035 /* Setup our intr mask. */
2036 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2037 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2038 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2039
2040 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2041 sc->imask |= ATH9K_INT_GTT;
2042
2043 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2044 sc->imask |= ATH9K_INT_CST;
2045
2046 ath_cache_conf_rate(sc, &hw->conf);
2047
2048 sc->sc_flags &= ~SC_OP_INVALID;
2049
2050 /* Disable BMISS interrupt when we're not associated */
2051 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2052 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2053
2054 ieee80211_wake_queues(hw);
2055
2056 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2057 r = ath_start_rfkill_poll(sc);
2058 #endif
2059
2060 mutex_unlock:
2061 mutex_unlock(&sc->mutex);
2062
2063 return r;
2064 }
2065
2066 static int ath9k_tx(struct ieee80211_hw *hw,
2067 struct sk_buff *skb)
2068 {
2069 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2070 struct ath_wiphy *aphy = hw->priv;
2071 struct ath_softc *sc = aphy->sc;
2072 struct ath_tx_control txctl;
2073 int hdrlen, padsize;
2074
2075 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2076 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2077 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2078 goto exit;
2079 }
2080
2081 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2082 /*
2083 * We are using PS-Poll and mac80211 can request TX while in
2084 * power save mode. Need to wake up hardware for the TX to be
2085 * completed and if needed, also for RX of buffered frames.
2086 */
2087 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2088 ath9k_ps_wakeup(sc);
2089 ath9k_hw_setrxabort(sc->sc_ah, 0);
2090 if (ieee80211_is_pspoll(hdr->frame_control)) {
2091 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2092 "buffered frame\n");
2093 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2094 } else {
2095 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2096 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2097 }
2098 /*
2099 * The actual restore operation will happen only after
2100 * the sc_flags bit is cleared. We are just dropping
2101 * the ps_usecount here.
2102 */
2103 ath9k_ps_restore(sc);
2104 }
2105
2106 memset(&txctl, 0, sizeof(struct ath_tx_control));
2107
2108 /*
2109 * As a temporary workaround, assign seq# here; this will likely need
2110 * to be cleaned up to work better with Beacon transmission and virtual
2111 * BSSes.
2112 */
2113 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2114 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2115 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2116 sc->tx.seq_no += 0x10;
2117 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2118 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2119 }
2120
2121 /* Add the padding after the header if this is not already done */
2122 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2123 if (hdrlen & 3) {
2124 padsize = hdrlen % 4;
2125 if (skb_headroom(skb) < padsize)
2126 return -1;
2127 skb_push(skb, padsize);
2128 memmove(skb->data, skb->data + padsize, hdrlen);
2129 }
2130
2131 /* Check if a tx queue is available */
2132
2133 txctl.txq = ath_test_get_txq(sc, skb);
2134 if (!txctl.txq)
2135 goto exit;
2136
2137 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2138
2139 if (ath_tx_start(hw, skb, &txctl) != 0) {
2140 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2141 goto exit;
2142 }
2143
2144 return 0;
2145 exit:
2146 dev_kfree_skb_any(skb);
2147 return 0;
2148 }
2149
2150 static void ath9k_stop(struct ieee80211_hw *hw)
2151 {
2152 struct ath_wiphy *aphy = hw->priv;
2153 struct ath_softc *sc = aphy->sc;
2154
2155 aphy->state = ATH_WIPHY_INACTIVE;
2156
2157 if (sc->sc_flags & SC_OP_INVALID) {
2158 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2159 return;
2160 }
2161
2162 mutex_lock(&sc->mutex);
2163
2164 ieee80211_stop_queues(hw);
2165
2166 if (ath9k_wiphy_started(sc)) {
2167 mutex_unlock(&sc->mutex);
2168 return; /* another wiphy still in use */
2169 }
2170
2171 /* make sure h/w will not generate any interrupt
2172 * before setting the invalid flag. */
2173 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2174
2175 if (!(sc->sc_flags & SC_OP_INVALID)) {
2176 ath_drain_all_txq(sc, false);
2177 ath_stoprecv(sc);
2178 ath9k_hw_phy_disable(sc->sc_ah);
2179 } else
2180 sc->rx.rxlink = NULL;
2181
2182 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2183 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2184 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2185 #endif
2186 /* disable HAL and put h/w to sleep */
2187 ath9k_hw_disable(sc->sc_ah);
2188 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2189
2190 sc->sc_flags |= SC_OP_INVALID;
2191
2192 mutex_unlock(&sc->mutex);
2193
2194 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2195 }
2196
2197 static int ath9k_add_interface(struct ieee80211_hw *hw,
2198 struct ieee80211_if_init_conf *conf)
2199 {
2200 struct ath_wiphy *aphy = hw->priv;
2201 struct ath_softc *sc = aphy->sc;
2202 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2203 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2204 int ret = 0;
2205
2206 mutex_lock(&sc->mutex);
2207
2208 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2209 sc->nvifs > 0) {
2210 ret = -ENOBUFS;
2211 goto out;
2212 }
2213
2214 switch (conf->type) {
2215 case NL80211_IFTYPE_STATION:
2216 ic_opmode = NL80211_IFTYPE_STATION;
2217 break;
2218 case NL80211_IFTYPE_ADHOC:
2219 case NL80211_IFTYPE_AP:
2220 case NL80211_IFTYPE_MESH_POINT:
2221 if (sc->nbcnvifs >= ATH_BCBUF) {
2222 ret = -ENOBUFS;
2223 goto out;
2224 }
2225 ic_opmode = conf->type;
2226 break;
2227 default:
2228 DPRINTF(sc, ATH_DBG_FATAL,
2229 "Interface type %d not yet supported\n", conf->type);
2230 ret = -EOPNOTSUPP;
2231 goto out;
2232 }
2233
2234 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2235
2236 /* Set the VIF opmode */
2237 avp->av_opmode = ic_opmode;
2238 avp->av_bslot = -1;
2239
2240 sc->nvifs++;
2241
2242 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2243 ath9k_set_bssid_mask(hw);
2244
2245 if (sc->nvifs > 1)
2246 goto out; /* skip global settings for secondary vif */
2247
2248 if (ic_opmode == NL80211_IFTYPE_AP) {
2249 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2250 sc->sc_flags |= SC_OP_TSF_RESET;
2251 }
2252
2253 /* Set the device opmode */
2254 sc->sc_ah->opmode = ic_opmode;
2255
2256 /*
2257 * Enable MIB interrupts when there are hardware phy counters.
2258 * Note we only do this (at the moment) for station mode.
2259 */
2260 if ((conf->type == NL80211_IFTYPE_STATION) ||
2261 (conf->type == NL80211_IFTYPE_ADHOC) ||
2262 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2263 if (ath9k_hw_phycounters(sc->sc_ah))
2264 sc->imask |= ATH9K_INT_MIB;
2265 sc->imask |= ATH9K_INT_TSFOOR;
2266 }
2267
2268 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2269
2270 if (conf->type == NL80211_IFTYPE_AP)
2271 ath_start_ani(sc);
2272
2273 out:
2274 mutex_unlock(&sc->mutex);
2275 return ret;
2276 }
2277
2278 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2279 struct ieee80211_if_init_conf *conf)
2280 {
2281 struct ath_wiphy *aphy = hw->priv;
2282 struct ath_softc *sc = aphy->sc;
2283 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2284 int i;
2285
2286 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2287
2288 mutex_lock(&sc->mutex);
2289
2290 /* Stop ANI */
2291 del_timer_sync(&sc->ani.timer);
2292
2293 /* Reclaim beacon resources */
2294 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2295 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2296 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2297 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2298 ath_beacon_return(sc, avp);
2299 }
2300
2301 sc->sc_flags &= ~SC_OP_BEACONS;
2302
2303 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2304 if (sc->beacon.bslot[i] == conf->vif) {
2305 printk(KERN_DEBUG "%s: vif had allocated beacon "
2306 "slot\n", __func__);
2307 sc->beacon.bslot[i] = NULL;
2308 sc->beacon.bslot_aphy[i] = NULL;
2309 }
2310 }
2311
2312 sc->nvifs--;
2313
2314 mutex_unlock(&sc->mutex);
2315 }
2316
2317 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2318 {
2319 struct ath_wiphy *aphy = hw->priv;
2320 struct ath_softc *sc = aphy->sc;
2321 struct ieee80211_conf *conf = &hw->conf;
2322 struct ath_hw *ah = sc->sc_ah;
2323
2324 mutex_lock(&sc->mutex);
2325
2326 if (changed & IEEE80211_CONF_CHANGE_PS) {
2327 if (conf->flags & IEEE80211_CONF_PS) {
2328 if (!(ah->caps.hw_caps &
2329 ATH9K_HW_CAP_AUTOSLEEP)) {
2330 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2331 sc->imask |= ATH9K_INT_TIM_TIMER;
2332 ath9k_hw_set_interrupts(sc->sc_ah,
2333 sc->imask);
2334 }
2335 ath9k_hw_setrxabort(sc->sc_ah, 1);
2336 }
2337 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2338 } else {
2339 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2340 if (!(ah->caps.hw_caps &
2341 ATH9K_HW_CAP_AUTOSLEEP)) {
2342 ath9k_hw_setrxabort(sc->sc_ah, 0);
2343 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2344 SC_OP_WAIT_FOR_CAB |
2345 SC_OP_WAIT_FOR_PSPOLL_DATA |
2346 SC_OP_WAIT_FOR_TX_ACK);
2347 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2348 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2349 ath9k_hw_set_interrupts(sc->sc_ah,
2350 sc->imask);
2351 }
2352 }
2353 }
2354 }
2355
2356 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2357 struct ieee80211_channel *curchan = hw->conf.channel;
2358 int pos = curchan->hw_value;
2359
2360 aphy->chan_idx = pos;
2361 aphy->chan_is_ht = conf_is_ht(conf);
2362
2363 if (aphy->state == ATH_WIPHY_SCAN ||
2364 aphy->state == ATH_WIPHY_ACTIVE)
2365 ath9k_wiphy_pause_all_forced(sc, aphy);
2366 else {
2367 /*
2368 * Do not change operational channel based on a paused
2369 * wiphy changes.
2370 */
2371 goto skip_chan_change;
2372 }
2373
2374 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2375 curchan->center_freq);
2376
2377 /* XXX: remove me eventualy */
2378 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2379
2380 ath_update_chainmask(sc, conf_is_ht(conf));
2381
2382 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2383 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2384 mutex_unlock(&sc->mutex);
2385 return -EINVAL;
2386 }
2387 }
2388
2389 skip_chan_change:
2390 if (changed & IEEE80211_CONF_CHANGE_POWER)
2391 sc->config.txpowlimit = 2 * conf->power_level;
2392
2393 mutex_unlock(&sc->mutex);
2394
2395 return 0;
2396 }
2397
2398 #define SUPPORTED_FILTERS \
2399 (FIF_PROMISC_IN_BSS | \
2400 FIF_ALLMULTI | \
2401 FIF_CONTROL | \
2402 FIF_OTHER_BSS | \
2403 FIF_BCN_PRBRESP_PROMISC | \
2404 FIF_FCSFAIL)
2405
2406 /* FIXME: sc->sc_full_reset ? */
2407 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2408 unsigned int changed_flags,
2409 unsigned int *total_flags,
2410 int mc_count,
2411 struct dev_mc_list *mclist)
2412 {
2413 struct ath_wiphy *aphy = hw->priv;
2414 struct ath_softc *sc = aphy->sc;
2415 u32 rfilt;
2416
2417 changed_flags &= SUPPORTED_FILTERS;
2418 *total_flags &= SUPPORTED_FILTERS;
2419
2420 sc->rx.rxfilter = *total_flags;
2421 rfilt = ath_calcrxfilter(sc);
2422 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2423
2424 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2425 }
2426
2427 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2428 struct ieee80211_vif *vif,
2429 enum sta_notify_cmd cmd,
2430 struct ieee80211_sta *sta)
2431 {
2432 struct ath_wiphy *aphy = hw->priv;
2433 struct ath_softc *sc = aphy->sc;
2434
2435 switch (cmd) {
2436 case STA_NOTIFY_ADD:
2437 ath_node_attach(sc, sta);
2438 break;
2439 case STA_NOTIFY_REMOVE:
2440 ath_node_detach(sc, sta);
2441 break;
2442 default:
2443 break;
2444 }
2445 }
2446
2447 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2448 const struct ieee80211_tx_queue_params *params)
2449 {
2450 struct ath_wiphy *aphy = hw->priv;
2451 struct ath_softc *sc = aphy->sc;
2452 struct ath9k_tx_queue_info qi;
2453 int ret = 0, qnum;
2454
2455 if (queue >= WME_NUM_AC)
2456 return 0;
2457
2458 mutex_lock(&sc->mutex);
2459
2460 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2461
2462 qi.tqi_aifs = params->aifs;
2463 qi.tqi_cwmin = params->cw_min;
2464 qi.tqi_cwmax = params->cw_max;
2465 qi.tqi_burstTime = params->txop;
2466 qnum = ath_get_hal_qnum(queue, sc);
2467
2468 DPRINTF(sc, ATH_DBG_CONFIG,
2469 "Configure tx [queue/halq] [%d/%d], "
2470 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2471 queue, qnum, params->aifs, params->cw_min,
2472 params->cw_max, params->txop);
2473
2474 ret = ath_txq_update(sc, qnum, &qi);
2475 if (ret)
2476 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2477
2478 mutex_unlock(&sc->mutex);
2479
2480 return ret;
2481 }
2482
2483 static int ath9k_set_key(struct ieee80211_hw *hw,
2484 enum set_key_cmd cmd,
2485 struct ieee80211_vif *vif,
2486 struct ieee80211_sta *sta,
2487 struct ieee80211_key_conf *key)
2488 {
2489 struct ath_wiphy *aphy = hw->priv;
2490 struct ath_softc *sc = aphy->sc;
2491 int ret = 0;
2492
2493 if (modparam_nohwcrypt)
2494 return -ENOSPC;
2495
2496 mutex_lock(&sc->mutex);
2497 ath9k_ps_wakeup(sc);
2498 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2499
2500 switch (cmd) {
2501 case SET_KEY:
2502 ret = ath_key_config(sc, vif, sta, key);
2503 if (ret >= 0) {
2504 key->hw_key_idx = ret;
2505 /* push IV and Michael MIC generation to stack */
2506 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2507 if (key->alg == ALG_TKIP)
2508 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2509 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2510 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2511 ret = 0;
2512 }
2513 break;
2514 case DISABLE_KEY:
2515 ath_key_delete(sc, key);
2516 break;
2517 default:
2518 ret = -EINVAL;
2519 }
2520
2521 ath9k_ps_restore(sc);
2522 mutex_unlock(&sc->mutex);
2523
2524 return ret;
2525 }
2526
2527 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2528 struct ieee80211_vif *vif,
2529 struct ieee80211_bss_conf *bss_conf,
2530 u32 changed)
2531 {
2532 struct ath_wiphy *aphy = hw->priv;
2533 struct ath_softc *sc = aphy->sc;
2534 struct ath_hw *ah = sc->sc_ah;
2535 struct ath_vif *avp = (void *)vif->drv_priv;
2536 u32 rfilt = 0;
2537 int error, i;
2538
2539 mutex_lock(&sc->mutex);
2540
2541 /*
2542 * TODO: Need to decide which hw opmode to use for
2543 * multi-interface cases
2544 * XXX: This belongs into add_interface!
2545 */
2546 if (vif->type == NL80211_IFTYPE_AP &&
2547 ah->opmode != NL80211_IFTYPE_AP) {
2548 ah->opmode = NL80211_IFTYPE_STATION;
2549 ath9k_hw_setopmode(ah);
2550 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2551 sc->curaid = 0;
2552 ath9k_hw_write_associd(sc);
2553 /* Request full reset to get hw opmode changed properly */
2554 sc->sc_flags |= SC_OP_FULL_RESET;
2555 }
2556
2557 if ((changed & BSS_CHANGED_BSSID) &&
2558 !is_zero_ether_addr(bss_conf->bssid)) {
2559 switch (vif->type) {
2560 case NL80211_IFTYPE_STATION:
2561 case NL80211_IFTYPE_ADHOC:
2562 case NL80211_IFTYPE_MESH_POINT:
2563 /* Set BSSID */
2564 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2565 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2566 sc->curaid = 0;
2567 ath9k_hw_write_associd(sc);
2568
2569 /* Set aggregation protection mode parameters */
2570 sc->config.ath_aggr_prot = 0;
2571
2572 DPRINTF(sc, ATH_DBG_CONFIG,
2573 "RX filter 0x%x bssid %pM aid 0x%x\n",
2574 rfilt, sc->curbssid, sc->curaid);
2575
2576 /* need to reconfigure the beacon */
2577 sc->sc_flags &= ~SC_OP_BEACONS ;
2578
2579 break;
2580 default:
2581 break;
2582 }
2583 }
2584
2585 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2586 (vif->type == NL80211_IFTYPE_AP) ||
2587 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2588 if ((changed & BSS_CHANGED_BEACON) ||
2589 (changed & BSS_CHANGED_BEACON_ENABLED &&
2590 bss_conf->enable_beacon)) {
2591 /*
2592 * Allocate and setup the beacon frame.
2593 *
2594 * Stop any previous beacon DMA. This may be
2595 * necessary, for example, when an ibss merge
2596 * causes reconfiguration; we may be called
2597 * with beacon transmission active.
2598 */
2599 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2600
2601 error = ath_beacon_alloc(aphy, vif);
2602 if (!error)
2603 ath_beacon_config(sc, vif);
2604 }
2605 }
2606
2607 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2608 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2609 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2610 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2611 ath9k_hw_keysetmac(sc->sc_ah,
2612 (u16)i,
2613 sc->curbssid);
2614 }
2615
2616 /* Only legacy IBSS for now */
2617 if (vif->type == NL80211_IFTYPE_ADHOC)
2618 ath_update_chainmask(sc, 0);
2619
2620 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2621 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2622 bss_conf->use_short_preamble);
2623 if (bss_conf->use_short_preamble)
2624 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2625 else
2626 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2627 }
2628
2629 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2630 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2631 bss_conf->use_cts_prot);
2632 if (bss_conf->use_cts_prot &&
2633 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2634 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2635 else
2636 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2637 }
2638
2639 if (changed & BSS_CHANGED_ASSOC) {
2640 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2641 bss_conf->assoc);
2642 ath9k_bss_assoc_info(sc, vif, bss_conf);
2643 }
2644
2645 /*
2646 * The HW TSF has to be reset when the beacon interval changes.
2647 * We set the flag here, and ath_beacon_config_ap() would take this
2648 * into account when it gets called through the subsequent
2649 * config_interface() call - with IFCC_BEACON in the changed field.
2650 */
2651
2652 if (changed & BSS_CHANGED_BEACON_INT) {
2653 sc->sc_flags |= SC_OP_TSF_RESET;
2654 sc->beacon_interval = bss_conf->beacon_int;
2655 }
2656
2657 mutex_unlock(&sc->mutex);
2658 }
2659
2660 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2661 {
2662 u64 tsf;
2663 struct ath_wiphy *aphy = hw->priv;
2664 struct ath_softc *sc = aphy->sc;
2665
2666 mutex_lock(&sc->mutex);
2667 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2668 mutex_unlock(&sc->mutex);
2669
2670 return tsf;
2671 }
2672
2673 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2674 {
2675 struct ath_wiphy *aphy = hw->priv;
2676 struct ath_softc *sc = aphy->sc;
2677
2678 mutex_lock(&sc->mutex);
2679 ath9k_hw_settsf64(sc->sc_ah, tsf);
2680 mutex_unlock(&sc->mutex);
2681 }
2682
2683 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2684 {
2685 struct ath_wiphy *aphy = hw->priv;
2686 struct ath_softc *sc = aphy->sc;
2687
2688 mutex_lock(&sc->mutex);
2689 ath9k_hw_reset_tsf(sc->sc_ah);
2690 mutex_unlock(&sc->mutex);
2691 }
2692
2693 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2694 enum ieee80211_ampdu_mlme_action action,
2695 struct ieee80211_sta *sta,
2696 u16 tid, u16 *ssn)
2697 {
2698 struct ath_wiphy *aphy = hw->priv;
2699 struct ath_softc *sc = aphy->sc;
2700 int ret = 0;
2701
2702 switch (action) {
2703 case IEEE80211_AMPDU_RX_START:
2704 if (!(sc->sc_flags & SC_OP_RXAGGR))
2705 ret = -ENOTSUPP;
2706 break;
2707 case IEEE80211_AMPDU_RX_STOP:
2708 break;
2709 case IEEE80211_AMPDU_TX_START:
2710 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2711 if (ret < 0)
2712 DPRINTF(sc, ATH_DBG_FATAL,
2713 "Unable to start TX aggregation\n");
2714 else
2715 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2716 break;
2717 case IEEE80211_AMPDU_TX_STOP:
2718 ret = ath_tx_aggr_stop(sc, sta, tid);
2719 if (ret < 0)
2720 DPRINTF(sc, ATH_DBG_FATAL,
2721 "Unable to stop TX aggregation\n");
2722
2723 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2724 break;
2725 case IEEE80211_AMPDU_TX_OPERATIONAL:
2726 ath_tx_aggr_resume(sc, sta, tid);
2727 break;
2728 default:
2729 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2730 }
2731
2732 return ret;
2733 }
2734
2735 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2736 {
2737 struct ath_wiphy *aphy = hw->priv;
2738 struct ath_softc *sc = aphy->sc;
2739
2740 if (ath9k_wiphy_scanning(sc)) {
2741 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2742 "same time\n");
2743 /*
2744 * Do not allow the concurrent scanning state for now. This
2745 * could be improved with scanning control moved into ath9k.
2746 */
2747 return;
2748 }
2749
2750 aphy->state = ATH_WIPHY_SCAN;
2751 ath9k_wiphy_pause_all_forced(sc, aphy);
2752
2753 mutex_lock(&sc->mutex);
2754 sc->sc_flags |= SC_OP_SCANNING;
2755 mutex_unlock(&sc->mutex);
2756 }
2757
2758 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2759 {
2760 struct ath_wiphy *aphy = hw->priv;
2761 struct ath_softc *sc = aphy->sc;
2762
2763 mutex_lock(&sc->mutex);
2764 aphy->state = ATH_WIPHY_ACTIVE;
2765 sc->sc_flags &= ~SC_OP_SCANNING;
2766 sc->sc_flags |= SC_OP_FULL_RESET;
2767 mutex_unlock(&sc->mutex);
2768 }
2769
2770 struct ieee80211_ops ath9k_ops = {
2771 .tx = ath9k_tx,
2772 .start = ath9k_start,
2773 .stop = ath9k_stop,
2774 .add_interface = ath9k_add_interface,
2775 .remove_interface = ath9k_remove_interface,
2776 .config = ath9k_config,
2777 .configure_filter = ath9k_configure_filter,
2778 .sta_notify = ath9k_sta_notify,
2779 .conf_tx = ath9k_conf_tx,
2780 .bss_info_changed = ath9k_bss_info_changed,
2781 .set_key = ath9k_set_key,
2782 .get_tsf = ath9k_get_tsf,
2783 .set_tsf = ath9k_set_tsf,
2784 .reset_tsf = ath9k_reset_tsf,
2785 .ampdu_action = ath9k_ampdu_action,
2786 .sw_scan_start = ath9k_sw_scan_start,
2787 .sw_scan_complete = ath9k_sw_scan_complete,
2788 };
2789
2790 static struct {
2791 u32 version;
2792 const char * name;
2793 } ath_mac_bb_names[] = {
2794 { AR_SREV_VERSION_5416_PCI, "5416" },
2795 { AR_SREV_VERSION_5416_PCIE, "5418" },
2796 { AR_SREV_VERSION_9100, "9100" },
2797 { AR_SREV_VERSION_9160, "9160" },
2798 { AR_SREV_VERSION_9280, "9280" },
2799 { AR_SREV_VERSION_9285, "9285" }
2800 };
2801
2802 static struct {
2803 u16 version;
2804 const char * name;
2805 } ath_rf_names[] = {
2806 { 0, "5133" },
2807 { AR_RAD5133_SREV_MAJOR, "5133" },
2808 { AR_RAD5122_SREV_MAJOR, "5122" },
2809 { AR_RAD2133_SREV_MAJOR, "2133" },
2810 { AR_RAD2122_SREV_MAJOR, "2122" }
2811 };
2812
2813 /*
2814 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2815 */
2816 const char *
2817 ath_mac_bb_name(u32 mac_bb_version)
2818 {
2819 int i;
2820
2821 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2822 if (ath_mac_bb_names[i].version == mac_bb_version) {
2823 return ath_mac_bb_names[i].name;
2824 }
2825 }
2826
2827 return "????";
2828 }
2829
2830 /*
2831 * Return the RF name. "????" is returned if the RF is unknown.
2832 */
2833 const char *
2834 ath_rf_name(u16 rf_version)
2835 {
2836 int i;
2837
2838 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2839 if (ath_rf_names[i].version == rf_version) {
2840 return ath_rf_names[i].name;
2841 }
2842 }
2843
2844 return "????";
2845 }
2846
2847 static int __init ath9k_init(void)
2848 {
2849 int error;
2850
2851 /* Register rate control algorithm */
2852 error = ath_rate_control_register();
2853 if (error != 0) {
2854 printk(KERN_ERR
2855 "ath9k: Unable to register rate control "
2856 "algorithm: %d\n",
2857 error);
2858 goto err_out;
2859 }
2860
2861 error = ath9k_debug_create_root();
2862 if (error) {
2863 printk(KERN_ERR
2864 "ath9k: Unable to create debugfs root: %d\n",
2865 error);
2866 goto err_rate_unregister;
2867 }
2868
2869 error = ath_pci_init();
2870 if (error < 0) {
2871 printk(KERN_ERR
2872 "ath9k: No PCI devices found, driver not installed.\n");
2873 error = -ENODEV;
2874 goto err_remove_root;
2875 }
2876
2877 error = ath_ahb_init();
2878 if (error < 0) {
2879 error = -ENODEV;
2880 goto err_pci_exit;
2881 }
2882
2883 return 0;
2884
2885 err_pci_exit:
2886 ath_pci_exit();
2887
2888 err_remove_root:
2889 ath9k_debug_remove_root();
2890 err_rate_unregister:
2891 ath_rate_control_unregister();
2892 err_out:
2893 return error;
2894 }
2895 module_init(ath9k_init);
2896
2897 static void __exit ath9k_exit(void)
2898 {
2899 ath_ahb_exit();
2900 ath_pci_exit();
2901 ath9k_debug_remove_root();
2902 ath_rate_control_unregister();
2903 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2904 }
2905 module_exit(ath9k_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree