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rt2x00: Disable synchronization during initialization
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
blobf7731fb82555745488391a0f4e3f9f72a81c3119
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
38
39 /*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
53 {
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65 }
66
67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value)
69 {
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2500pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91 }
92
93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94 const unsigned int word, u8 *value)
95 {
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2500pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2500pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128 }
129
130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
131 const unsigned int word, const u32 value)
132 {
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149 rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158 }
159
160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161 {
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173 }
174
175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176 {
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188 }
189
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
194 const unsigned int word, u32 *data)
195 {
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197 }
198
199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, u32 data)
201 {
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203 }
204
205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2500pci_read_csr,
209 .write = rt2500pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2500pci_bbp_read,
221 .write = rt2500pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2500pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231 };
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234 #ifdef CONFIG_RT2500PCI_RFKILL
235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236 {
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241 }
242 #else
243 #define rt2500pci_rfkill_poll NULL
244 #endif /* CONFIG_RT2500PCI_RFKILL */
245
246 #ifdef CONFIG_RT2500PCI_LEDS
247 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
249 {
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 u32 reg;
254
255 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
257 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
258 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
259 else if (led->type == LED_TYPE_ACTIVITY)
260 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
261
262 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263 }
264
265 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
266 unsigned long *delay_on,
267 unsigned long *delay_off)
268 {
269 struct rt2x00_led *led =
270 container_of(led_cdev, struct rt2x00_led, led_dev);
271 u32 reg;
272
273 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278 return 0;
279 }
280 #endif /* CONFIG_RT2500PCI_LEDS */
281
282 /*
283 * Configuration handlers.
284 */
285 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
286 const unsigned int filter_flags)
287 {
288 u32 reg;
289
290 /*
291 * Start configuration steps.
292 * Note that the version error will always be dropped
293 * and broadcast frames will always be accepted since
294 * there is no filter for it at this time.
295 */
296 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
297 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
298 !(filter_flags & FIF_FCSFAIL));
299 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
300 !(filter_flags & FIF_PLCPFAIL));
301 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
302 !(filter_flags & FIF_CONTROL));
303 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
304 !(filter_flags & FIF_PROMISC_IN_BSS));
305 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
306 !(filter_flags & FIF_PROMISC_IN_BSS) &&
307 !rt2x00dev->intf_ap_count);
308 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
309 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
310 !(filter_flags & FIF_ALLMULTI));
311 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
312 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
313 }
314
315 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
316 struct rt2x00_intf *intf,
317 struct rt2x00intf_conf *conf,
318 const unsigned int flags)
319 {
320 struct data_queue *queue =
321 rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
322 unsigned int bcn_preload;
323 u32 reg;
324
325 if (flags & CONFIG_UPDATE_TYPE) {
326 /*
327 * Enable beacon config
328 */
329 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
330 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
331 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
332 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
333 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
334
335 /*
336 * Enable synchronisation.
337 */
338 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
339 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
340 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
341 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
342 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
343 }
344
345 if (flags & CONFIG_UPDATE_MAC)
346 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
347 conf->mac, sizeof(conf->mac));
348
349 if (flags & CONFIG_UPDATE_BSSID)
350 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
351 conf->bssid, sizeof(conf->bssid));
352 }
353
354 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
355 struct rt2x00lib_erp *erp)
356 {
357 int preamble_mask;
358 u32 reg;
359
360 /*
361 * When short preamble is enabled, we should set bit 0x08
362 */
363 preamble_mask = erp->short_preamble << 3;
364
365 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
366 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
367 erp->ack_timeout);
368 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
369 erp->ack_consume_time);
370 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
371
372 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
373 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
374 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
375 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
376 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
377
378 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
379 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
380 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
381 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
382 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
383
384 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
385 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
386 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
387 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
388 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
389
390 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
391 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
392 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
393 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
394 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
395 }
396
397 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
398 const int basic_rate_mask)
399 {
400 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
401 }
402
403 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
404 struct rf_channel *rf, const int txpower)
405 {
406 u8 r70;
407
408 /*
409 * Set TXpower.
410 */
411 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
412
413 /*
414 * Switch on tuning bits.
415 * For RT2523 devices we do not need to update the R1 register.
416 */
417 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
418 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
419 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
420
421 /*
422 * For RT2525 we should first set the channel to half band higher.
423 */
424 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
425 static const u32 vals[] = {
426 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
427 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
428 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
429 0x00080d2e, 0x00080d3a
430 };
431
432 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
433 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
434 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
435 if (rf->rf4)
436 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
437 }
438
439 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
440 rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
441 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
442 if (rf->rf4)
443 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
444
445 /*
446 * Channel 14 requires the Japan filter bit to be set.
447 */
448 r70 = 0x46;
449 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
450 rt2500pci_bbp_write(rt2x00dev, 70, r70);
451
452 msleep(1);
453
454 /*
455 * Switch off tuning bits.
456 * For RT2523 devices we do not need to update the R1 register.
457 */
458 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
459 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
460 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
461 }
462
463 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
464 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
465
466 /*
467 * Clear false CRC during channel switch.
468 */
469 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
470 }
471
472 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
473 const int txpower)
474 {
475 u32 rf3;
476
477 rt2x00_rf_read(rt2x00dev, 3, &rf3);
478 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
479 rt2500pci_rf_write(rt2x00dev, 3, rf3);
480 }
481
482 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
483 struct antenna_setup *ant)
484 {
485 u32 reg;
486 u8 r14;
487 u8 r2;
488
489 /*
490 * We should never come here because rt2x00lib is supposed
491 * to catch this and send us the correct antenna explicitely.
492 */
493 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
494 ant->tx == ANTENNA_SW_DIVERSITY);
495
496 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
497 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
498 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
499
500 /*
501 * Configure the TX antenna.
502 */
503 switch (ant->tx) {
504 case ANTENNA_A:
505 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
506 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
507 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
508 break;
509 case ANTENNA_B:
510 default:
511 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
512 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
513 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
514 break;
515 }
516
517 /*
518 * Configure the RX antenna.
519 */
520 switch (ant->rx) {
521 case ANTENNA_A:
522 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
523 break;
524 case ANTENNA_B:
525 default:
526 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
527 break;
528 }
529
530 /*
531 * RT2525E and RT5222 need to flip TX I/Q
532 */
533 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
534 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
535 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
536 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
537 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
538
539 /*
540 * RT2525E does not need RX I/Q Flip.
541 */
542 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
543 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
544 } else {
545 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
546 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
547 }
548
549 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
550 rt2500pci_bbp_write(rt2x00dev, 14, r14);
551 rt2500pci_bbp_write(rt2x00dev, 2, r2);
552 }
553
554 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
555 struct rt2x00lib_conf *libconf)
556 {
557 u32 reg;
558
559 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
560 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
561 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
562
563 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
564 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
565 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
566 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
567
568 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
569 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
570 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
571 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
572
573 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
574 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
575 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
576 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
577
578 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
579 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
580 libconf->conf->beacon_int * 16);
581 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
582 libconf->conf->beacon_int * 16);
583 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
584 }
585
586 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
587 struct rt2x00lib_conf *libconf,
588 const unsigned int flags)
589 {
590 if (flags & CONFIG_UPDATE_PHYMODE)
591 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
592 if (flags & CONFIG_UPDATE_CHANNEL)
593 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
594 libconf->conf->power_level);
595 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
596 rt2500pci_config_txpower(rt2x00dev,
597 libconf->conf->power_level);
598 if (flags & CONFIG_UPDATE_ANTENNA)
599 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
600 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
601 rt2500pci_config_duration(rt2x00dev, libconf);
602 }
603
604 /*
605 * Link tuning
606 */
607 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
608 struct link_qual *qual)
609 {
610 u32 reg;
611
612 /*
613 * Update FCS error count from register.
614 */
615 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
616 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
617
618 /*
619 * Update False CCA count from register.
620 */
621 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
622 qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
623 }
624
625 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
626 {
627 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
628 rt2x00dev->link.vgc_level = 0x48;
629 }
630
631 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
632 {
633 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
634 u8 r17;
635
636 /*
637 * To prevent collisions with MAC ASIC on chipsets
638 * up to version C the link tuning should halt after 20
639 * seconds while being associated.
640 */
641 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
642 rt2x00dev->intf_associated &&
643 rt2x00dev->link.count > 20)
644 return;
645
646 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
647
648 /*
649 * Chipset versions C and lower should directly continue
650 * to the dynamic CCA tuning. Chipset version D and higher
651 * should go straight to dynamic CCA tuning when they
652 * are not associated.
653 */
654 if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
655 !rt2x00dev->intf_associated)
656 goto dynamic_cca_tune;
657
658 /*
659 * A too low RSSI will cause too much false CCA which will
660 * then corrupt the R17 tuning. To remidy this the tuning should
661 * be stopped (While making sure the R17 value will not exceed limits)
662 */
663 if (rssi < -80 && rt2x00dev->link.count > 20) {
664 if (r17 >= 0x41) {
665 r17 = rt2x00dev->link.vgc_level;
666 rt2500pci_bbp_write(rt2x00dev, 17, r17);
667 }
668 return;
669 }
670
671 /*
672 * Special big-R17 for short distance
673 */
674 if (rssi >= -58) {
675 if (r17 != 0x50)
676 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
677 return;
678 }
679
680 /*
681 * Special mid-R17 for middle distance
682 */
683 if (rssi >= -74) {
684 if (r17 != 0x41)
685 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
686 return;
687 }
688
689 /*
690 * Leave short or middle distance condition, restore r17
691 * to the dynamic tuning range.
692 */
693 if (r17 >= 0x41) {
694 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
695 return;
696 }
697
698 dynamic_cca_tune:
699
700 /*
701 * R17 is inside the dynamic tuning range,
702 * start tuning the link based on the false cca counter.
703 */
704 if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
705 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
706 rt2x00dev->link.vgc_level = r17;
707 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
708 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
709 rt2x00dev->link.vgc_level = r17;
710 }
711 }
712
713 /*
714 * Initialization functions.
715 */
716 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
717 struct queue_entry *entry)
718 {
719 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
720 u32 word;
721
722 rt2x00_desc_read(priv_rx->desc, 1, &word);
723 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
724 rt2x00_desc_write(priv_rx->desc, 1, word);
725
726 rt2x00_desc_read(priv_rx->desc, 0, &word);
727 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
728 rt2x00_desc_write(priv_rx->desc, 0, word);
729 }
730
731 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
732 struct queue_entry *entry)
733 {
734 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
735 u32 word;
736
737 rt2x00_desc_read(priv_tx->desc, 1, &word);
738 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
739 rt2x00_desc_write(priv_tx->desc, 1, word);
740
741 rt2x00_desc_read(priv_tx->desc, 0, &word);
742 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
743 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
744 rt2x00_desc_write(priv_tx->desc, 0, word);
745 }
746
747 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
748 {
749 struct queue_entry_priv_pci_rx *priv_rx;
750 struct queue_entry_priv_pci_tx *priv_tx;
751 u32 reg;
752
753 /*
754 * Initialize registers.
755 */
756 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
757 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
758 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
759 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
760 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
761 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
762
763 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
764 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
765 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
766 priv_tx->desc_dma);
767 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
768
769 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
770 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
771 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
772 priv_tx->desc_dma);
773 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
774
775 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
776 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
777 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
778 priv_tx->desc_dma);
779 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
780
781 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
782 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
783 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
784 priv_tx->desc_dma);
785 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
786
787 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
788 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
789 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
790 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
791
792 priv_rx = rt2x00dev->rx->entries[0].priv_data;
793 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
794 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
795 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
796
797 return 0;
798 }
799
800 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
801 {
802 u32 reg;
803
804 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
805 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
806 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
807 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
808
809 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
810 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
811 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
812 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
813 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
814
815 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
816 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
817 rt2x00dev->rx->data_size / 128);
818 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
819
820 /*
821 * Always use CWmin and CWmax set in descriptor.
822 */
823 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
824 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
825 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
826
827 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
828 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
829 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
830 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
831 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
832 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
833 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
834 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
835 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
836 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
837
838 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
839
840 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
841 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
842 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
843 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
844 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
845 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
846 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
847 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
848 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
849 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
850
851 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
852 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
853 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
854 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
855 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
856 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
857
858 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
859 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
860 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
861 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
862 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
863 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
864
865 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
866 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
867 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
868 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
869 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
870 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
871
872 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
873 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
874 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
875 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
876 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
877 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
878 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
879 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
880 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
881 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
882
883 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
884 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
885 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
886 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
887 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
888 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
889 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
890 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
891 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
892
893 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
894
895 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
896 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
897
898 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
899 return -EBUSY;
900
901 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
902 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
903
904 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
905 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
906 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
907
908 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
909 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
910 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
911 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
912 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
913 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
914 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
915 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
916
917 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
918
919 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
920
921 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
922 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
923 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
924 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
925 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
926
927 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
928 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
929 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
930 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
931
932 /*
933 * We must clear the FCS and FIFO error count.
934 * These registers are cleared on read,
935 * so we may pass a useless variable to store the value.
936 */
937 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
938 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
939
940 return 0;
941 }
942
943 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
944 {
945 unsigned int i;
946 u16 eeprom;
947 u8 reg_id;
948 u8 value;
949
950 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
951 rt2500pci_bbp_read(rt2x00dev, 0, &value);
952 if ((value != 0xff) && (value != 0x00))
953 goto continue_csr_init;
954 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
955 udelay(REGISTER_BUSY_DELAY);
956 }
957
958 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
959 return -EACCES;
960
961 continue_csr_init:
962 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
963 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
964 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
965 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
966 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
967 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
968 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
969 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
970 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
971 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
972 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
973 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
974 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
975 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
976 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
977 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
978 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
979 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
980 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
981 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
982 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
983 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
984 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
985 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
986 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
987 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
988 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
989 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
990 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
991 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
992
993 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
994 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
995
996 if (eeprom != 0xffff && eeprom != 0x0000) {
997 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
998 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
999 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1000 }
1001 }
1002
1003 return 0;
1004 }
1005
1006 /*
1007 * Device state switch handlers.
1008 */
1009 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1010 enum dev_state state)
1011 {
1012 u32 reg;
1013
1014 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1015 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1016 state == STATE_RADIO_RX_OFF);
1017 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1018 }
1019
1020 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1021 enum dev_state state)
1022 {
1023 int mask = (state == STATE_RADIO_IRQ_OFF);
1024 u32 reg;
1025
1026 /*
1027 * When interrupts are being enabled, the interrupt registers
1028 * should clear the register to assure a clean state.
1029 */
1030 if (state == STATE_RADIO_IRQ_ON) {
1031 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1032 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1033 }
1034
1035 /*
1036 * Only toggle the interrupts bits we are going to use.
1037 * Non-checked interrupt bits are disabled by default.
1038 */
1039 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1040 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1041 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1042 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1043 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1044 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1045 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1046 }
1047
1048 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1049 {
1050 /*
1051 * Initialize all registers.
1052 */
1053 if (rt2500pci_init_queues(rt2x00dev) ||
1054 rt2500pci_init_registers(rt2x00dev) ||
1055 rt2500pci_init_bbp(rt2x00dev)) {
1056 ERROR(rt2x00dev, "Register initialization failed.\n");
1057 return -EIO;
1058 }
1059
1060 /*
1061 * Enable interrupts.
1062 */
1063 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1064
1065 return 0;
1066 }
1067
1068 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1069 {
1070 u32 reg;
1071
1072 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1073
1074 /*
1075 * Disable synchronisation.
1076 */
1077 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1078
1079 /*
1080 * Cancel RX and TX.
1081 */
1082 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1083 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1084 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1085
1086 /*
1087 * Disable interrupts.
1088 */
1089 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1090 }
1091
1092 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1093 enum dev_state state)
1094 {
1095 u32 reg;
1096 unsigned int i;
1097 char put_to_sleep;
1098 char bbp_state;
1099 char rf_state;
1100
1101 put_to_sleep = (state != STATE_AWAKE);
1102
1103 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1104 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1105 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1106 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1107 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1108 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1109
1110 /*
1111 * Device is not guaranteed to be in the requested state yet.
1112 * We must wait until the register indicates that the
1113 * device has entered the correct state.
1114 */
1115 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1116 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1117 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1118 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1119 if (bbp_state == state && rf_state == state)
1120 return 0;
1121 msleep(10);
1122 }
1123
1124 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1125 "current device state: bbp %d and rf %d.\n",
1126 state, bbp_state, rf_state);
1127
1128 return -EBUSY;
1129 }
1130
1131 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1132 enum dev_state state)
1133 {
1134 int retval = 0;
1135
1136 switch (state) {
1137 case STATE_RADIO_ON:
1138 retval = rt2500pci_enable_radio(rt2x00dev);
1139 break;
1140 case STATE_RADIO_OFF:
1141 rt2500pci_disable_radio(rt2x00dev);
1142 break;
1143 case STATE_RADIO_RX_ON:
1144 case STATE_RADIO_RX_ON_LINK:
1145 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1146 break;
1147 case STATE_RADIO_RX_OFF:
1148 case STATE_RADIO_RX_OFF_LINK:
1149 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1150 break;
1151 case STATE_DEEP_SLEEP:
1152 case STATE_SLEEP:
1153 case STATE_STANDBY:
1154 case STATE_AWAKE:
1155 retval = rt2500pci_set_state(rt2x00dev, state);
1156 break;
1157 default:
1158 retval = -ENOTSUPP;
1159 break;
1160 }
1161
1162 return retval;
1163 }
1164
1165 /*
1166 * TX descriptor initialization
1167 */
1168 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1169 struct sk_buff *skb,
1170 struct txentry_desc *txdesc,
1171 struct ieee80211_tx_control *control)
1172 {
1173 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1174 __le32 *txd = skbdesc->desc;
1175 u32 word;
1176
1177 /*
1178 * Start writing the descriptor words.
1179 */
1180 rt2x00_desc_read(txd, 2, &word);
1181 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1182 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1183 rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1184 rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1185 rt2x00_desc_write(txd, 2, word);
1186
1187 rt2x00_desc_read(txd, 3, &word);
1188 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1189 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1190 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1191 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1192 rt2x00_desc_write(txd, 3, word);
1193
1194 rt2x00_desc_read(txd, 10, &word);
1195 rt2x00_set_field32(&word, TXD_W10_RTS,
1196 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1197 rt2x00_desc_write(txd, 10, word);
1198
1199 rt2x00_desc_read(txd, 0, &word);
1200 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1201 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1202 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1203 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1204 rt2x00_set_field32(&word, TXD_W0_ACK,
1205 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1206 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1207 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1208 rt2x00_set_field32(&word, TXD_W0_OFDM,
1209 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1210 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1211 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1212 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1213 !!(control->flags &
1214 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1215 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1216 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1217 rt2x00_desc_write(txd, 0, word);
1218 }
1219
1220 /*
1221 * TX data initialization
1222 */
1223 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1224 const unsigned int queue)
1225 {
1226 u32 reg;
1227
1228 if (queue == RT2X00_BCN_QUEUE_BEACON) {
1229 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1230 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1231 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1232 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1233 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1234 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1235 }
1236 return;
1237 }
1238
1239 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1240 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1241 (queue == IEEE80211_TX_QUEUE_DATA0));
1242 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1243 (queue == IEEE80211_TX_QUEUE_DATA1));
1244 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1245 (queue == RT2X00_BCN_QUEUE_ATIM));
1246 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1247 }
1248
1249 /*
1250 * RX control handlers
1251 */
1252 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1253 struct rxdone_entry_desc *rxdesc)
1254 {
1255 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1256 u32 word0;
1257 u32 word2;
1258
1259 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1260 rt2x00_desc_read(priv_rx->desc, 2, &word2);
1261
1262 rxdesc->flags = 0;
1263 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1264 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1265 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1266 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1267
1268 /*
1269 * Obtain the status about this packet.
1270 * When frame was received with an OFDM bitrate,
1271 * the signal is the PLCP value. If it was received with
1272 * a CCK bitrate the signal is the rate in 100kbit/s.
1273 */
1274 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1275 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1276 entry->queue->rt2x00dev->rssi_offset;
1277 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1278
1279 rxdesc->dev_flags = 0;
1280 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1281 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1282 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1283 rxdesc->dev_flags |= RXDONE_MY_BSS;
1284 }
1285
1286 /*
1287 * Interrupt functions.
1288 */
1289 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1290 const enum ieee80211_tx_queue queue_idx)
1291 {
1292 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1293 struct queue_entry_priv_pci_tx *priv_tx;
1294 struct queue_entry *entry;
1295 struct txdone_entry_desc txdesc;
1296 u32 word;
1297
1298 while (!rt2x00queue_empty(queue)) {
1299 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1300 priv_tx = entry->priv_data;
1301 rt2x00_desc_read(priv_tx->desc, 0, &word);
1302
1303 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1304 !rt2x00_get_field32(word, TXD_W0_VALID))
1305 break;
1306
1307 /*
1308 * Obtain the status about this packet.
1309 */
1310 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1311 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1312
1313 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1314 }
1315 }
1316
1317 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1318 {
1319 struct rt2x00_dev *rt2x00dev = dev_instance;
1320 u32 reg;
1321
1322 /*
1323 * Get the interrupt sources & saved to local variable.
1324 * Write register value back to clear pending interrupts.
1325 */
1326 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1327 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1328
1329 if (!reg)
1330 return IRQ_NONE;
1331
1332 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1333 return IRQ_HANDLED;
1334
1335 /*
1336 * Handle interrupts, walk through all bits
1337 * and run the tasks, the bits are checked in order of
1338 * priority.
1339 */
1340
1341 /*
1342 * 1 - Beacon timer expired interrupt.
1343 */
1344 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1345 rt2x00lib_beacondone(rt2x00dev);
1346
1347 /*
1348 * 2 - Rx ring done interrupt.
1349 */
1350 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1351 rt2x00pci_rxdone(rt2x00dev);
1352
1353 /*
1354 * 3 - Atim ring transmit done interrupt.
1355 */
1356 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1357 rt2500pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1358
1359 /*
1360 * 4 - Priority ring transmit done interrupt.
1361 */
1362 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1363 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1364
1365 /*
1366 * 5 - Tx ring transmit done interrupt.
1367 */
1368 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1369 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1370
1371 return IRQ_HANDLED;
1372 }
1373
1374 /*
1375 * Device probe functions.
1376 */
1377 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1378 {
1379 struct eeprom_93cx6 eeprom;
1380 u32 reg;
1381 u16 word;
1382 u8 *mac;
1383
1384 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1385
1386 eeprom.data = rt2x00dev;
1387 eeprom.register_read = rt2500pci_eepromregister_read;
1388 eeprom.register_write = rt2500pci_eepromregister_write;
1389 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1390 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1391 eeprom.reg_data_in = 0;
1392 eeprom.reg_data_out = 0;
1393 eeprom.reg_data_clock = 0;
1394 eeprom.reg_chip_select = 0;
1395
1396 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1397 EEPROM_SIZE / sizeof(u16));
1398
1399 /*
1400 * Start validation of the data that has been read.
1401 */
1402 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1403 if (!is_valid_ether_addr(mac)) {
1404 DECLARE_MAC_BUF(macbuf);
1405
1406 random_ether_addr(mac);
1407 EEPROM(rt2x00dev, "MAC: %s\n",
1408 print_mac(macbuf, mac));
1409 }
1410
1411 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1412 if (word == 0xffff) {
1413 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1414 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1415 ANTENNA_SW_DIVERSITY);
1416 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1417 ANTENNA_SW_DIVERSITY);
1418 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1419 LED_MODE_DEFAULT);
1420 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1421 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1422 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1423 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1424 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1425 }
1426
1427 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1428 if (word == 0xffff) {
1429 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1430 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1431 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1432 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1433 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1434 }
1435
1436 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1437 if (word == 0xffff) {
1438 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1439 DEFAULT_RSSI_OFFSET);
1440 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1441 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1442 }
1443
1444 return 0;
1445 }
1446
1447 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1448 {
1449 u32 reg;
1450 u16 value;
1451 u16 eeprom;
1452
1453 /*
1454 * Read EEPROM word for configuration.
1455 */
1456 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1457
1458 /*
1459 * Identify RF chipset.
1460 */
1461 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1462 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1463 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1464
1465 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1466 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1467 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1468 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1469 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1470 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1471 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1472 return -ENODEV;
1473 }
1474
1475 /*
1476 * Identify default antenna configuration.
1477 */
1478 rt2x00dev->default_ant.tx =
1479 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1480 rt2x00dev->default_ant.rx =
1481 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1482
1483 /*
1484 * Store led mode, for correct led behaviour.
1485 */
1486 #ifdef CONFIG_RT2500PCI_LEDS
1487 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1488
1489 rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1490 rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1491 rt2x00dev->led_radio.led_dev.brightness_set =
1492 rt2500pci_brightness_set;
1493 rt2x00dev->led_radio.led_dev.blink_set =
1494 rt2500pci_blink_set;
1495 rt2x00dev->led_radio.flags = LED_INITIALIZED;
1496
1497 if (value == LED_MODE_TXRX_ACTIVITY) {
1498 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1499 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1500 rt2x00dev->led_qual.led_dev.brightness_set =
1501 rt2500pci_brightness_set;
1502 rt2x00dev->led_qual.led_dev.blink_set =
1503 rt2500pci_blink_set;
1504 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1505 }
1506 #endif /* CONFIG_RT2500PCI_LEDS */
1507
1508 /*
1509 * Detect if this device has an hardware controlled radio.
1510 */
1511 #ifdef CONFIG_RT2500PCI_RFKILL
1512 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1513 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1514 #endif /* CONFIG_RT2500PCI_RFKILL */
1515
1516 /*
1517 * Check if the BBP tuning should be enabled.
1518 */
1519 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1520
1521 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1522 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1523
1524 /*
1525 * Read the RSSI <-> dBm offset information.
1526 */
1527 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1528 rt2x00dev->rssi_offset =
1529 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1530
1531 return 0;
1532 }
1533
1534 /*
1535 * RF value list for RF2522
1536 * Supports: 2.4 GHz
1537 */
1538 static const struct rf_channel rf_vals_bg_2522[] = {
1539 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1540 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1541 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1542 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1543 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1544 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1545 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1546 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1547 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1548 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1549 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1550 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1551 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1552 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1553 };
1554
1555 /*
1556 * RF value list for RF2523
1557 * Supports: 2.4 GHz
1558 */
1559 static const struct rf_channel rf_vals_bg_2523[] = {
1560 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1561 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1562 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1563 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1564 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1565 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1566 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1567 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1568 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1569 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1570 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1571 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1572 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1573 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1574 };
1575
1576 /*
1577 * RF value list for RF2524
1578 * Supports: 2.4 GHz
1579 */
1580 static const struct rf_channel rf_vals_bg_2524[] = {
1581 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1582 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1583 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1584 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1585 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1586 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1587 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1588 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1589 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1590 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1591 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1592 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1593 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1594 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1595 };
1596
1597 /*
1598 * RF value list for RF2525
1599 * Supports: 2.4 GHz
1600 */
1601 static const struct rf_channel rf_vals_bg_2525[] = {
1602 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1603 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1604 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1605 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1606 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1607 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1608 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1609 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1610 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1611 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1612 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1613 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1614 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1615 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1616 };
1617
1618 /*
1619 * RF value list for RF2525e
1620 * Supports: 2.4 GHz
1621 */
1622 static const struct rf_channel rf_vals_bg_2525e[] = {
1623 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1624 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1625 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1626 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1627 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1628 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1629 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1630 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1631 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1632 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1633 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1634 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1635 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1636 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1637 };
1638
1639 /*
1640 * RF value list for RF5222
1641 * Supports: 2.4 GHz & 5.2 GHz
1642 */
1643 static const struct rf_channel rf_vals_5222[] = {
1644 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1645 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1646 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1647 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1648 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1649 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1650 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1651 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1652 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1653 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1654 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1655 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1656 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1657 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1658
1659 /* 802.11 UNI / HyperLan 2 */
1660 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1661 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1662 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1663 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1664 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1665 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1666 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1667 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1668
1669 /* 802.11 HyperLan 2 */
1670 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1671 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1672 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1673 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1674 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1675 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1676 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1677 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1678 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1679 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1680
1681 /* 802.11 UNII */
1682 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1683 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1684 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1685 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1686 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1687 };
1688
1689 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1690 {
1691 struct hw_mode_spec *spec = &rt2x00dev->spec;
1692 u8 *txpower;
1693 unsigned int i;
1694
1695 /*
1696 * Initialize all hw fields.
1697 */
1698 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1699 rt2x00dev->hw->extra_tx_headroom = 0;
1700 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1701 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1702 rt2x00dev->hw->queues = 2;
1703
1704 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1705 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1706 rt2x00_eeprom_addr(rt2x00dev,
1707 EEPROM_MAC_ADDR_0));
1708
1709 /*
1710 * Convert tx_power array in eeprom.
1711 */
1712 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1713 for (i = 0; i < 14; i++)
1714 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1715
1716 /*
1717 * Initialize hw_mode information.
1718 */
1719 spec->supported_bands = SUPPORT_BAND_2GHZ;
1720 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1721 spec->tx_power_a = NULL;
1722 spec->tx_power_bg = txpower;
1723 spec->tx_power_default = DEFAULT_TXPOWER;
1724
1725 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1726 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1727 spec->channels = rf_vals_bg_2522;
1728 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1729 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1730 spec->channels = rf_vals_bg_2523;
1731 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1732 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1733 spec->channels = rf_vals_bg_2524;
1734 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1735 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1736 spec->channels = rf_vals_bg_2525;
1737 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1738 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1739 spec->channels = rf_vals_bg_2525e;
1740 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1741 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1742 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1743 spec->channels = rf_vals_5222;
1744 }
1745 }
1746
1747 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1748 {
1749 int retval;
1750
1751 /*
1752 * Allocate eeprom data.
1753 */
1754 retval = rt2500pci_validate_eeprom(rt2x00dev);
1755 if (retval)
1756 return retval;
1757
1758 retval = rt2500pci_init_eeprom(rt2x00dev);
1759 if (retval)
1760 return retval;
1761
1762 /*
1763 * Initialize hw specifications.
1764 */
1765 rt2500pci_probe_hw_mode(rt2x00dev);
1766
1767 /*
1768 * This device requires the atim queue
1769 */
1770 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1771
1772 /*
1773 * Set the rssi offset.
1774 */
1775 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1776
1777 return 0;
1778 }
1779
1780 /*
1781 * IEEE80211 stack callback functions.
1782 */
1783 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1784 u32 short_retry, u32 long_retry)
1785 {
1786 struct rt2x00_dev *rt2x00dev = hw->priv;
1787 u32 reg;
1788
1789 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1790 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1791 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1792 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1793
1794 return 0;
1795 }
1796
1797 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1798 {
1799 struct rt2x00_dev *rt2x00dev = hw->priv;
1800 u64 tsf;
1801 u32 reg;
1802
1803 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1804 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1805 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1806 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1807
1808 return tsf;
1809 }
1810
1811 static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1812 struct ieee80211_tx_control *control)
1813 {
1814 struct rt2x00_dev *rt2x00dev = hw->priv;
1815 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1816 struct queue_entry_priv_pci_tx *priv_tx;
1817 struct skb_frame_desc *skbdesc;
1818 u32 reg;
1819
1820 if (unlikely(!intf->beacon))
1821 return -ENOBUFS;
1822
1823 priv_tx = intf->beacon->priv_data;
1824
1825 /*
1826 * Fill in skb descriptor
1827 */
1828 skbdesc = get_skb_frame_desc(skb);
1829 memset(skbdesc, 0, sizeof(*skbdesc));
1830 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1831 skbdesc->data = skb->data;
1832 skbdesc->data_len = skb->len;
1833 skbdesc->desc = priv_tx->desc;
1834 skbdesc->desc_len = intf->beacon->queue->desc_size;
1835 skbdesc->entry = intf->beacon;
1836
1837 /*
1838 * Disable beaconing while we are reloading the beacon data,
1839 * otherwise we might be sending out invalid data.
1840 */
1841 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1842 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1843 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1844 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1845 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1846
1847 /*
1848 * mac80211 doesn't provide the control->queue variable
1849 * for beacons. Set our own queue identification so
1850 * it can be used during descriptor initialization.
1851 */
1852 control->queue = RT2X00_BCN_QUEUE_BEACON;
1853 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1854
1855 /*
1856 * Enable beacon generation.
1857 * Write entire beacon with descriptor to register,
1858 * and kick the beacon generator.
1859 */
1860 memcpy(priv_tx->data, skb->data, skb->len);
1861 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1862
1863 return 0;
1864 }
1865
1866 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1867 {
1868 struct rt2x00_dev *rt2x00dev = hw->priv;
1869 u32 reg;
1870
1871 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1872 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1873 }
1874
1875 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1876 .tx = rt2x00mac_tx,
1877 .start = rt2x00mac_start,
1878 .stop = rt2x00mac_stop,
1879 .add_interface = rt2x00mac_add_interface,
1880 .remove_interface = rt2x00mac_remove_interface,
1881 .config = rt2x00mac_config,
1882 .config_interface = rt2x00mac_config_interface,
1883 .configure_filter = rt2x00mac_configure_filter,
1884 .get_stats = rt2x00mac_get_stats,
1885 .set_retry_limit = rt2500pci_set_retry_limit,
1886 .bss_info_changed = rt2x00mac_bss_info_changed,
1887 .conf_tx = rt2x00mac_conf_tx,
1888 .get_tx_stats = rt2x00mac_get_tx_stats,
1889 .get_tsf = rt2500pci_get_tsf,
1890 .beacon_update = rt2500pci_beacon_update,
1891 .tx_last_beacon = rt2500pci_tx_last_beacon,
1892 };
1893
1894 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1895 .irq_handler = rt2500pci_interrupt,
1896 .probe_hw = rt2500pci_probe_hw,
1897 .initialize = rt2x00pci_initialize,
1898 .uninitialize = rt2x00pci_uninitialize,
1899 .init_rxentry = rt2500pci_init_rxentry,
1900 .init_txentry = rt2500pci_init_txentry,
1901 .set_device_state = rt2500pci_set_device_state,
1902 .rfkill_poll = rt2500pci_rfkill_poll,
1903 .link_stats = rt2500pci_link_stats,
1904 .reset_tuner = rt2500pci_reset_tuner,
1905 .link_tuner = rt2500pci_link_tuner,
1906 .write_tx_desc = rt2500pci_write_tx_desc,
1907 .write_tx_data = rt2x00pci_write_tx_data,
1908 .kick_tx_queue = rt2500pci_kick_tx_queue,
1909 .fill_rxdone = rt2500pci_fill_rxdone,
1910 .config_filter = rt2500pci_config_filter,
1911 .config_intf = rt2500pci_config_intf,
1912 .config_erp = rt2500pci_config_erp,
1913 .config = rt2500pci_config,
1914 };
1915
1916 static const struct data_queue_desc rt2500pci_queue_rx = {
1917 .entry_num = RX_ENTRIES,
1918 .data_size = DATA_FRAME_SIZE,
1919 .desc_size = RXD_DESC_SIZE,
1920 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1921 };
1922
1923 static const struct data_queue_desc rt2500pci_queue_tx = {
1924 .entry_num = TX_ENTRIES,
1925 .data_size = DATA_FRAME_SIZE,
1926 .desc_size = TXD_DESC_SIZE,
1927 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1928 };
1929
1930 static const struct data_queue_desc rt2500pci_queue_bcn = {
1931 .entry_num = BEACON_ENTRIES,
1932 .data_size = MGMT_FRAME_SIZE,
1933 .desc_size = TXD_DESC_SIZE,
1934 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1935 };
1936
1937 static const struct data_queue_desc rt2500pci_queue_atim = {
1938 .entry_num = ATIM_ENTRIES,
1939 .data_size = DATA_FRAME_SIZE,
1940 .desc_size = TXD_DESC_SIZE,
1941 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1942 };
1943
1944 static const struct rt2x00_ops rt2500pci_ops = {
1945 .name = KBUILD_MODNAME,
1946 .max_sta_intf = 1,
1947 .max_ap_intf = 1,
1948 .eeprom_size = EEPROM_SIZE,
1949 .rf_size = RF_SIZE,
1950 .rx = &rt2500pci_queue_rx,
1951 .tx = &rt2500pci_queue_tx,
1952 .bcn = &rt2500pci_queue_bcn,
1953 .atim = &rt2500pci_queue_atim,
1954 .lib = &rt2500pci_rt2x00_ops,
1955 .hw = &rt2500pci_mac80211_ops,
1956 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1957 .debugfs = &rt2500pci_rt2x00debug,
1958 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1959 };
1960
1961 /*
1962 * RT2500pci module information.
1963 */
1964 static struct pci_device_id rt2500pci_device_table[] = {
1965 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1966 { 0, }
1967 };
1968
1969 MODULE_AUTHOR(DRV_PROJECT);
1970 MODULE_VERSION(DRV_VERSION);
1971 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1972 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1973 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1974 MODULE_LICENSE("GPL");
1975
1976 static struct pci_driver rt2500pci_driver = {
1977 .name = KBUILD_MODNAME,
1978 .id_table = rt2500pci_device_table,
1979 .probe = rt2x00pci_probe,
1980 .remove = __devexit_p(rt2x00pci_remove),
1981 .suspend = rt2x00pci_suspend,
1982 .resume = rt2x00pci_resume,
1983 };
1984
1985 static int __init rt2500pci_init(void)
1986 {
1987 return pci_register_driver(&rt2500pci_driver);
1988 }
1989
1990 static void __exit rt2500pci_exit(void)
1991 {
1992 pci_unregister_driver(&rt2500pci_driver);
1993 }
1994
1995 module_init(rt2500pci_init);
1996 module_exit(rt2500pci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree