drivers/video/via/viamode.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include <linux/via-core.h>
  23 #include "global.h"
  24
  25 struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
  26 {VIASR, SR15, 0x02, 0x02},
  27 {VIASR, SR16, 0xBF, 0x08},
  28 {VIASR, SR17, 0xFF, 0x1F},
  29 {VIASR, SR18, 0xFF, 0x4E},
  30 {VIASR, SR1A, 0xFB, 0x08},
  31 {VIASR, SR1E, 0x0F, 0x01},
  32 {VIASR, SR2A, 0xFF, 0x00},
  33 {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                        */
  34 {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                          */
  35 {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High                */
  36 {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low                */
  37 {VIACR, CR32, 0xFF, 0x00},
  38 {VIACR, CR33, 0xFF, 0x00},
  39 {VIACR, CR35, 0xFF, 0x00},
  40 {VIACR, CR36, 0x08, 0x00},
  41 {VIACR, CR69, 0xFF, 0x00},
  42 {VIACR, CR6A, 0xFF, 0x40},
  43 {VIACR, CR6B, 0xFF, 0x00},
  44 {VIACR, CR6C, 0xFF, 0x00},
  45 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                      */
  46 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0                */
  47 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1                */
  48 {VIACR, CR8B, 0xFF, 0x69},      /* LCD Power Sequence Control 0        */
  49 {VIACR, CR8C, 0xFF, 0x57},      /* LCD Power Sequence Control 1        */
  50 {VIACR, CR8D, 0xFF, 0x00},      /* LCD Power Sequence Control 2        */
  51 {VIACR, CR8E, 0xFF, 0x7B},      /* LCD Power Sequence Control 3        */
  52 {VIACR, CR8F, 0xFF, 0x03},      /* LCD Power Sequence Control 4        */
  53 {VIACR, CR90, 0xFF, 0x30},      /* LCD Power Sequence Control 5        */
  54 {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off             */
  55 {VIACR, CR96, 0xFF, 0x00},
  56 {VIACR, CR97, 0xFF, 0x00},
  57 {VIACR, CR99, 0xFF, 0x00},
  58 {VIACR, CR9B, 0xFF, 0x00}
  59 };
  60
  61 /* Video Mode Table for VT3314 chipset*/
  62 /* Common Setting for Video Mode */
  63 struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
  64 {VIASR, SR15, 0x02, 0x02},
  65 {VIASR, SR16, 0xBF, 0x08},
  66 {VIASR, SR17, 0xFF, 0x1F},
  67 {VIASR, SR18, 0xFF, 0x4E},
  68 {VIASR, SR1A, 0xFB, 0x82},
  69 {VIASR, SR1B, 0xFF, 0xF0},
  70 {VIASR, SR1F, 0xFF, 0x00},
  71 {VIASR, SR1E, 0xFF, 0x01},
  72 {VIASR, SR22, 0xFF, 0x1F},
  73 {VIASR, SR2A, 0x0F, 0x00},
  74 {VIASR, SR2E, 0xFF, 0xFF},
  75 {VIASR, SR3F, 0xFF, 0xFF},
  76 {VIASR, SR40, 0xF7, 0x00},
  77 {VIASR, CR30, 0xFF, 0x04},
  78 {VIACR, CR32, 0xFF, 0x00},
  79 {VIACR, CR33, 0x7F, 0x00},
  80 {VIACR, CR35, 0xFF, 0x00},
  81 {VIACR, CR36, 0xFF, 0x31},
  82 {VIACR, CR41, 0xFF, 0x80},
  83 {VIACR, CR42, 0xFF, 0x00},
  84 {VIACR, CR55, 0x80, 0x00},
  85 {VIACR, CR5D, 0x80, 0x00},      /*Horizontal Retrace Start bit[11] should be 0*/
  86 {VIACR, CR68, 0xFF, 0x67},      /* Default FIFO For IGA2 */
  87 {VIACR, CR69, 0xFF, 0x00},
  88 {VIACR, CR6A, 0xFD, 0x40},
  89 {VIACR, CR6B, 0xFF, 0x00},
  90 {VIACR, CR6C, 0xFF, 0x00},
  91 {VIACR, CR77, 0xFF, 0x00},      /* LCD scaling Factor */
  92 {VIACR, CR78, 0xFF, 0x00},      /* LCD scaling Factor */
  93 {VIACR, CR79, 0xFF, 0x00},      /* LCD scaling Factor */
  94 {VIACR, CR9F, 0x03, 0x00},      /* LCD scaling Factor */
  95 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type */
  96 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0 */
  97 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1 */
  98 {VIACR, CR8B, 0xFF, 0x5D},      /* LCD Power Sequence Control 0 */
  99 {VIACR, CR8C, 0xFF, 0x2B},      /* LCD Power Sequence Control 1 */
 100 {VIACR, CR8D, 0xFF, 0x6F},      /* LCD Power Sequence Control 2 */
 101 {VIACR, CR8E, 0xFF, 0x2B},      /* LCD Power Sequence Control 3 */
 102 {VIACR, CR8F, 0xFF, 0x01},      /* LCD Power Sequence Control 4 */
 103 {VIACR, CR90, 0xFF, 0x01},      /* LCD Power Sequence Control 5 */
 104 {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off */
 105 {VIACR, CR96, 0xFF, 0x00},
 106 {VIACR, CR97, 0xFF, 0x00},
 107 {VIACR, CR99, 0xFF, 0x00},
 108 {VIACR, CR9B, 0xFF, 0x00},
 109 {VIACR, CR9D, 0xFF, 0x80},
 110 {VIACR, CR9E, 0xFF, 0x80}
 111 };
 112
 113 struct io_reg KM400_ModeXregs[] = {
 114         {VIASR, SR10, 0xFF, 0x01},      /* Unlock Register                 */
 115         {VIASR, SR16, 0xFF, 0x08},      /* Display FIFO threshold Control  */
 116         {VIASR, SR17, 0xFF, 0x1F},      /* Display FIFO Control            */
 117         {VIASR, SR18, 0xFF, 0x4E},      /* GFX PREQ threshold              */
 118         {VIASR, SR1A, 0xFF, 0x0a},      /* GFX PREQ threshold              */
 119         {VIASR, SR1F, 0xFF, 0x00},      /* Memory Control 0                */
 120         {VIASR, SR1B, 0xFF, 0xF0},      /* Power Management Control 0      */
 121         {VIASR, SR1E, 0xFF, 0x01},      /* Power Management Control        */
 122         {VIASR, SR20, 0xFF, 0x00},      /* Sequencer Arbiter Control 0     */
 123         {VIASR, SR21, 0xFF, 0x00},      /* Sequencer Arbiter Control 1     */
 124         {VIASR, SR22, 0xFF, 0x1F},      /* Display Arbiter Control 1       */
 125         {VIASR, SR2A, 0xFF, 0x00},      /* Power Management Control 5      */
 126         {VIASR, SR2D, 0xFF, 0xFF},      /* Power Management Control 1      */
 127         {VIASR, SR2E, 0xFF, 0xFF},      /* Power Management Control 2      */
 128         {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                    */
 129         {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                      */
 130         {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High            */
 131         {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low            */
 132         {VIACR, CR33, 0xFF, 0x00},
 133         {VIACR, CR55, 0x80, 0x00},
 134         {VIACR, CR5D, 0x80, 0x00},
 135         {VIACR, CR36, 0xFF, 0x01},      /* Power Mangement 3                  */
 136         {VIACR, CR68, 0xFF, 0x67},      /* Default FIFO For IGA2              */
 137         {VIACR, CR6A, 0x20, 0x20},      /* Extended FIFO On                   */
 138         {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                     */
 139         {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0               */
 140         {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1               */
 141         {VIACR, CR8B, 0xFF, 0x2D},      /* LCD Power Sequence Control 0       */
 142         {VIACR, CR8C, 0xFF, 0x2D},      /* LCD Power Sequence Control 1       */
 143         {VIACR, CR8D, 0xFF, 0xC8},      /* LCD Power Sequence Control 2       */
 144         {VIACR, CR8E, 0xFF, 0x36},      /* LCD Power Sequence Control 3       */
 145         {VIACR, CR8F, 0xFF, 0x00},      /* LCD Power Sequence Control 4       */
 146         {VIACR, CR90, 0xFF, 0x10},      /* LCD Power Sequence Control 5       */
 147         {VIACR, CR91, 0xFF, 0xA0},      /* 24/12 bit LVDS Data off            */
 148         {VIACR, CR96, 0xFF, 0x03},      /* DVP0        ; DVP0 Clock Skew */
 149         {VIACR, CR97, 0xFF, 0x03},      /* DFP high    ; DFPH Clock Skew */
 150         {VIACR, CR99, 0xFF, 0x03},      /* DFP low           ; DFPL Clock Skew*/
 151         {VIACR, CR9B, 0xFF, 0x07}       /* DVI on DVP1       ; DVP1 Clock Skew*/
 152 };
 153
 154 /* For VT3324: Common Setting for Video Mode */
 155 struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
 156 {VIASR, SR15, 0x02, 0x02},
 157 {VIASR, SR16, 0xBF, 0x08},
 158 {VIASR, SR17, 0xFF, 0x1F},
 159 {VIASR, SR18, 0xFF, 0x4E},
 160 {VIASR, SR1A, 0xFB, 0x08},
 161 {VIASR, SR1B, 0xFF, 0xF0},
 162 {VIASR, SR1E, 0xFF, 0x01},
 163 {VIASR, SR2A, 0xFF, 0x00},
 164 {VIASR, SR2D, 0xFF, 0xFF},      /* VCK and LCK PLL power on.           */
 165 {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                        */
 166 {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                          */
 167 {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High                */
 168 {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low                */
 169 {VIACR, CR32, 0xFF, 0x00},
 170 {VIACR, CR33, 0xFF, 0x00},
 171 {VIACR, CR35, 0xFF, 0x00},
 172 {VIACR, CR36, 0x08, 0x00},
 173 {VIACR, CR47, 0xC8, 0x00},      /* Clear VCK Plus. */
 174 {VIACR, CR69, 0xFF, 0x00},
 175 {VIACR, CR6A, 0xFF, 0x40},
 176 {VIACR, CR6B, 0xFF, 0x00},
 177 {VIACR, CR6C, 0xFF, 0x00},
 178 {VIACR, CR88, 0xFF, 0x40},      /* LCD Panel Type                      */
 179 {VIACR, CR89, 0xFF, 0x00},      /* LCD Timing Control 0                */
 180 {VIACR, CR8A, 0xFF, 0x88},      /* LCD Timing Control 1                */
 181 {VIACR, CRD4, 0xFF, 0x81},      /* Second power sequence control       */
 182 {VIACR, CR8B, 0xFF, 0x5D},      /* LCD Power Sequence Control 0        */
 183 {VIACR, CR8C, 0xFF, 0x2B},      /* LCD Power Sequence Control 1        */
 184 {VIACR, CR8D, 0xFF, 0x6F},      /* LCD Power Sequence Control 2        */
 185 {VIACR, CR8E, 0xFF, 0x2B},      /* LCD Power Sequence Control 3        */
 186 {VIACR, CR8F, 0xFF, 0x01},      /* LCD Power Sequence Control 4        */
 187 {VIACR, CR90, 0xFF, 0x01},      /* LCD Power Sequence Control 5        */
 188 {VIACR, CR91, 0xFF, 0x80},      /* 24/12 bit LVDS Data off             */
 189 {VIACR, CR96, 0xFF, 0x00},
 190 {VIACR, CR97, 0xFF, 0x00},
 191 {VIACR, CR99, 0xFF, 0x00},
 192 {VIACR, CR9B, 0xFF, 0x00}
 193 };
 194
 195 struct io_reg VX855_ModeXregs[] = {
 196 {VIASR, SR10, 0xFF, 0x01},
 197 {VIASR, SR15, 0x02, 0x02},
 198 {VIASR, SR16, 0xBF, 0x08},
 199 {VIASR, SR17, 0xFF, 0x1F},
 200 {VIASR, SR18, 0xFF, 0x4E},
 201 {VIASR, SR1A, 0xFB, 0x08},
 202 {VIASR, SR1B, 0xFF, 0xF0},
 203 {VIASR, SR1E, 0x07, 0x01},
 204 {VIASR, SR2A, 0xF0, 0x00},
 205 {VIASR, SR58, 0xFF, 0x00},
 206 {VIASR, SR59, 0xFF, 0x00},
 207 {VIASR, SR2D, 0xFF, 0xFF},      /* VCK and LCK PLL power on.           */
 208 {VIACR, CR09, 0xFF, 0x00},      /* Initial CR09=0*/
 209 {VIACR, CR11, 0x8F, 0x00},      /* IGA1 initial  Vertical end       */
 210 {VIACR, CR17, 0x7F, 0x00},      /* IGA1 CRT Mode control init   */
 211 {VIACR, CR0A, 0xFF, 0x1E},      /* Cursor Start                        */
 212 {VIACR, CR0B, 0xFF, 0x00},      /* Cursor End                          */
 213 {VIACR, CR0E, 0xFF, 0x00},      /* Cursor Location High                */
 214 {VIACR, CR0F, 0xFF, 0x00},      /* Cursor Localtion Low                */
 215 {VIACR, CR32, 0xFF, 0x00},
 216 {VIACR, CR33, 0x7F, 0x00},
 217 {VIACR, CR35, 0xFF, 0x00},
 218 {VIACR, CR36, 0x08, 0x00},
 219 {VIACR, CR69, 0xFF, 0x00},
 220 {VIACR, CR6A, 0xFD, 0x60},
 221 {VIACR, CR6B, 0xFF, 0x00},
 222 {VIACR, CR6C, 0xFF, 0x00},
 223 {VIACR, CR88, 0xFF, 0x40},          /* LCD Panel Type                      */
 224 {VIACR, CR89, 0xFF, 0x00},          /* LCD Timing Control 0                */
 225 {VIACR, CR8A, 0xFF, 0x88},          /* LCD Timing Control 1                */
 226 {VIACR, CRD4, 0xFF, 0x81},          /* Second power sequence control       */
 227 {VIACR, CR91, 0xFF, 0x80},          /* 24/12 bit LVDS Data off             */
 228 {VIACR, CR96, 0xFF, 0x00},
 229 {VIACR, CR97, 0xFF, 0x00},
 230 {VIACR, CR99, 0xFF, 0x00},
 231 {VIACR, CR9B, 0xFF, 0x00},
 232 {VIACR, CRD2, 0xFF, 0xFF}           /* TMDS/LVDS control register.         */
 233 };
 234
 235 /* Video Mode Table */
 236 /* Common Setting for Video Mode */
 237 struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
 238 {VIASR, SR2A, 0x0F, 0x00},
 239 {VIASR, SR15, 0x02, 0x02},
 240 {VIASR, SR16, 0xBF, 0x08},
 241 {VIASR, SR17, 0xFF, 0x1F},
 242 {VIASR, SR18, 0xFF, 0x4E},
 243 {VIASR, SR1A, 0xFB, 0x08},
 244
 245 {VIACR, CR32, 0xFF, 0x00},
 246 {VIACR, CR35, 0xFF, 0x00},
 247 {VIACR, CR36, 0x08, 0x00},
 248 {VIACR, CR6A, 0xFF, 0x80},
 249 {VIACR, CR6A, 0xFF, 0xC0},
 250
 251 {VIACR, CR55, 0x80, 0x00},
 252 {VIACR, CR5D, 0x80, 0x00},
 253
 254 {VIAGR, GR20, 0xFF, 0x00},
 255 {VIAGR, GR21, 0xFF, 0x00},
 256 {VIAGR, GR22, 0xFF, 0x00},
 257
 258 };
 259
 260 /* Mode:1024X768 */
 261 struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
 262 {VIASR, 0x18, 0xFF, 0x4C}
 263 };
 264
 265 struct patch_table res_patch_table[] = {
 266         {ARRAY_SIZE(PM1024x768), PM1024x768}
 267 };
 268
 269 /* struct VPITTable {
 270         unsigned char  Misc;
 271         unsigned char  SR[StdSR];
 272         unsigned char  CR[StdCR];
 273         unsigned char  GR[StdGR];
 274         unsigned char  AR[StdAR];
 275  };*/
 276
 277 struct VPITTable VPIT = {
 278         /* Msic */
 279         0xC7,
 280         /* Sequencer */
 281         {0x01, 0x0F, 0x00, 0x0E},
 282         /* Graphic Controller */
 283         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF},
 284         /* Attribute Controller */
 285         {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 286          0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
 287          0x01, 0x00, 0x0F, 0x00}
 288 };
 289
 290 /********************/
 291 /* Mode Table       */
 292 /********************/
 293
 294 /* 480x640 */
 295 static struct crt_mode_table CRTM480x640[] = {
 296         /* r_rate,              hsp,             vsp   */
 297         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 298         {REFRESH_60, M480X640_R60_HSP, M480X640_R60_VSP,
 299          {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} }     /* GTF*/
 300 };
 301
 302 /* 640x480*/
 303 static struct crt_mode_table CRTM640x480[] = {
 304         /*r_rate,hsp,vsp */
 305         /*HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 306         {REFRESH_60, M640X480_R60_HSP, M640X480_R60_VSP,
 307          {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} },
 308         {REFRESH_75, M640X480_R75_HSP, M640X480_R75_VSP,
 309          {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} },
 310         {REFRESH_85, M640X480_R85_HSP, M640X480_R85_VSP,
 311          {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} },
 312         {REFRESH_100, M640X480_R100_HSP, M640X480_R100_VSP,
 313          {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/
 314         {REFRESH_120, M640X480_R120_HSP, M640X480_R120_VSP,
 315          {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481, 3} } /*GTF*/
 316 };
 317
 318 /*720x480 (GTF)*/
 319 static struct crt_mode_table CRTM720x480[] = {
 320         /*r_rate,hsp,vsp      */
 321         /*HT, HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 322         {REFRESH_60, M720X480_R60_HSP, M720X480_R60_VSP,
 323          {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} }
 324
 325 };
 326
 327 /*720x576 (GTF)*/
 328 static struct crt_mode_table CRTM720x576[] = {
 329         /*r_rate,hsp,vsp */
 330         /*HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 331         {REFRESH_60, M720X576_R60_HSP, M720X576_R60_VSP,
 332          {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} }
 333 };
 334
 335 /* 800x480 (CVT) */
 336 static struct crt_mode_table CRTM800x480[] = {
 337         /* r_rate,              hsp,             vsp   */
 338         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 339         {REFRESH_60, M800X480_R60_HSP, M800X480_R60_VSP,
 340          {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} }
 341 };
 342
 343 /* 800x600*/
 344 static struct crt_mode_table CRTM800x600[] = {
 345         /*r_rate,hsp,vsp     */
 346         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 347         {REFRESH_60, M800X600_R60_HSP, M800X600_R60_VSP,
 348          {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} },
 349         {REFRESH_75, M800X600_R75_HSP, M800X600_R75_VSP,
 350          {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} },
 351         {REFRESH_85, M800X600_R85_HSP, M800X600_R85_VSP,
 352          {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} },
 353         {REFRESH_100, M800X600_R100_HSP, M800X600_R100_VSP,
 354          {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} },
 355         {REFRESH_120, M800X600_R120_HSP, M800X600_R120_VSP,
 356          {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601, 3} }
 357 };
 358
 359 /* 848x480 (CVT) */
 360 static struct crt_mode_table CRTM848x480[] = {
 361         /* r_rate,              hsp,             vsp   */
 362         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 363         {REFRESH_60, M848X480_R60_HSP, M848X480_R60_VSP,
 364          {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} }
 365 };
 366
 367 /*856x480 (GTF) convert to 852x480*/
 368 static struct crt_mode_table CRTM852x480[] = {
 369         /*r_rate,hsp,vsp     */
 370         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 371         {REFRESH_60, M852X480_R60_HSP, M852X480_R60_VSP,
 372         {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
 373 };
 374
 375 /*1024x512 (GTF)*/
 376 static struct crt_mode_table CRTM1024x512[] = {
 377         /*r_rate,hsp,vsp     */
 378         /*HT,   HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 379         {REFRESH_60, M1024X512_R60_HSP, M1024X512_R60_VSP,
 380          {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
 381
 382 };
 383
 384 /* 1024x600*/
 385 static struct crt_mode_table CRTM1024x600[] = {
 386         /*r_rate,hsp,vsp */
 387         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 388         {REFRESH_60, M1024X600_R60_HSP, M1024X600_R60_VSP,
 389          {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
 390 };
 391
 392 /* 1024x768*/
 393 static struct crt_mode_table CRTM1024x768[] = {
 394         /*r_rate,hsp,vsp */
 395         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 396         {REFRESH_60, M1024X768_R60_HSP, M1024X768_R60_VSP,
 397         {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
 398         {REFRESH_75, M1024X768_R75_HSP, M1024X768_R75_VSP,
 399         {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
 400         {REFRESH_85, M1024X768_R85_HSP, M1024X768_R85_VSP,
 401         {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
 402         {REFRESH_100, M1024X768_R100_HSP, M1024X768_R100_VSP,
 403         {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
 404 };
 405
 406 /* 1152x864*/
 407 static struct crt_mode_table CRTM1152x864[] = {
 408         /*r_rate,hsp,vsp      */
 409         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 410         {REFRESH_75, M1152X864_R75_HSP, M1152X864_R75_VSP,
 411          {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
 412
 413 };
 414
 415 /* 1280x720 (HDMI 720P)*/
 416 static struct crt_mode_table CRTM1280x720[] = {
 417         /*r_rate,hsp,vsp */
 418         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE      */
 419         {REFRESH_60, M1280X720_R60_HSP, M1280X720_R60_VSP,
 420          {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
 421         {REFRESH_50, M1280X720_R50_HSP, M1280X720_R50_VSP,
 422          {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
 423 };
 424
 425 /*1280x768 (GTF)*/
 426 static struct crt_mode_table CRTM1280x768[] = {
 427         /*r_rate,hsp,vsp     */
 428         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 429         {REFRESH_60, M1280X768_R60_HSP, M1280X768_R60_VSP,
 430          {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
 431         {REFRESH_50, M1280X768_R50_HSP, M1280X768_R50_VSP,
 432          {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
 433 };
 434
 435 /* 1280x800 (CVT) */
 436 static struct crt_mode_table CRTM1280x800[] = {
 437         /* r_rate,              hsp,             vsp   */
 438         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 439         {REFRESH_60, M1280X800_R60_HSP, M1280X800_R60_VSP,
 440          {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
 441 };
 442
 443 /*1280x960*/
 444 static struct crt_mode_table CRTM1280x960[] = {
 445         /*r_rate,hsp,vsp */
 446         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 447         {REFRESH_60, M1280X960_R60_HSP, M1280X960_R60_VSP,
 448          {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
 449 };
 450
 451 /* 1280x1024*/
 452 static struct crt_mode_table CRTM1280x1024[] = {
 453         /*r_rate,hsp,vsp */
 454         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 455         {REFRESH_60, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
 456          {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
 457           3} },
 458         {REFRESH_75, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
 459          {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
 460           3} },
 461         {REFRESH_85, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
 462          {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
 463 };
 464
 465 /* 1368x768 (GTF) */
 466 static struct crt_mode_table CRTM1368x768[] = {
 467         /* r_rate,  hsp, vsp */
 468         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 469         {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
 470          {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
 471 };
 472
 473 /*1440x1050 (GTF)*/
 474 static struct crt_mode_table CRTM1440x1050[] = {
 475         /*r_rate,hsp,vsp      */
 476         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 477         {REFRESH_60, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
 478          {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
 479 };
 480
 481 /* 1600x1200*/
 482 static struct crt_mode_table CRTM1600x1200[] = {
 483         /*r_rate,hsp,vsp */
 484         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 485         {REFRESH_60, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
 486          {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
 487           3} },
 488         {REFRESH_75, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
 489          {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
 490
 491 };
 492
 493 /* 1680x1050 (CVT) */
 494 static struct crt_mode_table CRTM1680x1050[] = {
 495         /* r_rate,              hsp,             vsp  */
 496         /* HT,  HA,  HBS, HBE, HSS, HSE,    VT,  VA,  VBS, VBE,  VSS, VSE */
 497         {REFRESH_60, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
 498          {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
 499           6} },
 500         {REFRESH_75, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
 501          {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
 502 };
 503
 504 /* 1680x1050 (CVT Reduce Blanking) */
 505 static struct crt_mode_table CRTM1680x1050_RB[] = {
 506         /* r_rate,              hsp,             vsp   */
 507         /* HT,  HA,  HBS, HBE, HSS, HSE,    VT,  VA,  VBS, VBE,  VSS, VSE */
 508         {REFRESH_60, M1680x1050_RB_R60_HSP, M1680x1050_RB_R60_VSP,
 509          {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
 510 };
 511
 512 /* 1920x1080 (CVT)*/
 513 static struct crt_mode_table CRTM1920x1080[] = {
 514         /*r_rate,hsp,vsp */
 515         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 516         {REFRESH_60, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
 517          {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
 518 };
 519
 520 /* 1920x1080 (CVT with Reduce Blanking) */
 521 static struct crt_mode_table CRTM1920x1080_RB[] = {
 522         /* r_rate,              hsp,             vsp   */
 523         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 524         {REFRESH_60, M1920X1080_RB_R60_HSP, M1920X1080_RB_R60_VSP,
 525          {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
 526 };
 527
 528 /* 1920x1440*/
 529 static struct crt_mode_table CRTM1920x1440[] = {
 530         /*r_rate,hsp,vsp */
 531         /*HT,  HA,   HBS,  HBE, HSS,  HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 532         {REFRESH_60, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
 533          {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
 534           3} },
 535         {REFRESH_75, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
 536          {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
 537 };
 538
 539 /* 1400x1050 (CVT) */
 540 static struct crt_mode_table CRTM1400x1050[] = {
 541         /* r_rate,              hsp,             vsp   */
 542         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 543         {REFRESH_60, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
 544          {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
 545           4} },
 546         {REFRESH_75, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
 547          {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
 548 };
 549
 550 /* 1400x1050 (CVT Reduce Blanking) */
 551 static struct crt_mode_table CRTM1400x1050_RB[] = {
 552         /* r_rate,              hsp,             vsp   */
 553         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 554         {REFRESH_60, M1400X1050_RB_R60_HSP, M1400X1050_RB_R60_VSP,
 555          {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
 556 };
 557
 558 /* 960x600 (CVT) */
 559 static struct crt_mode_table CRTM960x600[] = {
 560         /* r_rate,          hsp,             vsp   */
 561         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 562         {REFRESH_60, M960X600_R60_HSP, M960X600_R60_VSP,
 563          {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
 564 };
 565
 566 /* 1000x600 (GTF) */
 567 static struct crt_mode_table CRTM1000x600[] = {
 568         /* r_rate,              hsp,             vsp   */
 569         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 570         {REFRESH_60, M1000X600_R60_HSP, M1000X600_R60_VSP,
 571          {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
 572 };
 573
 574 /* 1024x576 (GTF) */
 575 static struct crt_mode_table CRTM1024x576[] = {
 576         /* r_rate,              hsp,             vsp   */
 577         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 578         {REFRESH_60, M1024X576_R60_HSP, M1024X576_R60_VSP,
 579          {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
 580 };
 581
 582 /* 1088x612 (CVT) */
 583 static struct crt_mode_table CRTM1088x612[] = {
 584         /* r_rate,              hsp,             vsp   */
 585         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 586         {REFRESH_60, M1088X612_R60_HSP, M1088X612_R60_VSP,
 587          {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
 588 };
 589
 590 /* 1152x720 (CVT) */
 591 static struct crt_mode_table CRTM1152x720[] = {
 592         /* r_rate,              hsp,             vsp   */
 593         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 594         {REFRESH_60, M1152X720_R60_HSP, M1152X720_R60_VSP,
 595          {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
 596 };
 597
 598 /* 1200x720 (GTF) */
 599 static struct crt_mode_table CRTM1200x720[] = {
 600         /* r_rate,              hsp,             vsp   */
 601         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 602         {REFRESH_60, M1200X720_R60_HSP, M1200X720_R60_VSP,
 603          {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
 604 };
 605
 606 /* 1200x900 (DCON) */
 607 static struct crt_mode_table DCON1200x900[] = {
 608         /* r_rate,               hsp,               vsp   */
 609         {REFRESH_60, M1200X900_R60_HSP, M1200X900_R60_VSP,
 610         /* The correct htotal is 1240, but this doesn't raster on VX855. */
 611         /* Via suggested changing to a multiple of 16, hence 1264.       */
 612         /*  HT,   HA,  HBS, HBE,  HSS, HSE,  VT,  VA, VBS, VBE, VSS, VSE */
 613          {1264, 1200, 1200,  64, 1211,  32, 912, 900, 900,  12, 901, 10} }
 614 };
 615
 616 /* 1280x600 (GTF) */
 617 static struct crt_mode_table CRTM1280x600[] = {
 618         /* r_rate,              hsp,             vsp   */
 619         /* HT,  HA,  HBS, HBE,  HSS, HSE, VT,  VA,  VBS, VBE,  VSS, VSE */
 620         {REFRESH_60, M1280x600_R60_HSP, M1280x600_R60_VSP,
 621          {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
 622 };
 623
 624 /* 1360x768 (CVT) */
 625 static struct crt_mode_table CRTM1360x768[] = {
 626         /* r_rate,              hsp,             vsp   */
 627         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 628         {REFRESH_60, M1360X768_R60_HSP, M1360X768_R60_VSP,
 629          {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
 630 };
 631
 632 /* 1360x768 (CVT Reduce Blanking) */
 633 static struct crt_mode_table CRTM1360x768_RB[] = {
 634         /* r_rate,              hsp,             vsp   */
 635         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 636         {REFRESH_60, M1360X768_RB_R60_HSP, M1360X768_RB_R60_VSP,
 637          {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
 638 };
 639
 640 /* 1366x768 (GTF) */
 641 static struct crt_mode_table CRTM1366x768[] = {
 642         /* r_rate,          hsp,             vsp   */
 643         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 644         {REFRESH_60, M1368X768_R60_HSP, M1368X768_R60_VSP,
 645          {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
 646         {REFRESH_50, M1368X768_R50_HSP, M1368X768_R50_VSP,
 647          {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
 648 };
 649
 650 /* 1440x900 (CVT) */
 651 static struct crt_mode_table CRTM1440x900[] = {
 652         /* r_rate,              hsp,             vsp   */
 653         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 654         {REFRESH_60, M1440X900_R60_HSP, M1440X900_R60_VSP,
 655          {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
 656         {REFRESH_75, M1440X900_R75_HSP, M1440X900_R75_VSP,
 657          {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
 658 };
 659
 660 /* 1440x900 (CVT Reduce Blanking) */
 661 static struct crt_mode_table CRTM1440x900_RB[] = {
 662         /* r_rate,              hsp,             vsp   */
 663         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 664         {REFRESH_60, M1440X900_RB_R60_HSP, M1440X900_RB_R60_VSP,
 665          {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
 666 };
 667
 668 /* 1600x900 (CVT) */
 669 static struct crt_mode_table CRTM1600x900[] = {
 670         /* r_rate,          hsp,             vsp   */
 671         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 672         {REFRESH_60, M1600X900_R60_HSP, M1600X900_R60_VSP,
 673          {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
 674 };
 675
 676 /* 1600x900 (CVT Reduce Blanking) */
 677 static struct crt_mode_table CRTM1600x900_RB[] = {
 678         /* r_rate,           hsp,        vsp   */
 679         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 680         {REFRESH_60, M1600X900_RB_R60_HSP, M1600X900_RB_R60_VSP,
 681          {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
 682 };
 683
 684 /* 1600x1024 (GTF) */
 685 static struct crt_mode_table CRTM1600x1024[] = {
 686         /* r_rate,          hsp,             vsp   */
 687         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 688         {REFRESH_60, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
 689          {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
 690 };
 691
 692 /* 1792x1344 (DMT) */
 693 static struct crt_mode_table CRTM1792x1344[] = {
 694         /* r_rate,              hsp,             vsp   */
 695         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 696         {REFRESH_60, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
 697          {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
 698 };
 699
 700 /* 1856x1392 (DMT) */
 701 static struct crt_mode_table CRTM1856x1392[] = {
 702         /* r_rate,              hsp,             vsp   */
 703         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 704         {REFRESH_60, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
 705          {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
 706 };
 707
 708 /* 1920x1200 (CVT) */
 709 static struct crt_mode_table CRTM1920x1200[] = {
 710         /* r_rate,              hsp,             vsp   */
 711         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 712         {REFRESH_60, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
 713          {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
 714 };
 715
 716 /* 1920x1200 (CVT with Reduce Blanking) */
 717 static struct crt_mode_table CRTM1920x1200_RB[] = {
 718         /* r_rate,              hsp,             vsp   */
 719         /* HT,  HA,  HBS, HBE, HSS, HSE, VT,  VA,  VBS, VBE, VSS, VSE */
 720         {REFRESH_60, M1920X1200_RB_R60_HSP, M1920X1200_RB_R60_VSP,
 721          {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
 722 };
 723
 724 /* 2048x1536 (CVT) */
 725 static struct crt_mode_table CRTM2048x1536[] = {
 726         /* r_rate,              hsp,             vsp   */
 727         /* HT,  HA,  HBS, HBE,  HSS, HSE,   VT,  VA,  VBS, VBE,  VSS, VSE */
 728         {REFRESH_60, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
 729          {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
 730 };
 731
 732 static struct VideoModeTable viafb_modes[] = {
 733         /* Display : 480x640 (GTF) */
 734         {CRTM480x640, ARRAY_SIZE(CRTM480x640)},
 735
 736         /* Display : 640x480 */
 737         {CRTM640x480, ARRAY_SIZE(CRTM640x480)},
 738
 739         /* Display : 720x480 (GTF) */
 740         {CRTM720x480, ARRAY_SIZE(CRTM720x480)},
 741
 742         /* Display : 720x576 (GTF) */
 743         {CRTM720x576, ARRAY_SIZE(CRTM720x576)},
 744
 745         /* Display : 800x600 */
 746         {CRTM800x600, ARRAY_SIZE(CRTM800x600)},
 747
 748         /* Display : 800x480 (CVT) */
 749         {CRTM800x480, ARRAY_SIZE(CRTM800x480)},
 750
 751         /* Display : 848x480 (CVT) */
 752         {CRTM848x480, ARRAY_SIZE(CRTM848x480)},
 753
 754         /* Display : 852x480 (GTF) */
 755         {CRTM852x480, ARRAY_SIZE(CRTM852x480)},
 756
 757         /* Display : 1024x512 (GTF) */
 758         {CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
 759
 760         /* Display : 1024x600 */
 761         {CRTM1024x600, ARRAY_SIZE(CRTM1024x600)},
 762
 763         /* Display : 1024x768 */
 764         {CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
 765
 766         /* Display : 1152x864 */
 767         {CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
 768
 769         /* Display : 1280x768 (GTF) */
 770         {CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
 771
 772         /* Display : 960x600 (CVT) */
 773         {CRTM960x600, ARRAY_SIZE(CRTM960x600)},
 774
 775         /* Display : 1000x600 (GTF) */
 776         {CRTM1000x600, ARRAY_SIZE(CRTM1000x600)},
 777
 778         /* Display : 1024x576 (GTF) */
 779         {CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
 780
 781         /* Display : 1088x612 (GTF) */
 782         {CRTM1088x612, ARRAY_SIZE(CRTM1088x612)},
 783
 784         /* Display : 1152x720 (CVT) */
 785         {CRTM1152x720, ARRAY_SIZE(CRTM1152x720)},
 786
 787         /* Display : 1200x720 (GTF) */
 788         {CRTM1200x720, ARRAY_SIZE(CRTM1200x720)},
 789
 790         /* Display : 1200x900 (DCON) */
 791         {DCON1200x900, ARRAY_SIZE(DCON1200x900)},
 792
 793         /* Display : 1280x600 (GTF) */
 794         {CRTM1280x600, ARRAY_SIZE(CRTM1280x600)},
 795
 796         /* Display : 1280x800 (CVT) */
 797         {CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
 798
 799         /* Display : 1280x960 */
 800         {CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
 801
 802         /* Display : 1280x1024 */
 803         {CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)},
 804
 805         /* Display : 1360x768 (CVT) */
 806         {CRTM1360x768, ARRAY_SIZE(CRTM1360x768)},
 807
 808         /* Display : 1366x768 */
 809         {CRTM1366x768, ARRAY_SIZE(CRTM1366x768)},
 810
 811         /* Display : 1368x768 (GTF) */
 812         {CRTM1368x768, ARRAY_SIZE(CRTM1368x768)},
 813
 814         /* Display : 1440x900 (CVT) */
 815         {CRTM1440x900, ARRAY_SIZE(CRTM1440x900)},
 816
 817         /* Display : 1440x1050 (GTF) */
 818         {CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
 819
 820         /* Display : 1600x900 (CVT) */
 821         {CRTM1600x900, ARRAY_SIZE(CRTM1600x900)},
 822
 823         /* Display : 1600x1024 (GTF) */
 824         {CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)},
 825
 826         /* Display : 1600x1200 */
 827         {CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
 828
 829         /* Display : 1680x1050 (CVT) */
 830         {CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)},
 831
 832         /* Display : 1792x1344 (DMT) */
 833         {CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)},
 834
 835         /* Display : 1856x1392 (DMT) */
 836         {CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)},
 837
 838         /* Display : 1920x1440 */
 839         {CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
 840
 841         /* Display : 2048x1536 */
 842         {CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)},
 843
 844         /* Display : 1280x720 */
 845         {CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
 846
 847         /* Display : 1920x1080 (CVT) */
 848         {CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
 849
 850         /* Display : 1920x1200 (CVT) */
 851         {CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)},
 852
 853         /* Display : 1400x1050 (CVT) */
 854         {CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
 855 };
 856
 857 static struct VideoModeTable viafb_rb_modes[] = {
 858         /* Display : 1360x768 (CVT Reduce Blanking) */
 859         {CRTM1360x768_RB, ARRAY_SIZE(CRTM1360x768_RB)},
 860
 861         /* Display : 1440x900 (CVT Reduce Blanking) */
 862         {CRTM1440x900_RB, ARRAY_SIZE(CRTM1440x900_RB)},
 863
 864         /* Display : 1400x1050 (CVT Reduce Blanking) */
 865         {CRTM1400x1050_RB, ARRAY_SIZE(CRTM1400x1050_RB)},
 866
 867         /* Display : 1600x900 (CVT Reduce Blanking) */
 868         {CRTM1600x900_RB, ARRAY_SIZE(CRTM1600x900_RB)},
 869
 870         /* Display : 1680x1050 (CVT Reduce Blanking) */
 871         {CRTM1680x1050_RB, ARRAY_SIZE(CRTM1680x1050_RB)},
 872
 873         /* Display : 1920x1080 (CVT Reduce Blanking) */
 874         {CRTM1920x1080_RB, ARRAY_SIZE(CRTM1920x1080_RB)},
 875
 876         /* Display : 1920x1200 (CVT Reduce Blanking) */
 877         {CRTM1920x1200_RB, ARRAY_SIZE(CRTM1920x1200_RB)}
 878 };
 879
 880 struct crt_mode_table CEAM1280x720[] = {
 881         {REFRESH_60, M1280X720_CEA_R60_HSP, M1280X720_CEA_R60_VSP,
 882          /* HT,    HA,   HBS,  HBE,  HSS, HSE,  VT,   VA,  VBS, VBE, VSS, VSE */
 883          {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} }
 884 };
 885 struct crt_mode_table CEAM1920x1080[] = {
 886         {REFRESH_60, M1920X1080_CEA_R60_HSP, M1920X1080_CEA_R60_VSP,
 887          /* HT,    HA,   HBS,  HBE,  HSS, HSE,  VT,  VA, VBS, VBE,  VSS, VSE */
 888          {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} }
 889 };
 890 struct VideoModeTable CEA_HDMI_Modes[] = {
 891         /* Display : 1280x720 */
 892         {CEAM1280x720, ARRAY_SIZE(CEAM1280x720)},
 893         {CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)}
 894 };
 895
 896 int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes);
 897 int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
 898 int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
 899 int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs);
 900 int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs);
 901 int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs);
 902 int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
 903 int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
 904
 905
 906 struct VideoModeTable *viafb_get_mode(int hres, int vres)
 907 {
 908         u32 i;
 909         for (i = 0; i < ARRAY_SIZE(viafb_modes); i++)
 910                 if (viafb_modes[i].mode_array &&
 911                         viafb_modes[i].crtc[0].crtc.hor_addr == hres &&
 912                         viafb_modes[i].crtc[0].crtc.ver_addr == vres)
 913                         return &viafb_modes[i];
 914
 915         return NULL;
 916 }
 917
 918 struct VideoModeTable *viafb_get_rb_mode(int hres, int vres)
 919 {
 920         u32 i;
 921         for (i = 0; i < ARRAY_SIZE(viafb_rb_modes); i++)
 922                 if (viafb_rb_modes[i].mode_array &&
 923                         viafb_rb_modes[i].crtc[0].crtc.hor_addr == hres &&
 924                         viafb_rb_modes[i].crtc[0].crtc.ver_addr == vres)
 925                         return &viafb_rb_modes[i];
 926
 927         return NULL;
 928 }