2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2007 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
9 #include <linux/init.h>
10 #include <linux/console.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
14 #include <linux/serial.h>
15 #include <linux/smp.h>
16 #include <linux/types.h>
17 #include <linux/string.h> /* for memset */
18 #include <linux/tty.h>
19 #include <linux/time.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial_8250.h>
24 #include <asm/processor.h>
25 #include <asm/reboot.h>
26 #include <asm/smp-ops.h>
27 #include <asm/system.h>
28 #include <asm/irq_cpu.h>
29 #include <asm/mipsregs.h>
30 #include <asm/bootinfo.h>
31 #include <asm/sections.h>
34 #include <asm/octeon/octeon.h>
36 #ifdef CONFIG_CAVIUM_DECODE_RSL
37 extern void cvmx_interrupt_rsl_decode(void);
38 extern int __cvmx_interrupt_ecc_report_single_bit_errors
;
39 extern void cvmx_interrupt_rsl_enable(void);
42 extern struct plat_smp_ops octeon_smp_ops
;
45 extern void pci_console_init(const char *arg
);
48 #ifdef CONFIG_CAVIUM_RESERVE32
49 extern uint64_t octeon_reserve32_memory
;
51 static unsigned long long MAX_MEMORY
= 512ull << 20;
53 struct octeon_boot_descriptor
*octeon_boot_desc_ptr
;
55 struct cvmx_bootinfo
*octeon_bootinfo
;
56 EXPORT_SYMBOL(octeon_bootinfo
);
58 #ifdef CONFIG_CAVIUM_RESERVE32
59 uint64_t octeon_reserve32_memory
;
60 EXPORT_SYMBOL(octeon_reserve32_memory
);
63 static int octeon_uart
;
65 extern asmlinkage
void handle_int(void);
66 extern asmlinkage
void plat_irq_dispatch(void);
69 * Return non zero if we are currently running in the Octeon simulator
73 int octeon_is_simulation(void)
75 return octeon_bootinfo
->board_type
== CVMX_BOARD_TYPE_SIM
;
77 EXPORT_SYMBOL(octeon_is_simulation
);
80 * Return true if Octeon is in PCI Host mode. This means
81 * Linux can control the PCI bus.
83 * Returns Non zero if Octeon in host mode.
85 int octeon_is_pci_host(void)
88 return octeon_bootinfo
->config_flags
& CVMX_BOOTINFO_CFG_FLAG_PCI_HOST
;
95 * Get the clock rate of Octeon
97 * Returns Clock rate in HZ
99 uint64_t octeon_get_clock_rate(void)
101 if (octeon_is_simulation())
102 octeon_bootinfo
->eclock_hz
= 6000000;
103 return octeon_bootinfo
->eclock_hz
;
105 EXPORT_SYMBOL(octeon_get_clock_rate
);
108 * Write to the LCD display connected to the bootbus. This display
109 * exists on most Cavium evaluation boards. If it doesn't exist, then
110 * this function doesn't do anything.
112 * @s: String to write
114 void octeon_write_lcd(const char *s
)
116 if (octeon_bootinfo
->led_display_base_addr
) {
117 void __iomem
*lcd_address
=
118 ioremap_nocache(octeon_bootinfo
->led_display_base_addr
,
121 for (i
= 0; i
< 8; i
++, s
++) {
123 iowrite8(*s
, lcd_address
+ i
);
125 iowrite8(' ', lcd_address
+ i
);
127 iounmap(lcd_address
);
132 * Return the console uart passed by the bootloader
134 * Returns uart (0 or 1)
136 int octeon_get_boot_uart(void)
139 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
142 uart
= (octeon_boot_desc_ptr
->flags
& OCTEON_BL_FLAG_CONSOLE_UART1
) ?
149 * Get the coremask Linux was booted on.
153 int octeon_get_boot_coremask(void)
155 return octeon_boot_desc_ptr
->core_mask
;
159 * Check the hardware BIST results for a CPU
161 void octeon_check_cpu_bist(void)
163 const int coreid
= cvmx_get_core_num();
164 unsigned long long mask
;
165 unsigned long long bist_val
;
167 /* Check BIST results for COP0 registers */
168 mask
= 0x1f00000000ull
;
169 bist_val
= read_octeon_c0_icacheerr();
171 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
174 bist_val
= read_octeon_c0_dcacheerr();
176 pr_err("Core%d L1 Dcache parity error: "
177 "CacheErr(dcache) = 0x%llx\n",
180 mask
= 0xfc00000000000000ull
;
181 bist_val
= read_c0_cvmmemctl();
183 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
186 write_octeon_c0_dcacheerr(0);
192 * @command: Command to pass to the bootloader. Currently ignored.
194 static void octeon_restart(char *command
)
196 /* Disable all watchdogs before soft reset. They don't get cleared */
199 for_each_online_cpu(cpu
)
200 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu
)), 0);
202 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
207 cvmx_write_csr(CVMX_CIU_SOFT_RST
, 1);
212 * Permanently stop a core.
216 static void octeon_kill_core(void *arg
)
219 if (octeon_is_simulation()) {
220 /* The simulator needs the watchdog to stop for dead cores */
221 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
222 /* A break instruction causes the simulator stop a core */
223 asm volatile ("sync\nbreak");
231 static void octeon_halt(void)
233 smp_call_function(octeon_kill_core
, NULL
, 0);
235 switch (octeon_bootinfo
->board_type
) {
236 case CVMX_BOARD_TYPE_NAO38
:
237 /* Driving a 1 to GPIO 12 shuts off this board */
238 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
239 cvmx_write_csr(CVMX_GPIO_TX_SET
, 0x1000);
242 octeon_write_lcd("PowerOff");
246 octeon_kill_core(NULL
);
251 * Platform time init specifics.
254 void __init
plat_time_init(void)
256 /* Nothing special here, but we are required to have one */
262 * Handle all the error condition interrupts that might occur.
265 #ifdef CONFIG_CAVIUM_DECODE_RSL
266 static irqreturn_t
octeon_rlm_interrupt(int cpl
, void *dev_id
)
268 cvmx_interrupt_rsl_decode();
274 * Return a string representing the system type
278 const char *octeon_board_type_string(void)
280 static char name
[80];
281 sprintf(name
, "%s (%s)",
282 cvmx_board_type_to_string(octeon_bootinfo
->board_type
),
283 octeon_model_get_string(read_c0_prid()));
287 const char *get_system_type(void)
288 __attribute__ ((alias("octeon_board_type_string")));
290 void octeon_user_io_init(void)
292 union octeon_cvmemctl cvmmemctl
;
293 union cvmx_iob_fau_timeout fau_timeout
;
294 union cvmx_pow_nw_tim nm_tim
;
297 /* Get the current settings for CP0_CVMMEMCTL_REG */
298 cvmmemctl
.u64
= read_c0_cvmmemctl();
299 /* R/W If set, marked write-buffer entries time out the same
300 * as as other entries; if clear, marked write-buffer entries
301 * use the maximum timeout. */
302 cvmmemctl
.s
.dismarkwblongto
= 1;
303 /* R/W If set, a merged store does not clear the write-buffer
304 * entry timeout state. */
305 cvmmemctl
.s
.dismrgclrwbto
= 0;
306 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
307 * word location for an IOBDMA. The other 8 bits come from the
308 * SCRADDR field of the IOBDMA. */
309 cvmmemctl
.s
.iobdmascrmsb
= 0;
310 /* R/W If set, SYNCWS and SYNCS only order marked stores; if
311 * clear, SYNCWS and SYNCS only order unmarked
312 * stores. SYNCWSMARKED has no effect when DISSYNCWS is
314 cvmmemctl
.s
.syncwsmarked
= 0;
315 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
316 cvmmemctl
.s
.dissyncws
= 0;
317 /* R/W If set, no stall happens on write buffer full. */
318 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2
))
319 cvmmemctl
.s
.diswbfst
= 1;
321 cvmmemctl
.s
.diswbfst
= 0;
322 /* R/W If set (and SX set), supervisor-level loads/stores can
323 * use XKPHYS addresses with <48>==0 */
324 cvmmemctl
.s
.xkmemenas
= 0;
326 /* R/W If set (and UX set), user-level loads/stores can use
327 * XKPHYS addresses with VA<48>==0 */
328 cvmmemctl
.s
.xkmemenau
= 0;
330 /* R/W If set (and SX set), supervisor-level loads/stores can
331 * use XKPHYS addresses with VA<48>==1 */
332 cvmmemctl
.s
.xkioenas
= 0;
334 /* R/W If set (and UX set), user-level loads/stores can use
335 * XKPHYS addresses with VA<48>==1 */
336 cvmmemctl
.s
.xkioenau
= 0;
338 /* R/W If set, all stores act as SYNCW (NOMERGE must be set
339 * when this is set) RW, reset to 0. */
340 cvmmemctl
.s
.allsyncw
= 0;
342 /* R/W If set, no stores merge, and all stores reach the
343 * coherent bus in order. */
344 cvmmemctl
.s
.nomerge
= 0;
345 /* R/W Selects the bit in the counter used for DID time-outs 0
346 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
347 * between 1x and 2x this interval. For example, with
348 * DIDTTO=3, expiration interval is between 16K and 32K. */
349 cvmmemctl
.s
.didtto
= 0;
350 /* R/W If set, the (mem) CSR clock never turns off. */
351 cvmmemctl
.s
.csrckalwys
= 0;
352 /* R/W If set, mclk never turns off. */
353 cvmmemctl
.s
.mclkalwys
= 0;
354 /* R/W Selects the bit in the counter used for write buffer
355 * flush time-outs (WBFLT+11) is the bit position in an
356 * internal counter used to determine expiration. The write
357 * buffer expires between 1x and 2x this interval. For
358 * example, with WBFLT = 0, a write buffer expires between 2K
359 * and 4K cycles after the write buffer entry is allocated. */
360 cvmmemctl
.s
.wbfltime
= 0;
361 /* R/W If set, do not put Istream in the L2 cache. */
362 cvmmemctl
.s
.istrnol2
= 0;
363 /* R/W The write buffer threshold. */
364 cvmmemctl
.s
.wbthresh
= 10;
365 /* R/W If set, CVMSEG is available for loads/stores in
366 * kernel/debug mode. */
367 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
368 cvmmemctl
.s
.cvmsegenak
= 1;
370 cvmmemctl
.s
.cvmsegenak
= 0;
372 /* R/W If set, CVMSEG is available for loads/stores in
373 * supervisor mode. */
374 cvmmemctl
.s
.cvmsegenas
= 0;
375 /* R/W If set, CVMSEG is available for loads/stores in user
377 cvmmemctl
.s
.cvmsegenau
= 0;
378 /* R/W Size of local memory in cache blocks, 54 (6912 bytes)
379 * is max legal value. */
380 cvmmemctl
.s
.lmemsz
= CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
;
383 if (smp_processor_id() == 0)
384 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
385 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
,
386 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
* 128);
388 write_c0_cvmmemctl(cvmmemctl
.u64
);
390 /* Move the performance counter interrupts to IRQ 6 */
391 cvmctl
= read_c0_cvmctl();
394 write_c0_cvmctl(cvmctl
);
396 /* Set a default for the hardware timeouts */
398 fau_timeout
.s
.tout_val
= 0xfff;
399 /* Disable tagwait FAU timeout */
400 fau_timeout
.s
.tout_enb
= 0;
401 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT
, fau_timeout
.u64
);
406 cvmx_write_csr(CVMX_POW_NW_TIM
, nm_tim
.u64
);
408 write_octeon_c0_icacheerr(0);
409 write_c0_derraddr1(0);
413 * Early entry point for arch setup
415 void __init
prom_init(void)
417 struct cvmx_sysinfo
*sysinfo
;
418 const int coreid
= cvmx_get_core_num();
421 struct uart_port octeon_port
;
422 #ifdef CONFIG_CAVIUM_RESERVE32
426 * The bootloader passes a pointer to the boot descriptor in
427 * $a3, this is available as fw_arg3.
429 octeon_boot_desc_ptr
= (struct octeon_boot_descriptor
*)fw_arg3
;
431 cvmx_phys_to_ptr(octeon_boot_desc_ptr
->cvmx_desc_vaddr
);
432 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo
->phy_mem_desc_addr
));
435 * Only enable the LED controller if we're running on a CN38XX, CN58XX,
436 * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
438 if (!octeon_is_simulation() &&
439 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER
)) {
440 cvmx_write_csr(CVMX_LED_EN
, 0);
441 cvmx_write_csr(CVMX_LED_PRT
, 0);
442 cvmx_write_csr(CVMX_LED_DBG
, 0);
443 cvmx_write_csr(CVMX_LED_PRT_FMT
, 0);
444 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
445 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
446 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
447 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
448 cvmx_write_csr(CVMX_LED_EN
, 1);
450 #ifdef CONFIG_CAVIUM_RESERVE32
452 * We need to temporarily allocate all memory in the reserve32
453 * region. This makes sure the kernel doesn't allocate this
454 * memory when it is getting memory from the
455 * bootloader. Later, after the memory allocations are
456 * complete, the reserve32 will be freed.
458 * Allocate memory for RESERVED32 aligned on 2MB boundary. This
459 * is in case we later use hugetlb entries with it.
461 addr
= cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32
<< 20,
463 "CAVIUM_RESERVE32", 0);
465 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
467 octeon_reserve32_memory
= addr
;
470 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
471 if (cvmx_read_csr(CVMX_L2D_FUS3
) & (3ull << 34)) {
472 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
474 uint32_t ebase
= read_c0_ebase() & 0x3ffff000;
475 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
477 cvmx_l2c_lock_mem_region(ebase
, 0x100);
479 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
480 /* General exception */
481 cvmx_l2c_lock_mem_region(ebase
+ 0x180, 0x80);
483 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
484 /* Interrupt handler */
485 cvmx_l2c_lock_mem_region(ebase
+ 0x200, 0x80);
487 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
488 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int
), 0x100);
489 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch
), 0x80);
491 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
492 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy
), 0x480);
497 sysinfo
= cvmx_sysinfo_get();
498 memset(sysinfo
, 0, sizeof(*sysinfo
));
499 sysinfo
->system_dram_size
= octeon_bootinfo
->dram_size
<< 20;
500 sysinfo
->phy_mem_desc_ptr
=
501 cvmx_phys_to_ptr(octeon_bootinfo
->phy_mem_desc_addr
);
502 sysinfo
->core_mask
= octeon_bootinfo
->core_mask
;
503 sysinfo
->exception_base_addr
= octeon_bootinfo
->exception_base_addr
;
504 sysinfo
->cpu_clock_hz
= octeon_bootinfo
->eclock_hz
;
505 sysinfo
->dram_data_rate_hz
= octeon_bootinfo
->dclock_hz
* 2;
506 sysinfo
->board_type
= octeon_bootinfo
->board_type
;
507 sysinfo
->board_rev_major
= octeon_bootinfo
->board_rev_major
;
508 sysinfo
->board_rev_minor
= octeon_bootinfo
->board_rev_minor
;
509 memcpy(sysinfo
->mac_addr_base
, octeon_bootinfo
->mac_addr_base
,
510 sizeof(sysinfo
->mac_addr_base
));
511 sysinfo
->mac_addr_count
= octeon_bootinfo
->mac_addr_count
;
512 memcpy(sysinfo
->board_serial_number
,
513 octeon_bootinfo
->board_serial_number
,
514 sizeof(sysinfo
->board_serial_number
));
515 sysinfo
->compact_flash_common_base_addr
=
516 octeon_bootinfo
->compact_flash_common_base_addr
;
517 sysinfo
->compact_flash_attribute_base_addr
=
518 octeon_bootinfo
->compact_flash_attribute_base_addr
;
519 sysinfo
->led_display_base_addr
= octeon_bootinfo
->led_display_base_addr
;
520 sysinfo
->dfa_ref_clock_hz
= octeon_bootinfo
->dfa_ref_clock_hz
;
521 sysinfo
->bootloader_config_flags
= octeon_bootinfo
->config_flags
;
524 octeon_check_cpu_bist();
526 octeon_uart
= octeon_get_boot_uart();
529 * Disable All CIU Interrupts. The ones we need will be
530 * enabled later. Read the SUM register so we know the write
533 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid
* 2)), 0);
534 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid
* 2 + 1)), 0);
535 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid
* 2)), 0);
536 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid
* 2 + 1)), 0);
537 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid
* 2)));
540 octeon_write_lcd("LinuxSMP");
542 octeon_write_lcd("Linux");
545 #ifdef CONFIG_CAVIUM_GDB
547 * When debugging the linux kernel, force the cores to enter
548 * the debug exception handler to break in.
550 if (octeon_get_boot_debug_flag()) {
551 cvmx_write_csr(CVMX_CIU_DINT
, 1 << cvmx_get_core_num());
552 cvmx_read_csr(CVMX_CIU_DINT
);
557 * BIST should always be enabled when doing a soft reset. L2
558 * Cache locking for instance is not cleared unless BIST is
559 * enabled. Unfortunately due to a chip errata G-200 for
560 * Cn38XX and CN31XX, BIST msut be disabled on these parts.
562 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2
) ||
563 OCTEON_IS_MODEL(OCTEON_CN31XX
))
564 cvmx_write_csr(CVMX_CIU_SOFT_BIST
, 0);
566 cvmx_write_csr(CVMX_CIU_SOFT_BIST
, 1);
568 /* Default to 64MB in the simulator to speed things up */
569 if (octeon_is_simulation())
570 MAX_MEMORY
= 64ull << 20;
573 argc
= octeon_boot_desc_ptr
->argc
;
574 for (i
= 0; i
< argc
; i
++) {
576 cvmx_phys_to_ptr(octeon_boot_desc_ptr
->argv
[i
]);
577 if ((strncmp(arg
, "MEM=", 4) == 0) ||
578 (strncmp(arg
, "mem=", 4) == 0)) {
579 sscanf(arg
+ 4, "%llu", &MAX_MEMORY
);
582 MAX_MEMORY
= 32ull << 30;
583 } else if (strcmp(arg
, "ecc_verbose") == 0) {
584 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
585 __cvmx_interrupt_ecc_report_single_bit_errors
= 1;
586 pr_notice("Reporting of single bit ECC errors is "
589 } else if (strlen(arcs_cmdline
) + strlen(arg
) + 1 <
590 sizeof(arcs_cmdline
) - 1) {
591 strcat(arcs_cmdline
, " ");
592 strcat(arcs_cmdline
, arg
);
596 if (strstr(arcs_cmdline
, "console=") == NULL
) {
597 #ifdef CONFIG_GDB_CONSOLE
598 strcat(arcs_cmdline
, " console=gdb");
600 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
601 strcat(arcs_cmdline
, " console=ttyS0,115200");
603 if (octeon_uart
== 1)
604 strcat(arcs_cmdline
, " console=ttyS1,115200");
606 strcat(arcs_cmdline
, " console=ttyS0,115200");
611 if (octeon_is_simulation()) {
613 * The simulator uses a mtdram device pre filled with
614 * the filesystem. Also specify the calibration delay
615 * to avoid calculating it every time.
617 strcat(arcs_cmdline
, " rw root=1f00"
618 " lpj=60176 slram=root,0x40000000,+1073741824");
621 mips_hpt_frequency
= octeon_get_clock_rate();
623 octeon_init_cvmcount();
625 _machine_restart
= octeon_restart
;
626 _machine_halt
= octeon_halt
;
628 memset(&octeon_port
, 0, sizeof(octeon_port
));
630 * For early_serial_setup we don't set the port type or
633 octeon_port
.flags
= ASYNC_SKIP_TEST
| UPF_SHARE_IRQ
;
634 octeon_port
.iotype
= UPIO_MEM
;
635 /* I/O addresses are every 8 bytes */
636 octeon_port
.regshift
= 3;
637 /* Clock rate of the chip */
638 octeon_port
.uartclk
= mips_hpt_frequency
;
639 octeon_port
.fifosize
= 64;
640 octeon_port
.mapbase
= 0x0001180000000800ull
+ (1024 * octeon_uart
);
641 octeon_port
.membase
= cvmx_phys_to_ptr(octeon_port
.mapbase
);
642 octeon_port
.serial_in
= octeon_serial_in
;
643 octeon_port
.serial_out
= octeon_serial_out
;
644 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
645 octeon_port
.line
= 0;
647 octeon_port
.line
= octeon_uart
;
649 octeon_port
.irq
= 42 + octeon_uart
;
650 early_serial_setup(&octeon_port
);
652 octeon_user_io_init();
653 register_smp_ops(&octeon_smp_ops
);
656 void __init
plat_mem_setup(void)
658 uint64_t mem_alloc_size
;
664 /* First add the init memory we will be returning. */
665 memory
= __pa_symbol(&__init_begin
) & PAGE_MASK
;
666 mem_alloc_size
= (__pa_symbol(&__init_end
) & PAGE_MASK
) - memory
;
667 if (mem_alloc_size
> 0) {
668 add_memory_region(memory
, mem_alloc_size
, BOOT_MEM_RAM
);
669 total
+= mem_alloc_size
;
673 * The Mips memory init uses the first memory location for
674 * some memory vectors. When SPARSEMEM is in use, it doesn't
675 * verify that the size is big enough for the final
676 * vectors. Making the smallest chuck 4MB seems to be enough
677 * to consistantly work.
679 mem_alloc_size
= 4 << 20;
680 if (mem_alloc_size
> MAX_MEMORY
)
681 mem_alloc_size
= MAX_MEMORY
;
684 * When allocating memory, we want incrementing addresses from
685 * bootmem_alloc so the code in add_memory_region can merge
686 * regions next to each other.
689 while ((boot_mem_map
.nr_map
< BOOT_MEM_MAP_MAX
)
690 && (total
< MAX_MEMORY
)) {
691 #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR)
692 memory
= cvmx_bootmem_phy_alloc(mem_alloc_size
,
693 __pa_symbol(&__init_end
), -1,
695 CVMX_BOOTMEM_FLAG_NO_LOCKING
);
696 #elif defined(CONFIG_HIGHMEM)
697 memory
= cvmx_bootmem_phy_alloc(mem_alloc_size
, 0, 1ull << 31,
699 CVMX_BOOTMEM_FLAG_NO_LOCKING
);
701 memory
= cvmx_bootmem_phy_alloc(mem_alloc_size
, 0, 512 << 20,
703 CVMX_BOOTMEM_FLAG_NO_LOCKING
);
707 * This function automatically merges address
708 * regions next to each other if they are
709 * received in incrementing order.
711 add_memory_region(memory
, mem_alloc_size
, BOOT_MEM_RAM
);
712 total
+= mem_alloc_size
;
717 cvmx_bootmem_unlock();
719 #ifdef CONFIG_CAVIUM_RESERVE32
721 * Now that we've allocated the kernel memory it is safe to
722 * free the reserved region. We free it here so that builtin
723 * drivers can use the memory.
725 if (octeon_reserve32_memory
)
726 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
727 #endif /* CONFIG_CAVIUM_RESERVE32 */
730 panic("Unable to allocate memory from "
731 "cvmx_bootmem_phy_alloc\n");
735 int prom_putchar(char c
)
739 /* Spin until there is room */
741 lsrval
= cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart
));
742 } while ((lsrval
& 0x20) == 0);
745 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart
), c
);
749 void prom_free_prom_memory(void)
751 #ifdef CONFIG_CAVIUM_DECODE_RSL
752 cvmx_interrupt_rsl_enable();
754 /* Add an interrupt handler for general failures. */
755 if (request_irq(OCTEON_IRQ_RML
, octeon_rlm_interrupt
, IRQF_SHARED
,
756 "RML/RSL", octeon_rlm_interrupt
)) {
757 panic("Unable to request_irq(OCTEON_IRQ_RML)\n");