arch/arm/plat-omap/include/plat/usb.h

   1 // include/asm-arm/mach-omap/usb.h
   2
   3 #ifndef __ASM_ARCH_OMAP_USB_H
   4 #define __ASM_ARCH_OMAP_USB_H
   5
   6 #include <linux/usb/musb.h>
   7 #include <plat/board.h>
   8
   9 #define OMAP3_HS_USB_PORTS      3
  10 enum ehci_hcd_omap_mode {
  11         EHCI_HCD_OMAP_MODE_UNKNOWN,
  12         EHCI_HCD_OMAP_MODE_PHY,
  13         EHCI_HCD_OMAP_MODE_TLL,
  14         EHCI_HCD_OMAP_MODE_HSIC,
  15 };
  16
  17 enum ohci_omap3_port_mode {
  18         OMAP_OHCI_PORT_MODE_UNUSED,
  19         OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
  20         OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
  21         OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
  22         OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
  23         OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
  24         OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
  25         OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
  26         OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
  27         OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
  28         OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM,
  29 };
  30
  31 struct ehci_hcd_omap_platform_data {
  32         enum ehci_hcd_omap_mode         port_mode[OMAP3_HS_USB_PORTS];
  33         unsigned                        phy_reset:1;
  34
  35         /* have to be valid if phy_reset is true and portx is in phy mode */
  36         int     reset_gpio_port[OMAP3_HS_USB_PORTS];
  37 };
  38
  39 struct ohci_hcd_omap_platform_data {
  40         enum ohci_omap3_port_mode       port_mode[OMAP3_HS_USB_PORTS];
  41
  42         /* Set this to true for ES2.x silicon */
  43         unsigned                        es2_compatibility:1;
  44 };
  45
  46 /*-------------------------------------------------------------------------*/
  47
  48 #define OMAP1_OTG_BASE                  0xfffb0400
  49 #define OMAP1_UDC_BASE                  0xfffb4000
  50 #define OMAP1_OHCI_BASE                 0xfffba000
  51
  52 #define OMAP2_OHCI_BASE                 0x4805e000
  53 #define OMAP2_UDC_BASE                  0x4805e200
  54 #define OMAP2_OTG_BASE                  0x4805e300
  55
  56 #ifdef CONFIG_ARCH_OMAP1
  57
  58 #define OTG_BASE                        OMAP1_OTG_BASE
  59 #define UDC_BASE                        OMAP1_UDC_BASE
  60 #define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
  61
  62 #else
  63
  64 #define OTG_BASE                        OMAP2_OTG_BASE
  65 #define UDC_BASE                        OMAP2_UDC_BASE
  66 #define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
  67
  68 struct omap_musb_board_data {
  69         u8      interface_type;
  70         u8      mode;
  71         u16     power;
  72         unsigned extvbus:1;
  73 };
  74
  75 enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
  76
  77 extern void usb_musb_init(struct omap_musb_board_data *board_data);
  78
  79 extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata);
  80
  81 extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
  82
  83 #endif
  84
  85
  86 /*
  87  * FIXME correct answer depends on hmc_mode,
  88  * as does (on omap1) any nonzero value for config->otg port number
  89  */
  90 #ifdef  CONFIG_USB_GADGET_OMAP
  91 #define is_usb0_device(config)  1
  92 #else
  93 #define is_usb0_device(config)  0
  94 #endif
  95
  96 void omap_otg_init(struct omap_usb_config *config);
  97
  98 #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
  99 void omap1_usb_init(struct omap_usb_config *pdata);
 100 #else
 101 static inline void omap1_usb_init(struct omap_usb_config *pdata)
 102 {
 103 }
 104 #endif
 105
 106 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
 107 void omap2_usbfs_init(struct omap_usb_config *pdata);
 108 #else
 109 static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
 110 {
 111 }
 112 #endif
 113
 114 /*-------------------------------------------------------------------------*/
 115
 116 /*
 117  * OTG and transceiver registers, for OMAPs starting with ARM926
 118  */
 119 #define OTG_REV                         (OTG_BASE + 0x00)
 120 #define OTG_SYSCON_1                    (OTG_BASE + 0x04)
 121 #       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
 122 #       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
 123 #       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
 124 #       define   OTG_IDLE_EN            (1 << 15)
 125 #       define   HST_IDLE_EN            (1 << 14)
 126 #       define   DEV_IDLE_EN            (1 << 13)
 127 #       define   OTG_RESET_DONE         (1 << 2)
 128 #       define   OTG_SOFT_RESET         (1 << 1)
 129 #define OTG_SYSCON_2                    (OTG_BASE + 0x08)
 130 #       define   OTG_EN                 (1 << 31)
 131 #       define   USBX_SYNCHRO           (1 << 30)
 132 #       define   OTG_MST16              (1 << 29)
 133 #       define   SRP_GPDATA             (1 << 28)
 134 #       define   SRP_GPDVBUS            (1 << 27)
 135 #       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
 136 #       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
 137 #       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
 138 #       define   SRP_DPW                (1 << 14)
 139 #       define   SRP_DATA               (1 << 13)
 140 #       define   SRP_VBUS               (1 << 12)
 141 #       define   OTG_PADEN              (1 << 10)
 142 #       define   HMC_PADEN              (1 << 9)
 143 #       define   UHOST_EN               (1 << 8)
 144 #       define   HMC_TLLSPEED           (1 << 7)
 145 #       define   HMC_TLLATTACH          (1 << 6)
 146 #       define   OTG_HMC(w)             (((w)>>0)&0x3f)
 147 #define OTG_CTRL                        (OTG_BASE + 0x0c)
 148 #       define   OTG_USB2_EN            (1 << 29)
 149 #       define   OTG_USB2_DP            (1 << 28)
 150 #       define   OTG_USB2_DM            (1 << 27)
 151 #       define   OTG_USB1_EN            (1 << 26)
 152 #       define   OTG_USB1_DP            (1 << 25)
 153 #       define   OTG_USB1_DM            (1 << 24)
 154 #       define   OTG_USB0_EN            (1 << 23)
 155 #       define   OTG_USB0_DP            (1 << 22)
 156 #       define   OTG_USB0_DM            (1 << 21)
 157 #       define   OTG_ASESSVLD           (1 << 20)
 158 #       define   OTG_BSESSEND           (1 << 19)
 159 #       define   OTG_BSESSVLD           (1 << 18)
 160 #       define   OTG_VBUSVLD            (1 << 17)
 161 #       define   OTG_ID                 (1 << 16)
 162 #       define   OTG_DRIVER_SEL         (1 << 15)
 163 #       define   OTG_A_SETB_HNPEN       (1 << 12)
 164 #       define   OTG_A_BUSREQ           (1 << 11)
 165 #       define   OTG_B_HNPEN            (1 << 9)
 166 #       define   OTG_B_BUSREQ           (1 << 8)
 167 #       define   OTG_BUSDROP            (1 << 7)
 168 #       define   OTG_PULLDOWN           (1 << 5)
 169 #       define   OTG_PULLUP             (1 << 4)
 170 #       define   OTG_DRV_VBUS           (1 << 3)
 171 #       define   OTG_PD_VBUS            (1 << 2)
 172 #       define   OTG_PU_VBUS            (1 << 1)
 173 #       define   OTG_PU_ID              (1 << 0)
 174 #define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
 175 #       define   DRIVER_SWITCH          (1 << 15)
 176 #       define   A_VBUS_ERR             (1 << 13)
 177 #       define   A_REQ_TMROUT           (1 << 12)
 178 #       define   A_SRP_DETECT           (1 << 11)
 179 #       define   B_HNP_FAIL             (1 << 10)
 180 #       define   B_SRP_TMROUT           (1 << 9)
 181 #       define   B_SRP_DONE             (1 << 8)
 182 #       define   B_SRP_STARTED          (1 << 7)
 183 #       define   OPRT_CHG               (1 << 0)
 184 #define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
 185         // same bits as in IRQ_EN
 186 #define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
 187 #       define   OTGVPD                 (1 << 14)
 188 #       define   OTGVPU                 (1 << 13)
 189 #       define   OTGPUID                (1 << 12)
 190 #       define   USB2VDR                (1 << 10)
 191 #       define   USB2PDEN               (1 << 9)
 192 #       define   USB2PUEN               (1 << 8)
 193 #       define   USB1VDR                (1 << 6)
 194 #       define   USB1PDEN               (1 << 5)
 195 #       define   USB1PUEN               (1 << 4)
 196 #       define   USB0VDR                (1 << 2)
 197 #       define   USB0PDEN               (1 << 1)
 198 #       define   USB0PUEN               (1 << 0)
 199 #define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
 200 #define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
 201
 202 /*-------------------------------------------------------------------------*/
 203
 204 /* OMAP1 */
 205 #define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
 206 #       define  CONF_USB2_UNI_R         (1 << 8)
 207 #       define  CONF_USB1_UNI_R         (1 << 7)
 208 #       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
 209 #       define  CONF_USB0_ISOLATE_R     (1 << 3)
 210 #       define  CONF_USB_PWRDN_DM_R     (1 << 2)
 211 #       define  CONF_USB_PWRDN_DP_R     (1 << 1)
 212
 213 /* OMAP2 */
 214 #       define  USB_UNIDIR                      0x0
 215 #       define  USB_UNIDIR_TLL                  0x1
 216 #       define  USB_BIDIR                       0x2
 217 #       define  USB_BIDIR_TLL                   0x3
 218 #       define  USBTXWRMODEI(port, x)   ((x) << (22 - (port * 2)))
 219 #       define  USBT2TLL5PI             (1 << 17)
 220 #       define  USB0PUENACTLOI          (1 << 16)
 221 #       define  USBSTANDBYCTRL          (1 << 15)
 222 /* AM35x */
 223 /* USB 2.0 PHY Control */
 224 #define CONF2_PHY_GPIOMODE      (1 << 23)
 225 #define CONF2_OTGMODE           (3 << 14)
 226 #define CONF2_NO_OVERRIDE       (0 << 14)
 227 #define CONF2_FORCE_HOST        (1 << 14)
 228 #define CONF2_FORCE_DEVICE      (2 << 14)
 229 #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
 230 #define CONF2_SESENDEN          (1 << 13)
 231 #define CONF2_VBDTCTEN          (1 << 12)
 232 #define CONF2_REFFREQ_24MHZ     (2 << 8)
 233 #define CONF2_REFFREQ_26MHZ     (7 << 8)
 234 #define CONF2_REFFREQ_13MHZ     (6 << 8)
 235 #define CONF2_REFFREQ           (0xf << 8)
 236 #define CONF2_PHYCLKGD          (1 << 7)
 237 #define CONF2_VBUSSENSE         (1 << 6)
 238 #define CONF2_PHY_PLLON         (1 << 5)
 239 #define CONF2_RESET             (1 << 4)
 240 #define CONF2_PHYPWRDN          (1 << 3)
 241 #define CONF2_OTGPWRDN          (1 << 2)
 242 #define CONF2_DATPOL            (1 << 1)
 243
 244 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
 245 u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
 246 u32 omap1_usb1_init(unsigned nwires);
 247 u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
 248 #else
 249 static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
 250 {
 251         return 0;
 252 }
 253 static inline u32 omap1_usb1_init(unsigned nwires)
 254 {
 255         return 0;
 256
 257 }
 258 static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
 259 {
 260         return 0;
 261 }
 262 #endif
 263
 264 #endif  /* __ASM_ARCH_OMAP_USB_H */