2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 #include <linux/device.h>
24 #include <asm/setup.h>
27 unsigned int pci_pm_d3_delay
= PCI_PM_D3_WAIT
;
29 #ifdef CONFIG_PCI_DOMAINS
30 int pci_domains_supported
= 1;
33 #define DEFAULT_CARDBUS_IO_SIZE (256)
34 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
35 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
36 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
37 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
40 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
41 * @bus: pointer to PCI bus structure to search
43 * Given a PCI bus, returns the highest PCI bus number present in the set
44 * including the given PCI bus and its list of child PCI buses.
46 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
48 struct list_head
*tmp
;
51 max
= bus
->subordinate
;
52 list_for_each(tmp
, &bus
->children
) {
53 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
59 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
61 #ifdef CONFIG_HAS_IOMEM
62 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
65 * Make sure the BAR is actually a memory resource, not an IO resource
67 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
71 return ioremap_nocache(pci_resource_start(pdev
, bar
),
72 pci_resource_len(pdev
, bar
));
74 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
79 * pci_max_busnr - returns maximum PCI bus number
81 * Returns the highest PCI bus number present in the system global list of
84 unsigned char __devinit
87 struct pci_bus
*bus
= NULL
;
91 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
92 n
= pci_bus_max_busnr(bus
);
101 #define PCI_FIND_CAP_TTL 48
103 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
104 u8 pos
, int cap
, int *ttl
)
109 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
113 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
119 pos
+= PCI_CAP_LIST_NEXT
;
124 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
127 int ttl
= PCI_FIND_CAP_TTL
;
129 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
132 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
134 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
135 pos
+ PCI_CAP_LIST_NEXT
, cap
);
137 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
139 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
140 unsigned int devfn
, u8 hdr_type
)
144 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
145 if (!(status
& PCI_STATUS_CAP_LIST
))
149 case PCI_HEADER_TYPE_NORMAL
:
150 case PCI_HEADER_TYPE_BRIDGE
:
151 return PCI_CAPABILITY_LIST
;
152 case PCI_HEADER_TYPE_CARDBUS
:
153 return PCI_CB_CAPABILITY_LIST
;
162 * pci_find_capability - query for devices' capabilities
163 * @dev: PCI device to query
164 * @cap: capability code
166 * Tell if a device supports a given PCI capability.
167 * Returns the address of the requested capability structure within the
168 * device's PCI configuration space or 0 in case the device does not
169 * support it. Possible values for @cap:
171 * %PCI_CAP_ID_PM Power Management
172 * %PCI_CAP_ID_AGP Accelerated Graphics Port
173 * %PCI_CAP_ID_VPD Vital Product Data
174 * %PCI_CAP_ID_SLOTID Slot Identification
175 * %PCI_CAP_ID_MSI Message Signalled Interrupts
176 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
177 * %PCI_CAP_ID_PCIX PCI-X
178 * %PCI_CAP_ID_EXP PCI Express
180 int pci_find_capability(struct pci_dev
*dev
, int cap
)
184 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
186 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
192 * pci_bus_find_capability - query for devices' capabilities
193 * @bus: the PCI bus to query
194 * @devfn: PCI device to query
195 * @cap: capability code
197 * Like pci_find_capability() but works for pci devices that do not have a
198 * pci_dev structure set up yet.
200 * Returns the address of the requested capability structure within the
201 * device's PCI configuration space or 0 in case the device does not
204 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
209 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
211 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
213 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
219 * pci_find_ext_capability - Find an extended capability
220 * @dev: PCI device to query
221 * @cap: capability code
223 * Returns the address of the requested extended capability structure
224 * within the device's PCI configuration space or 0 if the device does
225 * not support it. Possible values for @cap:
227 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
228 * %PCI_EXT_CAP_ID_VC Virtual Channel
229 * %PCI_EXT_CAP_ID_DSN Device Serial Number
230 * %PCI_EXT_CAP_ID_PWR Power Budgeting
232 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
236 int pos
= PCI_CFG_SPACE_SIZE
;
238 /* minimum 8 bytes per capability */
239 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
241 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
244 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
248 * If we have no capabilities, this is indicated by cap ID,
249 * cap version and next pointer all being 0.
255 if (PCI_EXT_CAP_ID(header
) == cap
)
258 pos
= PCI_EXT_CAP_NEXT(header
);
259 if (pos
< PCI_CFG_SPACE_SIZE
)
262 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
268 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
270 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
272 int rc
, ttl
= PCI_FIND_CAP_TTL
;
275 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
276 mask
= HT_3BIT_CAP_MASK
;
278 mask
= HT_5BIT_CAP_MASK
;
280 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
281 PCI_CAP_ID_HT
, &ttl
);
283 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
284 if (rc
!= PCIBIOS_SUCCESSFUL
)
287 if ((cap
& mask
) == ht_cap
)
290 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
291 pos
+ PCI_CAP_LIST_NEXT
,
292 PCI_CAP_ID_HT
, &ttl
);
298 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
299 * @dev: PCI device to query
300 * @pos: Position from which to continue searching
301 * @ht_cap: Hypertransport capability code
303 * To be used in conjunction with pci_find_ht_capability() to search for
304 * all capabilities matching @ht_cap. @pos should always be a value returned
305 * from pci_find_ht_capability().
307 * NB. To be 100% safe against broken PCI devices, the caller should take
308 * steps to avoid an infinite loop.
310 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
312 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
314 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
317 * pci_find_ht_capability - query a device's Hypertransport capabilities
318 * @dev: PCI device to query
319 * @ht_cap: Hypertransport capability code
321 * Tell if a device supports a given Hypertransport capability.
322 * Returns an address within the device's PCI configuration space
323 * or 0 in case the device does not support the request capability.
324 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
325 * which has a Hypertransport capability matching @ht_cap.
327 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
331 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
333 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
337 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
340 * pci_find_parent_resource - return resource region of parent bus of given region
341 * @dev: PCI device structure contains resources to be searched
342 * @res: child resource record for which parent is sought
344 * For given resource region of given device, return the resource
345 * region of parent bus the given region is contained in or where
346 * it should be allocated from.
349 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
351 const struct pci_bus
*bus
= dev
->bus
;
353 struct resource
*best
= NULL
;
355 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
356 struct resource
*r
= bus
->resource
[i
];
359 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
360 continue; /* Not contained */
361 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
362 continue; /* Wrong type */
363 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
364 return r
; /* Exact match */
365 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
366 best
= r
; /* Approximating prefetchable by non-prefetchable */
372 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
373 * @dev: PCI device to have its BARs restored
375 * Restore the BAR values for a given device, so as to make it
376 * accessible by its driver.
379 pci_restore_bars(struct pci_dev
*dev
)
383 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
384 pci_update_resource(dev
, i
);
387 static struct pci_platform_pm_ops
*pci_platform_pm
;
389 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
391 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
392 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
394 pci_platform_pm
= ops
;
398 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
400 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
403 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
406 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
409 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
411 return pci_platform_pm
?
412 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
415 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
417 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
420 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
422 return pci_platform_pm
?
423 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
427 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
429 * @dev: PCI device to handle.
430 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
433 * -EINVAL if the requested state is invalid.
434 * -EIO if device does not support PCI PM or its PM capabilities register has a
435 * wrong version, or device doesn't support the requested state.
436 * 0 if device already is in the requested state.
437 * 0 if device's power state has been successfully changed.
439 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
442 bool need_restore
= false;
444 /* Check if we're already there */
445 if (dev
->current_state
== state
)
451 if (state
< PCI_D0
|| state
> PCI_D3hot
)
454 /* Validate current state:
455 * Can enter D0 from any state, but if we can only go deeper
456 * to sleep if we're already in a low power state
458 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
459 && dev
->current_state
> state
) {
460 dev_err(&dev
->dev
, "invalid power transition "
461 "(from state %d to %d)\n", dev
->current_state
, state
);
465 /* check if this device supports the desired state */
466 if ((state
== PCI_D1
&& !dev
->d1_support
)
467 || (state
== PCI_D2
&& !dev
->d2_support
))
470 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
472 /* If we're (effectively) in D3, force entire word to 0.
473 * This doesn't affect PME_Status, disables PME_En, and
474 * sets PowerState to 0.
476 switch (dev
->current_state
) {
480 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
485 case PCI_UNKNOWN
: /* Boot-up */
486 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
487 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
489 /* Fall-through: force to D0 */
495 /* enter specified state */
496 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
498 /* Mandatory power management transition delays */
499 /* see PCI PM 1.1 5.6.1 table 18 */
500 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
501 msleep(pci_pm_d3_delay
);
502 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
503 udelay(PCI_PM_D2_DELAY
);
505 dev
->current_state
= state
;
507 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
508 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
509 * from D3hot to D0 _may_ perform an internal reset, thereby
510 * going to "D0 Uninitialized" rather than "D0 Initialized".
511 * For example, at least some versions of the 3c905B and the
512 * 3c556B exhibit this behaviour.
514 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
515 * devices in a D3hot state at boot. Consequently, we need to
516 * restore at least the BARs so that the device will be
517 * accessible to its driver.
520 pci_restore_bars(dev
);
523 pcie_aspm_pm_state_change(dev
->bus
->self
);
529 * pci_update_current_state - Read PCI power state of given device from its
530 * PCI PM registers and cache it
531 * @dev: PCI device to handle.
532 * @state: State to cache in case the device doesn't have the PM capability
534 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
539 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
540 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
542 dev
->current_state
= state
;
547 * pci_platform_power_transition - Use platform to change device power state
548 * @dev: PCI device to handle.
549 * @state: State to put the device into.
551 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
555 if (platform_pci_power_manageable(dev
)) {
556 error
= platform_pci_set_power_state(dev
, state
);
558 pci_update_current_state(dev
, state
);
561 /* Fall back to PCI_D0 if native PM is not supported */
563 dev
->current_state
= PCI_D0
;
570 * __pci_start_power_transition - Start power transition of a PCI device
571 * @dev: PCI device to handle.
572 * @state: State to put the device into.
574 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
577 pci_platform_power_transition(dev
, PCI_D0
);
581 * __pci_complete_power_transition - Complete power transition of a PCI device
582 * @dev: PCI device to handle.
583 * @state: State to put the device into.
585 * This function should not be called directly by device drivers.
587 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
589 return state
> PCI_D0
?
590 pci_platform_power_transition(dev
, state
) : -EINVAL
;
592 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
595 * pci_set_power_state - Set the power state of a PCI device
596 * @dev: PCI device to handle.
597 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
599 * Transition a device to a new power state, using the platform firmware and/or
600 * the device's PCI PM registers.
603 * -EINVAL if the requested state is invalid.
604 * -EIO if device does not support PCI PM or its PM capabilities register has a
605 * wrong version, or device doesn't support the requested state.
606 * 0 if device already is in the requested state.
607 * 0 if device's power state has been successfully changed.
609 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
613 /* bound the state we're entering */
614 if (state
> PCI_D3hot
)
616 else if (state
< PCI_D0
)
618 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
620 * If the device or the parent bridge do not support PCI PM,
621 * ignore the request if we're doing anything other than putting
622 * it into D0 (which would only happen on boot).
626 /* Check if we're already there */
627 if (dev
->current_state
== state
)
630 __pci_start_power_transition(dev
, state
);
632 /* This device is quirked not to be put into D3, so
633 don't put it in D3 */
634 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
637 error
= pci_raw_set_power_state(dev
, state
);
639 if (!__pci_complete_power_transition(dev
, state
))
646 * pci_choose_state - Choose the power state of a PCI device
647 * @dev: PCI device to be suspended
648 * @state: target sleep state for the whole system. This is the value
649 * that is passed to suspend() function.
651 * Returns PCI power state suitable for given device and given system
655 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
659 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
662 ret
= platform_pci_choose_state(dev
);
663 if (ret
!= PCI_POWER_ERROR
)
666 switch (state
.event
) {
669 case PM_EVENT_FREEZE
:
670 case PM_EVENT_PRETHAW
:
671 /* REVISIT both freeze and pre-thaw "should" use D0 */
672 case PM_EVENT_SUSPEND
:
673 case PM_EVENT_HIBERNATE
:
676 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
683 EXPORT_SYMBOL(pci_choose_state
);
685 #define PCI_EXP_SAVE_REGS 7
687 #define pcie_cap_has_devctl(type, flags) 1
688 #define pcie_cap_has_lnkctl(type, flags) \
689 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
690 (type == PCI_EXP_TYPE_ROOT_PORT || \
691 type == PCI_EXP_TYPE_ENDPOINT || \
692 type == PCI_EXP_TYPE_LEG_END))
693 #define pcie_cap_has_sltctl(type, flags) \
694 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
695 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
696 (type == PCI_EXP_TYPE_DOWNSTREAM && \
697 (flags & PCI_EXP_FLAGS_SLOT))))
698 #define pcie_cap_has_rtctl(type, flags) \
699 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
700 (type == PCI_EXP_TYPE_ROOT_PORT || \
701 type == PCI_EXP_TYPE_RC_EC))
702 #define pcie_cap_has_devctl2(type, flags) \
703 ((flags & PCI_EXP_FLAGS_VERS) > 1)
704 #define pcie_cap_has_lnkctl2(type, flags) \
705 ((flags & PCI_EXP_FLAGS_VERS) > 1)
706 #define pcie_cap_has_sltctl2(type, flags) \
707 ((flags & PCI_EXP_FLAGS_VERS) > 1)
709 static int pci_save_pcie_state(struct pci_dev
*dev
)
712 struct pci_cap_saved_state
*save_state
;
716 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
720 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
722 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
725 cap
= (u16
*)&save_state
->data
[0];
727 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
729 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
730 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
731 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
732 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
733 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
734 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
735 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
736 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
737 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
738 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &cap
[i
++]);
739 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
740 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, &cap
[i
++]);
741 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
742 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, &cap
[i
++]);
747 static void pci_restore_pcie_state(struct pci_dev
*dev
)
750 struct pci_cap_saved_state
*save_state
;
754 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
755 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
756 if (!save_state
|| pos
<= 0)
758 cap
= (u16
*)&save_state
->data
[0];
760 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
762 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
763 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
764 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
765 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
766 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
767 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
768 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
769 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
770 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
771 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, cap
[i
++]);
772 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
773 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, cap
[i
++]);
774 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
775 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, cap
[i
++]);
779 static int pci_save_pcix_state(struct pci_dev
*dev
)
782 struct pci_cap_saved_state
*save_state
;
784 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
788 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
790 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
794 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
799 static void pci_restore_pcix_state(struct pci_dev
*dev
)
802 struct pci_cap_saved_state
*save_state
;
805 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
806 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
807 if (!save_state
|| pos
<= 0)
809 cap
= (u16
*)&save_state
->data
[0];
811 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
816 * pci_save_state - save the PCI configuration space of a device before suspending
817 * @dev: - PCI device that we're dealing with
820 pci_save_state(struct pci_dev
*dev
)
823 /* XXX: 100% dword access ok here? */
824 for (i
= 0; i
< 16; i
++)
825 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
826 dev
->state_saved
= true;
827 if ((i
= pci_save_pcie_state(dev
)) != 0)
829 if ((i
= pci_save_pcix_state(dev
)) != 0)
835 * pci_restore_state - Restore the saved state of a PCI device
836 * @dev: - PCI device that we're dealing with
839 pci_restore_state(struct pci_dev
*dev
)
844 /* PCI Express register must be restored first */
845 pci_restore_pcie_state(dev
);
848 * The Base Address register should be programmed before the command
851 for (i
= 15; i
>= 0; i
--) {
852 pci_read_config_dword(dev
, i
* 4, &val
);
853 if (val
!= dev
->saved_config_space
[i
]) {
854 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
855 "space at offset %#x (was %#x, writing %#x)\n",
856 i
, val
, (int)dev
->saved_config_space
[i
]);
857 pci_write_config_dword(dev
,i
* 4,
858 dev
->saved_config_space
[i
]);
861 pci_restore_pcix_state(dev
);
862 pci_restore_msi_state(dev
);
863 pci_restore_iov_state(dev
);
868 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
872 err
= pci_set_power_state(dev
, PCI_D0
);
873 if (err
< 0 && err
!= -EIO
)
875 err
= pcibios_enable_device(dev
, bars
);
878 pci_fixup_device(pci_fixup_enable
, dev
);
884 * pci_reenable_device - Resume abandoned device
885 * @dev: PCI device to be resumed
887 * Note this function is a backend of pci_default_resume and is not supposed
888 * to be called by normal code, write proper resume handler and use it instead.
890 int pci_reenable_device(struct pci_dev
*dev
)
892 if (pci_is_enabled(dev
))
893 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
897 static int __pci_enable_device_flags(struct pci_dev
*dev
,
898 resource_size_t flags
)
903 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
904 return 0; /* already enabled */
906 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
907 if (dev
->resource
[i
].flags
& flags
)
910 err
= do_pci_enable_device(dev
, bars
);
912 atomic_dec(&dev
->enable_cnt
);
917 * pci_enable_device_io - Initialize a device for use with IO space
918 * @dev: PCI device to be initialized
920 * Initialize device before it's used by a driver. Ask low-level code
921 * to enable I/O resources. Wake up the device if it was suspended.
922 * Beware, this function can fail.
924 int pci_enable_device_io(struct pci_dev
*dev
)
926 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
930 * pci_enable_device_mem - Initialize a device for use with Memory space
931 * @dev: PCI device to be initialized
933 * Initialize device before it's used by a driver. Ask low-level code
934 * to enable Memory resources. Wake up the device if it was suspended.
935 * Beware, this function can fail.
937 int pci_enable_device_mem(struct pci_dev
*dev
)
939 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
943 * pci_enable_device - Initialize device before it's used by a driver.
944 * @dev: PCI device to be initialized
946 * Initialize device before it's used by a driver. Ask low-level code
947 * to enable I/O and memory. Wake up the device if it was suspended.
948 * Beware, this function can fail.
950 * Note we don't actually enable the device many times if we call
951 * this function repeatedly (we just increment the count).
953 int pci_enable_device(struct pci_dev
*dev
)
955 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
959 * Managed PCI resources. This manages device on/off, intx/msi/msix
960 * on/off and BAR regions. pci_dev itself records msi/msix status, so
961 * there's no need to track it separately. pci_devres is initialized
962 * when a device is enabled using managed PCI device enable interface.
965 unsigned int enabled
:1;
966 unsigned int pinned
:1;
967 unsigned int orig_intx
:1;
968 unsigned int restore_intx
:1;
972 static void pcim_release(struct device
*gendev
, void *res
)
974 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
975 struct pci_devres
*this = res
;
978 if (dev
->msi_enabled
)
979 pci_disable_msi(dev
);
980 if (dev
->msix_enabled
)
981 pci_disable_msix(dev
);
983 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
984 if (this->region_mask
& (1 << i
))
985 pci_release_region(dev
, i
);
987 if (this->restore_intx
)
988 pci_intx(dev
, this->orig_intx
);
990 if (this->enabled
&& !this->pinned
)
991 pci_disable_device(dev
);
994 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
996 struct pci_devres
*dr
, *new_dr
;
998 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1002 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1005 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1008 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1010 if (pci_is_managed(pdev
))
1011 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1016 * pcim_enable_device - Managed pci_enable_device()
1017 * @pdev: PCI device to be initialized
1019 * Managed pci_enable_device().
1021 int pcim_enable_device(struct pci_dev
*pdev
)
1023 struct pci_devres
*dr
;
1026 dr
= get_pci_dr(pdev
);
1032 rc
= pci_enable_device(pdev
);
1034 pdev
->is_managed
= 1;
1041 * pcim_pin_device - Pin managed PCI device
1042 * @pdev: PCI device to pin
1044 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1045 * driver detach. @pdev must have been enabled with
1046 * pcim_enable_device().
1048 void pcim_pin_device(struct pci_dev
*pdev
)
1050 struct pci_devres
*dr
;
1052 dr
= find_pci_dr(pdev
);
1053 WARN_ON(!dr
|| !dr
->enabled
);
1059 * pcibios_disable_device - disable arch specific PCI resources for device dev
1060 * @dev: the PCI device to disable
1062 * Disables architecture specific PCI resources for the device. This
1063 * is the default implementation. Architecture implementations can
1066 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
1068 static void do_pci_disable_device(struct pci_dev
*dev
)
1072 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1073 if (pci_command
& PCI_COMMAND_MASTER
) {
1074 pci_command
&= ~PCI_COMMAND_MASTER
;
1075 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1078 pcibios_disable_device(dev
);
1082 * pci_disable_enabled_device - Disable device without updating enable_cnt
1083 * @dev: PCI device to disable
1085 * NOTE: This function is a backend of PCI power management routines and is
1086 * not supposed to be called drivers.
1088 void pci_disable_enabled_device(struct pci_dev
*dev
)
1090 if (pci_is_enabled(dev
))
1091 do_pci_disable_device(dev
);
1095 * pci_disable_device - Disable PCI device after use
1096 * @dev: PCI device to be disabled
1098 * Signal to the system that the PCI device is not in use by the system
1099 * anymore. This only involves disabling PCI bus-mastering, if active.
1101 * Note we don't actually disable the device until all callers of
1102 * pci_device_enable() have called pci_device_disable().
1105 pci_disable_device(struct pci_dev
*dev
)
1107 struct pci_devres
*dr
;
1109 dr
= find_pci_dr(dev
);
1113 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1116 do_pci_disable_device(dev
);
1118 dev
->is_busmaster
= 0;
1122 * pcibios_set_pcie_reset_state - set reset state for device dev
1123 * @dev: the PCI-E device reset
1124 * @state: Reset state to enter into
1127 * Sets the PCI-E reset state for the device. This is the default
1128 * implementation. Architecture implementations can override this.
1130 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1131 enum pcie_reset_state state
)
1137 * pci_set_pcie_reset_state - set reset state for device dev
1138 * @dev: the PCI-E device reset
1139 * @state: Reset state to enter into
1142 * Sets the PCI reset state for the device.
1144 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1146 return pcibios_set_pcie_reset_state(dev
, state
);
1150 * pci_pme_capable - check the capability of PCI device to generate PME#
1151 * @dev: PCI device to handle.
1152 * @state: PCI state from which device will issue PME#.
1154 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1159 return !!(dev
->pme_support
& (1 << state
));
1163 * pci_pme_active - enable or disable PCI device's PME# function
1164 * @dev: PCI device to handle.
1165 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1167 * The caller must verify that the device is capable of generating PME# before
1168 * calling this function with @enable equal to 'true'.
1170 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1177 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1178 /* Clear PME_Status by writing 1 to it and enable PME# */
1179 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1181 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1183 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1185 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1186 enable
? "enabled" : "disabled");
1190 * pci_enable_wake - enable PCI device as wakeup event source
1191 * @dev: PCI device affected
1192 * @state: PCI state from which device will issue wakeup events
1193 * @enable: True to enable event generation; false to disable
1195 * This enables the device as a wakeup event source, or disables it.
1196 * When such events involves platform-specific hooks, those hooks are
1197 * called automatically by this routine.
1199 * Devices with legacy power management (no standard PCI PM capabilities)
1200 * always require such platform hooks.
1203 * 0 is returned on success
1204 * -EINVAL is returned if device is not supposed to wake up the system
1205 * Error code depending on the platform is returned if both the platform and
1206 * the native mechanism fail to enable the generation of wake-up events
1208 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
1211 bool pme_done
= false;
1213 if (enable
&& !device_may_wakeup(&dev
->dev
))
1217 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1218 * Anderson we should be doing PME# wake enable followed by ACPI wake
1219 * enable. To disable wake-up we call the platform first, for symmetry.
1222 if (!enable
&& platform_pci_can_wakeup(dev
))
1223 error
= platform_pci_sleep_wake(dev
, false);
1225 if (!enable
|| pci_pme_capable(dev
, state
)) {
1226 pci_pme_active(dev
, enable
);
1230 if (enable
&& platform_pci_can_wakeup(dev
))
1231 error
= platform_pci_sleep_wake(dev
, true);
1233 return pme_done
? 0 : error
;
1237 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1238 * @dev: PCI device to prepare
1239 * @enable: True to enable wake-up event generation; false to disable
1241 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1242 * and this function allows them to set that up cleanly - pci_enable_wake()
1243 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1244 * ordering constraints.
1246 * This function only returns error code if the device is not capable of
1247 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1248 * enable wake-up power for it.
1250 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1252 return pci_pme_capable(dev
, PCI_D3cold
) ?
1253 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1254 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1258 * pci_target_state - find an appropriate low power state for a given PCI dev
1261 * Use underlying platform code to find a supported low power state for @dev.
1262 * If the platform can't manage @dev, return the deepest state from which it
1263 * can generate wake events, based on any available PME info.
1265 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1267 pci_power_t target_state
= PCI_D3hot
;
1269 if (platform_pci_power_manageable(dev
)) {
1271 * Call the platform to choose the target state of the device
1272 * and enable wake-up from this state if supported.
1274 pci_power_t state
= platform_pci_choose_state(dev
);
1277 case PCI_POWER_ERROR
:
1282 if (pci_no_d1d2(dev
))
1285 target_state
= state
;
1287 } else if (device_may_wakeup(&dev
->dev
)) {
1289 * Find the deepest state from which the device can generate
1290 * wake-up events, make it the target state and enable device
1294 return PCI_POWER_ERROR
;
1296 if (dev
->pme_support
) {
1298 && !(dev
->pme_support
& (1 << target_state
)))
1303 return target_state
;
1307 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1308 * @dev: Device to handle.
1310 * Choose the power state appropriate for the device depending on whether
1311 * it can wake up the system and/or is power manageable by the platform
1312 * (PCI_D3hot is the default) and put the device into that state.
1314 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1316 pci_power_t target_state
= pci_target_state(dev
);
1319 if (target_state
== PCI_POWER_ERROR
)
1322 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1324 error
= pci_set_power_state(dev
, target_state
);
1327 pci_enable_wake(dev
, target_state
, false);
1333 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1334 * @dev: Device to handle.
1336 * Disable device's sytem wake-up capability and put it into D0.
1338 int pci_back_from_sleep(struct pci_dev
*dev
)
1340 pci_enable_wake(dev
, PCI_D0
, false);
1341 return pci_set_power_state(dev
, PCI_D0
);
1345 * pci_pm_init - Initialize PM functions of given PCI device
1346 * @dev: PCI device to handle.
1348 void pci_pm_init(struct pci_dev
*dev
)
1355 /* find PCI PM capability in list */
1356 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1359 /* Check device's ability to generate PME# */
1360 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1362 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1363 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1364 pmc
& PCI_PM_CAP_VER_MASK
);
1370 dev
->d1_support
= false;
1371 dev
->d2_support
= false;
1372 if (!pci_no_d1d2(dev
)) {
1373 if (pmc
& PCI_PM_CAP_D1
)
1374 dev
->d1_support
= true;
1375 if (pmc
& PCI_PM_CAP_D2
)
1376 dev
->d2_support
= true;
1378 if (dev
->d1_support
|| dev
->d2_support
)
1379 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1380 dev
->d1_support
? " D1" : "",
1381 dev
->d2_support
? " D2" : "");
1384 pmc
&= PCI_PM_CAP_PME_MASK
;
1386 dev_info(&dev
->dev
, "PME# supported from%s%s%s%s%s\n",
1387 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1388 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1389 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1390 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1391 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1392 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1394 * Make device's PM flags reflect the wake-up capability, but
1395 * let the user space enable it to wake up the system as needed.
1397 device_set_wakeup_capable(&dev
->dev
, true);
1398 device_set_wakeup_enable(&dev
->dev
, false);
1399 /* Disable the PME# generation functionality */
1400 pci_pme_active(dev
, false);
1402 dev
->pme_support
= 0;
1407 * platform_pci_wakeup_init - init platform wakeup if present
1410 * Some devices don't have PCI PM caps but can still generate wakeup
1411 * events through platform methods (like ACPI events). If @dev supports
1412 * platform wakeup events, set the device flag to indicate as much. This
1413 * may be redundant if the device also supports PCI PM caps, but double
1414 * initialization should be safe in that case.
1416 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1418 if (!platform_pci_can_wakeup(dev
))
1421 device_set_wakeup_capable(&dev
->dev
, true);
1422 device_set_wakeup_enable(&dev
->dev
, false);
1423 platform_pci_sleep_wake(dev
, false);
1427 * pci_add_save_buffer - allocate buffer for saving given capability registers
1428 * @dev: the PCI device
1429 * @cap: the capability to allocate the buffer for
1430 * @size: requested size of the buffer
1432 static int pci_add_cap_save_buffer(
1433 struct pci_dev
*dev
, char cap
, unsigned int size
)
1436 struct pci_cap_saved_state
*save_state
;
1438 pos
= pci_find_capability(dev
, cap
);
1442 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1446 save_state
->cap_nr
= cap
;
1447 pci_add_saved_cap(dev
, save_state
);
1453 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1454 * @dev: the PCI device
1456 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1460 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
1461 PCI_EXP_SAVE_REGS
* sizeof(u16
));
1464 "unable to preallocate PCI Express save buffer\n");
1466 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1469 "unable to preallocate PCI-X save buffer\n");
1473 * pci_enable_ari - enable ARI forwarding if hardware support it
1474 * @dev: the PCI device
1476 void pci_enable_ari(struct pci_dev
*dev
)
1481 struct pci_dev
*bridge
;
1483 if (!dev
->is_pcie
|| dev
->devfn
)
1486 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1490 bridge
= dev
->bus
->self
;
1491 if (!bridge
|| !bridge
->is_pcie
)
1494 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
1498 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1499 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1502 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1503 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1504 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1506 bridge
->ari_enabled
= 1;
1510 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1511 * @dev: the PCI device
1512 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1514 * Perform INTx swizzling for a device behind one level of bridge. This is
1515 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1516 * behind bridges on add-in cards.
1518 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1520 return (((pin
- 1) + PCI_SLOT(dev
->devfn
)) % 4) + 1;
1524 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1532 while (!pci_is_root_bus(dev
->bus
)) {
1533 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1534 dev
= dev
->bus
->self
;
1541 * pci_common_swizzle - swizzle INTx all the way to root bridge
1542 * @dev: the PCI device
1543 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1545 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1546 * bridges all the way up to a PCI root bus.
1548 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
1552 while (!pci_is_root_bus(dev
->bus
)) {
1553 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1554 dev
= dev
->bus
->self
;
1557 return PCI_SLOT(dev
->devfn
);
1561 * pci_release_region - Release a PCI bar
1562 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1563 * @bar: BAR to release
1565 * Releases the PCI I/O and memory resources previously reserved by a
1566 * successful call to pci_request_region. Call this function only
1567 * after all use of the PCI regions has ceased.
1569 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1571 struct pci_devres
*dr
;
1573 if (pci_resource_len(pdev
, bar
) == 0)
1575 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1576 release_region(pci_resource_start(pdev
, bar
),
1577 pci_resource_len(pdev
, bar
));
1578 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1579 release_mem_region(pci_resource_start(pdev
, bar
),
1580 pci_resource_len(pdev
, bar
));
1582 dr
= find_pci_dr(pdev
);
1584 dr
->region_mask
&= ~(1 << bar
);
1588 * __pci_request_region - Reserved PCI I/O and memory resource
1589 * @pdev: PCI device whose resources are to be reserved
1590 * @bar: BAR to be reserved
1591 * @res_name: Name to be associated with resource.
1592 * @exclusive: whether the region access is exclusive or not
1594 * Mark the PCI region associated with PCI device @pdev BR @bar as
1595 * being reserved by owner @res_name. Do not access any
1596 * address inside the PCI regions unless this call returns
1599 * If @exclusive is set, then the region is marked so that userspace
1600 * is explicitly not allowed to map the resource via /dev/mem or
1601 * sysfs MMIO access.
1603 * Returns 0 on success, or %EBUSY on error. A warning
1604 * message is also printed on failure.
1606 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
1609 struct pci_devres
*dr
;
1611 if (pci_resource_len(pdev
, bar
) == 0)
1614 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1615 if (!request_region(pci_resource_start(pdev
, bar
),
1616 pci_resource_len(pdev
, bar
), res_name
))
1619 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1620 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
1621 pci_resource_len(pdev
, bar
), res_name
,
1626 dr
= find_pci_dr(pdev
);
1628 dr
->region_mask
|= 1 << bar
;
1633 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region %pR\n",
1635 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1636 &pdev
->resource
[bar
]);
1641 * pci_request_region - Reserve PCI I/O and memory resource
1642 * @pdev: PCI device whose resources are to be reserved
1643 * @bar: BAR to be reserved
1644 * @res_name: Name to be associated with resource
1646 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1647 * being reserved by owner @res_name. Do not access any
1648 * address inside the PCI regions unless this call returns
1651 * Returns 0 on success, or %EBUSY on error. A warning
1652 * message is also printed on failure.
1654 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1656 return __pci_request_region(pdev
, bar
, res_name
, 0);
1660 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1661 * @pdev: PCI device whose resources are to be reserved
1662 * @bar: BAR to be reserved
1663 * @res_name: Name to be associated with resource.
1665 * Mark the PCI region associated with PCI device @pdev BR @bar as
1666 * being reserved by owner @res_name. Do not access any
1667 * address inside the PCI regions unless this call returns
1670 * Returns 0 on success, or %EBUSY on error. A warning
1671 * message is also printed on failure.
1673 * The key difference that _exclusive makes it that userspace is
1674 * explicitly not allowed to map the resource via /dev/mem or
1677 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1679 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
1682 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1683 * @pdev: PCI device whose resources were previously reserved
1684 * @bars: Bitmask of BARs to be released
1686 * Release selected PCI I/O and memory resources previously reserved.
1687 * Call this function only after all use of the PCI regions has ceased.
1689 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1693 for (i
= 0; i
< 6; i
++)
1694 if (bars
& (1 << i
))
1695 pci_release_region(pdev
, i
);
1698 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1699 const char *res_name
, int excl
)
1703 for (i
= 0; i
< 6; i
++)
1704 if (bars
& (1 << i
))
1705 if (__pci_request_region(pdev
, i
, res_name
, excl
))
1711 if (bars
& (1 << i
))
1712 pci_release_region(pdev
, i
);
1719 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1720 * @pdev: PCI device whose resources are to be reserved
1721 * @bars: Bitmask of BARs to be requested
1722 * @res_name: Name to be associated with resource
1724 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1725 const char *res_name
)
1727 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
1730 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
1731 int bars
, const char *res_name
)
1733 return __pci_request_selected_regions(pdev
, bars
, res_name
,
1734 IORESOURCE_EXCLUSIVE
);
1738 * pci_release_regions - Release reserved PCI I/O and memory resources
1739 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1741 * Releases all PCI I/O and memory resources previously reserved by a
1742 * successful call to pci_request_regions. Call this function only
1743 * after all use of the PCI regions has ceased.
1746 void pci_release_regions(struct pci_dev
*pdev
)
1748 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1752 * pci_request_regions - Reserved PCI I/O and memory resources
1753 * @pdev: PCI device whose resources are to be reserved
1754 * @res_name: Name to be associated with resource.
1756 * Mark all PCI regions associated with PCI device @pdev as
1757 * being reserved by owner @res_name. Do not access any
1758 * address inside the PCI regions unless this call returns
1761 * Returns 0 on success, or %EBUSY on error. A warning
1762 * message is also printed on failure.
1764 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1766 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1770 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1771 * @pdev: PCI device whose resources are to be reserved
1772 * @res_name: Name to be associated with resource.
1774 * Mark all PCI regions associated with PCI device @pdev as
1775 * being reserved by owner @res_name. Do not access any
1776 * address inside the PCI regions unless this call returns
1779 * pci_request_regions_exclusive() will mark the region so that
1780 * /dev/mem and the sysfs MMIO access will not be allowed.
1782 * Returns 0 on success, or %EBUSY on error. A warning
1783 * message is also printed on failure.
1785 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
1787 return pci_request_selected_regions_exclusive(pdev
,
1788 ((1 << 6) - 1), res_name
);
1791 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
1795 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
1797 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
1799 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
1800 if (cmd
!= old_cmd
) {
1801 dev_dbg(&dev
->dev
, "%s bus mastering\n",
1802 enable
? "enabling" : "disabling");
1803 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1805 dev
->is_busmaster
= enable
;
1809 * pci_set_master - enables bus-mastering for device dev
1810 * @dev: the PCI device to enable
1812 * Enables bus-mastering on the device and calls pcibios_set_master()
1813 * to do the needed arch specific settings.
1815 void pci_set_master(struct pci_dev
*dev
)
1817 __pci_set_master(dev
, true);
1818 pcibios_set_master(dev
);
1822 * pci_clear_master - disables bus-mastering for device dev
1823 * @dev: the PCI device to disable
1825 void pci_clear_master(struct pci_dev
*dev
)
1827 __pci_set_master(dev
, false);
1830 #ifdef PCI_DISABLE_MWI
1831 int pci_set_mwi(struct pci_dev
*dev
)
1836 int pci_try_set_mwi(struct pci_dev
*dev
)
1841 void pci_clear_mwi(struct pci_dev
*dev
)
1847 #ifndef PCI_CACHE_LINE_BYTES
1848 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1851 /* This can be overridden by arch code. */
1852 /* Don't forget this is measured in 32-bit words, not bytes */
1853 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1856 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1857 * @dev: the PCI device for which MWI is to be enabled
1859 * Helper function for pci_set_mwi.
1860 * Originally copied from drivers/net/acenic.c.
1861 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1863 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1866 pci_set_cacheline_size(struct pci_dev
*dev
)
1870 if (!pci_cache_line_size
)
1871 return -EINVAL
; /* The system doesn't support MWI. */
1873 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1874 equal to or multiple of the right value. */
1875 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1876 if (cacheline_size
>= pci_cache_line_size
&&
1877 (cacheline_size
% pci_cache_line_size
) == 0)
1880 /* Write the correct value. */
1881 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1883 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1884 if (cacheline_size
== pci_cache_line_size
)
1887 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1888 "supported\n", pci_cache_line_size
<< 2);
1894 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1895 * @dev: the PCI device for which MWI is enabled
1897 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1899 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1902 pci_set_mwi(struct pci_dev
*dev
)
1907 rc
= pci_set_cacheline_size(dev
);
1911 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1912 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1913 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1914 cmd
|= PCI_COMMAND_INVALIDATE
;
1915 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1922 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1923 * @dev: the PCI device for which MWI is enabled
1925 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1926 * Callers are not required to check the return value.
1928 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1930 int pci_try_set_mwi(struct pci_dev
*dev
)
1932 int rc
= pci_set_mwi(dev
);
1937 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1938 * @dev: the PCI device to disable
1940 * Disables PCI Memory-Write-Invalidate transaction on the device
1943 pci_clear_mwi(struct pci_dev
*dev
)
1947 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1948 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1949 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1950 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1953 #endif /* ! PCI_DISABLE_MWI */
1956 * pci_intx - enables/disables PCI INTx for device dev
1957 * @pdev: the PCI device to operate on
1958 * @enable: boolean: whether to enable or disable PCI INTx
1960 * Enables/disables PCI INTx for device dev
1963 pci_intx(struct pci_dev
*pdev
, int enable
)
1965 u16 pci_command
, new;
1967 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1970 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1972 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1975 if (new != pci_command
) {
1976 struct pci_devres
*dr
;
1978 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1980 dr
= find_pci_dr(pdev
);
1981 if (dr
&& !dr
->restore_intx
) {
1982 dr
->restore_intx
= 1;
1983 dr
->orig_intx
= !enable
;
1989 * pci_msi_off - disables any msi or msix capabilities
1990 * @dev: the PCI device to operate on
1992 * If you want to use msi see pci_enable_msi and friends.
1993 * This is a lower level primitive that allows us to disable
1994 * msi operation at the device level.
1996 void pci_msi_off(struct pci_dev
*dev
)
2001 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
2003 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
2004 control
&= ~PCI_MSI_FLAGS_ENABLE
;
2005 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
2007 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
2009 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
2010 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
2011 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
2015 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2017 * These can be overridden by arch-specific implementations
2020 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
2022 if (!pci_dma_supported(dev
, mask
))
2025 dev
->dma_mask
= mask
;
2031 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
2033 if (!pci_dma_supported(dev
, mask
))
2036 dev
->dev
.coherent_dma_mask
= mask
;
2042 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2043 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
2045 return dma_set_max_seg_size(&dev
->dev
, size
);
2047 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
2050 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2051 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
2053 return dma_set_seg_boundary(&dev
->dev
, mask
);
2055 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
2058 static int __pcie_flr(struct pci_dev
*dev
, int probe
)
2062 int exppos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2066 pci_read_config_dword(dev
, exppos
+ PCI_EXP_DEVCAP
, &cap
);
2067 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
2073 pci_block_user_cfg_access(dev
);
2075 /* Wait for Transaction Pending bit clean */
2076 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2077 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2078 goto transaction_done
;
2081 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2082 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2083 goto transaction_done
;
2085 dev_info(&dev
->dev
, "Busy after 100ms while trying to reset; "
2086 "sleeping for 1 second\n");
2088 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2089 if (status
& PCI_EXP_DEVSTA_TRPND
)
2090 dev_info(&dev
->dev
, "Still busy after 1s; "
2091 "proceeding with reset anyway\n");
2094 pci_write_config_word(dev
, exppos
+ PCI_EXP_DEVCTL
,
2095 PCI_EXP_DEVCTL_BCR_FLR
);
2098 pci_unblock_user_cfg_access(dev
);
2102 static int __pci_af_flr(struct pci_dev
*dev
, int probe
)
2104 int cappos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
2110 pci_read_config_byte(dev
, cappos
+ PCI_AF_CAP
, &cap
);
2111 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
2117 pci_block_user_cfg_access(dev
);
2119 /* Wait for Transaction Pending bit clean */
2120 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2121 if (!(status
& PCI_AF_STATUS_TP
))
2122 goto transaction_done
;
2125 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2126 if (!(status
& PCI_AF_STATUS_TP
))
2127 goto transaction_done
;
2129 dev_info(&dev
->dev
, "Busy after 100ms while trying to"
2130 " reset; sleeping for 1 second\n");
2132 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2133 if (status
& PCI_AF_STATUS_TP
)
2134 dev_info(&dev
->dev
, "Still busy after 1s; "
2135 "proceeding with reset anyway\n");
2138 pci_write_config_byte(dev
, cappos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
2141 pci_unblock_user_cfg_access(dev
);
2145 static int __pci_reset_function(struct pci_dev
*pdev
, int probe
)
2149 res
= __pcie_flr(pdev
, probe
);
2153 res
= __pci_af_flr(pdev
, probe
);
2161 * pci_execute_reset_function() - Reset a PCI device function
2162 * @dev: Device function to reset
2164 * Some devices allow an individual function to be reset without affecting
2165 * other functions in the same device. The PCI device must be responsive
2166 * to PCI config space in order to use this function.
2168 * The device function is presumed to be unused when this function is called.
2169 * Resetting the device will make the contents of PCI configuration space
2170 * random, so any caller of this must be prepared to reinitialise the
2171 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2174 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2175 * device doesn't support resetting a single function.
2177 int pci_execute_reset_function(struct pci_dev
*dev
)
2179 return __pci_reset_function(dev
, 0);
2181 EXPORT_SYMBOL_GPL(pci_execute_reset_function
);
2184 * pci_reset_function() - quiesce and reset a PCI device function
2185 * @dev: Device function to reset
2187 * Some devices allow an individual function to be reset without affecting
2188 * other functions in the same device. The PCI device must be responsive
2189 * to PCI config space in order to use this function.
2191 * This function does not just reset the PCI portion of a device, but
2192 * clears all the state associated with the device. This function differs
2193 * from pci_execute_reset_function in that it saves and restores device state
2196 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2197 * device doesn't support resetting a single function.
2199 int pci_reset_function(struct pci_dev
*dev
)
2201 int r
= __pci_reset_function(dev
, 1);
2206 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2207 disable_irq(dev
->irq
);
2208 pci_save_state(dev
);
2210 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2212 r
= pci_execute_reset_function(dev
);
2214 pci_restore_state(dev
);
2215 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2216 enable_irq(dev
->irq
);
2220 EXPORT_SYMBOL_GPL(pci_reset_function
);
2223 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2224 * @dev: PCI device to query
2226 * Returns mmrbc: maximum designed memory read count in bytes
2227 * or appropriate error value.
2229 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2234 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2238 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2242 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
2244 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2247 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2248 * @dev: PCI device to query
2250 * Returns mmrbc: maximum memory read count in bytes
2251 * or appropriate error value.
2253 int pcix_get_mmrbc(struct pci_dev
*dev
)
2258 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2262 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2264 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2268 EXPORT_SYMBOL(pcix_get_mmrbc
);
2271 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2272 * @dev: PCI device to query
2273 * @mmrbc: maximum memory read count in bytes
2274 * valid values are 512, 1024, 2048, 4096
2276 * If possible sets maximum memory read byte count, some bridges have erratas
2277 * that prevent this.
2279 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2281 int cap
, err
= -EINVAL
;
2282 u32 stat
, cmd
, v
, o
;
2284 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2287 v
= ffs(mmrbc
) - 10;
2289 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2293 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2297 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2300 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2304 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2306 if (v
> o
&& dev
->bus
&&
2307 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2310 cmd
&= ~PCI_X_CMD_MAX_READ
;
2312 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
2317 EXPORT_SYMBOL(pcix_set_mmrbc
);
2320 * pcie_get_readrq - get PCI Express read request size
2321 * @dev: PCI device to query
2323 * Returns maximum memory read request in bytes
2324 * or appropriate error value.
2326 int pcie_get_readrq(struct pci_dev
*dev
)
2331 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2335 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2337 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2341 EXPORT_SYMBOL(pcie_get_readrq
);
2344 * pcie_set_readrq - set PCI Express maximum memory read request
2345 * @dev: PCI device to query
2346 * @rq: maximum memory read count in bytes
2347 * valid values are 128, 256, 512, 1024, 2048, 4096
2349 * If possible sets maximum read byte count
2351 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2353 int cap
, err
= -EINVAL
;
2356 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2359 v
= (ffs(rq
) - 8) << 12;
2361 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2365 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2369 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2370 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2372 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2378 EXPORT_SYMBOL(pcie_set_readrq
);
2381 * pci_select_bars - Make BAR mask from the type of resource
2382 * @dev: the PCI device for which BAR mask is made
2383 * @flags: resource type mask to be selected
2385 * This helper routine makes bar mask from the type of resource.
2387 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2390 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2391 if (pci_resource_flags(dev
, i
) & flags
)
2397 * pci_resource_bar - get position of the BAR associated with a resource
2398 * @dev: the PCI device
2399 * @resno: the resource number
2400 * @type: the BAR type to be filled in
2402 * Returns BAR position in config space, or 0 if the BAR is invalid.
2404 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
2408 if (resno
< PCI_ROM_RESOURCE
) {
2409 *type
= pci_bar_unknown
;
2410 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
2411 } else if (resno
== PCI_ROM_RESOURCE
) {
2412 *type
= pci_bar_mem32
;
2413 return dev
->rom_base_reg
;
2414 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
2415 /* device specific resource */
2416 reg
= pci_iov_resource_bar(dev
, resno
, type
);
2421 dev_err(&dev
->dev
, "BAR: invalid resource #%d\n", resno
);
2425 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2426 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
2427 spinlock_t resource_alignment_lock
= SPIN_LOCK_UNLOCKED
;
2430 * pci_specified_resource_alignment - get resource alignment specified by user.
2431 * @dev: the PCI device to get
2433 * RETURNS: Resource alignment if it is specified.
2434 * Zero if it is not specified.
2436 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
2438 int seg
, bus
, slot
, func
, align_order
, count
;
2439 resource_size_t align
= 0;
2442 spin_lock(&resource_alignment_lock
);
2443 p
= resource_alignment_param
;
2446 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
2452 if (sscanf(p
, "%x:%x:%x.%x%n",
2453 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
2455 if (sscanf(p
, "%x:%x.%x%n",
2456 &bus
, &slot
, &func
, &count
) != 3) {
2457 /* Invalid format */
2458 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
2464 if (seg
== pci_domain_nr(dev
->bus
) &&
2465 bus
== dev
->bus
->number
&&
2466 slot
== PCI_SLOT(dev
->devfn
) &&
2467 func
== PCI_FUNC(dev
->devfn
)) {
2468 if (align_order
== -1) {
2471 align
= 1 << align_order
;
2476 if (*p
!= ';' && *p
!= ',') {
2477 /* End of param or invalid format */
2482 spin_unlock(&resource_alignment_lock
);
2487 * pci_is_reassigndev - check if specified PCI is target device to reassign
2488 * @dev: the PCI device to check
2490 * RETURNS: non-zero for PCI device is a target device to reassign,
2493 int pci_is_reassigndev(struct pci_dev
*dev
)
2495 return (pci_specified_resource_alignment(dev
) != 0);
2498 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
2500 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
2501 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
2502 spin_lock(&resource_alignment_lock
);
2503 strncpy(resource_alignment_param
, buf
, count
);
2504 resource_alignment_param
[count
] = '\0';
2505 spin_unlock(&resource_alignment_lock
);
2509 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
2512 spin_lock(&resource_alignment_lock
);
2513 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
2514 spin_unlock(&resource_alignment_lock
);
2518 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
2520 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
2523 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
2524 const char *buf
, size_t count
)
2526 return pci_set_resource_alignment_param(buf
, count
);
2529 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
2530 pci_resource_alignment_store
);
2532 static int __init
pci_resource_alignment_sysfs_init(void)
2534 return bus_create_file(&pci_bus_type
,
2535 &bus_attr_resource_alignment
);
2538 late_initcall(pci_resource_alignment_sysfs_init
);
2540 static void __devinit
pci_no_domains(void)
2542 #ifdef CONFIG_PCI_DOMAINS
2543 pci_domains_supported
= 0;
2548 * pci_ext_cfg_enabled - can we access extended PCI config space?
2549 * @dev: The PCI device of the root bridge.
2551 * Returns 1 if we can access PCI extended config space (offsets
2552 * greater than 0xff). This is the default implementation. Architecture
2553 * implementations can override this.
2555 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
2560 static int __devinit
pci_init(void)
2562 struct pci_dev
*dev
= NULL
;
2564 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2565 pci_fixup_device(pci_fixup_final
, dev
);
2571 static int __init
pci_setup(char *str
)
2574 char *k
= strchr(str
, ',');
2577 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
2578 if (!strcmp(str
, "nomsi")) {
2580 } else if (!strcmp(str
, "noaer")) {
2582 } else if (!strcmp(str
, "nodomains")) {
2584 } else if (!strncmp(str
, "cbiosize=", 9)) {
2585 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
2586 } else if (!strncmp(str
, "cbmemsize=", 10)) {
2587 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
2588 } else if (!strncmp(str
, "resource_alignment=", 19)) {
2589 pci_set_resource_alignment_param(str
+ 19,
2591 } else if (!strncmp(str
, "ecrc=", 5)) {
2592 pcie_ecrc_get_policy(str
+ 5);
2594 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
2602 early_param("pci", pci_setup
);
2604 device_initcall(pci_init
);
2606 EXPORT_SYMBOL(pci_reenable_device
);
2607 EXPORT_SYMBOL(pci_enable_device_io
);
2608 EXPORT_SYMBOL(pci_enable_device_mem
);
2609 EXPORT_SYMBOL(pci_enable_device
);
2610 EXPORT_SYMBOL(pcim_enable_device
);
2611 EXPORT_SYMBOL(pcim_pin_device
);
2612 EXPORT_SYMBOL(pci_disable_device
);
2613 EXPORT_SYMBOL(pci_find_capability
);
2614 EXPORT_SYMBOL(pci_bus_find_capability
);
2615 EXPORT_SYMBOL(pci_release_regions
);
2616 EXPORT_SYMBOL(pci_request_regions
);
2617 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2618 EXPORT_SYMBOL(pci_release_region
);
2619 EXPORT_SYMBOL(pci_request_region
);
2620 EXPORT_SYMBOL(pci_request_region_exclusive
);
2621 EXPORT_SYMBOL(pci_release_selected_regions
);
2622 EXPORT_SYMBOL(pci_request_selected_regions
);
2623 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2624 EXPORT_SYMBOL(pci_set_master
);
2625 EXPORT_SYMBOL(pci_clear_master
);
2626 EXPORT_SYMBOL(pci_set_mwi
);
2627 EXPORT_SYMBOL(pci_try_set_mwi
);
2628 EXPORT_SYMBOL(pci_clear_mwi
);
2629 EXPORT_SYMBOL_GPL(pci_intx
);
2630 EXPORT_SYMBOL(pci_set_dma_mask
);
2631 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
2632 EXPORT_SYMBOL(pci_assign_resource
);
2633 EXPORT_SYMBOL(pci_find_parent_resource
);
2634 EXPORT_SYMBOL(pci_select_bars
);
2636 EXPORT_SYMBOL(pci_set_power_state
);
2637 EXPORT_SYMBOL(pci_save_state
);
2638 EXPORT_SYMBOL(pci_restore_state
);
2639 EXPORT_SYMBOL(pci_pme_capable
);
2640 EXPORT_SYMBOL(pci_pme_active
);
2641 EXPORT_SYMBOL(pci_enable_wake
);
2642 EXPORT_SYMBOL(pci_wake_from_d3
);
2643 EXPORT_SYMBOL(pci_target_state
);
2644 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2645 EXPORT_SYMBOL(pci_back_from_sleep
);
2646 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);