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net: Fix recursive descent in __scm_destroy().
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / agp / amd64-agp.c
blob7495c522d8e477ac3aa0431c95fead255e7879ac
1 /*
2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
4 *
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
9 */
10
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/agp_backend.h>
15 #include <linux/mmzone.h>
16 #include <asm/page.h> /* PAGE_SIZE */
17 #include <asm/e820.h>
18 #include <asm/k8.h>
19 #include <asm/gart.h>
20 #include "agp.h"
21
22 /* NVIDIA K8 registers */
23 #define NVIDIA_X86_64_0_APBASE 0x10
24 #define NVIDIA_X86_64_1_APBASE1 0x50
25 #define NVIDIA_X86_64_1_APLIMIT1 0x54
26 #define NVIDIA_X86_64_1_APSIZE 0xa8
27 #define NVIDIA_X86_64_1_APBASE2 0xd8
28 #define NVIDIA_X86_64_1_APLIMIT2 0xdc
29
30 /* ULi K8 registers */
31 #define ULI_X86_64_BASE_ADDR 0x10
32 #define ULI_X86_64_HTT_FEA_REG 0x50
33 #define ULI_X86_64_ENU_SCR_REG 0x54
34
35 static struct resource *aperture_resource;
36 static int __initdata agp_try_unsupported = 1;
37 static int agp_bridges_found;
38
39 static void amd64_tlbflush(struct agp_memory *temp)
40 {
41 k8_flush_garts();
42 }
43
44 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
45 {
46 int i, j, num_entries;
47 long long tmp;
48 int mask_type;
49 struct agp_bridge_data *bridge = mem->bridge;
50 u32 pte;
51
52 num_entries = agp_num_entries();
53
54 if (type != mem->type)
55 return -EINVAL;
56 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
57 if (mask_type != 0)
58 return -EINVAL;
59
60
61 /* Make sure we can fit the range in the gatt table. */
62 /* FIXME: could wrap */
63 if (((unsigned long)pg_start + mem->page_count) > num_entries)
64 return -EINVAL;
65
66 j = pg_start;
67
68 /* gatt table should be empty. */
69 while (j < (pg_start + mem->page_count)) {
70 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
71 return -EBUSY;
72 j++;
73 }
74
75 if (!mem->is_flushed) {
76 global_cache_flush();
77 mem->is_flushed = true;
78 }
79
80 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
81 tmp = agp_bridge->driver->mask_memory(agp_bridge,
82 mem->memory[i], mask_type);
83
84 BUG_ON(tmp & 0xffffff0000000ffcULL);
85 pte = (tmp & 0x000000ff00000000ULL) >> 28;
86 pte |=(tmp & 0x00000000fffff000ULL);
87 pte |= GPTE_VALID | GPTE_COHERENT;
88
89 writel(pte, agp_bridge->gatt_table+j);
90 readl(agp_bridge->gatt_table+j); /* PCI Posting. */
91 }
92 amd64_tlbflush(mem);
93 return 0;
94 }
95
96 /*
97 * This hack alters the order element according
98 * to the size of a long. It sucks. I totally disown this, even
99 * though it does appear to work for the most part.
100 */
101 static struct aper_size_info_32 amd64_aperture_sizes[7] =
102 {
103 {32, 8192, 3+(sizeof(long)/8), 0 },
104 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
105 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
106 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
107 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
108 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
109 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
110 };
111
112
113 /*
114 * Get the current Aperture size from the x86-64.
115 * Note, that there may be multiple x86-64's, but we just return
116 * the value from the first one we find. The set_size functions
117 * keep the rest coherent anyway. Or at least should do.
118 */
119 static int amd64_fetch_size(void)
120 {
121 struct pci_dev *dev;
122 int i;
123 u32 temp;
124 struct aper_size_info_32 *values;
125
126 dev = k8_northbridges[0];
127 if (dev==NULL)
128 return 0;
129
130 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
131 temp = (temp & 0xe);
132 values = A_SIZE_32(amd64_aperture_sizes);
133
134 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
135 if (temp == values[i].size_value) {
136 agp_bridge->previous_size =
137 agp_bridge->current_size = (void *) (values + i);
138
139 agp_bridge->aperture_size_idx = i;
140 return values[i].size;
141 }
142 }
143 return 0;
144 }
145
146 /*
147 * In a multiprocessor x86-64 system, this function gets
148 * called once for each CPU.
149 */
150 static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
151 {
152 u64 aperturebase;
153 u32 tmp;
154 u64 aper_base;
155
156 /* Address to map to */
157 pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
158 aperturebase = tmp << 25;
159 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
160
161 enable_gart_translation(hammer, gatt_table);
162
163 return aper_base;
164 }
165
166
167 static const struct aper_size_info_32 amd_8151_sizes[7] =
168 {
169 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
170 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
171 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
172 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
173 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
174 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
175 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
176 };
177
178 static int amd_8151_configure(void)
179 {
180 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real);
181 int i;
182
183 /* Configure AGP regs in each x86-64 host bridge. */
184 for (i = 0; i < num_k8_northbridges; i++) {
185 agp_bridge->gart_bus_addr =
186 amd64_configure(k8_northbridges[i], gatt_bus);
187 }
188 k8_flush_garts();
189 return 0;
190 }
191
192
193 static void amd64_cleanup(void)
194 {
195 u32 tmp;
196 int i;
197 for (i = 0; i < num_k8_northbridges; i++) {
198 struct pci_dev *dev = k8_northbridges[i];
199 /* disable gart translation */
200 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
201 tmp &= ~AMD64_GARTEN;
202 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
203 }
204 }
205
206
207 static const struct agp_bridge_driver amd_8151_driver = {
208 .owner = THIS_MODULE,
209 .aperture_sizes = amd_8151_sizes,
210 .size_type = U32_APER_SIZE,
211 .num_aperture_sizes = 7,
212 .configure = amd_8151_configure,
213 .fetch_size = amd64_fetch_size,
214 .cleanup = amd64_cleanup,
215 .tlb_flush = amd64_tlbflush,
216 .mask_memory = agp_generic_mask_memory,
217 .masks = NULL,
218 .agp_enable = agp_generic_enable,
219 .cache_flush = global_cache_flush,
220 .create_gatt_table = agp_generic_create_gatt_table,
221 .free_gatt_table = agp_generic_free_gatt_table,
222 .insert_memory = amd64_insert_memory,
223 .remove_memory = agp_generic_remove_memory,
224 .alloc_by_type = agp_generic_alloc_by_type,
225 .free_by_type = agp_generic_free_by_type,
226 .agp_alloc_page = agp_generic_alloc_page,
227 .agp_destroy_page = agp_generic_destroy_page,
228 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
229 };
230
231 /* Some basic sanity checks for the aperture. */
232 static int __devinit agp_aperture_valid(u64 aper, u32 size)
233 {
234 if (!aperture_valid(aper, size, 32*1024*1024))
235 return 0;
236
237 /* Request the Aperture. This catches cases when someone else
238 already put a mapping in there - happens with some very broken BIOS
239
240 Maybe better to use pci_assign_resource/pci_enable_device instead
241 trusting the bridges? */
242 if (!aperture_resource &&
243 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
244 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
245 return 0;
246 }
247 return 1;
248 }
249
250 /*
251 * W*s centric BIOS sometimes only set up the aperture in the AGP
252 * bridge, not the northbridge. On AMD64 this is handled early
253 * in aperture.c, but when IOMMU is not enabled or we run
254 * on a 32bit kernel this needs to be redone.
255 * Unfortunately it is impossible to fix the aperture here because it's too late
256 * to allocate that much memory. But at least error out cleanly instead of
257 * crashing.
258 */
259 static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
260 u16 cap)
261 {
262 u32 aper_low, aper_hi;
263 u64 aper, nb_aper;
264 int order = 0;
265 u32 nb_order, nb_base;
266 u16 apsize;
267
268 pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
269 nb_order = (nb_order >> 1) & 7;
270 pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
271 nb_aper = nb_base << 25;
272 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
273 return 0;
274 }
275
276 /* Northbridge seems to contain crap. Try the AGP bridge. */
277
278 pci_read_config_word(agp, cap+0x14, &apsize);
279 if (apsize == 0xffff)
280 return -1;
281
282 apsize &= 0xfff;
283 /* Some BIOS use weird encodings not in the AGPv3 table. */
284 if (apsize & 0xff)
285 apsize |= 0xf00;
286 order = 7 - hweight16(apsize);
287
288 pci_read_config_dword(agp, 0x10, &aper_low);
289 pci_read_config_dword(agp, 0x14, &aper_hi);
290 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
291
292 /*
293 * On some sick chips APSIZE is 0. This means it wants 4G
294 * so let double check that order, and lets trust the AMD NB settings
295 */
296 if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
297 dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n",
298 32 << order);
299 order = nb_order;
300 }
301
302 dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n",
303 aper, 32 << order);
304 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
305 return -1;
306
307 pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
308 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
309
310 return 0;
311 }
312
313 static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
314 {
315 int i;
316
317 if (cache_k8_northbridges() < 0)
318 return -ENODEV;
319
320 i = 0;
321 for (i = 0; i < num_k8_northbridges; i++) {
322 struct pci_dev *dev = k8_northbridges[i];
323 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
324 dev_err(&dev->dev, "no usable aperture found\n");
325 #ifdef __x86_64__
326 /* should port this to i386 */
327 dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n");
328 #endif
329 return -1;
330 }
331 }
332 return 0;
333 }
334
335 /* Handle AMD 8151 quirks */
336 static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
337 {
338 char *revstring;
339
340 switch (pdev->revision) {
341 case 0x01: revstring="A0"; break;
342 case 0x02: revstring="A1"; break;
343 case 0x11: revstring="B0"; break;
344 case 0x12: revstring="B1"; break;
345 case 0x13: revstring="B2"; break;
346 case 0x14: revstring="B3"; break;
347 default: revstring="??"; break;
348 }
349
350 dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring);
351
352 /*
353 * Work around errata.
354 * Chips before B2 stepping incorrectly reporting v3.5
355 */
356 if (pdev->revision < 0x13) {
357 dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n");
358 bridge->major_version = 3;
359 bridge->minor_version = 0;
360 }
361 }
362
363
364 static const struct aper_size_info_32 uli_sizes[7] =
365 {
366 {256, 65536, 6, 10},
367 {128, 32768, 5, 9},
368 {64, 16384, 4, 8},
369 {32, 8192, 3, 7},
370 {16, 4096, 2, 6},
371 {8, 2048, 1, 4},
372 {4, 1024, 0, 3}
373 };
374 static int __devinit uli_agp_init(struct pci_dev *pdev)
375 {
376 u32 httfea,baseaddr,enuscr;
377 struct pci_dev *dev1;
378 int i;
379 unsigned size = amd64_fetch_size();
380
381 dev_info(&pdev->dev, "setting up ULi AGP\n");
382 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
383 if (dev1 == NULL) {
384 dev_info(&pdev->dev, "can't find ULi secondary device\n");
385 return -ENODEV;
386 }
387
388 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
389 if (uli_sizes[i].size == size)
390 break;
391
392 if (i == ARRAY_SIZE(uli_sizes)) {
393 dev_info(&pdev->dev, "no ULi size found for %d\n", size);
394 return -ENODEV;
395 }
396
397 /* shadow x86-64 registers into ULi registers */
398 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
399
400 /* if x86-64 aperture base is beyond 4G, exit here */
401 if ((httfea & 0x7fff) >> (32 - 25))
402 return -ENODEV;
403
404 httfea = (httfea& 0x7fff) << 25;
405
406 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
407 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
408 baseaddr|= httfea;
409 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
410
411 enuscr= httfea+ (size * 1024 * 1024) - 1;
412 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
413 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
414
415 pci_dev_put(dev1);
416 return 0;
417 }
418
419
420 static const struct aper_size_info_32 nforce3_sizes[5] =
421 {
422 {512, 131072, 7, 0x00000000 },
423 {256, 65536, 6, 0x00000008 },
424 {128, 32768, 5, 0x0000000C },
425 {64, 16384, 4, 0x0000000E },
426 {32, 8192, 3, 0x0000000F }
427 };
428
429 /* Handle shadow device of the Nvidia NForce3 */
430 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
431 static int nforce3_agp_init(struct pci_dev *pdev)
432 {
433 u32 tmp, apbase, apbar, aplimit;
434 struct pci_dev *dev1;
435 int i;
436 unsigned size = amd64_fetch_size();
437
438 dev_info(&pdev->dev, "setting up Nforce3 AGP\n");
439
440 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
441 if (dev1 == NULL) {
442 dev_info(&pdev->dev, "can't find Nforce3 secondary device\n");
443 return -ENODEV;
444 }
445
446 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
447 if (nforce3_sizes[i].size == size)
448 break;
449
450 if (i == ARRAY_SIZE(nforce3_sizes)) {
451 dev_info(&pdev->dev, "no NForce3 size found for %d\n", size);
452 return -ENODEV;
453 }
454
455 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
456 tmp &= ~(0xf);
457 tmp |= nforce3_sizes[i].size_value;
458 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
459
460 /* shadow x86-64 registers into NVIDIA registers */
461 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
462
463 /* if x86-64 aperture base is beyond 4G, exit here */
464 if ( (apbase & 0x7fff) >> (32 - 25) ) {
465 dev_info(&pdev->dev, "aperture base > 4G\n");
466 return -ENODEV;
467 }
468
469 apbase = (apbase & 0x7fff) << 25;
470
471 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
472 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
473 apbar |= apbase;
474 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
475
476 aplimit = apbase + (size * 1024 * 1024) - 1;
477 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
478 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
479 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
480 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
481
482 pci_dev_put(dev1);
483
484 return 0;
485 }
486
487 static int __devinit agp_amd64_probe(struct pci_dev *pdev,
488 const struct pci_device_id *ent)
489 {
490 struct agp_bridge_data *bridge;
491 u8 cap_ptr;
492 int err;
493
494 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
495 if (!cap_ptr)
496 return -ENODEV;
497
498 /* Could check for AGPv3 here */
499
500 bridge = agp_alloc_bridge();
501 if (!bridge)
502 return -ENOMEM;
503
504 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
505 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
506 amd8151_init(pdev, bridge);
507 } else {
508 dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n",
509 pdev->vendor, pdev->device);
510 }
511
512 bridge->driver = &amd_8151_driver;
513 bridge->dev = pdev;
514 bridge->capndx = cap_ptr;
515
516 /* Fill in the mode register */
517 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
518
519 if (cache_nbs(pdev, cap_ptr) == -1) {
520 agp_put_bridge(bridge);
521 return -ENODEV;
522 }
523
524 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
525 int ret = nforce3_agp_init(pdev);
526 if (ret) {
527 agp_put_bridge(bridge);
528 return ret;
529 }
530 }
531
532 if (pdev->vendor == PCI_VENDOR_ID_AL) {
533 int ret = uli_agp_init(pdev);
534 if (ret) {
535 agp_put_bridge(bridge);
536 return ret;
537 }
538 }
539
540 pci_set_drvdata(pdev, bridge);
541 err = agp_add_bridge(bridge);
542 if (err < 0)
543 return err;
544
545 agp_bridges_found++;
546 return 0;
547 }
548
549 static void __devexit agp_amd64_remove(struct pci_dev *pdev)
550 {
551 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
552
553 release_mem_region(virt_to_gart(bridge->gatt_table_real),
554 amd64_aperture_sizes[bridge->aperture_size_idx].size);
555 agp_remove_bridge(bridge);
556 agp_put_bridge(bridge);
557 }
558
559 #ifdef CONFIG_PM
560
561 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
562 {
563 pci_save_state(pdev);
564 pci_set_power_state(pdev, pci_choose_state(pdev, state));
565
566 return 0;
567 }
568
569 static int agp_amd64_resume(struct pci_dev *pdev)
570 {
571 pci_set_power_state(pdev, PCI_D0);
572 pci_restore_state(pdev);
573
574 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
575 nforce3_agp_init(pdev);
576
577 return amd_8151_configure();
578 }
579
580 #endif /* CONFIG_PM */
581
582 static struct pci_device_id agp_amd64_pci_table[] = {
583 {
584 .class = (PCI_CLASS_BRIDGE_HOST << 8),
585 .class_mask = ~0,
586 .vendor = PCI_VENDOR_ID_AMD,
587 .device = PCI_DEVICE_ID_AMD_8151_0,
588 .subvendor = PCI_ANY_ID,
589 .subdevice = PCI_ANY_ID,
590 },
591 /* ULi M1689 */
592 {
593 .class = (PCI_CLASS_BRIDGE_HOST << 8),
594 .class_mask = ~0,
595 .vendor = PCI_VENDOR_ID_AL,
596 .device = PCI_DEVICE_ID_AL_M1689,
597 .subvendor = PCI_ANY_ID,
598 .subdevice = PCI_ANY_ID,
599 },
600 /* VIA K8T800Pro */
601 {
602 .class = (PCI_CLASS_BRIDGE_HOST << 8),
603 .class_mask = ~0,
604 .vendor = PCI_VENDOR_ID_VIA,
605 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
606 .subvendor = PCI_ANY_ID,
607 .subdevice = PCI_ANY_ID,
608 },
609 /* VIA K8T800 */
610 {
611 .class = (PCI_CLASS_BRIDGE_HOST << 8),
612 .class_mask = ~0,
613 .vendor = PCI_VENDOR_ID_VIA,
614 .device = PCI_DEVICE_ID_VIA_8385_0,
615 .subvendor = PCI_ANY_ID,
616 .subdevice = PCI_ANY_ID,
617 },
618 /* VIA K8M800 / K8N800 */
619 {
620 .class = (PCI_CLASS_BRIDGE_HOST << 8),
621 .class_mask = ~0,
622 .vendor = PCI_VENDOR_ID_VIA,
623 .device = PCI_DEVICE_ID_VIA_8380_0,
624 .subvendor = PCI_ANY_ID,
625 .subdevice = PCI_ANY_ID,
626 },
627 /* VIA K8M890 / K8N890 */
628 {
629 .class = (PCI_CLASS_BRIDGE_HOST << 8),
630 .class_mask = ~0,
631 .vendor = PCI_VENDOR_ID_VIA,
632 .device = PCI_DEVICE_ID_VIA_VT3336,
633 .subvendor = PCI_ANY_ID,
634 .subdevice = PCI_ANY_ID,
635 },
636 /* VIA K8T890 */
637 {
638 .class = (PCI_CLASS_BRIDGE_HOST << 8),
639 .class_mask = ~0,
640 .vendor = PCI_VENDOR_ID_VIA,
641 .device = PCI_DEVICE_ID_VIA_3238_0,
642 .subvendor = PCI_ANY_ID,
643 .subdevice = PCI_ANY_ID,
644 },
645 /* VIA K8T800/K8M800/K8N800 */
646 {
647 .class = (PCI_CLASS_BRIDGE_HOST << 8),
648 .class_mask = ~0,
649 .vendor = PCI_VENDOR_ID_VIA,
650 .device = PCI_DEVICE_ID_VIA_838X_1,
651 .subvendor = PCI_ANY_ID,
652 .subdevice = PCI_ANY_ID,
653 },
654 /* NForce3 */
655 {
656 .class = (PCI_CLASS_BRIDGE_HOST << 8),
657 .class_mask = ~0,
658 .vendor = PCI_VENDOR_ID_NVIDIA,
659 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
660 .subvendor = PCI_ANY_ID,
661 .subdevice = PCI_ANY_ID,
662 },
663 {
664 .class = (PCI_CLASS_BRIDGE_HOST << 8),
665 .class_mask = ~0,
666 .vendor = PCI_VENDOR_ID_NVIDIA,
667 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
668 .subvendor = PCI_ANY_ID,
669 .subdevice = PCI_ANY_ID,
670 },
671 /* SIS 755 */
672 {
673 .class = (PCI_CLASS_BRIDGE_HOST << 8),
674 .class_mask = ~0,
675 .vendor = PCI_VENDOR_ID_SI,
676 .device = PCI_DEVICE_ID_SI_755,
677 .subvendor = PCI_ANY_ID,
678 .subdevice = PCI_ANY_ID,
679 },
680 /* SIS 760 */
681 {
682 .class = (PCI_CLASS_BRIDGE_HOST << 8),
683 .class_mask = ~0,
684 .vendor = PCI_VENDOR_ID_SI,
685 .device = PCI_DEVICE_ID_SI_760,
686 .subvendor = PCI_ANY_ID,
687 .subdevice = PCI_ANY_ID,
688 },
689 /* ALI/ULI M1695 */
690 {
691 .class = (PCI_CLASS_BRIDGE_HOST << 8),
692 .class_mask = ~0,
693 .vendor = PCI_VENDOR_ID_AL,
694 .device = 0x1695,
695 .subvendor = PCI_ANY_ID,
696 .subdevice = PCI_ANY_ID,
697 },
698
699 { }
700 };
701
702 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
703
704 static struct pci_driver agp_amd64_pci_driver = {
705 .name = "agpgart-amd64",
706 .id_table = agp_amd64_pci_table,
707 .probe = agp_amd64_probe,
708 .remove = agp_amd64_remove,
709 #ifdef CONFIG_PM
710 .suspend = agp_amd64_suspend,
711 .resume = agp_amd64_resume,
712 #endif
713 };
714
715
716 /* Not static due to IOMMU code calling it early. */
717 int __init agp_amd64_init(void)
718 {
719 int err = 0;
720
721 if (agp_off)
722 return -EINVAL;
723 err = pci_register_driver(&agp_amd64_pci_driver);
724 if (err < 0)
725 return err;
726
727 if (agp_bridges_found == 0) {
728 struct pci_dev *dev;
729 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
730 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
731 #ifdef MODULE
732 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
733 #else
734 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
735 #endif
736 return -ENODEV;
737 }
738
739 /* First check that we have at least one AMD64 NB */
740 if (!pci_dev_present(k8_nb_ids))
741 return -ENODEV;
742
743 /* Look for any AGP bridge */
744 dev = NULL;
745 err = -ENODEV;
746 for_each_pci_dev(dev) {
747 if (!pci_find_capability(dev, PCI_CAP_ID_AGP))
748 continue;
749 /* Only one bridge supported right now */
750 if (agp_amd64_probe(dev, NULL) == 0) {
751 err = 0;
752 break;
753 }
754 }
755 }
756 return err;
757 }
758
759 static void __exit agp_amd64_cleanup(void)
760 {
761 if (aperture_resource)
762 release_resource(aperture_resource);
763 pci_unregister_driver(&agp_amd64_pci_driver);
764 }
765
766 /* On AMD64 the PCI driver needs to initialize this driver early
767 for the IOMMU, so it has to be called via a backdoor. */
768 #ifndef CONFIG_GART_IOMMU
769 module_init(agp_amd64_init);
770 module_exit(agp_amd64_cleanup);
771 #endif
772
773 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen");
774 module_param(agp_try_unsupported, bool, 0);
775 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree