2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
23 #include <linux/fsl_devices.h>
24 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
28 #define MPC_I2C_ADDR 0x00
29 #define MPC_I2C_FDR 0x04
30 #define MPC_I2C_CR 0x08
31 #define MPC_I2C_SR 0x0c
32 #define MPC_I2C_DR 0x10
33 #define MPC_I2C_DFSRR 0x14
34 #define MPC_I2C_REGION 0x20
54 wait_queue_head_t queue
;
55 struct i2c_adapter adap
;
60 static __inline__
void writeccr(struct mpc_i2c
*i2c
, u32 x
)
62 writeb(x
, i2c
->base
+ MPC_I2C_CR
);
65 static irqreturn_t
mpc_i2c_isr(int irq
, void *dev_id
, struct pt_regs
*regs
)
67 struct mpc_i2c
*i2c
= dev_id
;
68 if (readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MIF
) {
69 /* Read again to allow register to stabilise */
70 i2c
->interrupt
= readb(i2c
->base
+ MPC_I2C_SR
);
71 writeb(0, i2c
->base
+ MPC_I2C_SR
);
72 wake_up_interruptible(&i2c
->queue
);
77 static int i2c_wait(struct mpc_i2c
*i2c
, unsigned timeout
, int writing
)
79 unsigned long orig_jiffies
= jiffies
;
85 while (!(readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MIF
)) {
87 if (time_after(jiffies
, orig_jiffies
+ timeout
)) {
88 pr_debug("I2C: timeout\n");
93 x
= readb(i2c
->base
+ MPC_I2C_SR
);
94 writeb(0, i2c
->base
+ MPC_I2C_SR
);
97 result
= wait_event_interruptible_timeout(i2c
->queue
,
98 (i2c
->interrupt
& CSR_MIF
), timeout
* HZ
);
100 if (unlikely(result
< 0))
101 pr_debug("I2C: wait interrupted\n");
102 else if (unlikely(!(i2c
->interrupt
& CSR_MIF
))) {
103 pr_debug("I2C: wait timeout\n");
114 if (!(x
& CSR_MCF
)) {
115 pr_debug("I2C: unfinished\n");
120 pr_debug("I2C: MAL\n");
124 if (writing
&& (x
& CSR_RXAK
)) {
125 pr_debug("I2C: No RXAK\n");
127 writeccr(i2c
, CCR_MEN
);
133 static void mpc_i2c_setclock(struct mpc_i2c
*i2c
)
135 /* Set clock and filters */
136 if (i2c
->flags
& FSL_I2C_DEV_SEPARATE_DFSRR
) {
137 writeb(0x31, i2c
->base
+ MPC_I2C_FDR
);
138 writeb(0x10, i2c
->base
+ MPC_I2C_DFSRR
);
139 } else if (i2c
->flags
& FSL_I2C_DEV_CLOCK_5200
)
140 writeb(0x3f, i2c
->base
+ MPC_I2C_FDR
);
142 writel(0x1031, i2c
->base
+ MPC_I2C_FDR
);
145 static void mpc_i2c_start(struct mpc_i2c
*i2c
)
147 /* Clear arbitration */
148 writeb(0, i2c
->base
+ MPC_I2C_SR
);
150 writeccr(i2c
, CCR_MEN
);
153 static void mpc_i2c_stop(struct mpc_i2c
*i2c
)
155 writeccr(i2c
, CCR_MEN
);
158 static int mpc_write(struct mpc_i2c
*i2c
, int target
,
159 const u8
* data
, int length
, int restart
)
162 unsigned timeout
= i2c
->adap
.timeout
;
163 u32 flags
= restart
? CCR_RSTA
: 0;
167 writeccr(i2c
, CCR_MEN
);
168 /* Start as master */
169 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_MTX
| flags
);
170 /* Write target byte */
171 writeb((target
<< 1), i2c
->base
+ MPC_I2C_DR
);
173 if (i2c_wait(i2c
, timeout
, 1) < 0)
176 for (i
= 0; i
< length
; i
++) {
177 /* Write data byte */
178 writeb(data
[i
], i2c
->base
+ MPC_I2C_DR
);
180 if (i2c_wait(i2c
, timeout
, 1) < 0)
187 static int mpc_read(struct mpc_i2c
*i2c
, int target
,
188 u8
* data
, int length
, int restart
)
190 unsigned timeout
= i2c
->adap
.timeout
;
192 u32 flags
= restart
? CCR_RSTA
: 0;
196 writeccr(i2c
, CCR_MEN
);
197 /* Switch to read - restart */
198 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_MTX
| flags
);
199 /* Write target address byte - this time with the read flag set */
200 writeb((target
<< 1) | 1, i2c
->base
+ MPC_I2C_DR
);
202 if (i2c_wait(i2c
, timeout
, 1) < 0)
207 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_TXAK
);
209 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
);
211 readb(i2c
->base
+ MPC_I2C_DR
);
214 for (i
= 0; i
< length
; i
++) {
215 if (i2c_wait(i2c
, timeout
, 0) < 0)
218 /* Generate txack on next to last byte */
220 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_TXAK
);
221 /* Generate stop on last byte */
223 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_TXAK
);
224 data
[i
] = readb(i2c
->base
+ MPC_I2C_DR
);
230 static int mpc_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
, int num
)
232 struct i2c_msg
*pmsg
;
235 unsigned long orig_jiffies
= jiffies
;
236 struct mpc_i2c
*i2c
= i2c_get_adapdata(adap
);
240 /* Allow bus up to 1s to become not busy */
241 while (readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MBB
) {
242 if (signal_pending(current
)) {
243 pr_debug("I2C: Interrupted\n");
246 if (time_after(jiffies
, orig_jiffies
+ HZ
)) {
247 pr_debug("I2C: timeout\n");
253 for (i
= 0; ret
>= 0 && i
< num
; i
++) {
255 pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
256 pmsg
->flags
& I2C_M_RD
? "read" : "write",
257 pmsg
->len
, pmsg
->addr
, i
+ 1, num
);
258 if (pmsg
->flags
& I2C_M_RD
)
260 mpc_read(i2c
, pmsg
->addr
, pmsg
->buf
, pmsg
->len
, i
);
263 mpc_write(i2c
, pmsg
->addr
, pmsg
->buf
, pmsg
->len
, i
);
266 return (ret
< 0) ? ret
: num
;
269 static u32
mpc_functionality(struct i2c_adapter
*adap
)
271 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
274 static struct i2c_algorithm mpc_algo
= {
275 .master_xfer
= mpc_xfer
,
276 .functionality
= mpc_functionality
,
279 static struct i2c_adapter mpc_ops
= {
280 .owner
= THIS_MODULE
,
281 .name
= "MPC adapter",
282 .id
= I2C_ALGO_MPC107
| I2C_HW_MPC107
,
284 .class = I2C_CLASS_HWMON
,
289 static int fsl_i2c_probe(struct device
*device
)
293 struct platform_device
*pdev
= to_platform_device(device
);
294 struct fsl_i2c_platform_data
*pdata
;
295 struct resource
*r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
297 pdata
= (struct fsl_i2c_platform_data
*) pdev
->dev
.platform_data
;
299 if (!(i2c
= kmalloc(sizeof(*i2c
), GFP_KERNEL
))) {
302 memset(i2c
, 0, sizeof(*i2c
));
304 i2c
->irq
= platform_get_irq(pdev
, 0);
305 i2c
->flags
= pdata
->device_flags
;
306 init_waitqueue_head(&i2c
->queue
);
308 i2c
->base
= ioremap((phys_addr_t
)r
->start
, MPC_I2C_REGION
);
311 printk(KERN_ERR
"i2c-mpc - failed to map controller\n");
317 if ((result
= request_irq(i2c
->irq
, mpc_i2c_isr
,
318 SA_SHIRQ
, "i2c-mpc", i2c
)) < 0) {
320 "i2c-mpc - failed to attach interrupt\n");
324 mpc_i2c_setclock(i2c
);
325 dev_set_drvdata(device
, i2c
);
328 i2c_set_adapdata(&i2c
->adap
, i2c
);
329 i2c
->adap
.dev
.parent
= &pdev
->dev
;
330 if ((result
= i2c_add_adapter(&i2c
->adap
)) < 0) {
331 printk(KERN_ERR
"i2c-mpc - failed to add adapter\n");
339 free_irq(i2c
->irq
, NULL
);
347 static int fsl_i2c_remove(struct device
*device
)
349 struct mpc_i2c
*i2c
= dev_get_drvdata(device
);
351 i2c_del_adapter(&i2c
->adap
);
352 dev_set_drvdata(device
, NULL
);
355 free_irq(i2c
->irq
, i2c
);
362 /* Structure for a device driver */
363 static struct device_driver fsl_i2c_driver
= {
365 .bus
= &platform_bus_type
,
366 .probe
= fsl_i2c_probe
,
367 .remove
= fsl_i2c_remove
,
370 static int __init
fsl_i2c_init(void)
372 return driver_register(&fsl_i2c_driver
);
375 static void __exit
fsl_i2c_exit(void)
377 driver_unregister(&fsl_i2c_driver
);
380 module_init(fsl_i2c_init
);
381 module_exit(fsl_i2c_exit
);
383 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
385 ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
386 MODULE_LICENSE("GPL");