drivers/serial/21285.c

   1 /*
   2  * linux/drivers/serial/21285.c
   3  *
   4  * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
   5  *
   6  * Based on drivers/char/serial.c
   7  *
   8  *  $Id: 21285.c,v 1.37 2002/07/28 10:03:27 rmk Exp $
   9  */
  10 #include <linux/module.h>
  11 #include <linux/tty.h>
  12 #include <linux/ioport.h>
  13 #include <linux/init.h>
  14 #include <linux/console.h>
  15 #include <linux/device.h>
  16 #include <linux/tty_flip.h>
  17 #include <linux/serial_core.h>
  18 #include <linux/serial.h>
  19
  20 #include <asm/io.h>
  21 #include <asm/irq.h>
  22 #include <asm/mach-types.h>
  23 #include <asm/hardware/dec21285.h>
  24 #include <asm/hardware.h>
  25
  26 #define BAUD_BASE               (mem_fclk_21285/64)
  27
  28 #define SERIAL_21285_NAME       "ttyFB"
  29 #define SERIAL_21285_MAJOR      204
  30 #define SERIAL_21285_MINOR      4
  31
  32 #define RXSTAT_DUMMY_READ       0x80000000
  33 #define RXSTAT_FRAME            (1 << 0)
  34 #define RXSTAT_PARITY           (1 << 1)
  35 #define RXSTAT_OVERRUN          (1 << 2)
  36 #define RXSTAT_ANYERR           (RXSTAT_FRAME|RXSTAT_PARITY|RXSTAT_OVERRUN)
  37
  38 #define H_UBRLCR_BREAK          (1 << 0)
  39 #define H_UBRLCR_PARENB         (1 << 1)
  40 #define H_UBRLCR_PAREVN         (1 << 2)
  41 #define H_UBRLCR_STOPB          (1 << 3)
  42 #define H_UBRLCR_FIFO           (1 << 4)
  43
  44 static const char serial21285_name[] = "Footbridge UART";
  45
  46 #define tx_enabled(port)        ((port)->unused[0])
  47 #define rx_enabled(port)        ((port)->unused[1])
  48
  49 /*
  50  * The documented expression for selecting the divisor is:
  51  *  BAUD_BASE / baud - 1
  52  * However, typically BAUD_BASE is not divisible by baud, so
  53  * we want to select the divisor that gives us the minimum
  54  * error.  Therefore, we want:
  55  *  int(BAUD_BASE / baud - 0.5) ->
  56  *  int(BAUD_BASE / baud - (baud >> 1) / baud) ->
  57  *  int((BAUD_BASE - (baud >> 1)) / baud)
  58  */
  59
  60 static void serial21285_stop_tx(struct uart_port *port)
  61 {
  62         if (tx_enabled(port)) {
  63                 disable_irq(IRQ_CONTX);
  64                 tx_enabled(port) = 0;
  65         }
  66 }
  67
  68 static void serial21285_start_tx(struct uart_port *port)
  69 {
  70         if (!tx_enabled(port)) {
  71                 enable_irq(IRQ_CONTX);
  72                 tx_enabled(port) = 1;
  73         }
  74 }
  75
  76 static void serial21285_stop_rx(struct uart_port *port)
  77 {
  78         if (rx_enabled(port)) {
  79                 disable_irq(IRQ_CONRX);
  80                 rx_enabled(port) = 0;
  81         }
  82 }
  83
  84 static void serial21285_enable_ms(struct uart_port *port)
  85 {
  86 }
  87
  88 static irqreturn_t serial21285_rx_chars(int irq, void *dev_id)
  89 {
  90         struct uart_port *port = dev_id;
  91         struct tty_struct *tty = port->info->tty;
  92         unsigned int status, ch, flag, rxs, max_count = 256;
  93
  94         status = *CSR_UARTFLG;
  95         while (!(status & 0x10) && max_count--) {
  96                 ch = *CSR_UARTDR;
  97                 flag = TTY_NORMAL;
  98                 port->icount.rx++;
  99
 100                 rxs = *CSR_RXSTAT | RXSTAT_DUMMY_READ;
 101                 if (unlikely(rxs & RXSTAT_ANYERR)) {
 102                         if (rxs & RXSTAT_PARITY)
 103                                 port->icount.parity++;
 104                         else if (rxs & RXSTAT_FRAME)
 105                                 port->icount.frame++;
 106                         if (rxs & RXSTAT_OVERRUN)
 107                                 port->icount.overrun++;
 108
 109                         rxs &= port->read_status_mask;
 110
 111                         if (rxs & RXSTAT_PARITY)
 112                                 flag = TTY_PARITY;
 113                         else if (rxs & RXSTAT_FRAME)
 114                                 flag = TTY_FRAME;
 115                 }
 116
 117                 uart_insert_char(port, rxs, RXSTAT_OVERRUN, ch, flag);
 118
 119                 status = *CSR_UARTFLG;
 120         }
 121         tty_flip_buffer_push(tty);
 122
 123         return IRQ_HANDLED;
 124 }
 125
 126 static irqreturn_t serial21285_tx_chars(int irq, void *dev_id)
 127 {
 128         struct uart_port *port = dev_id;
 129         struct circ_buf *xmit = &port->info->xmit;
 130         int count = 256;
 131
 132         if (port->x_char) {
 133                 *CSR_UARTDR = port->x_char;
 134                 port->icount.tx++;
 135                 port->x_char = 0;
 136                 goto out;
 137         }
 138         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 139                 serial21285_stop_tx(port);
 140                 goto out;
 141         }
 142
 143         do {
 144                 *CSR_UARTDR = xmit->buf[xmit->tail];
 145                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 146                 port->icount.tx++;
 147                 if (uart_circ_empty(xmit))
 148                         break;
 149         } while (--count > 0 && !(*CSR_UARTFLG & 0x20));
 150
 151         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 152                 uart_write_wakeup(port);
 153
 154         if (uart_circ_empty(xmit))
 155                 serial21285_stop_tx(port);
 156
 157  out:
 158         return IRQ_HANDLED;
 159 }
 160
 161 static unsigned int serial21285_tx_empty(struct uart_port *port)
 162 {
 163         return (*CSR_UARTFLG & 8) ? 0 : TIOCSER_TEMT;
 164 }
 165
 166 /* no modem control lines */
 167 static unsigned int serial21285_get_mctrl(struct uart_port *port)
 168 {
 169         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 170 }
 171
 172 static void serial21285_set_mctrl(struct uart_port *port, unsigned int mctrl)
 173 {
 174 }
 175
 176 static void serial21285_break_ctl(struct uart_port *port, int break_state)
 177 {
 178         unsigned long flags;
 179         unsigned int h_lcr;
 180
 181         spin_lock_irqsave(&port->lock, flags);
 182         h_lcr = *CSR_H_UBRLCR;
 183         if (break_state)
 184                 h_lcr |= H_UBRLCR_BREAK;
 185         else
 186                 h_lcr &= ~H_UBRLCR_BREAK;
 187         *CSR_H_UBRLCR = h_lcr;
 188         spin_unlock_irqrestore(&port->lock, flags);
 189 }
 190
 191 static int serial21285_startup(struct uart_port *port)
 192 {
 193         int ret;
 194
 195         tx_enabled(port) = 1;
 196         rx_enabled(port) = 1;
 197
 198         ret = request_irq(IRQ_CONRX, serial21285_rx_chars, 0,
 199                           serial21285_name, port);
 200         if (ret == 0) {
 201                 ret = request_irq(IRQ_CONTX, serial21285_tx_chars, 0,
 202                                   serial21285_name, port);
 203                 if (ret)
 204                         free_irq(IRQ_CONRX, port);
 205         }
 206
 207         return ret;
 208 }
 209
 210 static void serial21285_shutdown(struct uart_port *port)
 211 {
 212         free_irq(IRQ_CONTX, port);
 213         free_irq(IRQ_CONRX, port);
 214 }
 215
 216 static void
 217 serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
 218                         struct ktermios *old)
 219 {
 220         unsigned long flags;
 221         unsigned int baud, quot, h_lcr;
 222
 223         /*
 224          * We don't support modem control lines.
 225          */
 226         termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
 227         termios->c_cflag |= CLOCAL;
 228
 229         /*
 230          * We don't support BREAK character recognition.
 231          */
 232         termios->c_iflag &= ~(IGNBRK | BRKINT);
 233
 234         /*
 235          * Ask the core to calculate the divisor for us.
 236          */
 237         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
 238         quot = uart_get_divisor(port, baud);
 239
 240         switch (termios->c_cflag & CSIZE) {
 241         case CS5:
 242                 h_lcr = 0x00;
 243                 break;
 244         case CS6:
 245                 h_lcr = 0x20;
 246                 break;
 247         case CS7:
 248                 h_lcr = 0x40;
 249                 break;
 250         default: /* CS8 */
 251                 h_lcr = 0x60;
 252                 break;
 253         }
 254
 255         if (termios->c_cflag & CSTOPB)
 256                 h_lcr |= H_UBRLCR_STOPB;
 257         if (termios->c_cflag & PARENB) {
 258                 h_lcr |= H_UBRLCR_PARENB;
 259                 if (!(termios->c_cflag & PARODD))
 260                         h_lcr |= H_UBRLCR_PAREVN;
 261         }
 262
 263         if (port->fifosize)
 264                 h_lcr |= H_UBRLCR_FIFO;
 265
 266         spin_lock_irqsave(&port->lock, flags);
 267
 268         /*
 269          * Update the per-port timeout.
 270          */
 271         uart_update_timeout(port, termios->c_cflag, baud);
 272
 273         /*
 274          * Which character status flags are we interested in?
 275          */
 276         port->read_status_mask = RXSTAT_OVERRUN;
 277         if (termios->c_iflag & INPCK)
 278                 port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
 279
 280         tty_encode_baud_rate(tty,  baud, baud);
 281
 282         /*
 283          * Which character status flags should we ignore?
 284          */
 285         port->ignore_status_mask = 0;
 286         if (termios->c_iflag & IGNPAR)
 287                 port->ignore_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
 288         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
 289                 port->ignore_status_mask |= RXSTAT_OVERRUN;
 290
 291         /*
 292          * Ignore all characters if CREAD is not set.
 293          */
 294         if ((termios->c_cflag & CREAD) == 0)
 295                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
 296
 297         quot -= 1;
 298
 299         *CSR_UARTCON = 0;
 300         *CSR_L_UBRLCR = quot & 0xff;
 301         *CSR_M_UBRLCR = (quot >> 8) & 0x0f;
 302         *CSR_H_UBRLCR = h_lcr;
 303         *CSR_UARTCON = 1;
 304
 305         spin_unlock_irqrestore(&port->lock, flags);
 306 }
 307
 308 static const char *serial21285_type(struct uart_port *port)
 309 {
 310         return port->type == PORT_21285 ? "DC21285" : NULL;
 311 }
 312
 313 static void serial21285_release_port(struct uart_port *port)
 314 {
 315         release_mem_region(port->mapbase, 32);
 316 }
 317
 318 static int serial21285_request_port(struct uart_port *port)
 319 {
 320         return request_mem_region(port->mapbase, 32, serial21285_name)
 321                          != NULL ? 0 : -EBUSY;
 322 }
 323
 324 static void serial21285_config_port(struct uart_port *port, int flags)
 325 {
 326         if (flags & UART_CONFIG_TYPE && serial21285_request_port(port) == 0)
 327                 port->type = PORT_21285;
 328 }
 329
 330 /*
 331  * verify the new serial_struct (for TIOCSSERIAL).
 332  */
 333 static int serial21285_verify_port(struct uart_port *port, struct serial_struct *ser)
 334 {
 335         int ret = 0;
 336         if (ser->type != PORT_UNKNOWN && ser->type != PORT_21285)
 337                 ret = -EINVAL;
 338         if (ser->irq != NO_IRQ)
 339                 ret = -EINVAL;
 340         if (ser->baud_base != port->uartclk / 16)
 341                 ret = -EINVAL;
 342         return ret;
 343 }
 344
 345 static struct uart_ops serial21285_ops = {
 346         .tx_empty       = serial21285_tx_empty,
 347         .get_mctrl      = serial21285_get_mctrl,
 348         .set_mctrl      = serial21285_set_mctrl,
 349         .stop_tx        = serial21285_stop_tx,
 350         .start_tx       = serial21285_start_tx,
 351         .stop_rx        = serial21285_stop_rx,
 352         .enable_ms      = serial21285_enable_ms,
 353         .break_ctl      = serial21285_break_ctl,
 354         .startup        = serial21285_startup,
 355         .shutdown       = serial21285_shutdown,
 356         .set_termios    = serial21285_set_termios,
 357         .type           = serial21285_type,
 358         .release_port   = serial21285_release_port,
 359         .request_port   = serial21285_request_port,
 360         .config_port    = serial21285_config_port,
 361         .verify_port    = serial21285_verify_port,
 362 };
 363
 364 static struct uart_port serial21285_port = {
 365         .mapbase        = 0x42000160,
 366         .iotype         = UPIO_MEM,
 367         .irq            = NO_IRQ,
 368         .fifosize       = 16,
 369         .ops            = &serial21285_ops,
 370         .flags          = UPF_BOOT_AUTOCONF,
 371 };
 372
 373 static void serial21285_setup_ports(void)
 374 {
 375         serial21285_port.uartclk = mem_fclk_21285 / 4;
 376 }
 377
 378 #ifdef CONFIG_SERIAL_21285_CONSOLE
 379 static void serial21285_console_putchar(struct uart_port *port, int ch)
 380 {
 381         while (*CSR_UARTFLG & 0x20)
 382                 barrier();
 383         *CSR_UARTDR = ch;
 384 }
 385
 386 static void
 387 serial21285_console_write(struct console *co, const char *s,
 388                           unsigned int count)
 389 {
 390         uart_console_write(&serial21285_port, s, count, serial21285_console_putchar);
 391 }
 392
 393 static void __init
 394 serial21285_get_options(struct uart_port *port, int *baud,
 395                         int *parity, int *bits)
 396 {
 397         if (*CSR_UARTCON == 1) {
 398                 unsigned int tmp;
 399
 400                 tmp = *CSR_H_UBRLCR;
 401                 switch (tmp & 0x60) {
 402                 case 0x00:
 403                         *bits = 5;
 404                         break;
 405                 case 0x20:
 406                         *bits = 6;
 407                         break;
 408                 case 0x40:
 409                         *bits = 7;
 410                         break;
 411                 default:
 412                 case 0x60:
 413                         *bits = 8;
 414                         break;
 415                 }
 416
 417                 if (tmp & H_UBRLCR_PARENB) {
 418                         *parity = 'o';
 419                         if (tmp & H_UBRLCR_PAREVN)
 420                                 *parity = 'e';
 421                 }
 422
 423                 tmp = *CSR_L_UBRLCR | (*CSR_M_UBRLCR << 8);
 424
 425                 *baud = port->uartclk / (16 * (tmp + 1));
 426         }
 427 }
 428
 429 static int __init serial21285_console_setup(struct console *co, char *options)
 430 {
 431         struct uart_port *port = &serial21285_port;
 432         int baud = 9600;
 433         int bits = 8;
 434         int parity = 'n';
 435         int flow = 'n';
 436
 437         if (machine_is_personal_server())
 438                 baud = 57600;
 439
 440         /*
 441          * Check whether an invalid uart number has been specified, and
 442          * if so, search for the first available port that does have
 443          * console support.
 444          */
 445         if (options)
 446                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 447         else
 448                 serial21285_get_options(port, &baud, &parity, &bits);
 449
 450         return uart_set_options(port, co, baud, parity, bits, flow);
 451 }
 452
 453 static struct uart_driver serial21285_reg;
 454
 455 static struct console serial21285_console =
 456 {
 457         .name           = SERIAL_21285_NAME,
 458         .write          = serial21285_console_write,
 459         .device         = uart_console_device,
 460         .setup          = serial21285_console_setup,
 461         .flags          = CON_PRINTBUFFER,
 462         .index          = -1,
 463         .data           = &serial21285_reg,
 464 };
 465
 466 static int __init rs285_console_init(void)
 467 {
 468         serial21285_setup_ports();
 469         register_console(&serial21285_console);
 470         return 0;
 471 }
 472 console_initcall(rs285_console_init);
 473
 474 #define SERIAL_21285_CONSOLE    &serial21285_console
 475 #else
 476 #define SERIAL_21285_CONSOLE    NULL
 477 #endif
 478
 479 static struct uart_driver serial21285_reg = {
 480         .owner                  = THIS_MODULE,
 481         .driver_name            = "ttyFB",
 482         .dev_name               = "ttyFB",
 483         .major                  = SERIAL_21285_MAJOR,
 484         .minor                  = SERIAL_21285_MINOR,
 485         .nr                     = 1,
 486         .cons                   = SERIAL_21285_CONSOLE,
 487 };
 488
 489 static int __init serial21285_init(void)
 490 {
 491         int ret;
 492
 493         printk(KERN_INFO "Serial: 21285 driver $Revision: 1.37 $\n");
 494
 495         serial21285_setup_ports();
 496
 497         ret = uart_register_driver(&serial21285_reg);
 498         if (ret == 0)
 499                 uart_add_one_port(&serial21285_reg, &serial21285_port);
 500
 501         return ret;
 502 }
 503
 504 static void __exit serial21285_exit(void)
 505 {
 506         uart_remove_one_port(&serial21285_reg, &serial21285_port);
 507         uart_unregister_driver(&serial21285_reg);
 508 }
 509
 510 module_init(serial21285_init);
 511 module_exit(serial21285_exit);
 512
 513 MODULE_LICENSE("GPL");
 514 MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver $Revision: 1.37 $");
 515 MODULE_ALIAS_CHARDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR);