drivers/gpu/drm/nouveau/nouveau_drv.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include <linux/console.h>
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "drm_crtc_helper.h"
  30 #include "nouveau_drv.h"
  31 #include "nouveau_hw.h"
  32 #include "nouveau_fb.h"
  33 #include "nouveau_fbcon.h"
  34 #include "nv50_display.h"
  35
  36 #include "drm_pciids.h"
  37
  38 MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
  39 int nouveau_ctxfw = 0;
  40 module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
  41
  42 MODULE_PARM_DESC(noagp, "Disable AGP");
  43 int nouveau_noagp;
  44 module_param_named(noagp, nouveau_noagp, int, 0400);
  45
  46 MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
  47 static int nouveau_modeset = -1; /* kms */
  48 module_param_named(modeset, nouveau_modeset, int, 0400);
  49
  50 MODULE_PARM_DESC(vbios, "Override default VBIOS location");
  51 char *nouveau_vbios;
  52 module_param_named(vbios, nouveau_vbios, charp, 0400);
  53
  54 MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
  55 int nouveau_vram_pushbuf;
  56 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  57
  58 MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
  59 int nouveau_vram_notify = 1;
  60 module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
  61
  62 MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
  63 int nouveau_duallink = 1;
  64 module_param_named(duallink, nouveau_duallink, int, 0400);
  65
  66 MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
  67 int nouveau_uscript_lvds = -1;
  68 module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
  69
  70 MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
  71 int nouveau_uscript_tmds = -1;
  72 module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
  73
  74 MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
  75 int nouveau_ignorelid = 0;
  76 module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
  77
  78 MODULE_PARM_DESC(noaccel, "Disable all acceleration");
  79 int nouveau_noaccel = 0;
  80 module_param_named(noaccel, nouveau_noaccel, int, 0400);
  81
  82 MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
  83 int nouveau_nofbaccel = 0;
  84 module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
  85
  86 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
  87                  "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
  88                  "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
  89                  "\t\tDefault: PAL\n"
  90                  "\t\t*NOTE* Ignored for cards with external TV encoders.");
  91 char *nouveau_tv_norm;
  92 module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
  93
  94 MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
  95                 "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
  96                 "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
  97                 "\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
  98 int nouveau_reg_debug;
  99 module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
 100
 101 int nouveau_fbpercrtc;
 102 #if 0
 103 module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
 104 #endif
 105
 106 static struct pci_device_id pciidlist[] = {
 107         {
 108                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
 109                 .class = PCI_BASE_CLASS_DISPLAY << 16,
 110                 .class_mask  = 0xff << 16,
 111         },
 112         {
 113                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
 114                 .class = PCI_BASE_CLASS_DISPLAY << 16,
 115                 .class_mask  = 0xff << 16,
 116         },
 117         {}
 118 };
 119
 120 MODULE_DEVICE_TABLE(pci, pciidlist);
 121
 122 static struct drm_driver driver;
 123
 124 static int __devinit
 125 nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 126 {
 127         return drm_get_dev(pdev, ent, &driver);
 128 }
 129
 130 static void
 131 nouveau_pci_remove(struct pci_dev *pdev)
 132 {
 133         struct drm_device *dev = pci_get_drvdata(pdev);
 134
 135         drm_put_dev(dev);
 136 }
 137
 138 int
 139 nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
 140 {
 141         struct drm_device *dev = pci_get_drvdata(pdev);
 142         struct drm_nouveau_private *dev_priv = dev->dev_private;
 143         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 144         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 145         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 146         struct nouveau_channel *chan;
 147         struct drm_crtc *crtc;
 148         uint32_t fbdev_flags;
 149         int ret, i;
 150
 151         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 152                 return -ENODEV;
 153
 154         if (pm_state.event == PM_EVENT_PRETHAW)
 155                 return 0;
 156
 157         fbdev_flags = dev_priv->fbdev_info->flags;
 158         dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
 159
 160         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 161                 struct nouveau_framebuffer *nouveau_fb;
 162
 163                 nouveau_fb = nouveau_framebuffer(crtc->fb);
 164                 if (!nouveau_fb || !nouveau_fb->nvbo)
 165                         continue;
 166
 167                 nouveau_bo_unpin(nouveau_fb->nvbo);
 168         }
 169
 170         NV_INFO(dev, "Evicting buffers...\n");
 171         ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 172
 173         NV_INFO(dev, "Idling channels...\n");
 174         for (i = 0; i < pfifo->channels; i++) {
 175                 struct nouveau_fence *fence = NULL;
 176
 177                 chan = dev_priv->fifos[i];
 178                 if (!chan || (dev_priv->card_type >= NV_50 &&
 179                               chan == dev_priv->fifos[0]))
 180                         continue;
 181
 182                 ret = nouveau_fence_new(chan, &fence, true);
 183                 if (ret == 0) {
 184                         ret = nouveau_fence_wait(fence, NULL, false, false);
 185                         nouveau_fence_unref((void *)&fence);
 186                 }
 187
 188                 if (ret) {
 189                         NV_ERROR(dev, "Failed to idle channel %d for suspend\n",
 190                                  chan->id);
 191                 }
 192         }
 193
 194         pgraph->fifo_access(dev, false);
 195         nouveau_wait_for_idle(dev);
 196         pfifo->reassign(dev, false);
 197         pfifo->disable(dev);
 198         pfifo->unload_context(dev);
 199         pgraph->unload_context(dev);
 200
 201         NV_INFO(dev, "Suspending GPU objects...\n");
 202         ret = nouveau_gpuobj_suspend(dev);
 203         if (ret) {
 204                 NV_ERROR(dev, "... failed: %d\n", ret);
 205                 goto out_abort;
 206         }
 207
 208         ret = pinstmem->suspend(dev);
 209         if (ret) {
 210                 NV_ERROR(dev, "... failed: %d\n", ret);
 211                 nouveau_gpuobj_suspend_cleanup(dev);
 212                 goto out_abort;
 213         }
 214
 215         NV_INFO(dev, "And we're gone!\n");
 216         pci_save_state(pdev);
 217         if (pm_state.event == PM_EVENT_SUSPEND) {
 218                 pci_disable_device(pdev);
 219                 pci_set_power_state(pdev, PCI_D3hot);
 220         }
 221
 222         acquire_console_sem();
 223         fb_set_suspend(dev_priv->fbdev_info, 1);
 224         release_console_sem();
 225         dev_priv->fbdev_info->flags = fbdev_flags;
 226         return 0;
 227
 228 out_abort:
 229         NV_INFO(dev, "Re-enabling acceleration..\n");
 230         pfifo->enable(dev);
 231         pfifo->reassign(dev, true);
 232         pgraph->fifo_access(dev, true);
 233         return ret;
 234 }
 235
 236 int
 237 nouveau_pci_resume(struct pci_dev *pdev)
 238 {
 239         struct drm_device *dev = pci_get_drvdata(pdev);
 240         struct drm_nouveau_private *dev_priv = dev->dev_private;
 241         struct nouveau_engine *engine = &dev_priv->engine;
 242         struct drm_crtc *crtc;
 243         uint32_t fbdev_flags;
 244         int ret, i;
 245
 246         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 247                 return -ENODEV;
 248
 249         fbdev_flags = dev_priv->fbdev_info->flags;
 250         dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
 251
 252         NV_INFO(dev, "We're back, enabling device...\n");
 253         pci_set_power_state(pdev, PCI_D0);
 254         pci_restore_state(pdev);
 255         if (pci_enable_device(pdev))
 256                 return -1;
 257         pci_set_master(dev->pdev);
 258
 259         NV_INFO(dev, "POSTing device...\n");
 260         ret = nouveau_run_vbios_init(dev);
 261         if (ret)
 262                 return ret;
 263
 264         if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
 265                 ret = nouveau_mem_init_agp(dev);
 266                 if (ret) {
 267                         NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
 268                         return ret;
 269                 }
 270         }
 271
 272         NV_INFO(dev, "Reinitialising engines...\n");
 273         engine->instmem.resume(dev);
 274         engine->mc.init(dev);
 275         engine->timer.init(dev);
 276         engine->fb.init(dev);
 277         engine->graph.init(dev);
 278         engine->fifo.init(dev);
 279
 280         NV_INFO(dev, "Restoring GPU objects...\n");
 281         nouveau_gpuobj_resume(dev);
 282
 283         nouveau_irq_postinstall(dev);
 284
 285         /* Re-write SKIPS, they'll have been lost over the suspend */
 286         if (nouveau_vram_pushbuf) {
 287                 struct nouveau_channel *chan;
 288                 int j;
 289
 290                 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 291                         chan = dev_priv->fifos[i];
 292                         if (!chan || !chan->pushbuf_bo)
 293                                 continue;
 294
 295                         for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
 296                                 nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
 297                 }
 298         }
 299
 300         NV_INFO(dev, "Restoring mode...\n");
 301         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 302                 struct nouveau_framebuffer *nouveau_fb;
 303
 304                 nouveau_fb = nouveau_framebuffer(crtc->fb);
 305                 if (!nouveau_fb || !nouveau_fb->nvbo)
 306                         continue;
 307
 308                 nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
 309         }
 310
 311         if (dev_priv->card_type < NV_50) {
 312                 nv04_display_restore(dev);
 313                 NVLockVgaCrtcs(dev, false);
 314         } else
 315                 nv50_display_init(dev);
 316
 317         /* Force CLUT to get re-loaded during modeset */
 318         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 319                 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 320
 321                 nv_crtc->lut.depth = 0;
 322         }
 323
 324         acquire_console_sem();
 325         fb_set_suspend(dev_priv->fbdev_info, 0);
 326         release_console_sem();
 327
 328         nouveau_fbcon_zfill(dev);
 329
 330         drm_helper_resume_force_mode(dev);
 331         dev_priv->fbdev_info->flags = fbdev_flags;
 332         return 0;
 333 }
 334
 335 static struct drm_driver driver = {
 336         .driver_features =
 337                 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
 338                 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 339         .load = nouveau_load,
 340         .firstopen = nouveau_firstopen,
 341         .lastclose = nouveau_lastclose,
 342         .unload = nouveau_unload,
 343         .preclose = nouveau_preclose,
 344 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
 345         .debugfs_init = nouveau_debugfs_init,
 346         .debugfs_cleanup = nouveau_debugfs_takedown,
 347 #endif
 348         .irq_preinstall = nouveau_irq_preinstall,
 349         .irq_postinstall = nouveau_irq_postinstall,
 350         .irq_uninstall = nouveau_irq_uninstall,
 351         .irq_handler = nouveau_irq_handler,
 352         .reclaim_buffers = drm_core_reclaim_buffers,
 353         .get_map_ofs = drm_core_get_map_ofs,
 354         .get_reg_ofs = drm_core_get_reg_ofs,
 355         .ioctls = nouveau_ioctls,
 356         .fops = {
 357                 .owner = THIS_MODULE,
 358                 .open = drm_open,
 359                 .release = drm_release,
 360                 .unlocked_ioctl = drm_ioctl,
 361                 .mmap = nouveau_ttm_mmap,
 362                 .poll = drm_poll,
 363                 .fasync = drm_fasync,
 364 #if defined(CONFIG_COMPAT)
 365                 .compat_ioctl = nouveau_compat_ioctl,
 366 #endif
 367         },
 368         .pci_driver = {
 369                 .name = DRIVER_NAME,
 370                 .id_table = pciidlist,
 371                 .probe = nouveau_pci_probe,
 372                 .remove = nouveau_pci_remove,
 373                 .suspend = nouveau_pci_suspend,
 374                 .resume = nouveau_pci_resume
 375         },
 376
 377         .gem_init_object = nouveau_gem_object_new,
 378         .gem_free_object = nouveau_gem_object_del,
 379
 380         .name = DRIVER_NAME,
 381         .desc = DRIVER_DESC,
 382 #ifdef GIT_REVISION
 383         .date = GIT_REVISION,
 384 #else
 385         .date = DRIVER_DATE,
 386 #endif
 387         .major = DRIVER_MAJOR,
 388         .minor = DRIVER_MINOR,
 389         .patchlevel = DRIVER_PATCHLEVEL,
 390 };
 391
 392 static int __init nouveau_init(void)
 393 {
 394         driver.num_ioctls = nouveau_max_ioctl;
 395
 396         if (nouveau_modeset == -1) {
 397 #ifdef CONFIG_VGA_CONSOLE
 398                 if (vgacon_text_force())
 399                         nouveau_modeset = 0;
 400                 else
 401 #endif
 402                         nouveau_modeset = 1;
 403         }
 404
 405         if (nouveau_modeset == 1) {
 406                 driver.driver_features |= DRIVER_MODESET;
 407                 nouveau_register_dsm_handler();
 408         }
 409
 410         return drm_init(&driver);
 411 }
 412
 413 static void __exit nouveau_exit(void)
 414 {
 415         drm_exit(&driver);
 416         nouveau_unregister_dsm_handler();
 417 }
 418
 419 module_init(nouveau_init);
 420 module_exit(nouveau_exit);
 421
 422 MODULE_AUTHOR(DRIVER_AUTHOR);
 423 MODULE_DESCRIPTION(DRIVER_DESC);
 424 MODULE_LICENSE("GPL and additional rights");