2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
9 #include <linux/kernel.h>
10 #include <linux/slab.h>
11 #include <linux/dmaengine.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
17 #include <plat/ste_dma40.h>
19 #include "ste_dma40_ll.h"
21 #define D40_NAME "dma40"
23 #define D40_PHY_CHAN -1
25 /* For masking out/in 2 bit channel positions */
26 #define D40_CHAN_POS(chan) (2 * (chan / 2))
27 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
29 /* Maximum iterations taken before giving up suspending a channel */
30 #define D40_SUSPEND_MAX_IT 500
32 /* Hardware requirement on LCLA alignment */
33 #define LCLA_ALIGNMENT 0x40000
35 /* Max number of links per event group */
36 #define D40_LCLA_LINK_PER_EVENT_GRP 128
37 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
39 /* Attempts before giving up to trying to get pages that are aligned */
40 #define MAX_LCLA_ALLOC_ATTEMPTS 256
42 /* Bit markings for allocation map */
43 #define D40_ALLOC_FREE (1 << 31)
44 #define D40_ALLOC_PHY (1 << 30)
45 #define D40_ALLOC_LOG_FREE 0
47 /* Hardware designer of the block */
48 #define D40_HW_DESIGNER 0x8
51 * enum 40_command - The different commands and/or statuses.
53 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
61 D40_DMA_SUSPEND_REQ
= 2,
66 * struct d40_lli_pool - Structure for keeping LLIs in memory
68 * @base: Pointer to memory area when the pre_alloc_lli's are not large
69 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70 * pre_alloc_lli is used.
71 * @dma_addr: DMA address, if mapped
72 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
73 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
74 * one buffer to one buffer.
80 /* Space for dst and src, plus an extra for padding */
81 u8 pre_alloc_lli
[3 * sizeof(struct d40_phy_lli
)];
85 * struct d40_desc - A descriptor is one DMA job.
87 * @lli_phy: LLI settings for physical channel. Both src and dst=
88 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
90 * @lli_log: Same as above but for logical channels.
91 * @lli_pool: The pool with two entries pre-allocated.
92 * @lli_len: Number of llis of current descriptor.
93 * @lli_current: Number of transfered llis.
94 * @lcla_alloc: Number of LCLA entries allocated.
95 * @txd: DMA engine struct. Used for among other things for communication
98 * @is_in_client_list: true if the client owns this descriptor.
101 * This descriptor is used for both logical and physical transfers.
105 struct d40_phy_lli_bidir lli_phy
;
107 struct d40_log_lli_bidir lli_log
;
109 struct d40_lli_pool lli_pool
;
114 struct dma_async_tx_descriptor txd
;
115 struct list_head node
;
117 bool is_in_client_list
;
121 * struct d40_lcla_pool - LCLA pool settings and data.
123 * @base: The virtual address of LCLA. 18 bit aligned.
124 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
125 * This pointer is only there for clean-up on error.
126 * @pages: The number of pages needed for all physical channels.
127 * Only used later for clean-up on error
128 * @lock: Lock to protect the content in this struct.
129 * @alloc_map: big map over which LCLA entry is own by which job.
131 struct d40_lcla_pool
{
134 void *base_unaligned
;
137 struct d40_desc
**alloc_map
;
141 * struct d40_phy_res - struct for handling eventlines mapped to physical
144 * @lock: A lock protection this entity.
145 * @num: The physical channel number of this entity.
146 * @allocated_src: Bit mapped to show which src event line's are mapped to
147 * this physical channel. Can also be free or physically allocated.
148 * @allocated_dst: Same as for src but is dst.
149 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
162 * struct d40_chan - Struct that describes a channel.
164 * @lock: A spinlock to protect this struct.
165 * @log_num: The logical number, if any of this channel.
166 * @completed: Starts with 1, after first interrupt it is set to dma engine's
168 * @pending_tx: The number of pending transfers. Used between interrupt handler
170 * @busy: Set to true when transfer is ongoing on this channel.
171 * @phy_chan: Pointer to physical channel which this instance runs on. If this
172 * point is NULL, then the channel is not allocated.
173 * @chan: DMA engine handle.
174 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
175 * transfer and call client callback.
176 * @client: Cliented owned descriptor list.
177 * @active: Active descriptor.
178 * @queue: Queued jobs.
179 * @dma_cfg: The client configuration of this dma channel.
180 * @configured: whether the dma_cfg configuration is valid
181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
188 * This struct can either "be" a logical or a physical channel.
193 /* ID of the most recent completed transfer */
197 struct d40_phy_res
*phy_chan
;
198 struct dma_chan chan
;
199 struct tasklet_struct tasklet
;
200 struct list_head client
;
201 struct list_head active
;
202 struct list_head queue
;
203 struct stedma40_chan_cfg dma_cfg
;
205 struct d40_base
*base
;
206 /* Default register configurations */
209 struct d40_def_lcsp log_def
;
210 struct d40_log_lli_full
*lcpa
;
211 /* Runtime reconfiguration */
212 dma_addr_t runtime_addr
;
213 enum dma_data_direction runtime_direction
;
217 * struct d40_base - The big global struct, one for each probe'd instance.
219 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
220 * @execmd_lock: Lock for execute command usage since several channels share
221 * the same physical register.
222 * @dev: The device structure.
223 * @virtbase: The virtual base address of the DMA's register.
224 * @rev: silicon revision detected.
225 * @clk: Pointer to the DMA clock structure.
226 * @phy_start: Physical memory start of the DMA registers.
227 * @phy_size: Size of the DMA register map.
228 * @irq: The IRQ number.
229 * @num_phy_chans: The number of physical channels. Read from HW. This
230 * is the number of available channels for this driver, not counting "Secure
231 * mode" allocated physical channels.
232 * @num_log_chans: The number of logical channels. Calculated from
234 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
235 * @dma_slave: dma_device channels that can do only do slave transfers.
236 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
237 * @log_chans: Room for all possible logical channels in system.
238 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
239 * to log_chans entries.
240 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
241 * to phy_chans entries.
242 * @plat_data: Pointer to provided platform_data which is the driver
244 * @phy_res: Vector containing all physical channels.
245 * @lcla_pool: lcla pool settings and data.
246 * @lcpa_base: The virtual mapped address of LCPA.
247 * @phy_lcpa: The physical address of the LCPA.
248 * @lcpa_size: The size of the LCPA area.
249 * @desc_slab: cache for descriptors.
252 spinlock_t interrupt_lock
;
253 spinlock_t execmd_lock
;
255 void __iomem
*virtbase
;
258 phys_addr_t phy_start
;
259 resource_size_t phy_size
;
263 struct dma_device dma_both
;
264 struct dma_device dma_slave
;
265 struct dma_device dma_memcpy
;
266 struct d40_chan
*phy_chans
;
267 struct d40_chan
*log_chans
;
268 struct d40_chan
**lookup_log_chans
;
269 struct d40_chan
**lookup_phy_chans
;
270 struct stedma40_platform_data
*plat_data
;
271 /* Physical half channels */
272 struct d40_phy_res
*phy_res
;
273 struct d40_lcla_pool lcla_pool
;
276 resource_size_t lcpa_size
;
277 struct kmem_cache
*desc_slab
;
281 * struct d40_interrupt_lookup - lookup table for interrupt handler
283 * @src: Interrupt mask register.
284 * @clr: Interrupt clear register.
285 * @is_error: true if this is an error interrupt.
286 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
287 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
289 struct d40_interrupt_lookup
{
297 * struct d40_reg_val - simple lookup struct
299 * @reg: The register.
300 * @val: The value that belongs to the register in reg.
307 static struct device
*chan2dev(struct d40_chan
*d40c
)
309 return &d40c
->chan
.dev
->device
;
312 static bool chan_is_physical(struct d40_chan
*chan
)
314 return chan
->log_num
== D40_PHY_CHAN
;
317 static bool chan_is_logical(struct d40_chan
*chan
)
319 return !chan_is_physical(chan
);
322 static void __iomem
*chan_base(struct d40_chan
*chan
)
324 return chan
->base
->virtbase
+ D40_DREG_PCBASE
+
325 chan
->phy_chan
->num
* D40_DREG_PCDELTA
;
328 #define d40_err(dev, format, arg...) \
329 dev_err(dev, "[%s] " format, __func__, ## arg)
331 #define chan_err(d40c, format, arg...) \
332 d40_err(chan2dev(d40c), format, ## arg)
334 static int d40_pool_lli_alloc(struct d40_chan
*d40c
, struct d40_desc
*d40d
,
337 bool is_log
= chan_is_logical(d40c
);
342 align
= sizeof(struct d40_log_lli
);
344 align
= sizeof(struct d40_phy_lli
);
347 base
= d40d
->lli_pool
.pre_alloc_lli
;
348 d40d
->lli_pool
.size
= sizeof(d40d
->lli_pool
.pre_alloc_lli
);
349 d40d
->lli_pool
.base
= NULL
;
351 d40d
->lli_pool
.size
= lli_len
* 2 * align
;
353 base
= kmalloc(d40d
->lli_pool
.size
+ align
, GFP_NOWAIT
);
354 d40d
->lli_pool
.base
= base
;
356 if (d40d
->lli_pool
.base
== NULL
)
361 d40d
->lli_log
.src
= PTR_ALIGN(base
, align
);
362 d40d
->lli_log
.dst
= d40d
->lli_log
.src
+ lli_len
;
364 d40d
->lli_pool
.dma_addr
= 0;
366 d40d
->lli_phy
.src
= PTR_ALIGN(base
, align
);
367 d40d
->lli_phy
.dst
= d40d
->lli_phy
.src
+ lli_len
;
369 d40d
->lli_pool
.dma_addr
= dma_map_single(d40c
->base
->dev
,
374 if (dma_mapping_error(d40c
->base
->dev
,
375 d40d
->lli_pool
.dma_addr
)) {
376 kfree(d40d
->lli_pool
.base
);
377 d40d
->lli_pool
.base
= NULL
;
378 d40d
->lli_pool
.dma_addr
= 0;
386 static void d40_pool_lli_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
388 if (d40d
->lli_pool
.dma_addr
)
389 dma_unmap_single(d40c
->base
->dev
, d40d
->lli_pool
.dma_addr
,
390 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
392 kfree(d40d
->lli_pool
.base
);
393 d40d
->lli_pool
.base
= NULL
;
394 d40d
->lli_pool
.size
= 0;
395 d40d
->lli_log
.src
= NULL
;
396 d40d
->lli_log
.dst
= NULL
;
397 d40d
->lli_phy
.src
= NULL
;
398 d40d
->lli_phy
.dst
= NULL
;
401 static int d40_lcla_alloc_one(struct d40_chan
*d40c
,
402 struct d40_desc
*d40d
)
409 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
411 p
= d40c
->phy_chan
->num
* D40_LCLA_LINK_PER_EVENT_GRP
;
414 * Allocate both src and dst at the same time, therefore the half
415 * start on 1 since 0 can't be used since zero is used as end marker.
417 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
418 if (!d40c
->base
->lcla_pool
.alloc_map
[p
+ i
]) {
419 d40c
->base
->lcla_pool
.alloc_map
[p
+ i
] = d40d
;
426 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
431 static int d40_lcla_free_all(struct d40_chan
*d40c
,
432 struct d40_desc
*d40d
)
438 if (chan_is_physical(d40c
))
441 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
443 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
444 if (d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
445 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] == d40d
) {
446 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
447 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] = NULL
;
449 if (d40d
->lcla_alloc
== 0) {
456 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
462 static void d40_desc_remove(struct d40_desc
*d40d
)
464 list_del(&d40d
->node
);
467 static struct d40_desc
*d40_desc_get(struct d40_chan
*d40c
)
469 struct d40_desc
*desc
= NULL
;
471 if (!list_empty(&d40c
->client
)) {
475 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
)
476 if (async_tx_test_ack(&d
->txd
)) {
477 d40_pool_lli_free(d40c
, d
);
480 memset(desc
, 0, sizeof(*desc
));
486 desc
= kmem_cache_zalloc(d40c
->base
->desc_slab
, GFP_NOWAIT
);
489 INIT_LIST_HEAD(&desc
->node
);
494 static void d40_desc_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
497 d40_pool_lli_free(d40c
, d40d
);
498 d40_lcla_free_all(d40c
, d40d
);
499 kmem_cache_free(d40c
->base
->desc_slab
, d40d
);
502 static void d40_desc_submit(struct d40_chan
*d40c
, struct d40_desc
*desc
)
504 list_add_tail(&desc
->node
, &d40c
->active
);
507 static void d40_phy_lli_load(struct d40_chan
*chan
, struct d40_desc
*desc
)
509 struct d40_phy_lli
*lli_dst
= desc
->lli_phy
.dst
;
510 struct d40_phy_lli
*lli_src
= desc
->lli_phy
.src
;
511 void __iomem
*base
= chan_base(chan
);
513 writel(lli_src
->reg_cfg
, base
+ D40_CHAN_REG_SSCFG
);
514 writel(lli_src
->reg_elt
, base
+ D40_CHAN_REG_SSELT
);
515 writel(lli_src
->reg_ptr
, base
+ D40_CHAN_REG_SSPTR
);
516 writel(lli_src
->reg_lnk
, base
+ D40_CHAN_REG_SSLNK
);
518 writel(lli_dst
->reg_cfg
, base
+ D40_CHAN_REG_SDCFG
);
519 writel(lli_dst
->reg_elt
, base
+ D40_CHAN_REG_SDELT
);
520 writel(lli_dst
->reg_ptr
, base
+ D40_CHAN_REG_SDPTR
);
521 writel(lli_dst
->reg_lnk
, base
+ D40_CHAN_REG_SDLNK
);
524 static void d40_desc_load(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
526 int curr_lcla
= -EINVAL
, next_lcla
;
528 if (chan_is_physical(d40c
)) {
529 d40_phy_lli_load(d40c
, d40d
);
530 d40d
->lli_current
= d40d
->lli_len
;
533 if ((d40d
->lli_len
- d40d
->lli_current
) > 1)
534 curr_lcla
= d40_lcla_alloc_one(d40c
, d40d
);
536 d40_log_lli_lcpa_write(d40c
->lcpa
,
537 &d40d
->lli_log
.dst
[d40d
->lli_current
],
538 &d40d
->lli_log
.src
[d40d
->lli_current
],
542 for (; d40d
->lli_current
< d40d
->lli_len
; d40d
->lli_current
++) {
543 unsigned int lcla_offset
= d40c
->phy_chan
->num
* 1024 +
545 struct d40_lcla_pool
*pool
= &d40c
->base
->lcla_pool
;
546 struct d40_log_lli
*lcla
= pool
->base
+ lcla_offset
;
548 if (d40d
->lli_current
+ 1 < d40d
->lli_len
)
549 next_lcla
= d40_lcla_alloc_one(d40c
, d40d
);
553 d40_log_lli_lcla_write(lcla
,
554 &d40d
->lli_log
.dst
[d40d
->lli_current
],
555 &d40d
->lli_log
.src
[d40d
->lli_current
],
558 dma_sync_single_range_for_device(d40c
->base
->dev
,
559 pool
->dma_addr
, lcla_offset
,
560 2 * sizeof(struct d40_log_lli
),
563 curr_lcla
= next_lcla
;
565 if (curr_lcla
== -EINVAL
) {
574 static struct d40_desc
*d40_first_active_get(struct d40_chan
*d40c
)
578 if (list_empty(&d40c
->active
))
581 d
= list_first_entry(&d40c
->active
,
587 static void d40_desc_queue(struct d40_chan
*d40c
, struct d40_desc
*desc
)
589 list_add_tail(&desc
->node
, &d40c
->queue
);
592 static struct d40_desc
*d40_first_queued(struct d40_chan
*d40c
)
596 if (list_empty(&d40c
->queue
))
599 d
= list_first_entry(&d40c
->queue
,
605 static int d40_psize_2_burst_size(bool is_log
, int psize
)
608 if (psize
== STEDMA40_PSIZE_LOG_1
)
611 if (psize
== STEDMA40_PSIZE_PHY_1
)
619 * The dma only supports transmitting packages up to
620 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
621 * dma elements required to send the entire sg list
623 static int d40_size_2_dmalen(int size
, u32 data_width1
, u32 data_width2
)
626 u32 max_w
= max(data_width1
, data_width2
);
627 u32 min_w
= min(data_width1
, data_width2
);
628 u32 seg_max
= ALIGN(STEDMA40_MAX_SEG_SIZE
<< min_w
, 1 << max_w
);
630 if (seg_max
> STEDMA40_MAX_SEG_SIZE
)
631 seg_max
-= (1 << max_w
);
633 if (!IS_ALIGNED(size
, 1 << max_w
))
639 dmalen
= size
/ seg_max
;
640 if (dmalen
* seg_max
< size
)
646 static int d40_sg_2_dmalen(struct scatterlist
*sgl
, int sg_len
,
647 u32 data_width1
, u32 data_width2
)
649 struct scatterlist
*sg
;
654 for_each_sg(sgl
, sg
, sg_len
, i
) {
655 ret
= d40_size_2_dmalen(sg_dma_len(sg
),
656 data_width1
, data_width2
);
664 /* Support functions for logical channels */
666 static int d40_channel_execute_command(struct d40_chan
*d40c
,
667 enum d40_command command
)
671 void __iomem
*active_reg
;
676 spin_lock_irqsave(&d40c
->base
->execmd_lock
, flags
);
678 if (d40c
->phy_chan
->num
% 2 == 0)
679 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
681 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
683 if (command
== D40_DMA_SUSPEND_REQ
) {
684 status
= (readl(active_reg
) &
685 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
686 D40_CHAN_POS(d40c
->phy_chan
->num
);
688 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
692 wmask
= 0xffffffff & ~(D40_CHAN_POS_MASK(d40c
->phy_chan
->num
));
693 writel(wmask
| (command
<< D40_CHAN_POS(d40c
->phy_chan
->num
)),
696 if (command
== D40_DMA_SUSPEND_REQ
) {
698 for (i
= 0 ; i
< D40_SUSPEND_MAX_IT
; i
++) {
699 status
= (readl(active_reg
) &
700 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
701 D40_CHAN_POS(d40c
->phy_chan
->num
);
705 * Reduce the number of bus accesses while
706 * waiting for the DMA to suspend.
710 if (status
== D40_DMA_STOP
||
711 status
== D40_DMA_SUSPENDED
)
715 if (i
== D40_SUSPEND_MAX_IT
) {
717 "unable to suspend the chl %d (log: %d) status %x\n",
718 d40c
->phy_chan
->num
, d40c
->log_num
,
726 spin_unlock_irqrestore(&d40c
->base
->execmd_lock
, flags
);
730 static void d40_term_all(struct d40_chan
*d40c
)
732 struct d40_desc
*d40d
;
734 /* Release active descriptors */
735 while ((d40d
= d40_first_active_get(d40c
))) {
736 d40_desc_remove(d40d
);
737 d40_desc_free(d40c
, d40d
);
740 /* Release queued descriptors waiting for transfer */
741 while ((d40d
= d40_first_queued(d40c
))) {
742 d40_desc_remove(d40d
);
743 d40_desc_free(d40c
, d40d
);
747 d40c
->pending_tx
= 0;
751 static void __d40_config_set_event(struct d40_chan
*d40c
, bool enable
,
754 void __iomem
*addr
= chan_base(d40c
) + reg
;
758 writel((D40_DEACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
))
759 | ~D40_EVENTLINE_MASK(event
), addr
);
764 * The hardware sometimes doesn't register the enable when src and dst
765 * event lines are active on the same logical channel. Retry to ensure
766 * it does. Usually only one retry is sufficient.
770 writel((D40_ACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
))
771 | ~D40_EVENTLINE_MASK(event
), addr
);
773 if (readl(addr
) & D40_EVENTLINE_MASK(event
))
778 dev_dbg(chan2dev(d40c
),
779 "[%s] workaround enable S%cLNK (%d tries)\n",
780 __func__
, reg
== D40_CHAN_REG_SSLNK
? 'S' : 'D',
786 static void d40_config_set_event(struct d40_chan
*d40c
, bool do_enable
)
790 spin_lock_irqsave(&d40c
->phy_chan
->lock
, flags
);
792 /* Enable event line connected to device (or memcpy) */
793 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
794 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
)) {
795 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
797 __d40_config_set_event(d40c
, do_enable
, event
,
801 if (d40c
->dma_cfg
.dir
!= STEDMA40_PERIPH_TO_MEM
) {
802 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
804 __d40_config_set_event(d40c
, do_enable
, event
,
808 spin_unlock_irqrestore(&d40c
->phy_chan
->lock
, flags
);
811 static u32
d40_chan_has_events(struct d40_chan
*d40c
)
813 void __iomem
*chanbase
= chan_base(d40c
);
816 val
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
817 val
|= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
822 static u32
d40_get_prmo(struct d40_chan
*d40c
)
824 static const unsigned int phy_map
[] = {
825 [STEDMA40_PCHAN_BASIC_MODE
]
826 = D40_DREG_PRMO_PCHAN_BASIC
,
827 [STEDMA40_PCHAN_MODULO_MODE
]
828 = D40_DREG_PRMO_PCHAN_MODULO
,
829 [STEDMA40_PCHAN_DOUBLE_DST_MODE
]
830 = D40_DREG_PRMO_PCHAN_DOUBLE_DST
,
832 static const unsigned int log_map
[] = {
833 [STEDMA40_LCHAN_SRC_PHY_DST_LOG
]
834 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG
,
835 [STEDMA40_LCHAN_SRC_LOG_DST_PHY
]
836 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY
,
837 [STEDMA40_LCHAN_SRC_LOG_DST_LOG
]
838 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG
,
841 if (chan_is_physical(d40c
))
842 return phy_map
[d40c
->dma_cfg
.mode_opt
];
844 return log_map
[d40c
->dma_cfg
.mode_opt
];
847 static void d40_config_write(struct d40_chan
*d40c
)
852 /* Odd addresses are even addresses + 4 */
853 addr_base
= (d40c
->phy_chan
->num
% 2) * 4;
854 /* Setup channel mode to logical or physical */
855 var
= ((u32
)(chan_is_logical(d40c
)) + 1) <<
856 D40_CHAN_POS(d40c
->phy_chan
->num
);
857 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMSE
+ addr_base
);
859 /* Setup operational mode option register */
860 var
= d40_get_prmo(d40c
) << D40_CHAN_POS(d40c
->phy_chan
->num
);
862 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMOE
+ addr_base
);
864 if (chan_is_logical(d40c
)) {
865 int lidx
= (d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
)
866 & D40_SREG_ELEM_LOG_LIDX_MASK
;
867 void __iomem
*chanbase
= chan_base(d40c
);
869 /* Set default config for CFG reg */
870 writel(d40c
->src_def_cfg
, chanbase
+ D40_CHAN_REG_SSCFG
);
871 writel(d40c
->dst_def_cfg
, chanbase
+ D40_CHAN_REG_SDCFG
);
873 /* Set LIDX for lcla */
874 writel(lidx
, chanbase
+ D40_CHAN_REG_SSELT
);
875 writel(lidx
, chanbase
+ D40_CHAN_REG_SDELT
);
879 static u32
d40_residue(struct d40_chan
*d40c
)
883 if (chan_is_logical(d40c
))
884 num_elt
= (readl(&d40c
->lcpa
->lcsp2
) & D40_MEM_LCSP2_ECNT_MASK
)
885 >> D40_MEM_LCSP2_ECNT_POS
;
887 u32 val
= readl(chan_base(d40c
) + D40_CHAN_REG_SDELT
);
888 num_elt
= (val
& D40_SREG_ELEM_PHY_ECNT_MASK
)
889 >> D40_SREG_ELEM_PHY_ECNT_POS
;
892 return num_elt
* (1 << d40c
->dma_cfg
.dst_info
.data_width
);
895 static bool d40_tx_is_linked(struct d40_chan
*d40c
)
899 if (chan_is_logical(d40c
))
900 is_link
= readl(&d40c
->lcpa
->lcsp3
) & D40_MEM_LCSP3_DLOS_MASK
;
902 is_link
= readl(chan_base(d40c
) + D40_CHAN_REG_SDLNK
)
903 & D40_SREG_LNK_PHYS_LNK_MASK
;
908 static int d40_pause(struct dma_chan
*chan
)
910 struct d40_chan
*d40c
=
911 container_of(chan
, struct d40_chan
, chan
);
918 spin_lock_irqsave(&d40c
->lock
, flags
);
920 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
922 if (chan_is_logical(d40c
)) {
923 d40_config_set_event(d40c
, false);
924 /* Resume the other logical channels if any */
925 if (d40_chan_has_events(d40c
))
926 res
= d40_channel_execute_command(d40c
,
931 spin_unlock_irqrestore(&d40c
->lock
, flags
);
935 static int d40_resume(struct dma_chan
*chan
)
937 struct d40_chan
*d40c
=
938 container_of(chan
, struct d40_chan
, chan
);
945 spin_lock_irqsave(&d40c
->lock
, flags
);
947 if (d40c
->base
->rev
== 0)
948 if (chan_is_logical(d40c
)) {
949 res
= d40_channel_execute_command(d40c
,
950 D40_DMA_SUSPEND_REQ
);
954 /* If bytes left to transfer or linked tx resume job */
955 if (d40_residue(d40c
) || d40_tx_is_linked(d40c
)) {
957 if (chan_is_logical(d40c
))
958 d40_config_set_event(d40c
, true);
960 res
= d40_channel_execute_command(d40c
, D40_DMA_RUN
);
964 spin_unlock_irqrestore(&d40c
->lock
, flags
);
968 static dma_cookie_t
d40_tx_submit(struct dma_async_tx_descriptor
*tx
)
970 struct d40_chan
*d40c
= container_of(tx
->chan
,
973 struct d40_desc
*d40d
= container_of(tx
, struct d40_desc
, txd
);
976 spin_lock_irqsave(&d40c
->lock
, flags
);
980 if (d40c
->chan
.cookie
< 0)
981 d40c
->chan
.cookie
= 1;
983 d40d
->txd
.cookie
= d40c
->chan
.cookie
;
985 d40_desc_queue(d40c
, d40d
);
987 spin_unlock_irqrestore(&d40c
->lock
, flags
);
992 static int d40_start(struct d40_chan
*d40c
)
994 if (d40c
->base
->rev
== 0) {
997 if (chan_is_logical(d40c
)) {
998 err
= d40_channel_execute_command(d40c
,
999 D40_DMA_SUSPEND_REQ
);
1005 if (chan_is_logical(d40c
))
1006 d40_config_set_event(d40c
, true);
1008 return d40_channel_execute_command(d40c
, D40_DMA_RUN
);
1011 static struct d40_desc
*d40_queue_start(struct d40_chan
*d40c
)
1013 struct d40_desc
*d40d
;
1016 /* Start queued jobs, if any */
1017 d40d
= d40_first_queued(d40c
);
1022 /* Remove from queue */
1023 d40_desc_remove(d40d
);
1025 /* Add to active queue */
1026 d40_desc_submit(d40c
, d40d
);
1028 /* Initiate DMA job */
1029 d40_desc_load(d40c
, d40d
);
1032 err
= d40_start(d40c
);
1041 /* called from interrupt context */
1042 static void dma_tc_handle(struct d40_chan
*d40c
)
1044 struct d40_desc
*d40d
;
1046 /* Get first active entry from list */
1047 d40d
= d40_first_active_get(d40c
);
1052 d40_lcla_free_all(d40c
, d40d
);
1054 if (d40d
->lli_current
< d40d
->lli_len
) {
1055 d40_desc_load(d40c
, d40d
);
1057 (void) d40_start(d40c
);
1061 if (d40_queue_start(d40c
) == NULL
)
1065 tasklet_schedule(&d40c
->tasklet
);
1069 static void dma_tasklet(unsigned long data
)
1071 struct d40_chan
*d40c
= (struct d40_chan
*) data
;
1072 struct d40_desc
*d40d
;
1073 unsigned long flags
;
1074 dma_async_tx_callback callback
;
1075 void *callback_param
;
1077 spin_lock_irqsave(&d40c
->lock
, flags
);
1079 /* Get first active entry from list */
1080 d40d
= d40_first_active_get(d40c
);
1085 d40c
->completed
= d40d
->txd
.cookie
;
1088 * If terminating a channel pending_tx is set to zero.
1089 * This prevents any finished active jobs to return to the client.
1091 if (d40c
->pending_tx
== 0) {
1092 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1096 /* Callback to client */
1097 callback
= d40d
->txd
.callback
;
1098 callback_param
= d40d
->txd
.callback_param
;
1100 if (async_tx_test_ack(&d40d
->txd
)) {
1101 d40_pool_lli_free(d40c
, d40d
);
1102 d40_desc_remove(d40d
);
1103 d40_desc_free(d40c
, d40d
);
1105 if (!d40d
->is_in_client_list
) {
1106 d40_desc_remove(d40d
);
1107 d40_lcla_free_all(d40c
, d40d
);
1108 list_add_tail(&d40d
->node
, &d40c
->client
);
1109 d40d
->is_in_client_list
= true;
1115 if (d40c
->pending_tx
)
1116 tasklet_schedule(&d40c
->tasklet
);
1118 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1120 if (callback
&& (d40d
->txd
.flags
& DMA_PREP_INTERRUPT
))
1121 callback(callback_param
);
1126 /* Rescue manouver if receiving double interrupts */
1127 if (d40c
->pending_tx
> 0)
1129 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1132 static irqreturn_t
d40_handle_interrupt(int irq
, void *data
)
1134 static const struct d40_interrupt_lookup il
[] = {
1135 {D40_DREG_LCTIS0
, D40_DREG_LCICR0
, false, 0},
1136 {D40_DREG_LCTIS1
, D40_DREG_LCICR1
, false, 32},
1137 {D40_DREG_LCTIS2
, D40_DREG_LCICR2
, false, 64},
1138 {D40_DREG_LCTIS3
, D40_DREG_LCICR3
, false, 96},
1139 {D40_DREG_LCEIS0
, D40_DREG_LCICR0
, true, 0},
1140 {D40_DREG_LCEIS1
, D40_DREG_LCICR1
, true, 32},
1141 {D40_DREG_LCEIS2
, D40_DREG_LCICR2
, true, 64},
1142 {D40_DREG_LCEIS3
, D40_DREG_LCICR3
, true, 96},
1143 {D40_DREG_PCTIS
, D40_DREG_PCICR
, false, D40_PHY_CHAN
},
1144 {D40_DREG_PCEIS
, D40_DREG_PCICR
, true, D40_PHY_CHAN
},
1148 u32 regs
[ARRAY_SIZE(il
)];
1152 struct d40_chan
*d40c
;
1153 unsigned long flags
;
1154 struct d40_base
*base
= data
;
1156 spin_lock_irqsave(&base
->interrupt_lock
, flags
);
1158 /* Read interrupt status of both logical and physical channels */
1159 for (i
= 0; i
< ARRAY_SIZE(il
); i
++)
1160 regs
[i
] = readl(base
->virtbase
+ il
[i
].src
);
1164 chan
= find_next_bit((unsigned long *)regs
,
1165 BITS_PER_LONG
* ARRAY_SIZE(il
), chan
+ 1);
1167 /* No more set bits found? */
1168 if (chan
== BITS_PER_LONG
* ARRAY_SIZE(il
))
1171 row
= chan
/ BITS_PER_LONG
;
1172 idx
= chan
& (BITS_PER_LONG
- 1);
1175 writel(1 << idx
, base
->virtbase
+ il
[row
].clr
);
1177 if (il
[row
].offset
== D40_PHY_CHAN
)
1178 d40c
= base
->lookup_phy_chans
[idx
];
1180 d40c
= base
->lookup_log_chans
[il
[row
].offset
+ idx
];
1181 spin_lock(&d40c
->lock
);
1183 if (!il
[row
].is_error
)
1184 dma_tc_handle(d40c
);
1186 d40_err(base
->dev
, "IRQ chan: %ld offset %d idx %d\n",
1187 chan
, il
[row
].offset
, idx
);
1189 spin_unlock(&d40c
->lock
);
1192 spin_unlock_irqrestore(&base
->interrupt_lock
, flags
);
1197 static int d40_validate_conf(struct d40_chan
*d40c
,
1198 struct stedma40_chan_cfg
*conf
)
1201 u32 dst_event_group
= D40_TYPE_TO_GROUP(conf
->dst_dev_type
);
1202 u32 src_event_group
= D40_TYPE_TO_GROUP(conf
->src_dev_type
);
1203 bool is_log
= conf
->mode
== STEDMA40_MODE_LOGICAL
;
1206 chan_err(d40c
, "Invalid direction.\n");
1210 if (conf
->dst_dev_type
!= STEDMA40_DEV_DST_MEMORY
&&
1211 d40c
->base
->plat_data
->dev_tx
[conf
->dst_dev_type
] == 0 &&
1212 d40c
->runtime_addr
== 0) {
1214 chan_err(d40c
, "Invalid TX channel address (%d)\n",
1215 conf
->dst_dev_type
);
1219 if (conf
->src_dev_type
!= STEDMA40_DEV_SRC_MEMORY
&&
1220 d40c
->base
->plat_data
->dev_rx
[conf
->src_dev_type
] == 0 &&
1221 d40c
->runtime_addr
== 0) {
1222 chan_err(d40c
, "Invalid RX channel address (%d)\n",
1223 conf
->src_dev_type
);
1227 if (conf
->dir
== STEDMA40_MEM_TO_PERIPH
&&
1228 dst_event_group
== STEDMA40_DEV_DST_MEMORY
) {
1229 chan_err(d40c
, "Invalid dst\n");
1233 if (conf
->dir
== STEDMA40_PERIPH_TO_MEM
&&
1234 src_event_group
== STEDMA40_DEV_SRC_MEMORY
) {
1235 chan_err(d40c
, "Invalid src\n");
1239 if (src_event_group
== STEDMA40_DEV_SRC_MEMORY
&&
1240 dst_event_group
== STEDMA40_DEV_DST_MEMORY
&& is_log
) {
1241 chan_err(d40c
, "No event line\n");
1245 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
&&
1246 (src_event_group
!= dst_event_group
)) {
1247 chan_err(d40c
, "Invalid event group\n");
1251 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
) {
1253 * DMAC HW supports it. Will be added to this driver,
1254 * in case any dma client requires it.
1256 chan_err(d40c
, "periph to periph not supported\n");
1260 if (d40_psize_2_burst_size(is_log
, conf
->src_info
.psize
) *
1261 (1 << conf
->src_info
.data_width
) !=
1262 d40_psize_2_burst_size(is_log
, conf
->dst_info
.psize
) *
1263 (1 << conf
->dst_info
.data_width
)) {
1265 * The DMAC hardware only supports
1266 * src (burst x width) == dst (burst x width)
1269 chan_err(d40c
, "src (burst x width) != dst (burst x width)\n");
1276 static bool d40_alloc_mask_set(struct d40_phy_res
*phy
, bool is_src
,
1277 int log_event_line
, bool is_log
)
1279 unsigned long flags
;
1280 spin_lock_irqsave(&phy
->lock
, flags
);
1282 /* Physical interrupts are masked per physical full channel */
1283 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1284 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1285 phy
->allocated_dst
= D40_ALLOC_PHY
;
1286 phy
->allocated_src
= D40_ALLOC_PHY
;
1292 /* Logical channel */
1294 if (phy
->allocated_src
== D40_ALLOC_PHY
)
1297 if (phy
->allocated_src
== D40_ALLOC_FREE
)
1298 phy
->allocated_src
= D40_ALLOC_LOG_FREE
;
1300 if (!(phy
->allocated_src
& (1 << log_event_line
))) {
1301 phy
->allocated_src
|= 1 << log_event_line
;
1306 if (phy
->allocated_dst
== D40_ALLOC_PHY
)
1309 if (phy
->allocated_dst
== D40_ALLOC_FREE
)
1310 phy
->allocated_dst
= D40_ALLOC_LOG_FREE
;
1312 if (!(phy
->allocated_dst
& (1 << log_event_line
))) {
1313 phy
->allocated_dst
|= 1 << log_event_line
;
1320 spin_unlock_irqrestore(&phy
->lock
, flags
);
1323 spin_unlock_irqrestore(&phy
->lock
, flags
);
1327 static bool d40_alloc_mask_free(struct d40_phy_res
*phy
, bool is_src
,
1330 unsigned long flags
;
1331 bool is_free
= false;
1333 spin_lock_irqsave(&phy
->lock
, flags
);
1334 if (!log_event_line
) {
1335 phy
->allocated_dst
= D40_ALLOC_FREE
;
1336 phy
->allocated_src
= D40_ALLOC_FREE
;
1341 /* Logical channel */
1343 phy
->allocated_src
&= ~(1 << log_event_line
);
1344 if (phy
->allocated_src
== D40_ALLOC_LOG_FREE
)
1345 phy
->allocated_src
= D40_ALLOC_FREE
;
1347 phy
->allocated_dst
&= ~(1 << log_event_line
);
1348 if (phy
->allocated_dst
== D40_ALLOC_LOG_FREE
)
1349 phy
->allocated_dst
= D40_ALLOC_FREE
;
1352 is_free
= ((phy
->allocated_src
| phy
->allocated_dst
) ==
1356 spin_unlock_irqrestore(&phy
->lock
, flags
);
1361 static int d40_allocate_channel(struct d40_chan
*d40c
)
1366 struct d40_phy_res
*phys
;
1371 bool is_log
= d40c
->dma_cfg
.mode
== STEDMA40_MODE_LOGICAL
;
1373 phys
= d40c
->base
->phy_res
;
1375 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1376 dev_type
= d40c
->dma_cfg
.src_dev_type
;
1377 log_num
= 2 * dev_type
;
1379 } else if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1380 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1381 /* dst event lines are used for logical memcpy */
1382 dev_type
= d40c
->dma_cfg
.dst_dev_type
;
1383 log_num
= 2 * dev_type
+ 1;
1388 event_group
= D40_TYPE_TO_GROUP(dev_type
);
1389 event_line
= D40_TYPE_TO_EVENT(dev_type
);
1392 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1393 /* Find physical half channel */
1394 for (i
= 0; i
< d40c
->base
->num_phy_chans
; i
++) {
1396 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1401 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1402 int phy_num
= j
+ event_group
* 2;
1403 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1404 if (d40_alloc_mask_set(&phys
[i
],
1413 d40c
->phy_chan
= &phys
[i
];
1414 d40c
->log_num
= D40_PHY_CHAN
;
1420 /* Find logical channel */
1421 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1422 int phy_num
= j
+ event_group
* 2;
1424 * Spread logical channels across all available physical rather
1425 * than pack every logical channel at the first available phy
1429 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1430 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1431 event_line
, is_log
))
1435 for (i
= phy_num
+ 1; i
>= phy_num
; i
--) {
1436 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1437 event_line
, is_log
))
1445 d40c
->phy_chan
= &phys
[i
];
1446 d40c
->log_num
= log_num
;
1450 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = d40c
;
1452 d40c
->base
->lookup_phy_chans
[d40c
->phy_chan
->num
] = d40c
;
1458 static int d40_config_memcpy(struct d40_chan
*d40c
)
1460 dma_cap_mask_t cap
= d40c
->chan
.device
->cap_mask
;
1462 if (dma_has_cap(DMA_MEMCPY
, cap
) && !dma_has_cap(DMA_SLAVE
, cap
)) {
1463 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_log
;
1464 d40c
->dma_cfg
.src_dev_type
= STEDMA40_DEV_SRC_MEMORY
;
1465 d40c
->dma_cfg
.dst_dev_type
= d40c
->base
->plat_data
->
1466 memcpy
[d40c
->chan
.chan_id
];
1468 } else if (dma_has_cap(DMA_MEMCPY
, cap
) &&
1469 dma_has_cap(DMA_SLAVE
, cap
)) {
1470 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_phy
;
1472 chan_err(d40c
, "No memcpy\n");
1480 static int d40_free_dma(struct d40_chan
*d40c
)
1485 struct d40_phy_res
*phy
= d40c
->phy_chan
;
1488 struct d40_desc
*_d
;
1491 /* Terminate all queued and active transfers */
1494 /* Release client owned descriptors */
1495 if (!list_empty(&d40c
->client
))
1496 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
) {
1497 d40_pool_lli_free(d40c
, d
);
1499 d40_desc_free(d40c
, d
);
1503 chan_err(d40c
, "phy == null\n");
1507 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1508 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1509 chan_err(d40c
, "channel already free\n");
1513 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1514 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1515 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1517 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1518 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1521 chan_err(d40c
, "Unknown direction\n");
1525 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1527 chan_err(d40c
, "suspend failed\n");
1531 if (chan_is_logical(d40c
)) {
1532 /* Release logical channel, deactivate the event line */
1534 d40_config_set_event(d40c
, false);
1535 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = NULL
;
1538 * Check if there are more logical allocation
1539 * on this phy channel.
1541 if (!d40_alloc_mask_free(phy
, is_src
, event
)) {
1542 /* Resume the other logical channels if any */
1543 if (d40_chan_has_events(d40c
)) {
1544 res
= d40_channel_execute_command(d40c
,
1548 "Executing RUN command\n");
1555 (void) d40_alloc_mask_free(phy
, is_src
, 0);
1558 /* Release physical channel */
1559 res
= d40_channel_execute_command(d40c
, D40_DMA_STOP
);
1561 chan_err(d40c
, "Failed to stop channel\n");
1564 d40c
->phy_chan
= NULL
;
1565 d40c
->configured
= false;
1566 d40c
->base
->lookup_phy_chans
[phy
->num
] = NULL
;
1571 static bool d40_is_paused(struct d40_chan
*d40c
)
1573 void __iomem
*chanbase
= chan_base(d40c
);
1574 bool is_paused
= false;
1575 unsigned long flags
;
1576 void __iomem
*active_reg
;
1580 spin_lock_irqsave(&d40c
->lock
, flags
);
1582 if (chan_is_physical(d40c
)) {
1583 if (d40c
->phy_chan
->num
% 2 == 0)
1584 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
1586 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
1588 status
= (readl(active_reg
) &
1589 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
1590 D40_CHAN_POS(d40c
->phy_chan
->num
);
1591 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
1597 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1598 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1599 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1600 status
= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
1601 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1602 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1603 status
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
1605 chan_err(d40c
, "Unknown direction\n");
1609 status
= (status
& D40_EVENTLINE_MASK(event
)) >>
1610 D40_EVENTLINE_POS(event
);
1612 if (status
!= D40_DMA_RUN
)
1615 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1621 static u32
stedma40_residue(struct dma_chan
*chan
)
1623 struct d40_chan
*d40c
=
1624 container_of(chan
, struct d40_chan
, chan
);
1626 unsigned long flags
;
1628 spin_lock_irqsave(&d40c
->lock
, flags
);
1629 bytes_left
= d40_residue(d40c
);
1630 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1636 d40_prep_sg_log(struct d40_chan
*chan
, struct d40_desc
*desc
,
1637 struct scatterlist
*sg_src
, struct scatterlist
*sg_dst
,
1638 unsigned int sg_len
, enum dma_data_direction direction
,
1639 dma_addr_t dev_addr
)
1641 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
1642 struct stedma40_half_channel_info
*src_info
= &cfg
->src_info
;
1643 struct stedma40_half_channel_info
*dst_info
= &cfg
->dst_info
;
1645 if (direction
== DMA_NONE
) {
1647 (void) d40_log_sg_to_lli(sg_src
, sg_len
,
1649 chan
->log_def
.lcsp1
,
1650 src_info
->data_width
,
1651 dst_info
->data_width
);
1653 (void) d40_log_sg_to_lli(sg_dst
, sg_len
,
1655 chan
->log_def
.lcsp3
,
1656 dst_info
->data_width
,
1657 src_info
->data_width
);
1659 unsigned int total_size
;
1661 total_size
= d40_log_sg_to_dev(sg_src
, sg_len
,
1664 src_info
->data_width
,
1665 dst_info
->data_width
,
1666 direction
, dev_addr
);
1675 d40_prep_sg_phy(struct d40_chan
*chan
, struct d40_desc
*desc
,
1676 struct scatterlist
*sg_src
, struct scatterlist
*sg_dst
,
1677 unsigned int sg_len
, enum dma_data_direction direction
,
1678 dma_addr_t dev_addr
)
1680 dma_addr_t src_dev_addr
= direction
== DMA_FROM_DEVICE
? dev_addr
: 0;
1681 dma_addr_t dst_dev_addr
= direction
== DMA_TO_DEVICE
? dev_addr
: 0;
1682 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
1683 struct stedma40_half_channel_info
*src_info
= &cfg
->src_info
;
1684 struct stedma40_half_channel_info
*dst_info
= &cfg
->dst_info
;
1687 ret
= d40_phy_sg_to_lli(sg_src
, sg_len
, src_dev_addr
,
1689 virt_to_phys(desc
->lli_phy
.src
),
1691 src_info
->data_width
,
1692 dst_info
->data_width
,
1695 ret
= d40_phy_sg_to_lli(sg_dst
, sg_len
, dst_dev_addr
,
1697 virt_to_phys(desc
->lli_phy
.dst
),
1699 dst_info
->data_width
,
1700 src_info
->data_width
,
1703 dma_sync_single_for_device(chan
->base
->dev
, desc
->lli_pool
.dma_addr
,
1704 desc
->lli_pool
.size
, DMA_TO_DEVICE
);
1706 return ret
< 0 ? ret
: 0;
1710 static struct d40_desc
*
1711 d40_prep_desc(struct d40_chan
*chan
, struct scatterlist
*sg
,
1712 unsigned int sg_len
, unsigned long dma_flags
)
1714 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
1715 struct d40_desc
*desc
;
1718 desc
= d40_desc_get(chan
);
1722 desc
->lli_len
= d40_sg_2_dmalen(sg
, sg_len
, cfg
->src_info
.data_width
,
1723 cfg
->dst_info
.data_width
);
1724 if (desc
->lli_len
< 0) {
1725 chan_err(chan
, "Unaligned size\n");
1729 ret
= d40_pool_lli_alloc(chan
, desc
, desc
->lli_len
);
1731 chan_err(chan
, "Could not allocate lli\n");
1736 desc
->lli_current
= 0;
1737 desc
->txd
.flags
= dma_flags
;
1738 desc
->txd
.tx_submit
= d40_tx_submit
;
1740 dma_async_tx_descriptor_init(&desc
->txd
, &chan
->chan
);
1745 d40_desc_free(chan
, desc
);
1750 d40_get_dev_addr(struct d40_chan
*chan
, enum dma_data_direction direction
)
1752 struct stedma40_platform_data
*plat
= chan
->base
->plat_data
;
1753 struct stedma40_chan_cfg
*cfg
= &chan
->dma_cfg
;
1756 if (chan
->runtime_addr
)
1757 return chan
->runtime_addr
;
1759 if (direction
== DMA_FROM_DEVICE
)
1760 addr
= plat
->dev_rx
[cfg
->src_dev_type
];
1761 else if (direction
== DMA_TO_DEVICE
)
1762 addr
= plat
->dev_tx
[cfg
->dst_dev_type
];
1767 static struct dma_async_tx_descriptor
*
1768 d40_prep_sg(struct dma_chan
*dchan
, struct scatterlist
*sg_src
,
1769 struct scatterlist
*sg_dst
, unsigned int sg_len
,
1770 enum dma_data_direction direction
, unsigned long dma_flags
)
1772 struct d40_chan
*chan
= container_of(dchan
, struct d40_chan
, chan
);
1773 dma_addr_t dev_addr
= 0;
1774 struct d40_desc
*desc
;
1775 unsigned long flags
;
1778 if (!chan
->phy_chan
) {
1779 chan_err(chan
, "Cannot prepare unallocated channel\n");
1783 spin_lock_irqsave(&chan
->lock
, flags
);
1785 desc
= d40_prep_desc(chan
, sg_src
, sg_len
, dma_flags
);
1789 if (direction
!= DMA_NONE
)
1790 dev_addr
= d40_get_dev_addr(chan
, direction
);
1792 if (chan_is_logical(chan
))
1793 ret
= d40_prep_sg_log(chan
, desc
, sg_src
, sg_dst
,
1794 sg_len
, direction
, dev_addr
);
1796 ret
= d40_prep_sg_phy(chan
, desc
, sg_src
, sg_dst
,
1797 sg_len
, direction
, dev_addr
);
1800 chan_err(chan
, "Failed to prepare %s sg job: %d\n",
1801 chan_is_logical(chan
) ? "log" : "phy", ret
);
1805 spin_unlock_irqrestore(&chan
->lock
, flags
);
1811 d40_desc_free(chan
, desc
);
1812 spin_unlock_irqrestore(&chan
->lock
, flags
);
1816 bool stedma40_filter(struct dma_chan
*chan
, void *data
)
1818 struct stedma40_chan_cfg
*info
= data
;
1819 struct d40_chan
*d40c
=
1820 container_of(chan
, struct d40_chan
, chan
);
1824 err
= d40_validate_conf(d40c
, info
);
1826 d40c
->dma_cfg
= *info
;
1828 err
= d40_config_memcpy(d40c
);
1831 d40c
->configured
= true;
1835 EXPORT_SYMBOL(stedma40_filter
);
1837 static void __d40_set_prio_rt(struct d40_chan
*d40c
, int dev_type
, bool src
)
1839 bool realtime
= d40c
->dma_cfg
.realtime
;
1840 bool highprio
= d40c
->dma_cfg
.high_priority
;
1841 u32 prioreg
= highprio
? D40_DREG_PSEG1
: D40_DREG_PCEG1
;
1842 u32 rtreg
= realtime
? D40_DREG_RSEG1
: D40_DREG_RCEG1
;
1843 u32 event
= D40_TYPE_TO_EVENT(dev_type
);
1844 u32 group
= D40_TYPE_TO_GROUP(dev_type
);
1845 u32 bit
= 1 << event
;
1847 /* Destination event lines are stored in the upper halfword */
1851 writel(bit
, d40c
->base
->virtbase
+ prioreg
+ group
* 4);
1852 writel(bit
, d40c
->base
->virtbase
+ rtreg
+ group
* 4);
1855 static void d40_set_prio_realtime(struct d40_chan
*d40c
)
1857 if (d40c
->base
->rev
< 3)
1860 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
1861 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
1862 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.src_dev_type
, true);
1864 if ((d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
) ||
1865 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
1866 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.dst_dev_type
, false);
1869 /* DMA ENGINE functions */
1870 static int d40_alloc_chan_resources(struct dma_chan
*chan
)
1873 unsigned long flags
;
1874 struct d40_chan
*d40c
=
1875 container_of(chan
, struct d40_chan
, chan
);
1877 spin_lock_irqsave(&d40c
->lock
, flags
);
1879 d40c
->completed
= chan
->cookie
= 1;
1881 /* If no dma configuration is set use default configuration (memcpy) */
1882 if (!d40c
->configured
) {
1883 err
= d40_config_memcpy(d40c
);
1885 chan_err(d40c
, "Failed to configure memcpy channel\n");
1889 is_free_phy
= (d40c
->phy_chan
== NULL
);
1891 err
= d40_allocate_channel(d40c
);
1893 chan_err(d40c
, "Failed to allocate channel\n");
1897 /* Fill in basic CFG register values */
1898 d40_phy_cfg(&d40c
->dma_cfg
, &d40c
->src_def_cfg
,
1899 &d40c
->dst_def_cfg
, chan_is_logical(d40c
));
1901 d40_set_prio_realtime(d40c
);
1903 if (chan_is_logical(d40c
)) {
1904 d40_log_cfg(&d40c
->dma_cfg
,
1905 &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
1907 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
1908 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1909 d40c
->dma_cfg
.src_dev_type
* D40_LCPA_CHAN_SIZE
;
1911 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1912 d40c
->dma_cfg
.dst_dev_type
*
1913 D40_LCPA_CHAN_SIZE
+ D40_LCPA_CHAN_DST_DELTA
;
1917 * Only write channel configuration to the DMA if the physical
1918 * resource is free. In case of multiple logical channels
1919 * on the same physical resource, only the first write is necessary.
1922 d40_config_write(d40c
);
1924 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1928 static void d40_free_chan_resources(struct dma_chan
*chan
)
1930 struct d40_chan
*d40c
=
1931 container_of(chan
, struct d40_chan
, chan
);
1933 unsigned long flags
;
1935 if (d40c
->phy_chan
== NULL
) {
1936 chan_err(d40c
, "Cannot free unallocated channel\n");
1941 spin_lock_irqsave(&d40c
->lock
, flags
);
1943 err
= d40_free_dma(d40c
);
1946 chan_err(d40c
, "Failed to free channel\n");
1947 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1950 static struct dma_async_tx_descriptor
*d40_prep_memcpy(struct dma_chan
*chan
,
1954 unsigned long dma_flags
)
1956 struct scatterlist dst_sg
;
1957 struct scatterlist src_sg
;
1959 sg_init_table(&dst_sg
, 1);
1960 sg_init_table(&src_sg
, 1);
1962 sg_dma_address(&dst_sg
) = dst
;
1963 sg_dma_address(&src_sg
) = src
;
1965 sg_dma_len(&dst_sg
) = size
;
1966 sg_dma_len(&src_sg
) = size
;
1968 return d40_prep_sg(chan
, &src_sg
, &dst_sg
, 1, DMA_NONE
, dma_flags
);
1971 static struct dma_async_tx_descriptor
*
1972 d40_prep_memcpy_sg(struct dma_chan
*chan
,
1973 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
1974 struct scatterlist
*src_sg
, unsigned int src_nents
,
1975 unsigned long dma_flags
)
1977 if (dst_nents
!= src_nents
)
1980 return d40_prep_sg(chan
, src_sg
, dst_sg
, src_nents
, DMA_NONE
, dma_flags
);
1983 static struct dma_async_tx_descriptor
*d40_prep_slave_sg(struct dma_chan
*chan
,
1984 struct scatterlist
*sgl
,
1985 unsigned int sg_len
,
1986 enum dma_data_direction direction
,
1987 unsigned long dma_flags
)
1989 if (direction
!= DMA_FROM_DEVICE
&& direction
!= DMA_TO_DEVICE
)
1992 return d40_prep_sg(chan
, sgl
, sgl
, sg_len
, direction
, dma_flags
);
1995 static enum dma_status
d40_tx_status(struct dma_chan
*chan
,
1996 dma_cookie_t cookie
,
1997 struct dma_tx_state
*txstate
)
1999 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2000 dma_cookie_t last_used
;
2001 dma_cookie_t last_complete
;
2004 if (d40c
->phy_chan
== NULL
) {
2005 chan_err(d40c
, "Cannot read status of unallocated channel\n");
2009 last_complete
= d40c
->completed
;
2010 last_used
= chan
->cookie
;
2012 if (d40_is_paused(d40c
))
2015 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
2017 dma_set_tx_state(txstate
, last_complete
, last_used
,
2018 stedma40_residue(chan
));
2023 static void d40_issue_pending(struct dma_chan
*chan
)
2025 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2026 unsigned long flags
;
2028 if (d40c
->phy_chan
== NULL
) {
2029 chan_err(d40c
, "Channel is not allocated!\n");
2033 spin_lock_irqsave(&d40c
->lock
, flags
);
2035 /* Busy means that pending jobs are already being processed */
2037 (void) d40_queue_start(d40c
);
2039 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2042 /* Runtime reconfiguration extension */
2043 static void d40_set_runtime_config(struct dma_chan
*chan
,
2044 struct dma_slave_config
*config
)
2046 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2047 struct stedma40_chan_cfg
*cfg
= &d40c
->dma_cfg
;
2048 enum dma_slave_buswidth config_addr_width
;
2049 dma_addr_t config_addr
;
2050 u32 config_maxburst
;
2051 enum stedma40_periph_data_width addr_width
;
2054 if (config
->direction
== DMA_FROM_DEVICE
) {
2055 dma_addr_t dev_addr_rx
=
2056 d40c
->base
->plat_data
->dev_rx
[cfg
->src_dev_type
];
2058 config_addr
= config
->src_addr
;
2060 dev_dbg(d40c
->base
->dev
,
2061 "channel has a pre-wired RX address %08x "
2062 "overriding with %08x\n",
2063 dev_addr_rx
, config_addr
);
2064 if (cfg
->dir
!= STEDMA40_PERIPH_TO_MEM
)
2065 dev_dbg(d40c
->base
->dev
,
2066 "channel was not configured for peripheral "
2067 "to memory transfer (%d) overriding\n",
2069 cfg
->dir
= STEDMA40_PERIPH_TO_MEM
;
2071 config_addr_width
= config
->src_addr_width
;
2072 config_maxburst
= config
->src_maxburst
;
2074 } else if (config
->direction
== DMA_TO_DEVICE
) {
2075 dma_addr_t dev_addr_tx
=
2076 d40c
->base
->plat_data
->dev_tx
[cfg
->dst_dev_type
];
2078 config_addr
= config
->dst_addr
;
2080 dev_dbg(d40c
->base
->dev
,
2081 "channel has a pre-wired TX address %08x "
2082 "overriding with %08x\n",
2083 dev_addr_tx
, config_addr
);
2084 if (cfg
->dir
!= STEDMA40_MEM_TO_PERIPH
)
2085 dev_dbg(d40c
->base
->dev
,
2086 "channel was not configured for memory "
2087 "to peripheral transfer (%d) overriding\n",
2089 cfg
->dir
= STEDMA40_MEM_TO_PERIPH
;
2091 config_addr_width
= config
->dst_addr_width
;
2092 config_maxburst
= config
->dst_maxburst
;
2095 dev_err(d40c
->base
->dev
,
2096 "unrecognized channel direction %d\n",
2101 switch (config_addr_width
) {
2102 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
2103 addr_width
= STEDMA40_BYTE_WIDTH
;
2105 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
2106 addr_width
= STEDMA40_HALFWORD_WIDTH
;
2108 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
2109 addr_width
= STEDMA40_WORD_WIDTH
;
2111 case DMA_SLAVE_BUSWIDTH_8_BYTES
:
2112 addr_width
= STEDMA40_DOUBLEWORD_WIDTH
;
2115 dev_err(d40c
->base
->dev
,
2116 "illegal peripheral address width "
2118 config
->src_addr_width
);
2122 if (chan_is_logical(d40c
)) {
2123 if (config_maxburst
>= 16)
2124 psize
= STEDMA40_PSIZE_LOG_16
;
2125 else if (config_maxburst
>= 8)
2126 psize
= STEDMA40_PSIZE_LOG_8
;
2127 else if (config_maxburst
>= 4)
2128 psize
= STEDMA40_PSIZE_LOG_4
;
2130 psize
= STEDMA40_PSIZE_LOG_1
;
2132 if (config_maxburst
>= 16)
2133 psize
= STEDMA40_PSIZE_PHY_16
;
2134 else if (config_maxburst
>= 8)
2135 psize
= STEDMA40_PSIZE_PHY_8
;
2136 else if (config_maxburst
>= 4)
2137 psize
= STEDMA40_PSIZE_PHY_4
;
2138 else if (config_maxburst
>= 2)
2139 psize
= STEDMA40_PSIZE_PHY_2
;
2141 psize
= STEDMA40_PSIZE_PHY_1
;
2144 /* Set up all the endpoint configs */
2145 cfg
->src_info
.data_width
= addr_width
;
2146 cfg
->src_info
.psize
= psize
;
2147 cfg
->src_info
.big_endian
= false;
2148 cfg
->src_info
.flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2149 cfg
->dst_info
.data_width
= addr_width
;
2150 cfg
->dst_info
.psize
= psize
;
2151 cfg
->dst_info
.big_endian
= false;
2152 cfg
->dst_info
.flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2154 /* Fill in register values */
2155 if (chan_is_logical(d40c
))
2156 d40_log_cfg(cfg
, &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
2158 d40_phy_cfg(cfg
, &d40c
->src_def_cfg
,
2159 &d40c
->dst_def_cfg
, false);
2161 /* These settings will take precedence later */
2162 d40c
->runtime_addr
= config_addr
;
2163 d40c
->runtime_direction
= config
->direction
;
2164 dev_dbg(d40c
->base
->dev
,
2165 "configured channel %s for %s, data width %d, "
2166 "maxburst %d bytes, LE, no flow control\n",
2167 dma_chan_name(chan
),
2168 (config
->direction
== DMA_FROM_DEVICE
) ? "RX" : "TX",
2173 static int d40_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
2176 unsigned long flags
;
2177 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2179 if (d40c
->phy_chan
== NULL
) {
2180 chan_err(d40c
, "Channel is not allocated!\n");
2185 case DMA_TERMINATE_ALL
:
2186 spin_lock_irqsave(&d40c
->lock
, flags
);
2188 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2191 return d40_pause(chan
);
2193 return d40_resume(chan
);
2194 case DMA_SLAVE_CONFIG
:
2195 d40_set_runtime_config(chan
,
2196 (struct dma_slave_config
*) arg
);
2202 /* Other commands are unimplemented */
2206 /* Initialization functions */
2208 static void __init
d40_chan_init(struct d40_base
*base
, struct dma_device
*dma
,
2209 struct d40_chan
*chans
, int offset
,
2213 struct d40_chan
*d40c
;
2215 INIT_LIST_HEAD(&dma
->channels
);
2217 for (i
= offset
; i
< offset
+ num_chans
; i
++) {
2220 d40c
->chan
.device
= dma
;
2222 spin_lock_init(&d40c
->lock
);
2224 d40c
->log_num
= D40_PHY_CHAN
;
2226 INIT_LIST_HEAD(&d40c
->active
);
2227 INIT_LIST_HEAD(&d40c
->queue
);
2228 INIT_LIST_HEAD(&d40c
->client
);
2230 tasklet_init(&d40c
->tasklet
, dma_tasklet
,
2231 (unsigned long) d40c
);
2233 list_add_tail(&d40c
->chan
.device_node
,
2238 static int __init
d40_dmaengine_init(struct d40_base
*base
,
2239 int num_reserved_chans
)
2243 d40_chan_init(base
, &base
->dma_slave
, base
->log_chans
,
2244 0, base
->num_log_chans
);
2246 dma_cap_zero(base
->dma_slave
.cap_mask
);
2247 dma_cap_set(DMA_SLAVE
, base
->dma_slave
.cap_mask
);
2249 base
->dma_slave
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2250 base
->dma_slave
.device_free_chan_resources
= d40_free_chan_resources
;
2251 base
->dma_slave
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2252 base
->dma_slave
.device_prep_dma_sg
= d40_prep_memcpy_sg
;
2253 base
->dma_slave
.device_prep_slave_sg
= d40_prep_slave_sg
;
2254 base
->dma_slave
.device_tx_status
= d40_tx_status
;
2255 base
->dma_slave
.device_issue_pending
= d40_issue_pending
;
2256 base
->dma_slave
.device_control
= d40_control
;
2257 base
->dma_slave
.dev
= base
->dev
;
2259 err
= dma_async_device_register(&base
->dma_slave
);
2262 d40_err(base
->dev
, "Failed to register slave channels\n");
2266 d40_chan_init(base
, &base
->dma_memcpy
, base
->log_chans
,
2267 base
->num_log_chans
, base
->plat_data
->memcpy_len
);
2269 dma_cap_zero(base
->dma_memcpy
.cap_mask
);
2270 dma_cap_set(DMA_MEMCPY
, base
->dma_memcpy
.cap_mask
);
2271 dma_cap_set(DMA_SG
, base
->dma_slave
.cap_mask
);
2273 base
->dma_memcpy
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2274 base
->dma_memcpy
.device_free_chan_resources
= d40_free_chan_resources
;
2275 base
->dma_memcpy
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2276 base
->dma_slave
.device_prep_dma_sg
= d40_prep_memcpy_sg
;
2277 base
->dma_memcpy
.device_prep_slave_sg
= d40_prep_slave_sg
;
2278 base
->dma_memcpy
.device_tx_status
= d40_tx_status
;
2279 base
->dma_memcpy
.device_issue_pending
= d40_issue_pending
;
2280 base
->dma_memcpy
.device_control
= d40_control
;
2281 base
->dma_memcpy
.dev
= base
->dev
;
2283 * This controller can only access address at even
2284 * 32bit boundaries, i.e. 2^2
2286 base
->dma_memcpy
.copy_align
= 2;
2288 err
= dma_async_device_register(&base
->dma_memcpy
);
2292 "Failed to regsiter memcpy only channels\n");
2296 d40_chan_init(base
, &base
->dma_both
, base
->phy_chans
,
2297 0, num_reserved_chans
);
2299 dma_cap_zero(base
->dma_both
.cap_mask
);
2300 dma_cap_set(DMA_SLAVE
, base
->dma_both
.cap_mask
);
2301 dma_cap_set(DMA_MEMCPY
, base
->dma_both
.cap_mask
);
2302 dma_cap_set(DMA_SG
, base
->dma_slave
.cap_mask
);
2304 base
->dma_both
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2305 base
->dma_both
.device_free_chan_resources
= d40_free_chan_resources
;
2306 base
->dma_both
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2307 base
->dma_slave
.device_prep_dma_sg
= d40_prep_memcpy_sg
;
2308 base
->dma_both
.device_prep_slave_sg
= d40_prep_slave_sg
;
2309 base
->dma_both
.device_tx_status
= d40_tx_status
;
2310 base
->dma_both
.device_issue_pending
= d40_issue_pending
;
2311 base
->dma_both
.device_control
= d40_control
;
2312 base
->dma_both
.dev
= base
->dev
;
2313 base
->dma_both
.copy_align
= 2;
2314 err
= dma_async_device_register(&base
->dma_both
);
2318 "Failed to register logical and physical capable channels\n");
2323 dma_async_device_unregister(&base
->dma_memcpy
);
2325 dma_async_device_unregister(&base
->dma_slave
);
2330 /* Initialization functions. */
2332 static int __init
d40_phy_res_init(struct d40_base
*base
)
2335 int num_phy_chans_avail
= 0;
2337 int odd_even_bit
= -2;
2339 val
[0] = readl(base
->virtbase
+ D40_DREG_PRSME
);
2340 val
[1] = readl(base
->virtbase
+ D40_DREG_PRSMO
);
2342 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2343 base
->phy_res
[i
].num
= i
;
2344 odd_even_bit
+= 2 * ((i
% 2) == 0);
2345 if (((val
[i
% 2] >> odd_even_bit
) & 3) == 1) {
2346 /* Mark security only channels as occupied */
2347 base
->phy_res
[i
].allocated_src
= D40_ALLOC_PHY
;
2348 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_PHY
;
2350 base
->phy_res
[i
].allocated_src
= D40_ALLOC_FREE
;
2351 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_FREE
;
2352 num_phy_chans_avail
++;
2354 spin_lock_init(&base
->phy_res
[i
].lock
);
2357 /* Mark disabled channels as occupied */
2358 for (i
= 0; base
->plat_data
->disabled_channels
[i
] != -1; i
++) {
2359 int chan
= base
->plat_data
->disabled_channels
[i
];
2361 base
->phy_res
[chan
].allocated_src
= D40_ALLOC_PHY
;
2362 base
->phy_res
[chan
].allocated_dst
= D40_ALLOC_PHY
;
2363 num_phy_chans_avail
--;
2366 dev_info(base
->dev
, "%d of %d physical DMA channels available\n",
2367 num_phy_chans_avail
, base
->num_phy_chans
);
2369 /* Verify settings extended vs standard */
2370 val
[0] = readl(base
->virtbase
+ D40_DREG_PRTYP
);
2372 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2374 if (base
->phy_res
[i
].allocated_src
== D40_ALLOC_FREE
&&
2375 (val
[0] & 0x3) != 1)
2377 "[%s] INFO: channel %d is misconfigured (%d)\n",
2378 __func__
, i
, val
[0] & 0x3);
2380 val
[0] = val
[0] >> 2;
2383 return num_phy_chans_avail
;
2386 static struct d40_base
* __init
d40_hw_detect_init(struct platform_device
*pdev
)
2388 static const struct d40_reg_val dma_id_regs
[] = {
2390 { .reg
= D40_DREG_PERIPHID0
, .val
= 0x0040},
2391 { .reg
= D40_DREG_PERIPHID1
, .val
= 0x0000},
2393 * D40_DREG_PERIPHID2 Depends on HW revision:
2394 * DB8500ed has 0x0008,
2396 * DB8500v1 has 0x0028
2397 * DB8500v2 has 0x0038
2399 { .reg
= D40_DREG_PERIPHID3
, .val
= 0x0000},
2402 { .reg
= D40_DREG_CELLID0
, .val
= 0x000d},
2403 { .reg
= D40_DREG_CELLID1
, .val
= 0x00f0},
2404 { .reg
= D40_DREG_CELLID2
, .val
= 0x0005},
2405 { .reg
= D40_DREG_CELLID3
, .val
= 0x00b1}
2407 struct stedma40_platform_data
*plat_data
;
2408 struct clk
*clk
= NULL
;
2409 void __iomem
*virtbase
= NULL
;
2410 struct resource
*res
= NULL
;
2411 struct d40_base
*base
= NULL
;
2412 int num_log_chans
= 0;
2418 clk
= clk_get(&pdev
->dev
, NULL
);
2421 d40_err(&pdev
->dev
, "No matching clock found\n");
2427 /* Get IO for DMAC base address */
2428 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "base");
2432 if (request_mem_region(res
->start
, resource_size(res
),
2433 D40_NAME
" I/O base") == NULL
)
2436 virtbase
= ioremap(res
->start
, resource_size(res
));
2440 /* HW version check */
2441 for (i
= 0; i
< ARRAY_SIZE(dma_id_regs
); i
++) {
2442 if (dma_id_regs
[i
].val
!=
2443 readl(virtbase
+ dma_id_regs
[i
].reg
)) {
2445 "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2448 readl(virtbase
+ dma_id_regs
[i
].reg
));
2453 /* Get silicon revision and designer */
2454 val
= readl(virtbase
+ D40_DREG_PERIPHID2
);
2456 if ((val
& D40_DREG_PERIPHID2_DESIGNER_MASK
) !=
2458 d40_err(&pdev
->dev
, "Unknown designer! Got %x wanted %x\n",
2459 val
& D40_DREG_PERIPHID2_DESIGNER_MASK
,
2464 rev
= (val
& D40_DREG_PERIPHID2_REV_MASK
) >>
2465 D40_DREG_PERIPHID2_REV_POS
;
2467 /* The number of physical channels on this HW */
2468 num_phy_chans
= 4 * (readl(virtbase
+ D40_DREG_ICFG
) & 0x7) + 4;
2470 dev_info(&pdev
->dev
, "hardware revision: %d @ 0x%x\n",
2473 plat_data
= pdev
->dev
.platform_data
;
2475 /* Count the number of logical channels in use */
2476 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2477 if (plat_data
->dev_rx
[i
] != 0)
2480 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2481 if (plat_data
->dev_tx
[i
] != 0)
2484 base
= kzalloc(ALIGN(sizeof(struct d40_base
), 4) +
2485 (num_phy_chans
+ num_log_chans
+ plat_data
->memcpy_len
) *
2486 sizeof(struct d40_chan
), GFP_KERNEL
);
2489 d40_err(&pdev
->dev
, "Out of memory\n");
2495 base
->num_phy_chans
= num_phy_chans
;
2496 base
->num_log_chans
= num_log_chans
;
2497 base
->phy_start
= res
->start
;
2498 base
->phy_size
= resource_size(res
);
2499 base
->virtbase
= virtbase
;
2500 base
->plat_data
= plat_data
;
2501 base
->dev
= &pdev
->dev
;
2502 base
->phy_chans
= ((void *)base
) + ALIGN(sizeof(struct d40_base
), 4);
2503 base
->log_chans
= &base
->phy_chans
[num_phy_chans
];
2505 base
->phy_res
= kzalloc(num_phy_chans
* sizeof(struct d40_phy_res
),
2510 base
->lookup_phy_chans
= kzalloc(num_phy_chans
*
2511 sizeof(struct d40_chan
*),
2513 if (!base
->lookup_phy_chans
)
2516 if (num_log_chans
+ plat_data
->memcpy_len
) {
2518 * The max number of logical channels are event lines for all
2519 * src devices and dst devices
2521 base
->lookup_log_chans
= kzalloc(plat_data
->dev_len
* 2 *
2522 sizeof(struct d40_chan
*),
2524 if (!base
->lookup_log_chans
)
2528 base
->lcla_pool
.alloc_map
= kzalloc(num_phy_chans
*
2529 sizeof(struct d40_desc
*) *
2530 D40_LCLA_LINK_PER_EVENT_GRP
,
2532 if (!base
->lcla_pool
.alloc_map
)
2535 base
->desc_slab
= kmem_cache_create(D40_NAME
, sizeof(struct d40_desc
),
2536 0, SLAB_HWCACHE_ALIGN
,
2538 if (base
->desc_slab
== NULL
)
2551 release_mem_region(res
->start
,
2552 resource_size(res
));
2557 kfree(base
->lcla_pool
.alloc_map
);
2558 kfree(base
->lookup_log_chans
);
2559 kfree(base
->lookup_phy_chans
);
2560 kfree(base
->phy_res
);
2567 static void __init
d40_hw_init(struct d40_base
*base
)
2570 static const struct d40_reg_val dma_init_reg
[] = {
2571 /* Clock every part of the DMA block from start */
2572 { .reg
= D40_DREG_GCC
, .val
= 0x0000ff01},
2574 /* Interrupts on all logical channels */
2575 { .reg
= D40_DREG_LCMIS0
, .val
= 0xFFFFFFFF},
2576 { .reg
= D40_DREG_LCMIS1
, .val
= 0xFFFFFFFF},
2577 { .reg
= D40_DREG_LCMIS2
, .val
= 0xFFFFFFFF},
2578 { .reg
= D40_DREG_LCMIS3
, .val
= 0xFFFFFFFF},
2579 { .reg
= D40_DREG_LCICR0
, .val
= 0xFFFFFFFF},
2580 { .reg
= D40_DREG_LCICR1
, .val
= 0xFFFFFFFF},
2581 { .reg
= D40_DREG_LCICR2
, .val
= 0xFFFFFFFF},
2582 { .reg
= D40_DREG_LCICR3
, .val
= 0xFFFFFFFF},
2583 { .reg
= D40_DREG_LCTIS0
, .val
= 0xFFFFFFFF},
2584 { .reg
= D40_DREG_LCTIS1
, .val
= 0xFFFFFFFF},
2585 { .reg
= D40_DREG_LCTIS2
, .val
= 0xFFFFFFFF},
2586 { .reg
= D40_DREG_LCTIS3
, .val
= 0xFFFFFFFF}
2589 u32 prmseo
[2] = {0, 0};
2590 u32 activeo
[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2594 for (i
= 0; i
< ARRAY_SIZE(dma_init_reg
); i
++)
2595 writel(dma_init_reg
[i
].val
,
2596 base
->virtbase
+ dma_init_reg
[i
].reg
);
2598 /* Configure all our dma channels to default settings */
2599 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2601 activeo
[i
% 2] = activeo
[i
% 2] << 2;
2603 if (base
->phy_res
[base
->num_phy_chans
- i
- 1].allocated_src
2605 activeo
[i
% 2] |= 3;
2609 /* Enable interrupt # */
2610 pcmis
= (pcmis
<< 1) | 1;
2612 /* Clear interrupt # */
2613 pcicr
= (pcicr
<< 1) | 1;
2615 /* Set channel to physical mode */
2616 prmseo
[i
% 2] = prmseo
[i
% 2] << 2;
2621 writel(prmseo
[1], base
->virtbase
+ D40_DREG_PRMSE
);
2622 writel(prmseo
[0], base
->virtbase
+ D40_DREG_PRMSO
);
2623 writel(activeo
[1], base
->virtbase
+ D40_DREG_ACTIVE
);
2624 writel(activeo
[0], base
->virtbase
+ D40_DREG_ACTIVO
);
2626 /* Write which interrupt to enable */
2627 writel(pcmis
, base
->virtbase
+ D40_DREG_PCMIS
);
2629 /* Write which interrupt to clear */
2630 writel(pcicr
, base
->virtbase
+ D40_DREG_PCICR
);
2634 static int __init
d40_lcla_allocate(struct d40_base
*base
)
2636 struct d40_lcla_pool
*pool
= &base
->lcla_pool
;
2637 unsigned long *page_list
;
2642 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2643 * To full fill this hardware requirement without wasting 256 kb
2644 * we allocate pages until we get an aligned one.
2646 page_list
= kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS
,
2654 /* Calculating how many pages that are required */
2655 base
->lcla_pool
.pages
= SZ_1K
* base
->num_phy_chans
/ PAGE_SIZE
;
2657 for (i
= 0; i
< MAX_LCLA_ALLOC_ATTEMPTS
; i
++) {
2658 page_list
[i
] = __get_free_pages(GFP_KERNEL
,
2659 base
->lcla_pool
.pages
);
2660 if (!page_list
[i
]) {
2662 d40_err(base
->dev
, "Failed to allocate %d pages.\n",
2663 base
->lcla_pool
.pages
);
2665 for (j
= 0; j
< i
; j
++)
2666 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2670 if ((virt_to_phys((void *)page_list
[i
]) &
2671 (LCLA_ALIGNMENT
- 1)) == 0)
2675 for (j
= 0; j
< i
; j
++)
2676 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2678 if (i
< MAX_LCLA_ALLOC_ATTEMPTS
) {
2679 base
->lcla_pool
.base
= (void *)page_list
[i
];
2682 * After many attempts and no succees with finding the correct
2683 * alignment, try with allocating a big buffer.
2686 "[%s] Failed to get %d pages @ 18 bit align.\n",
2687 __func__
, base
->lcla_pool
.pages
);
2688 base
->lcla_pool
.base_unaligned
= kmalloc(SZ_1K
*
2689 base
->num_phy_chans
+
2692 if (!base
->lcla_pool
.base_unaligned
) {
2697 base
->lcla_pool
.base
= PTR_ALIGN(base
->lcla_pool
.base_unaligned
,
2701 pool
->dma_addr
= dma_map_single(base
->dev
, pool
->base
,
2702 SZ_1K
* base
->num_phy_chans
,
2704 if (dma_mapping_error(base
->dev
, pool
->dma_addr
)) {
2710 writel(virt_to_phys(base
->lcla_pool
.base
),
2711 base
->virtbase
+ D40_DREG_LCLA
);
2717 static int __init
d40_probe(struct platform_device
*pdev
)
2721 struct d40_base
*base
;
2722 struct resource
*res
= NULL
;
2723 int num_reserved_chans
;
2726 base
= d40_hw_detect_init(pdev
);
2731 num_reserved_chans
= d40_phy_res_init(base
);
2733 platform_set_drvdata(pdev
, base
);
2735 spin_lock_init(&base
->interrupt_lock
);
2736 spin_lock_init(&base
->execmd_lock
);
2738 /* Get IO for logical channel parameter address */
2739 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "lcpa");
2742 d40_err(&pdev
->dev
, "No \"lcpa\" memory resource\n");
2745 base
->lcpa_size
= resource_size(res
);
2746 base
->phy_lcpa
= res
->start
;
2748 if (request_mem_region(res
->start
, resource_size(res
),
2749 D40_NAME
" I/O lcpa") == NULL
) {
2752 "Failed to request LCPA region 0x%x-0x%x\n",
2753 res
->start
, res
->end
);
2757 /* We make use of ESRAM memory for this. */
2758 val
= readl(base
->virtbase
+ D40_DREG_LCPA
);
2759 if (res
->start
!= val
&& val
!= 0) {
2760 dev_warn(&pdev
->dev
,
2761 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2762 __func__
, val
, res
->start
);
2764 writel(res
->start
, base
->virtbase
+ D40_DREG_LCPA
);
2766 base
->lcpa_base
= ioremap(res
->start
, resource_size(res
));
2767 if (!base
->lcpa_base
) {
2769 d40_err(&pdev
->dev
, "Failed to ioremap LCPA region\n");
2773 ret
= d40_lcla_allocate(base
);
2775 d40_err(&pdev
->dev
, "Failed to allocate LCLA area\n");
2779 spin_lock_init(&base
->lcla_pool
.lock
);
2781 base
->irq
= platform_get_irq(pdev
, 0);
2783 ret
= request_irq(base
->irq
, d40_handle_interrupt
, 0, D40_NAME
, base
);
2785 d40_err(&pdev
->dev
, "No IRQ defined\n");
2789 err
= d40_dmaengine_init(base
, num_reserved_chans
);
2795 dev_info(base
->dev
, "initialized\n");
2800 if (base
->desc_slab
)
2801 kmem_cache_destroy(base
->desc_slab
);
2803 iounmap(base
->virtbase
);
2805 if (base
->lcla_pool
.dma_addr
)
2806 dma_unmap_single(base
->dev
, base
->lcla_pool
.dma_addr
,
2807 SZ_1K
* base
->num_phy_chans
,
2810 if (!base
->lcla_pool
.base_unaligned
&& base
->lcla_pool
.base
)
2811 free_pages((unsigned long)base
->lcla_pool
.base
,
2812 base
->lcla_pool
.pages
);
2814 kfree(base
->lcla_pool
.base_unaligned
);
2817 release_mem_region(base
->phy_lcpa
,
2819 if (base
->phy_start
)
2820 release_mem_region(base
->phy_start
,
2823 clk_disable(base
->clk
);
2827 kfree(base
->lcla_pool
.alloc_map
);
2828 kfree(base
->lookup_log_chans
);
2829 kfree(base
->lookup_phy_chans
);
2830 kfree(base
->phy_res
);
2834 d40_err(&pdev
->dev
, "probe failed\n");
2838 static struct platform_driver d40_driver
= {
2840 .owner
= THIS_MODULE
,
2845 static int __init
stedma40_init(void)
2847 return platform_driver_probe(&d40_driver
, d40_probe
);
2849 arch_initcall(stedma40_init
);