drivers/net/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _IGB_H_
  32 #define _IGB_H_
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36
  37 #include <linux/clocksource.h>
  38 #include <linux/timecompare.h>
  39 #include <linux/net_tstamp.h>
  40
  41 struct igb_adapter;
  42
  43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
  44 #define IGB_START_ITR 648
  45
  46 /* TX/RX descriptor defines */
  47 #define IGB_DEFAULT_TXD                  256
  48 #define IGB_MIN_TXD                       80
  49 #define IGB_MAX_TXD                     4096
  50
  51 #define IGB_DEFAULT_RXD                  256
  52 #define IGB_MIN_RXD                       80
  53 #define IGB_MAX_RXD                     4096
  54
  55 #define IGB_DEFAULT_ITR                    3 /* dynamic */
  56 #define IGB_MAX_ITR_USECS              10000
  57 #define IGB_MIN_ITR_USECS                 10
  58
  59 /* Transmit and receive queues */
  60 #define IGB_MAX_RX_QUEUES     (adapter->vfs_allocated_count ? \
  61                                (adapter->vfs_allocated_count > 6 ? 1 : 2) : 4)
  62 #define IGB_MAX_TX_QUEUES     IGB_MAX_RX_QUEUES
  63 #define IGB_ABS_MAX_TX_QUEUES     4
  64
  65 /* RX descriptor control thresholds.
  66  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
  67  *           descriptors available in its onboard memory.
  68  *           Setting this to 0 disables RX descriptor prefetch.
  69  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
  70  *           available in host memory.
  71  *           If PTHRESH is 0, this should also be 0.
  72  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
  73  *           descriptors until either it has this many to write back, or the
  74  *           ITR timer expires.
  75  */
  76 #define IGB_RX_PTHRESH                    16
  77 #define IGB_RX_HTHRESH                     8
  78 #define IGB_RX_WTHRESH                     1
  79
  80 /* this is the size past which hardware will drop packets when setting LPE=0 */
  81 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
  82
  83 /* Supported Rx Buffer Sizes */
  84 #define IGB_RXBUFFER_128   128    /* Used for packet split */
  85 #define IGB_RXBUFFER_256   256    /* Used for packet split */
  86 #define IGB_RXBUFFER_512   512
  87 #define IGB_RXBUFFER_1024  1024
  88 #define IGB_RXBUFFER_2048  2048
  89 #define IGB_RXBUFFER_16384 16384
  90
  91 /* Packet Buffer allocations */
  92
  93
  94 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
  95 #define IGB_TX_QUEUE_WAKE       16
  96 /* How many Rx Buffers do we bundle into one write to the hardware ? */
  97 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
  98
  99 #define AUTO_ALL_MODES            0
 100 #define IGB_EEPROM_APME         0x0400
 101
 102 #ifndef IGB_MASTER_SLAVE
 103 /* Switch to override PHY master/slave setting */
 104 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 105 #endif
 106
 107 #define IGB_MNG_VLAN_NONE -1
 108
 109 /* wrapper around a pointer to a socket buffer,
 110  * so a DMA handle can be stored along with the buffer */
 111 struct igb_buffer {
 112         struct sk_buff *skb;
 113         dma_addr_t dma;
 114         union {
 115                 /* TX */
 116                 struct {
 117                         unsigned long time_stamp;
 118                         u16 length;
 119                         u16 next_to_watch;
 120                 };
 121                 /* RX */
 122                 struct {
 123                         struct page *page;
 124                         u64 page_dma;
 125                         unsigned int page_offset;
 126                 };
 127         };
 128 };
 129
 130 struct igb_queue_stats {
 131         u64 packets;
 132         u64 bytes;
 133 };
 134
 135 struct igb_ring {
 136         struct igb_adapter *adapter; /* backlink */
 137         void *desc;                  /* descriptor ring memory */
 138         dma_addr_t dma;              /* phys address of the ring */
 139         unsigned int size;           /* length of desc. ring in bytes */
 140         unsigned int count;          /* number of desc. in the ring */
 141         u16 next_to_use;
 142         u16 next_to_clean;
 143         u16 head;
 144         u16 tail;
 145         struct igb_buffer *buffer_info; /* array of buffer info structs */
 146
 147         u32 eims_value;
 148         u32 itr_val;
 149         u16 itr_register;
 150         u16 cpu;
 151
 152         u16 queue_index;
 153         u16 reg_idx;
 154         unsigned int total_bytes;
 155         unsigned int total_packets;
 156
 157         union {
 158                 /* TX */
 159                 struct {
 160                         struct igb_queue_stats tx_stats;
 161                         bool detect_tx_hung;
 162                 };
 163                 /* RX */
 164                 struct {
 165                         struct igb_queue_stats rx_stats;
 166                         struct napi_struct napi;
 167                         int set_itr;
 168                         struct igb_ring *buddy;
 169                 };
 170         };
 171
 172         char name[IFNAMSIZ + 5];
 173 };
 174
 175 #define IGB_DESC_UNUSED(R) \
 176         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 177         (R)->next_to_clean - (R)->next_to_use - 1)
 178
 179 #define E1000_RX_DESC_ADV(R, i)     \
 180         (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
 181 #define E1000_TX_DESC_ADV(R, i)     \
 182         (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
 183 #define E1000_TX_CTXTDESC_ADV(R, i)         \
 184         (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
 185
 186 /* board specific private data structure */
 187
 188 struct igb_adapter {
 189         struct timer_list watchdog_timer;
 190         struct timer_list phy_info_timer;
 191         struct vlan_group *vlgrp;
 192         u16 mng_vlan_id;
 193         u32 bd_number;
 194         u32 rx_buffer_len;
 195         u32 wol;
 196         u32 en_mng_pt;
 197         u16 link_speed;
 198         u16 link_duplex;
 199         unsigned int total_tx_bytes;
 200         unsigned int total_tx_packets;
 201         unsigned int total_rx_bytes;
 202         unsigned int total_rx_packets;
 203         /* Interrupt Throttle Rate */
 204         u32 itr;
 205         u32 itr_setting;
 206         u16 tx_itr;
 207         u16 rx_itr;
 208
 209         struct work_struct reset_task;
 210         struct work_struct watchdog_task;
 211         bool fc_autoneg;
 212         u8  tx_timeout_factor;
 213         struct timer_list blink_timer;
 214         unsigned long led_status;
 215
 216         /* TX */
 217         struct igb_ring *tx_ring;      /* One per active queue */
 218         unsigned int restart_queue;
 219         unsigned long tx_queue_len;
 220         u32 txd_cmd;
 221         u32 gotc;
 222         u64 gotc_old;
 223         u64 tpt_old;
 224         u64 colc_old;
 225         u32 tx_timeout_count;
 226
 227         /* RX */
 228         struct igb_ring *rx_ring;      /* One per active queue */
 229         int num_tx_queues;
 230         int num_rx_queues;
 231
 232         u64 hw_csum_err;
 233         u64 hw_csum_good;
 234         u32 alloc_rx_buff_failed;
 235         bool rx_csum;
 236         u32 gorc;
 237         u64 gorc_old;
 238         u16 rx_ps_hdr_size;
 239         u32 max_frame_size;
 240         u32 min_frame_size;
 241
 242         /* OS defined structs */
 243         struct net_device *netdev;
 244         struct napi_struct napi;
 245         struct pci_dev *pdev;
 246         struct net_device_stats net_stats;
 247         struct cyclecounter cycles;
 248         struct timecounter clock;
 249         struct timecompare compare;
 250         struct hwtstamp_config hwtstamp_config;
 251
 252         /* structs defined in e1000_hw.h */
 253         struct e1000_hw hw;
 254         struct e1000_hw_stats stats;
 255         struct e1000_phy_info phy_info;
 256         struct e1000_phy_stats phy_stats;
 257
 258         u32 test_icr;
 259         struct igb_ring test_tx_ring;
 260         struct igb_ring test_rx_ring;
 261
 262         int msg_enable;
 263         struct msix_entry *msix_entries;
 264         u32 eims_enable_mask;
 265         u32 eims_other;
 266
 267         /* to not mess up cache alignment, always add to the bottom */
 268         unsigned long state;
 269         unsigned int flags;
 270         u32 eeprom_wol;
 271
 272         struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
 273         unsigned int tx_ring_count;
 274         unsigned int rx_ring_count;
 275         unsigned int vfs_allocated_count;
 276 };
 277
 278 #define IGB_FLAG_HAS_MSI           (1 << 0)
 279 #define IGB_FLAG_DCA_ENABLED       (1 << 1)
 280 #define IGB_FLAG_QUAD_PORT_A       (1 << 2)
 281 #define IGB_FLAG_NEED_CTX_IDX      (1 << 3)
 282
 283 enum e1000_state_t {
 284         __IGB_TESTING,
 285         __IGB_RESETTING,
 286         __IGB_DOWN
 287 };
 288
 289 enum igb_boards {
 290         board_82575,
 291 };
 292
 293 extern char igb_driver_name[];
 294 extern char igb_driver_version[];
 295
 296 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 297 extern int igb_up(struct igb_adapter *);
 298 extern void igb_down(struct igb_adapter *);
 299 extern void igb_reinit_locked(struct igb_adapter *);
 300 extern void igb_reset(struct igb_adapter *);
 301 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
 302 extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
 303 extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
 304 extern void igb_free_tx_resources(struct igb_ring *);
 305 extern void igb_free_rx_resources(struct igb_ring *);
 306 extern void igb_update_stats(struct igb_adapter *);
 307 extern void igb_set_ethtool_ops(struct net_device *);
 308
 309 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 310 {
 311         if (hw->phy.ops.reset)
 312                 return hw->phy.ops.reset(hw);
 313
 314         return 0;
 315 }
 316
 317 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 318 {
 319         if (hw->phy.ops.read_reg)
 320                 return hw->phy.ops.read_reg(hw, offset, data);
 321
 322         return 0;
 323 }
 324
 325 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 326 {
 327         if (hw->phy.ops.write_reg)
 328                 return hw->phy.ops.write_reg(hw, offset, data);
 329
 330         return 0;
 331 }
 332
 333 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 334 {
 335         if (hw->phy.ops.get_phy_info)
 336                 return hw->phy.ops.get_phy_info(hw);
 337
 338         return 0;
 339 }
 340
 341 #endif /* _IGB_H_ */