thinkpad-acpi: volume subdriver rewrite
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / mips / sgi-ip27 / ip27-nmi.c
blob64459e7d891b1a45f5d089b350b65598626f163f
1 #include <linux/kernel.h>
2 #include <linux/mmzone.h>
3 #include <linux/nodemask.h>
4 #include <linux/spinlock.h>
5 #include <linux/smp.h>
6 #include <asm/atomic.h>
7 #include <asm/sn/types.h>
8 #include <asm/sn/addrs.h>
9 #include <asm/sn/nmi.h>
10 #include <asm/sn/arch.h>
11 #include <asm/sn/sn0/hub.h>
13 #if 0
14 #define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n)
15 #else
16 #define NODE_NUM_CPUS(n) CPUS_PER_NODE
17 #endif
19 #define CNODEID_NONE (cnodeid_t)-1
20 #define enter_panic_mode() spin_lock(&nmi_lock)
22 typedef unsigned long machreg_t;
24 DEFINE_SPINLOCK(nmi_lock);
27 * Lets see what else we need to do here. Set up sp, gp?
29 void nmi_dump(void)
31 void cont_nmi_dump(void);
33 cont_nmi_dump();
36 void install_cpu_nmi_handler(int slice)
38 nmi_t *nmi_addr;
40 nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice);
41 if (nmi_addr->call_addr)
42 return;
43 nmi_addr->magic = NMI_MAGIC;
44 nmi_addr->call_addr = (void *)nmi_dump;
45 nmi_addr->call_addr_c =
46 (void *)(~((unsigned long)(nmi_addr->call_addr)));
47 nmi_addr->call_parm = 0;
51 * Copy the cpu registers which have been saved in the IP27prom format
52 * into the eframe format for the node under consideration.
55 void nmi_cpu_eframe_save(nasid_t nasid, int slice)
57 struct reg_struct *nr;
58 int i;
60 /* Get the pointer to the current cpu's register set. */
61 nr = (struct reg_struct *)
62 (TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) +
63 slice * IP27_NMI_KREGS_CPU_SIZE);
65 printk("NMI nasid %d: slice %d\n", nasid, slice);
68 * Saved main processor registers
70 for (i = 0; i < 32; ) {
71 if ((i % 4) == 0)
72 printk("$%2d :", i);
73 printk(" %016lx", nr->gpr[i]);
75 i++;
76 if ((i % 4) == 0)
77 printk("\n");
80 printk("Hi : (value lost)\n");
81 printk("Lo : (value lost)\n");
84 * Saved cp0 registers
86 printk("epc : %016lx %pS\n", nr->epc, (void *) nr->epc);
87 printk("%s\n", print_tainted());
88 printk("ErrEPC: %016lx %pS\n", nr->error_epc, (void *) nr->error_epc);
89 printk("ra : %016lx %pS\n", nr->gpr[31], (void *) nr->gpr[31]);
90 printk("Status: %08lx ", nr->sr);
92 if (nr->sr & ST0_KX)
93 printk("KX ");
94 if (nr->sr & ST0_SX)
95 printk("SX ");
96 if (nr->sr & ST0_UX)
97 printk("UX ");
99 switch (nr->sr & ST0_KSU) {
100 case KSU_USER:
101 printk("USER ");
102 break;
103 case KSU_SUPERVISOR:
104 printk("SUPERVISOR ");
105 break;
106 case KSU_KERNEL:
107 printk("KERNEL ");
108 break;
109 default:
110 printk("BAD_MODE ");
111 break;
114 if (nr->sr & ST0_ERL)
115 printk("ERL ");
116 if (nr->sr & ST0_EXL)
117 printk("EXL ");
118 if (nr->sr & ST0_IE)
119 printk("IE ");
120 printk("\n");
122 printk("Cause : %08lx\n", nr->cause);
123 printk("PrId : %08x\n", read_c0_prid());
124 printk("BadVA : %016lx\n", nr->badva);
125 printk("CErr : %016lx\n", nr->cache_err);
126 printk("NMI_SR: %016lx\n", nr->nmi_sr);
128 printk("\n");
131 void nmi_dump_hub_irq(nasid_t nasid, int slice)
133 hubreg_t mask0, mask1, pend0, pend1;
135 if (slice == 0) { /* Slice A */
136 mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A);
137 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A);
138 } else { /* Slice B */
139 mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B);
140 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B);
143 pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0);
144 pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1);
146 printk("PI_INT_MASK0: %16lx PI_INT_MASK1: %16lx\n", mask0, mask1);
147 printk("PI_INT_PEND0: %16lx PI_INT_PEND1: %16lx\n", pend0, pend1);
148 printk("\n\n");
152 * Copy the cpu registers which have been saved in the IP27prom format
153 * into the eframe format for the node under consideration.
155 void nmi_node_eframe_save(cnodeid_t cnode)
157 nasid_t nasid;
158 int slice;
160 /* Make sure that we have a valid node */
161 if (cnode == CNODEID_NONE)
162 return;
164 nasid = COMPACT_TO_NASID_NODEID(cnode);
165 if (nasid == INVALID_NASID)
166 return;
168 /* Save the registers into eframe for each cpu */
169 for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) {
170 nmi_cpu_eframe_save(nasid, slice);
171 nmi_dump_hub_irq(nasid, slice);
176 * Save the nmi cpu registers for all cpus in the system.
178 void
179 nmi_eframes_save(void)
181 cnodeid_t cnode;
183 for_each_online_node(cnode)
184 nmi_node_eframe_save(cnode);
187 void
188 cont_nmi_dump(void)
190 #ifndef REAL_NMI_SIGNAL
191 static atomic_t nmied_cpus = ATOMIC_INIT(0);
193 atomic_inc(&nmied_cpus);
194 #endif
196 * Use enter_panic_mode to allow only 1 cpu to proceed
198 enter_panic_mode();
200 #ifdef REAL_NMI_SIGNAL
202 * Wait up to 15 seconds for the other cpus to respond to the NMI.
203 * If a cpu has not responded after 10 sec, send it 1 additional NMI.
204 * This is for 2 reasons:
205 * - sometimes a MMSC fail to NMI all cpus.
206 * - on 512p SN0 system, the MMSC will only send NMIs to
207 * half the cpus. Unfortunately, we don't know which cpus may be
208 * NMIed - it depends on how the site chooses to configure.
210 * Note: it has been measure that it takes the MMSC up to 2.3 secs to
211 * send NMIs to all cpus on a 256p system.
213 for (i=0; i < 1500; i++) {
214 for_each_online_node(node)
215 if (NODEPDA(node)->dump_count == 0)
216 break;
217 if (node == MAX_NUMNODES)
218 break;
219 if (i == 1000) {
220 for_each_online_node(node)
221 if (NODEPDA(node)->dump_count == 0) {
222 cpu = node_to_first_cpu(node);
223 for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) {
224 CPUMASK_SETB(nmied_cpus, cpu);
226 * cputonasid, cputoslice
227 * needs kernel cpuid
229 SEND_NMI((cputonasid(cpu)), (cputoslice(cpu)));
234 udelay(10000);
236 #else
237 while (atomic_read(&nmied_cpus) != num_online_cpus());
238 #endif
241 * Save the nmi cpu registers for all cpu in the eframe format.
243 nmi_eframes_save();
244 LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);