arch/arm/mach-s5p64x0/clock-s5p6450.c

   1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * S5P6450 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/hardware.h>
  24 #include <mach/map.h>
  25 #include <mach/regs-clock.h>
  26 #include <mach/s5p64x0-clock.h>
  27
  28 #include <plat/cpu-freq.h>
  29 #include <plat/clock.h>
  30 #include <plat/cpu.h>
  31 #include <plat/pll.h>
  32 #include <plat/s5p-clock.h>
  33 #include <plat/clock-clksrc.h>
  34 #include <plat/s5p6450.h>
  35
  36 static struct clksrc_clk clk_mout_dpll = {
  37         .clk    = {
  38                 .name           = "mout_dpll",
  39                 .id             = -1,
  40         },
  41         .sources        = &clk_src_dpll,
  42         .reg_src        = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
  43 };
  44
  45 static u32 epll_div[][5] = {
  46         { 133000000,    27307,  55, 2, 2 },
  47         { 100000000,    43691,  41, 2, 2 },
  48         { 480000000,    0,      80, 2, 0 },
  49 };
  50
  51 static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
  52 {
  53         unsigned int epll_con, epll_con_k;
  54         unsigned int i;
  55
  56         if (clk->rate == rate)  /* Return if nothing changed */
  57                 return 0;
  58
  59         epll_con = __raw_readl(S5P64X0_EPLL_CON);
  60         epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
  61
  62         epll_con_k &= ~(PLL90XX_KDIV_MASK);
  63         epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
  64
  65         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
  66                  if (epll_div[i][0] == rate) {
  67                         epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
  68                         epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
  69                                     (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
  70                                     (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
  71                         break;
  72                 }
  73         }
  74
  75         if (i == ARRAY_SIZE(epll_div)) {
  76                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
  77                 return -EINVAL;
  78         }
  79
  80         __raw_writel(epll_con, S5P64X0_EPLL_CON);
  81         __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
  82
  83         clk->rate = rate;
  84
  85         return 0;
  86 }
  87
  88 static struct clk_ops s5p6450_epll_ops = {
  89         .get_rate = s5p64x0_epll_get_rate,
  90         .set_rate = s5p6450_epll_set_rate,
  91 };
  92
  93 static struct clksrc_clk clk_dout_epll = {
  94         .clk    = {
  95                 .name           = "dout_epll",
  96                 .id             = -1,
  97                 .parent         = &clk_mout_epll.clk,
  98         },
  99         .reg_div        = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
 100 };
 101
 102 static struct clksrc_clk clk_mout_hclk_sel = {
 103         .clk    = {
 104                 .name           = "mout_hclk_sel",
 105                 .id             = -1,
 106         },
 107         .sources        = &clkset_hclk_low,
 108         .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
 109 };
 110
 111 static struct clk *clkset_hclk_list[] = {
 112         &clk_mout_hclk_sel.clk,
 113         &clk_armclk.clk,
 114 };
 115
 116 static struct clksrc_sources clkset_hclk = {
 117         .sources        = clkset_hclk_list,
 118         .nr_sources     = ARRAY_SIZE(clkset_hclk_list),
 119 };
 120
 121 static struct clksrc_clk clk_hclk = {
 122         .clk    = {
 123                 .name           = "clk_hclk",
 124                 .id             = -1,
 125         },
 126         .sources        = &clkset_hclk,
 127         .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
 128         .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
 129 };
 130
 131 static struct clksrc_clk clk_pclk = {
 132         .clk    = {
 133                 .name           = "clk_pclk",
 134                 .id             = -1,
 135                 .parent         = &clk_hclk.clk,
 136         },
 137         .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
 138 };
 139 static struct clksrc_clk clk_dout_pwm_ratio0 = {
 140         .clk    = {
 141                 .name           = "clk_dout_pwm_ratio0",
 142                 .id             = -1,
 143                 .parent         = &clk_mout_hclk_sel.clk,
 144         },
 145         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
 146 };
 147
 148 static struct clksrc_clk clk_pclk_to_wdt_pwm = {
 149         .clk    = {
 150                 .name           = "clk_pclk_to_wdt_pwm",
 151                 .id             = -1,
 152                 .parent         = &clk_dout_pwm_ratio0.clk,
 153         },
 154         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
 155 };
 156
 157 static struct clksrc_clk clk_hclk_low = {
 158         .clk    = {
 159                 .name           = "clk_hclk_low",
 160                 .id             = -1,
 161         },
 162         .sources        = &clkset_hclk_low,
 163         .reg_src        = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
 164         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
 165 };
 166
 167 static struct clksrc_clk clk_pclk_low = {
 168         .clk    = {
 169                 .name           = "clk_pclk_low",
 170                 .id             = -1,
 171                 .parent         = &clk_hclk_low.clk,
 172         },
 173         .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
 174 };
 175
 176 /*
 177  * The following clocks will be disabled during clock initialization. It is
 178  * recommended to keep the following clocks disabled until the driver requests
 179  * for enabling the clock.
 180  */
 181 static struct clk init_clocks_disable[] = {
 182         {
 183                 .name           = "usbhost",
 184                 .id             = -1,
 185                 .parent         = &clk_hclk_low.clk,
 186                 .enable         = s5p64x0_hclk0_ctrl,
 187                 .ctrlbit        = (1 << 3),
 188         }, {
 189                 .name           = "hsmmc",
 190                 .id             = 0,
 191                 .parent         = &clk_hclk_low.clk,
 192                 .enable         = s5p64x0_hclk0_ctrl,
 193                 .ctrlbit        = (1 << 17),
 194         }, {
 195                 .name           = "hsmmc",
 196                 .id             = 1,
 197                 .parent         = &clk_hclk_low.clk,
 198                 .enable         = s5p64x0_hclk0_ctrl,
 199                 .ctrlbit        = (1 << 18),
 200         }, {
 201                 .name           = "hsmmc",
 202                 .id             = 2,
 203                 .parent         = &clk_hclk_low.clk,
 204                 .enable         = s5p64x0_hclk0_ctrl,
 205                 .ctrlbit        = (1 << 19),
 206         }, {
 207                 .name           = "usbotg",
 208                 .id             = -1,
 209                 .parent         = &clk_hclk_low.clk,
 210                 .enable         = s5p64x0_hclk0_ctrl,
 211                 .ctrlbit        = (1 << 20),
 212         }, {
 213                 .name           = "lcd",
 214                 .id             = -1,
 215                 .parent         = &clk_h,
 216                 .enable         = s5p64x0_hclk1_ctrl,
 217                 .ctrlbit        = (1 << 1),
 218         }, {
 219                 .name           = "watchdog",
 220                 .id             = -1,
 221                 .parent         = &clk_pclk_low.clk,
 222                 .enable         = s5p64x0_pclk_ctrl,
 223                 .ctrlbit        = (1 << 5),
 224         }, {
 225                 .name           = "adc",
 226                 .id             = -1,
 227                 .parent         = &clk_pclk_low.clk,
 228                 .enable         = s5p64x0_pclk_ctrl,
 229                 .ctrlbit        = (1 << 12),
 230         }, {
 231                 .name           = "i2c",
 232                 .id             = 0,
 233                 .parent         = &clk_pclk_low.clk,
 234                 .enable         = s5p64x0_pclk_ctrl,
 235                 .ctrlbit        = (1 << 17),
 236         }, {
 237                 .name           = "spi",
 238                 .id             = 0,
 239                 .parent         = &clk_pclk_low.clk,
 240                 .enable         = s5p64x0_pclk_ctrl,
 241                 .ctrlbit        = (1 << 21),
 242         }, {
 243                 .name           = "spi",
 244                 .id             = 1,
 245                 .parent         = &clk_pclk_low.clk,
 246                 .enable         = s5p64x0_pclk_ctrl,
 247                 .ctrlbit        = (1 << 22),
 248         }, {
 249                 .name           = "iis",
 250                 .id             = -1,
 251                 .parent         = &clk_pclk_low.clk,
 252                 .enable         = s5p64x0_pclk_ctrl,
 253                 .ctrlbit        = (1 << 26),
 254         }, {
 255                 .name           = "i2c",
 256                 .id             = 1,
 257                 .parent         = &clk_pclk_low.clk,
 258                 .enable         = s5p64x0_pclk_ctrl,
 259                 .ctrlbit        = (1 << 27),
 260         }, {
 261                 .name           = "dmc0",
 262                 .id             = -1,
 263                 .parent         = &clk_pclk.clk,
 264                 .enable         = s5p64x0_pclk_ctrl,
 265                 .ctrlbit        = (1 << 30),
 266         }
 267 };
 268
 269 /*
 270  * The following clocks will be enabled during clock initialization.
 271  */
 272 static struct clk init_clocks[] = {
 273         {
 274                 .name           = "intc",
 275                 .id             = -1,
 276                 .parent         = &clk_hclk.clk,
 277                 .enable         = s5p64x0_hclk0_ctrl,
 278                 .ctrlbit        = (1 << 1),
 279         }, {
 280                 .name           = "mem",
 281                 .id             = -1,
 282                 .parent         = &clk_hclk.clk,
 283                 .enable         = s5p64x0_hclk0_ctrl,
 284                 .ctrlbit        = (1 << 21),
 285         }, {
 286                 .name           = "dma",
 287                 .id             = -1,
 288                 .parent         = &clk_hclk_low.clk,
 289                 .enable         = s5p64x0_hclk0_ctrl,
 290                 .ctrlbit        = (1 << 12),
 291         }, {
 292                 .name           = "uart",
 293                 .id             = 0,
 294                 .parent         = &clk_pclk_low.clk,
 295                 .enable         = s5p64x0_pclk_ctrl,
 296                 .ctrlbit        = (1 << 1),
 297         }, {
 298                 .name           = "uart",
 299                 .id             = 1,
 300                 .parent         = &clk_pclk_low.clk,
 301                 .enable         = s5p64x0_pclk_ctrl,
 302                 .ctrlbit        = (1 << 2),
 303         }, {
 304                 .name           = "uart",
 305                 .id             = 2,
 306                 .parent         = &clk_pclk_low.clk,
 307                 .enable         = s5p64x0_pclk_ctrl,
 308                 .ctrlbit        = (1 << 3),
 309         }, {
 310                 .name           = "uart",
 311                 .id             = 3,
 312                 .parent         = &clk_pclk_low.clk,
 313                 .enable         = s5p64x0_pclk_ctrl,
 314                 .ctrlbit        = (1 << 4),
 315         }, {
 316                 .name           = "timers",
 317                 .id             = -1,
 318                 .parent         = &clk_pclk_to_wdt_pwm.clk,
 319                 .enable         = s5p64x0_pclk_ctrl,
 320                 .ctrlbit        = (1 << 7),
 321         }, {
 322                 .name           = "gpio",
 323                 .id             = -1,
 324                 .parent         = &clk_pclk_low.clk,
 325                 .enable         = s5p64x0_pclk_ctrl,
 326                 .ctrlbit        = (1 << 18),
 327         },
 328 };
 329
 330 static struct clk *clkset_uart_list[] = {
 331         &clk_dout_epll.clk,
 332         &clk_dout_mpll.clk,
 333 };
 334
 335 static struct clksrc_sources clkset_uart = {
 336         .sources        = clkset_uart_list,
 337         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 338 };
 339
 340 static struct clk *clkset_mali_list[] = {
 341         &clk_mout_epll.clk,
 342         &clk_mout_apll.clk,
 343         &clk_mout_mpll.clk,
 344 };
 345
 346 static struct clksrc_sources clkset_mali = {
 347         .sources        = clkset_mali_list,
 348         .nr_sources     = ARRAY_SIZE(clkset_mali_list),
 349 };
 350
 351 static struct clk *clkset_group2_list[] = {
 352         &clk_dout_epll.clk,
 353         &clk_dout_mpll.clk,
 354         &clk_ext_xtal_mux,
 355 };
 356
 357 static struct clksrc_sources clkset_group2 = {
 358         .sources        = clkset_group2_list,
 359         .nr_sources     = ARRAY_SIZE(clkset_group2_list),
 360 };
 361
 362 static struct clk *clkset_dispcon_list[] = {
 363         &clk_dout_epll.clk,
 364         &clk_dout_mpll.clk,
 365         &clk_ext_xtal_mux,
 366         &clk_mout_dpll.clk,
 367 };
 368
 369 static struct clksrc_sources clkset_dispcon = {
 370         .sources        = clkset_dispcon_list,
 371         .nr_sources     = ARRAY_SIZE(clkset_dispcon_list),
 372 };
 373
 374 static struct clk *clkset_hsmmc44_list[] = {
 375         &clk_dout_epll.clk,
 376         &clk_dout_mpll.clk,
 377         &clk_ext_xtal_mux,
 378         &s5p_clk_27m,
 379         &clk_48m,
 380 };
 381
 382 static struct clksrc_sources clkset_hsmmc44 = {
 383         .sources        = clkset_hsmmc44_list,
 384         .nr_sources     = ARRAY_SIZE(clkset_hsmmc44_list),
 385 };
 386
 387 static struct clk *clkset_sclk_audio0_list[] = {
 388         [0] = &clk_dout_epll.clk,
 389         [1] = &clk_dout_mpll.clk,
 390         [2] = &clk_ext_xtal_mux,
 391         [3] = NULL,
 392         [4] = NULL,
 393 };
 394
 395 static struct clksrc_sources clkset_sclk_audio0 = {
 396         .sources        = clkset_sclk_audio0_list,
 397         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
 398 };
 399
 400 static struct clksrc_clk clk_sclk_audio0 = {
 401         .clk            = {
 402                 .name           = "audio-bus",
 403                 .id             = -1,
 404                 .enable         = s5p64x0_sclk_ctrl,
 405                 .ctrlbit        = (1 << 8),
 406                 .parent         = &clk_dout_epll.clk,
 407         },
 408         .sources        = &clkset_sclk_audio0,
 409         .reg_src        = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
 410         .reg_div        = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
 411 };
 412
 413 static struct clksrc_clk clksrcs[] = {
 414         {
 415                 .clk    = {
 416                         .name           = "sclk_mmc",
 417                         .id             = 0,
 418                         .ctrlbit        = (1 << 24),
 419                         .enable         = s5p64x0_sclk_ctrl,
 420                 },
 421                 .sources = &clkset_group2,
 422                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
 423                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
 424         }, {
 425                 .clk    = {
 426                         .name           = "sclk_mmc",
 427                         .id             = 1,
 428                         .ctrlbit        = (1 << 25),
 429                         .enable         = s5p64x0_sclk_ctrl,
 430                 },
 431                 .sources = &clkset_group2,
 432                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
 433                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
 434         }, {
 435                 .clk    = {
 436                         .name           = "sclk_mmc",
 437                         .id             = 2,
 438                         .ctrlbit        = (1 << 26),
 439                         .enable         = s5p64x0_sclk_ctrl,
 440                 },
 441                 .sources = &clkset_group2,
 442                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
 443                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
 444         }, {
 445                 .clk    = {
 446                         .name           = "uclk1",
 447                         .id             = -1,
 448                         .ctrlbit        = (1 << 5),
 449                         .enable         = s5p64x0_sclk_ctrl,
 450                 },
 451                 .sources = &clkset_uart,
 452                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
 453                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
 454         }, {
 455                 .clk    = {
 456                         .name           = "sclk_spi",
 457                         .id             = 0,
 458                         .ctrlbit        = (1 << 20),
 459                         .enable         = s5p64x0_sclk_ctrl,
 460                 },
 461                 .sources = &clkset_group2,
 462                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
 463                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
 464         }, {
 465                 .clk    = {
 466                         .name           = "sclk_spi",
 467                         .id             = 1,
 468                         .ctrlbit        = (1 << 21),
 469                         .enable         = s5p64x0_sclk_ctrl,
 470                 },
 471                 .sources = &clkset_group2,
 472                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
 473                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
 474         }, {
 475                 .clk    = {
 476                         .name           = "sclk_fimc",
 477                         .id             = -1,
 478                         .ctrlbit        = (1 << 10),
 479                         .enable         = s5p64x0_sclk_ctrl,
 480                 },
 481                 .sources = &clkset_group2,
 482                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
 483                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
 484         }, {
 485                 .clk    = {
 486                         .name           = "aclk_mali",
 487                         .id             = -1,
 488                         .ctrlbit        = (1 << 2),
 489                         .enable         = s5p64x0_sclk1_ctrl,
 490                 },
 491                 .sources = &clkset_mali,
 492                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
 493                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
 494         }, {
 495                 .clk    = {
 496                         .name           = "sclk_2d",
 497                         .id             = -1,
 498                         .ctrlbit        = (1 << 12),
 499                         .enable         = s5p64x0_sclk_ctrl,
 500                 },
 501                 .sources = &clkset_mali,
 502                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
 503                 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
 504         }, {
 505                 .clk    = {
 506                         .name           = "sclk_usi",
 507                         .id             = -1,
 508                         .ctrlbit        = (1 << 7),
 509                         .enable         = s5p64x0_sclk_ctrl,
 510                 },
 511                 .sources = &clkset_group2,
 512                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
 513                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
 514         }, {
 515                 .clk    = {
 516                         .name           = "sclk_camif",
 517                         .id             = -1,
 518                         .ctrlbit        = (1 << 6),
 519                         .enable         = s5p64x0_sclk_ctrl,
 520                 },
 521                 .sources = &clkset_group2,
 522                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
 523                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
 524         }, {
 525                 .clk    = {
 526                         .name           = "sclk_dispcon",
 527                         .id             = -1,
 528                         .ctrlbit        = (1 << 1),
 529                         .enable         = s5p64x0_sclk1_ctrl,
 530                 },
 531                 .sources = &clkset_dispcon,
 532                 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
 533                 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
 534         }, {
 535                 .clk    = {
 536                         .name           = "sclk_hsmmc44",
 537                         .id             = -1,
 538                         .ctrlbit        = (1 << 30),
 539                         .enable         = s5p64x0_sclk_ctrl,
 540                 },
 541                 .sources = &clkset_hsmmc44,
 542                 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
 543                 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
 544         },
 545 };
 546
 547 /* Clock initialization code */
 548 static struct clksrc_clk *sysclks[] = {
 549         &clk_mout_apll,
 550         &clk_mout_epll,
 551         &clk_dout_epll,
 552         &clk_mout_mpll,
 553         &clk_dout_mpll,
 554         &clk_armclk,
 555         &clk_mout_hclk_sel,
 556         &clk_dout_pwm_ratio0,
 557         &clk_pclk_to_wdt_pwm,
 558         &clk_hclk,
 559         &clk_pclk,
 560         &clk_hclk_low,
 561         &clk_pclk_low,
 562         &clk_sclk_audio0,
 563 };
 564
 565 void __init_or_cpufreq s5p6450_setup_clocks(void)
 566 {
 567         struct clk *xtal_clk;
 568
 569         unsigned long xtal;
 570         unsigned long fclk;
 571         unsigned long hclk;
 572         unsigned long hclk_low;
 573         unsigned long pclk;
 574         unsigned long pclk_low;
 575
 576         unsigned long apll;
 577         unsigned long mpll;
 578         unsigned long epll;
 579         unsigned long dpll;
 580         unsigned int ptr;
 581
 582         /* Set S5P6450 functions for clk_fout_epll */
 583
 584         clk_fout_epll.enable = s5p64x0_epll_enable;
 585         clk_fout_epll.ops = &s5p6450_epll_ops;
 586
 587         clk_48m.enable = s5p64x0_clk48m_ctrl;
 588
 589         xtal_clk = clk_get(NULL, "ext_xtal");
 590         BUG_ON(IS_ERR(xtal_clk));
 591
 592         xtal = clk_get_rate(xtal_clk);
 593         clk_put(xtal_clk);
 594
 595         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
 596         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
 597         epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
 598                                 __raw_readl(S5P64X0_EPLL_CON_K));
 599         dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
 600                                 __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
 601
 602         clk_fout_apll.rate = apll;
 603         clk_fout_mpll.rate = mpll;
 604         clk_fout_epll.rate = epll;
 605         clk_fout_dpll.rate = dpll;
 606
 607         printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
 608                         " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
 609                         print_mhz(apll), print_mhz(mpll), print_mhz(epll),
 610                         print_mhz(dpll));
 611
 612         fclk = clk_get_rate(&clk_armclk.clk);
 613         hclk = clk_get_rate(&clk_hclk.clk);
 614         pclk = clk_get_rate(&clk_pclk.clk);
 615         hclk_low = clk_get_rate(&clk_hclk_low.clk);
 616         pclk_low = clk_get_rate(&clk_pclk_low.clk);
 617
 618         printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
 619                         " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
 620                         print_mhz(hclk), print_mhz(hclk_low),
 621                         print_mhz(pclk), print_mhz(pclk_low));
 622
 623         clk_f.rate = fclk;
 624         clk_h.rate = hclk;
 625         clk_p.rate = pclk;
 626
 627         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 628                 s3c_set_clksrc(&clksrcs[ptr], true);
 629 }
 630
 631 void __init s5p6450_register_clocks(void)
 632 {
 633         struct clk *clkp;
 634         int ret;
 635         int ptr;
 636
 637         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 638                 s3c_register_clksrc(sysclks[ptr], 1);
 639
 640         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 641         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 642
 643         clkp = init_clocks_disable;
 644         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 645
 646                 ret = s3c24xx_register_clock(clkp);
 647                 if (ret < 0) {
 648                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 649                                clkp->name, ret);
 650                 }
 651                 (clkp->enable)(clkp, 0);
 652         }
 653
 654         s3c_pwmclk_init();
 655 }