drivers/ide/pci/aec62xx.c

   1 /*
   2  * linux/drivers/ide/pci/aec62xx.c              Version 0.23    May 23, 2007
   3  *
   4  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2007           MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/delay.h>
  13 #include <linux/hdreg.h>
  14 #include <linux/ide.h>
  15 #include <linux/init.h>
  16
  17 #include <asm/io.h>
  18
  19 struct chipset_bus_clock_list_entry {
  20         u8 xfer_speed;
  21         u8 chipset_settings;
  22         u8 ultra_settings;
  23 };
  24
  25 static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
  26         {       XFER_UDMA_6,    0x31,   0x07    },
  27         {       XFER_UDMA_5,    0x31,   0x06    },
  28         {       XFER_UDMA_4,    0x31,   0x05    },
  29         {       XFER_UDMA_3,    0x31,   0x04    },
  30         {       XFER_UDMA_2,    0x31,   0x03    },
  31         {       XFER_UDMA_1,    0x31,   0x02    },
  32         {       XFER_UDMA_0,    0x31,   0x01    },
  33
  34         {       XFER_MW_DMA_2,  0x31,   0x00    },
  35         {       XFER_MW_DMA_1,  0x31,   0x00    },
  36         {       XFER_MW_DMA_0,  0x0a,   0x00    },
  37         {       XFER_PIO_4,     0x31,   0x00    },
  38         {       XFER_PIO_3,     0x33,   0x00    },
  39         {       XFER_PIO_2,     0x08,   0x00    },
  40         {       XFER_PIO_1,     0x0a,   0x00    },
  41         {       XFER_PIO_0,     0x00,   0x00    },
  42         {       0,              0x00,   0x00    }
  43 };
  44
  45 static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
  46         {       XFER_UDMA_6,    0x41,   0x06    },
  47         {       XFER_UDMA_5,    0x41,   0x05    },
  48         {       XFER_UDMA_4,    0x41,   0x04    },
  49         {       XFER_UDMA_3,    0x41,   0x03    },
  50         {       XFER_UDMA_2,    0x41,   0x02    },
  51         {       XFER_UDMA_1,    0x41,   0x01    },
  52         {       XFER_UDMA_0,    0x41,   0x01    },
  53
  54         {       XFER_MW_DMA_2,  0x41,   0x00    },
  55         {       XFER_MW_DMA_1,  0x42,   0x00    },
  56         {       XFER_MW_DMA_0,  0x7a,   0x00    },
  57         {       XFER_PIO_4,     0x41,   0x00    },
  58         {       XFER_PIO_3,     0x43,   0x00    },
  59         {       XFER_PIO_2,     0x78,   0x00    },
  60         {       XFER_PIO_1,     0x7a,   0x00    },
  61         {       XFER_PIO_0,     0x70,   0x00    },
  62         {       0,              0x00,   0x00    }
  63 };
  64
  65 #define BUSCLOCK(D)     \
  66         ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
  67
  68
  69 /*
  70  * TO DO: active tuning and correction of cards without a bios.
  71  */
  72 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  73 {
  74         for ( ; chipset_table->xfer_speed ; chipset_table++)
  75                 if (chipset_table->xfer_speed == speed) {
  76                         return chipset_table->chipset_settings;
  77                 }
  78         return chipset_table->chipset_settings;
  79 }
  80
  81 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
  82 {
  83         for ( ; chipset_table->xfer_speed ; chipset_table++)
  84                 if (chipset_table->xfer_speed == speed) {
  85                         return chipset_table->ultra_settings;
  86                 }
  87         return chipset_table->ultra_settings;
  88 }
  89
  90 static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
  91 {
  92         ide_hwif_t *hwif        = HWIF(drive);
  93         struct pci_dev *dev     = hwif->pci_dev;
  94         u16 d_conf              = 0;
  95         u8 speed                = ide_rate_filter(drive, xferspeed);
  96         u8 ultra = 0, ultra_conf = 0;
  97         u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
  98         unsigned long flags;
  99
 100         local_irq_save(flags);
 101         /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
 102         pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
 103         tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
 104         d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
 105         pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
 106
 107         tmp1 = 0x00;
 108         tmp2 = 0x00;
 109         pci_read_config_byte(dev, 0x54, &ultra);
 110         tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
 111         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 112         tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
 113         pci_write_config_byte(dev, 0x54, tmp2);
 114         local_irq_restore(flags);
 115         return(ide_config_drive_speed(drive, speed));
 116 }
 117
 118 static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 119 {
 120         ide_hwif_t *hwif        = HWIF(drive);
 121         struct pci_dev *dev     = hwif->pci_dev;
 122         u8 speed        = ide_rate_filter(drive, xferspeed);
 123         u8 unit         = (drive->select.b.unit & 0x01);
 124         u8 tmp1 = 0, tmp2 = 0;
 125         u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
 126         unsigned long flags;
 127
 128         local_irq_save(flags);
 129         /* high 4-bits: Active, low 4-bits: Recovery */
 130         pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
 131         drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
 132         pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
 133
 134         pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
 135         tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
 136         ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
 137         tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
 138         pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
 139         local_irq_restore(flags);
 140         return(ide_config_drive_speed(drive, speed));
 141 }
 142
 143 static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
 144 {
 145         switch (HWIF(drive)->pci_dev->device) {
 146                 case PCI_DEVICE_ID_ARTOP_ATP865:
 147                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 148                 case PCI_DEVICE_ID_ARTOP_ATP860:
 149                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 150                         return ((int) aec6260_tune_chipset(drive, speed));
 151                 case PCI_DEVICE_ID_ARTOP_ATP850UF:
 152                         return ((int) aec6210_tune_chipset(drive, speed));
 153                 default:
 154                         return -1;
 155         }
 156 }
 157
 158 static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
 159 {
 160         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 161         (void) aec62xx_tune_chipset(drive, pio + XFER_PIO_0);
 162 }
 163
 164 static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
 165 {
 166         if (ide_tune_dma(drive))
 167                 return 0;
 168
 169         if (ide_use_fast_pio(drive))
 170                 aec62xx_tune_drive(drive, 255);
 171
 172         return -1;
 173 }
 174
 175 static void aec62xx_dma_lost_irq (ide_drive_t *drive)
 176 {
 177         switch (HWIF(drive)->pci_dev->device) {
 178                 case PCI_DEVICE_ID_ARTOP_ATP860:
 179                 case PCI_DEVICE_ID_ARTOP_ATP860R:
 180                 case PCI_DEVICE_ID_ARTOP_ATP865:
 181                 case PCI_DEVICE_ID_ARTOP_ATP865R:
 182                         printk(" AEC62XX time out ");
 183                 default:
 184                         break;
 185         }
 186 }
 187
 188 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
 189 {
 190         int bus_speed = system_bus_clock();
 191
 192         if (dev->resource[PCI_ROM_RESOURCE].start) {
 193                 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 194                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
 195                         (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
 196         }
 197
 198         if (bus_speed <= 33)
 199                 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
 200         else
 201                 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
 202
 203         /* These are necessary to get AEC6280 Macintosh cards to work */
 204         if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
 205             (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
 206                 u8 reg49h = 0, reg4ah = 0;
 207                 /* Clear reset and test bits.  */
 208                 pci_read_config_byte(dev, 0x49, &reg49h);
 209                 pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
 210                 /* Enable chip interrupt output.  */
 211                 pci_read_config_byte(dev, 0x4a, &reg4ah);
 212                 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
 213                 /* Enable burst mode. */
 214                 pci_read_config_byte(dev, 0x4a, &reg4ah);
 215                 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
 216         }
 217
 218         return dev->irq;
 219 }
 220
 221 static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
 222 {
 223         struct pci_dev *dev     = hwif->pci_dev;
 224         u8 reg54 = 0,  mask     = hwif->channel ? 0xf0 : 0x0f;
 225         unsigned long flags;
 226
 227         hwif->tuneproc = &aec62xx_tune_drive;
 228         hwif->speedproc = &aec62xx_tune_chipset;
 229
 230         if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF && hwif->mate)
 231                 hwif->mate->serialized = hwif->serialized = 1;
 232
 233         if (!hwif->dma_base) {
 234                 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 235                 return;
 236         }
 237
 238         hwif->ultra_mask = hwif->cds->udma_mask;
 239         hwif->mwdma_mask = 0x07;
 240
 241         hwif->ide_dma_check     = &aec62xx_config_drive_xfer_rate;
 242         hwif->dma_lost_irq      = &aec62xx_dma_lost_irq;
 243
 244         if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
 245                 spin_lock_irqsave(&ide_lock, flags);
 246                 pci_read_config_byte (dev, 0x54, &reg54);
 247                 pci_write_config_byte(dev, 0x54, (reg54 & ~mask));
 248                 spin_unlock_irqrestore(&ide_lock, flags);
 249         } else if (!hwif->udma_four) {
 250                 u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
 251
 252                 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
 253                 hwif->udma_four = (ata66 & mask) ? 0 : 1;
 254         }
 255
 256         if (!noautodma)
 257                 hwif->autodma = 1;
 258         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 259 }
 260
 261 static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
 262 {
 263         return ide_setup_pci_device(dev, d);
 264 }
 265
 266 static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
 267 {
 268         unsigned long dma_base = pci_resource_start(dev, 4);
 269
 270         if (inb(dma_base + 2) & 0x10) {
 271                 d->name = (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R) ?
 272                           "AEC6880R" : "AEC6880";
 273                 d->udma_mask = 0x7f; /* udma0-6 */
 274         }
 275
 276         return ide_setup_pci_device(dev, d);
 277 }
 278
 279 static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
 280         {       /* 0 */
 281                 .name           = "AEC6210",
 282                 .init_setup     = init_setup_aec62xx,
 283                 .init_chipset   = init_chipset_aec62xx,
 284                 .init_hwif      = init_hwif_aec62xx,
 285                 .channels       = 2,
 286                 .autodma        = AUTODMA,
 287                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 288                 .bootable       = OFF_BOARD,
 289                 .udma_mask      = 0x07, /* udma0-2 */
 290         },{     /* 1 */
 291                 .name           = "AEC6260",
 292                 .init_setup     = init_setup_aec62xx,
 293                 .init_chipset   = init_chipset_aec62xx,
 294                 .init_hwif      = init_hwif_aec62xx,
 295                 .channels       = 2,
 296                 .autodma        = NOAUTODMA,
 297                 .bootable       = OFF_BOARD,
 298                 .udma_mask      = 0x1f, /* udma0-4 */
 299         },{     /* 2 */
 300                 .name           = "AEC6260R",
 301                 .init_setup     = init_setup_aec62xx,
 302                 .init_chipset   = init_chipset_aec62xx,
 303                 .init_hwif      = init_hwif_aec62xx,
 304                 .channels       = 2,
 305                 .autodma        = AUTODMA,
 306                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 307                 .bootable       = NEVER_BOARD,
 308                 .udma_mask      = 0x1f, /* udma0-4 */
 309         },{     /* 3 */
 310                 .name           = "AEC6280",
 311                 .init_setup     = init_setup_aec6x80,
 312                 .init_chipset   = init_chipset_aec62xx,
 313                 .init_hwif      = init_hwif_aec62xx,
 314                 .channels       = 2,
 315                 .autodma        = AUTODMA,
 316                 .bootable       = OFF_BOARD,
 317                 .udma_mask      = 0x3f, /* udma0-5 */
 318         },{     /* 4 */
 319                 .name           = "AEC6280R",
 320                 .init_setup     = init_setup_aec6x80,
 321                 .init_chipset   = init_chipset_aec62xx,
 322                 .init_hwif      = init_hwif_aec62xx,
 323                 .channels       = 2,
 324                 .autodma        = AUTODMA,
 325                 .enablebits     = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
 326                 .bootable       = OFF_BOARD,
 327                 .udma_mask      = 0x3f, /* udma0-5 */
 328         }
 329 };
 330
 331 /**
 332  *      aec62xx_init_one        -       called when a AEC is found
 333  *      @dev: the aec62xx device
 334  *      @id: the matching pci id
 335  *
 336  *      Called when the PCI registration layer (or the IDE initialization)
 337  *      finds a device matching our IDE device tables.
 338  *
 339  *      NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
 340  *      chips, pass a local copy of 'struct pci_device_id' down the call chain.
 341  */
 342
 343 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 344 {
 345         ide_pci_device_t d = aec62xx_chipsets[id->driver_data];
 346
 347         return d.init_setup(dev, &d);
 348 }
 349
 350 static struct pci_device_id aec62xx_pci_tbl[] = {
 351         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 352         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
 353         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
 354         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
 355         { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
 356         { 0, },
 357 };
 358 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
 359
 360 static struct pci_driver driver = {
 361         .name           = "AEC62xx_IDE",
 362         .id_table       = aec62xx_pci_tbl,
 363         .probe          = aec62xx_init_one,
 364 };
 365
 366 static int __init aec62xx_ide_init(void)
 367 {
 368         return ide_pci_register_driver(&driver);
 369 }
 370
 371 module_init(aec62xx_ide_init);
 372
 373 MODULE_AUTHOR("Andre Hedrick");
 374 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
 375 MODULE_LICENSE("GPL");