drivers/staging/ft1000/ft1000-usb/ft1000_usb.h

   1 #ifndef _FT1000_USB_H_
   2 #define _FT1000_USB_H_
   3
   4 /*Jim*/
   5 #include "ft1000_ioctl.h"
   6 #define FT1000_DRV_VER      0x01010403
   7
   8 #define  MODESZ              2
   9 #define  MAX_NUM_APP         6
  10 #define  MAX_MSG_LIMIT       200
  11 #define  NUM_OF_FREE_BUFFERS 1500
  12
  13 // Driver message types
  14 #define MEDIA_STATE        0x0010
  15 #define DSP_PROVISION      0x0030
  16 #define DSP_INIT_MSG       0x0050
  17 #define DSP_STORE_INFO       0x0070
  18 #define DSP_GET_INFO         0x0071
  19 #define GET_DRV_ERR_RPT_MSG  0x0073
  20 #define RSP_DRV_ERR_RPT_MSG  0x0074
  21
  22
  23 // Size of DPRAM Command
  24 #define MAX_CMD_SQSIZE          1780
  25 #define SLOWQ_TYPE              0
  26 #define PSEUDOSZ                16
  27 #define DSP_QID_OFFSET          4
  28
  29
  30 // MEMORY MAP FOR ELECTRABUZZ ASIC
  31 #define FT1000_REG_DFIFO_STAT   0x0008  // Downlink FIFO status register
  32 #define FT1000_REG_DPRAM_DATA   0x000C  // DPRAM VALUE in DPRAM ADDR
  33
  34 #define FT1000_DSP_LED          0xFFA  // dsp led status for PAD device
  35
  36 #define FT1000_MAG_DSP_LED               0x3FE   // dsp led status for PAD device
  37 #define FT1000_MAG_DSP_LED_INDX          0x1     // dsp led status for PAD device
  38
  39 #define  SUCCESS             0x00
  40
  41
  42 #define DRIVERID                0x00
  43
  44 // Driver Error Messages for DSP
  45 #define DSP_CONDRESET_INFO   0x7ef2
  46 #define DSP_HB_INFO          0x7ef0
  47
  48 // Magnemite specific defines
  49 #define hi_mag                  0x6968  // Byte swap hi to avoid additional system call
  50 #define ho_mag                  0x6f68  // Byte swap ho to avoid additional system call
  51
  52
  53
  54 struct media_msg {
  55         PSEUDO_HDR pseudo;
  56         u16 type;
  57         u16 length;
  58         u16 state;
  59         u32 ip_addr;
  60         u32 net_mask;
  61         u32 gateway;
  62         u32 dns_1;
  63         u32 dns_2;
  64 } __attribute__ ((packed));
  65
  66 typedef struct _DSPINITMSG {
  67     PSEUDO_HDR pseudo;
  68     u16 type;
  69     u16 length;
  70     u8 DspVer[DSPVERSZ];        // DSP version number
  71     u8 HwSerNum[HWSERNUMSZ];    // Hardware Serial Number
  72     u8 Sku[SKUSZ];              // SKU
  73     u8 eui64[EUISZ];            // EUI64
  74     u8 ProductMode[MODESZ];     // Product Mode (Market/Production)
  75     u8 RfCalVer[CALVERSZ];      // Rf Calibration version
  76     u8 RfCalDate[CALDATESZ];    // Rf Calibration date
  77 } __attribute__ ((packed)) DSPINITMSG, *PDSPINITMSG;
  78
  79
  80 typedef struct _APP_INFO_BLOCK
  81 {
  82     u32 nTxMsg;                    // DPRAM msg sent to DSP with app_id
  83     u32 nRxMsg;                    // DPRAM msg rcv from dsp with app_id
  84     u32 nTxMsgReject;              // DPRAM msg rejected due to DSP doorbell set
  85     u32 nRxMsgMiss;                // DPRAM msg dropped due to overflow
  86     struct fown_struct *fileobject;// Application's file object
  87     u16 app_id;                    // Application id
  88     int DspBCMsgFlag;
  89     int NumOfMsg;                   // number of messages queued up
  90     wait_queue_head_t   wait_dpram_msg;
  91     struct list_head app_sqlist;   // link list of msgs for applicaton on slow queue
  92 } APP_INFO_BLOCK, *PAPP_INFO_BLOCK;
  93
  94 typedef struct _PROV_RECORD {
  95     struct list_head list;
  96     u8 *pprov_data;
  97 } PROV_RECORD, *PPROV_RECORD;
  98
  99 /*end of Jim*/
 100 #define DEBUG(args...) printk(KERN_INFO args)
 101
 102 #define UCHAR               u8
 103 #define USHORT              u16
 104 #define ULONG               u32 /* WTF ??? */
 105 #define BOOLEAN             u8
 106 #define PULONG              u32 *
 107 #define PUSHORT             u16 *
 108 #define PUCHAR              u8 *
 109 #define PCHAR               u8 *
 110 #define UINT                u32
 111
 112 #define FALSE           0
 113 #define TRUE            1
 114
 115 #define STATUS_SUCCESS  0
 116 #define STATUS_FAILURE   0x1001
 117
 118 #define FT1000_STATUS_CLOSING  0x01
 119
 120 #define LARGE_TIMEOUT   5000
 121
 122 #define MAX_DSP_SESS_REC        1024
 123
 124 #define MAX_NUM_CARDS        32
 125
 126 #define DSPVERSZ                4
 127 #define HWSERNUMSZ              16
 128 #define SKUSZ                   20
 129 #define EUISZ                   8
 130 #define CALVERSZ                2
 131 #define CALDATESZ               6
 132 #define MODESZ                  2
 133
 134 #define DSPID                   0x20
 135 #define HOSTID                  0x10
 136
 137 #define DSPOAM                  0x80
 138 #define DSPAIRID                0x90
 139
 140 #define DRIVERID                0x00
 141 #define FMM                     0x10
 142 #define NETWORKID               0x20
 143 #define AUTOLNCHID              0x30
 144 #define DSPLPBKID               0x40
 145
 146 #define DSPBCMSGID              0x10
 147
 148 #define ENET_MAX_SIZE           1514
 149 #define ENET_HEADER_SIZE        14
 150
 151
 152 #define CIS_NET_ADDR_OFFSET 0xff0
 153
 154 // MAGNEMITE specific
 155
 156 #define FT1000_REG_MAG_UFDR             0x0000  // Uplink FIFO Data Register.
 157
 158 #define FT1000_REG_MAG_UFDRL            0x0000  // Uplink FIFO Data Register low-word.
 159
 160 #define FT1000_REG_MAG_UFDRH            0x0002  // Uplink FIFO Data Register high-word.
 161
 162 #define FT1000_REG_MAG_UFER                     0x0004  // Uplink FIFO End Register
 163
 164 #define FT1000_REG_MAG_UFSR                     0x0006  // Uplink FIFO Status Register
 165
 166 #define FT1000_REG_MAG_DFR                      0x0008  // Downlink FIFO Register
 167
 168 #define FT1000_REG_MAG_DFRL                     0x0008  // Downlink FIFO Register low-word
 169
 170 #define FT1000_REG_MAG_DFRH                     0x000a  // Downlink FIFO Register high-word
 171
 172 #define FT1000_REG_MAG_DFSR                     0x000c  // Downlink FIFO Status Register
 173
 174 #define FT1000_REG_MAG_DPDATA           0x0010  // Dual Port RAM Indirect Data Register
 175
 176 #define FT1000_REG_MAG_DPDATAL          0x0010  // Dual Port RAM Indirect Data Register low-word
 177
 178 #define FT1000_REG_MAG_DPDATAH          0x0012  // Dual Port RAM Indirect Data Register high-word
 179
 180 #define FT1000_REG_MAG_WATERMARK        0x002c  // Supv. Control Reg.                   LLC register
 181
 182 #define FT1000_REG_MAG_VERSION          0x0030  // LLC Version                                  LLC register
 183
 184
 185
 186 // Common
 187
 188 #define FT1000_REG_DPRAM_ADDR   0x000E  // DPRAM ADDRESS when card in IO mode
 189
 190 #define FT1000_REG_SUP_CTRL             0x0020  // Supv. Control Reg.                   LLC register
 191
 192 #define FT1000_REG_SUP_STAT             0x0022  // Supv. Status Reg                             LLC register
 193
 194 #define FT1000_REG_RESET                0x0024  // Reset Reg                                    LLC register
 195
 196 #define FT1000_REG_SUP_ISR              0x0026  // Supv ISR                                             LLC register
 197
 198 #define FT1000_REG_SUP_IMASK    0x0028  // Supervisor Interrupt Mask    LLC register
 199
 200 #define FT1000_REG_DOORBELL             0x002a  // Door Bell Reg                                LLC register
 201
 202 #define FT1000_REG_ASIC_ID      0x002e  // ASIC Identification Number
 203
 204                                                                                 // (Electrabuzz=0 Magnemite=TBD)
 205
 206
 207
 208 // DSP doorbells
 209
 210 #define FT1000_DB_DPRAM_RX              0x0001  // this value indicates that DSP has
 211
 212                                         //      data for host in DPRAM SlowQ
 213
 214 #define FT1000_DB_DNLD_RX       0x0002  // Downloader handshake doorbell
 215
 216 #define FT1000_ASIC_RESET_REQ   0x0004
 217
 218 #define FT1000_DSP_ASIC_RESET   0x0008
 219
 220
 221
 222 #define FT1000_DB_COND_RESET    0x0010
 223
 224
 225
 226 // Host doorbells
 227
 228 #define FT1000_DB_DPRAM_TX              0x0100  // this value indicates that host has
 229
 230                                         //      data for DSP in DPRAM.
 231
 232 #define FT1000_DB_DNLD_TX       0x0200  // Downloader handshake doorbell
 233
 234 #define FT1000_ASIC_RESET_DSP   0x0400
 235
 236 #define FT1000_DB_HB            0x1000  // this value indicates that supervisor
 237
 238
 239
 240 // Electrabuzz specific DPRAM mapping                                        //      has a heartbeat message for DSP.
 241
 242 #define FT1000_DPRAM_BASE               0x1000  //  0x0000 to 0x07FF    DPRAM   2Kx16 - R/W from PCMCIA or DSP
 243
 244 #define FT1000_DPRAM_TX_BASE    0x1002  //  TX AREA (SlowQ)
 245
 246 #define FT1000_DPRAM_RX_BASE    0x1800  //  RX AREA (SlowQ)
 247
 248 #define FT1000_DPRAM_SIZE       0x1000  //  4K bytes
 249
 250
 251
 252 #define FT1000_DRV_DEBUG        0x17E0  // Debug area for driver
 253
 254 #define FT1000_FIFO_LEN         0x17FC  // total length for DSP FIFO tracking
 255
 256 #define FT1000_HI_HO            0x17FE  // heartbeat with HI/HO
 257
 258 #define FT1000_DSP_STATUS       0x1FFE  // dsp status - non-zero is a request to reset dsp
 259
 260
 261
 262 #define FT1000_DSP_CON_STATE    0x1FF8  // DSP Connection Status Info
 263
 264 #define FT1000_DSP_LEDS         0x1FFA  // DSP LEDS for rcv pwr strength, Rx data, Tx data
 265
 266 #define DSP_TIMESTAMP           0x1FFC  // dsp timestamp
 267
 268 #define DSP_TIMESTAMP_DIFF      0x1FFA  // difference of dsp timestamp in DPRAM and Pseudo header.
 269
 270
 271
 272 #define FT1000_DPRAM_FEFE       0x1002  // Dsp Downloader handshake location
 273
 274
 275
 276 #define FT1000_DSP_TIMER0       0x1FF0
 277
 278 #define FT1000_DSP_TIMER1       0x1FF2
 279
 280 #define FT1000_DSP_TIMER2       0x1FF4
 281
 282 #define FT1000_DSP_TIMER3       0x1FF6
 283
 284
 285
 286 // MEMORY MAP FOR MAGNEMITE
 287
 288 #define FT1000_DPRAM_MAG_TX_BASE                 0x0000  //  TX AREA (SlowQ)
 289
 290 #define FT1000_DPRAM_MAG_RX_BASE                 0x0200  //  RX AREA (SlowQ)
 291
 292
 293
 294 #define FT1000_MAG_FIFO_LEN              0x1FF   // total length for DSP FIFO tracking
 295
 296 #define FT1000_MAG_FIFO_LEN_INDX         0x1     // low-word index
 297
 298 #define FT1000_MAG_HI_HO                 0x1FF   // heartbeat with HI/HO
 299
 300 #define FT1000_MAG_HI_HO_INDX            0x0     // high-word index
 301
 302 #define FT1000_MAG_DSP_LEDS              0x3FE   // dsp led status for PAD device
 303
 304 #define FT1000_MAG_DSP_LEDS_INDX         0x1     // dsp led status for PAD device
 305
 306
 307
 308 #define FT1000_MAG_DSP_CON_STATE         0x3FE   // DSP Connection Status Info
 309
 310 #define FT1000_MAG_DSP_CON_STATE_INDX    0x0     // DSP Connection Status Info
 311
 312
 313
 314 #define FT1000_MAG_DPRAM_FEFE            0x000   // location for dsp ready indicator
 315
 316 #define FT1000_MAG_DPRAM_FEFE_INDX       0x0     // location for dsp ready indicator
 317
 318
 319
 320 #define FT1000_MAG_DSP_TIMER0            0x3FC
 321
 322 #define FT1000_MAG_DSP_TIMER0_INDX       0x1
 323
 324
 325
 326 #define FT1000_MAG_DSP_TIMER1            0x3FC
 327
 328 #define FT1000_MAG_DSP_TIMER1_INDX       0x0
 329
 330
 331
 332 #define FT1000_MAG_DSP_TIMER2            0x3FD
 333
 334 #define FT1000_MAG_DSP_TIMER2_INDX       0x1
 335
 336
 337
 338 #define FT1000_MAG_DSP_TIMER3            0x3FD
 339
 340 #define FT1000_MAG_DSP_TIMER3_INDX       0x0
 341
 342
 343
 344 #define FT1000_MAG_TOTAL_LEN             0x200
 345
 346 #define FT1000_MAG_TOTAL_LEN_INDX        0x1
 347
 348
 349
 350 #define FT1000_MAG_PH_LEN                0x200
 351
 352 #define FT1000_MAG_PH_LEN_INDX           0x0
 353
 354
 355
 356 #define FT1000_MAG_PORT_ID               0x201
 357
 358 #define FT1000_MAG_PORT_ID_INDX          0x0
 359
 360
 361
 362 //
 363
 364 // Constants for the FT1000_REG_SUP_ISR
 365
 366 //
 367
 368 // Indicate the cause of an interrupt.
 369
 370 //
 371
 372 // SUPERVISOR ISR BIT MAPS
 373
 374
 375
 376 #define ISR_EMPTY                       (UCHAR)0x00      // no bits set in ISR
 377
 378 #define ISR_DOORBELL_ACK        (UCHAR)0x01              //  the doorbell i sent has been recieved.
 379
 380 #define ISR_DOORBELL_PEND       (UCHAR)0x02      //  doorbell for me
 381
 382 #define ISR_RCV                         (UCHAR)0x04      // packet received with no errors
 383
 384 #define ISR_WATERMARK           (UCHAR)0x08      //
 385
 386
 387
 388 // Interrupt mask register defines
 389
 390 // note these are different from the ISR BIT MAPS.
 391
 392 #define ISR_MASK_NONE                   0x0000
 393
 394 #define ISR_MASK_DOORBELL_ACK   0x0001
 395
 396 #define ISR_MASK_DOORBELL_PEND  0x0002
 397
 398 #define ISR_MASK_RCV                    0x0004
 399
 400 #define ISR_MASK_WATERMARK              0x0008    // Normally we will only mask the watermark interrupt when we want to enable interrupts.
 401
 402 #define ISR_MASK_ALL                    0xffff
 403
 404
 405
 406 #define HOST_INTF_LE            0x0000    // Host interface little endian
 407
 408 #define HOST_INTF_BE            0x0001    // Host interface big endian
 409
 410
 411
 412 #define ISR_DEFAULT_MASK                0x7ff9
 413
 414
 415
 416 #define hi                      0x6869
 417
 418 #define ho                      0x686f
 419
 420
 421
 422 #define FT1000_ASIC_RESET       0x80     // COR value for soft reset to PCMCIA core
 423
 424 #define FT1000_ASIC_BITS        0x51     // Bits set in COR register under normal operation
 425
 426 #define FT1000_ASIC_MAG_BITS    0x55     // Bits set in COR register under normal operation
 427
 428
 429
 430 #define FT1000_COR_OFFSET       0x100
 431
 432
 433
 434 #define ELECTRABUZZ_ID                  0        // ASIC ID for ELECTRABUZZ
 435
 436 #define MAGNEMITE_ID                    0x1a01   // ASIC ID for MAGNEMITE
 437
 438
 439
 440 // Maximum times trying to get ASIC out of reset
 441
 442 #define MAX_ASIC_RESET_CNT      20
 443
 444
 445
 446 #define DSP_RESET_BIT           0x1
 447
 448 #define ASIC_RESET_BIT          0x2
 449
 450 #define DSP_UNENCRYPTED         0x4
 451
 452 #define DSP_ENCRYPTED           0x8
 453
 454 #define EFUSE_MEM_DISABLE       0x0040
 455
 456
 457 #define MAX_BUF_SIZE            4096
 458
 459
 460 #if 0 //Removed by Jim
 461 typedef struct _PSEUDO_HDR
 462
 463 {
 464
 465    unsigned short    length;
 466
 467    unsigned char     source;
 468
 469    unsigned char     destination;
 470
 471    unsigned char     portdest;
 472
 473    unsigned char     portsrc;
 474
 475    unsigned short    sh_str_id;
 476
 477    unsigned char     control;
 478
 479    unsigned char     rsvd1;
 480
 481    unsigned char     seq_num;
 482
 483    unsigned char     rsvd2;
 484
 485    unsigned short    qos_class;
 486
 487    unsigned short    checksum;
 488
 489
 490
 491 } PSEUDO_HDR, *PPSEUDO_HDR;
 492 #endif //end of Jim
 493
 494 typedef struct _DRVMSG {
 495         PSEUDO_HDR pseudo;
 496         u16 type;
 497         u16 length;
 498         u8  data[0];
 499 } __attribute__ ((packed)) DRVMSG, *PDRVMSG;
 500
 501 struct ft1000_device
 502 {
 503         struct usb_device *dev;
 504         struct net_device *net;
 505         spinlock_t device_lock;
 506
 507         u32 status;
 508
 509         wait_queue_head_t control_wait;
 510
 511         struct urb *rx_urb;
 512         struct urb *tx_urb;
 513
 514         u8 tx_buf[MAX_BUF_SIZE];
 515         u8 rx_buf[MAX_BUF_SIZE];
 516
 517         u8 bulk_in_endpointAddr;
 518         u8 bulk_out_endpointAddr;
 519
 520         //struct ft1000_ethernet_configuration configuration;
 521
 522 //      struct net_device_stats stats; //mbelian
 523 } __attribute__ ((packed));
 524
 525 typedef struct _FT1000_INFO {
 526     struct ft1000_device *pFt1000Dev;
 527     struct net_device_stats stats;
 528
 529     struct task_struct *pPollThread;
 530
 531     unsigned char fcodeldr;
 532     unsigned char bootmode;
 533         unsigned char usbboot;
 534     unsigned short dspalive;
 535     u16 ASIC_ID;
 536     BOOLEAN fProvComplete;
 537     BOOLEAN fCondResetPend;
 538     BOOLEAN fAppMsgPend;
 539     char *pfwimg;
 540     int fwimgsz;
 541     u16 DrvErrNum;
 542     u8  *pTestImage;
 543     u16 AsicID;
 544     unsigned long TestImageIndx;
 545     unsigned long TestImageSz;
 546     u8  TestImageEnable;
 547     u8  TestImageReady;
 548     int ASICResetNum;
 549     int DspAsicReset;
 550     int PktIntfErr;
 551     int DSPResetNum;
 552     int NumIOCTLBufs;
 553     int IOCTLBufLvl;
 554     int DeviceCreated;
 555     int CardReady;
 556     int NetDevRegDone;
 557     u8 CardNumber;
 558     u8 DeviceName[15];
 559     int DeviceMajor;
 560     int registered;
 561     int mediastate;
 562     int dhcpflg;
 563     u16 packetseqnum;
 564     u8 squeseqnum;                 // sequence number on slow queue
 565     spinlock_t dpram_lock;
 566     spinlock_t fifo_lock;
 567     u16 CurrentInterruptEnableMask;
 568     int InterruptsEnabled;
 569     u16 fifo_cnt;
 570     u8 DspVer[DSPVERSZ];        // DSP version number
 571     u8 HwSerNum[HWSERNUMSZ];    // Hardware Serial Number
 572     u8 Sku[SKUSZ];              // SKU
 573     u8 eui64[EUISZ];            // EUI64
 574     time_t ConTm;               // Connection Time
 575     u8 ProductMode[MODESZ];
 576     u8 RfCalVer[CALVERSZ];
 577     u8 RfCalDate[CALDATESZ];
 578     u16 DSP_TIME[4];
 579     u16 ProgSnr;
 580     u16 LedStat;        //mbelian
 581     u16 ConStat;        //mbelian
 582     u16 ProgConStat;
 583     struct list_head prov_list;
 584     int appcnt;
 585     APP_INFO_BLOCK app_info[MAX_NUM_APP]; //Added by Jim
 586     u16 DSPInfoBlklen;
 587     u16 DrvMsgPend;
 588     int (*ft1000_reset)(struct net_device *dev);
 589     u16 DSPInfoBlk[MAX_DSP_SESS_REC];
 590     union {
 591         u16 Rec[MAX_DSP_SESS_REC];
 592         u32 MagRec[MAX_DSP_SESS_REC/2];
 593     } DSPSess;
 594         unsigned short tempbuf[32];
 595         char netdevname[IFNAMSIZ];
 596         struct proc_dir_entry *ft1000_proc_dir; //mbelian
 597 } FT1000_INFO, *PFT1000_INFO;
 598
 599
 600 typedef struct _DPRAM_BLK {
 601     struct list_head list;
 602     u16 *pbuffer;
 603 } __attribute__ ((packed)) DPRAM_BLK, *PDPRAM_BLK;
 604
 605 u16 ft1000_read_register(struct ft1000_device *ft1000dev, u16* Data, u16 nRegIndx);
 606 u16 ft1000_write_register(struct ft1000_device *ft1000dev, USHORT value, u16 nRegIndx);
 607 u16 ft1000_read_dpram32(struct ft1000_device *ft1000dev, USHORT indx, PUCHAR buffer, USHORT cnt);
 608 u16 ft1000_write_dpram32(struct ft1000_device *ft1000dev, USHORT indx, PUCHAR buffer, USHORT cnt);
 609 u16 ft1000_read_dpram16(struct ft1000_device *ft1000dev, USHORT indx, PUCHAR buffer, u8 highlow);
 610 u16 ft1000_write_dpram16(struct ft1000_device *ft1000dev, USHORT indx, USHORT value, u8 highlow);
 611 u16 fix_ft1000_read_dpram32(struct ft1000_device *ft1000dev, USHORT indx, PUCHAR buffer);
 612 u16 fix_ft1000_write_dpram32(struct ft1000_device *ft1000dev, USHORT indx, PUCHAR buffer);
 613
 614 extern void *pFileStart;
 615 extern size_t FileLength;
 616 extern int numofmsgbuf;
 617
 618 int ft1000_close (struct net_device *dev);
 619 u16 scram_dnldr(struct ft1000_device *ft1000dev, void *pFileStart, ULONG  FileLength);
 620
 621 extern struct list_head freercvpool;
 622 extern spinlock_t free_buff_lock;   // lock to arbitrate free buffer list for receive command data
 623
 624 int ft1000_CreateDevice(struct ft1000_device *dev);
 625 void ft1000_DestroyDevice(struct net_device *dev);
 626 extern void CardSendCommand(struct ft1000_device *ft1000dev, void *ptempbuffer, int size);
 627
 628 PDPRAM_BLK ft1000_get_buffer (struct list_head *bufflist);
 629 void ft1000_free_buffer (PDPRAM_BLK pdpram_blk, struct list_head *plist);
 630
 631 char *getfw (char *fn, size_t *pimgsz);
 632
 633 int dsp_reload(struct ft1000_device *ft1000dev);
 634 u16 init_ft1000_netdev(struct ft1000_device *ft1000dev);
 635 struct usb_interface;
 636 u16 reg_ft1000_netdev(struct ft1000_device *ft1000dev, struct usb_interface *intf);
 637 int ft1000_poll(void* dev_id);
 638
 639 void ft1000InitProc(struct net_device *dev);
 640 void ft1000CleanupProc(FT1000_INFO *info);
 641
 642
 643
 644 #endif