2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr
;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic
;
63 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
64 static int disable_apic_timer __cpuinitdata
;
65 /* Local APIC timer works in C2 */
66 int local_apic_timer_c2_ok
;
67 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
69 int first_system_vector
= 0xfe;
71 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
74 * Debug level, exported for io_apic.c
76 unsigned int apic_verbosity
;
80 /* Have we found an MP table */
83 static struct resource lapic_resource
= {
85 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
88 static unsigned int calibration_result
;
90 static int lapic_next_event(unsigned long delta
,
91 struct clock_event_device
*evt
);
92 static void lapic_timer_setup(enum clock_event_mode mode
,
93 struct clock_event_device
*evt
);
94 static void lapic_timer_broadcast(cpumask_t mask
);
95 static void apic_pm_activate(void);
98 * The local apic timer can be used for any function which is CPU local.
100 static struct clock_event_device lapic_clockevent
= {
102 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
103 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
105 .set_mode
= lapic_timer_setup
,
106 .set_next_event
= lapic_next_event
,
107 .broadcast
= lapic_timer_broadcast
,
111 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
113 /* Local APIC was disabled by the BIOS and enabled by the kernel */
114 static int enabled_via_apicbase
;
116 static unsigned long apic_phys
;
117 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
121 * Get the LAPIC version
123 static inline int lapic_get_version(void)
125 return GET_APIC_VERSION(apic_read(APIC_LVR
));
129 * Check, if the APIC is integrated or a separate chip
131 static inline int lapic_is_integrated(void)
136 return APIC_INTEGRATED(lapic_get_version());
141 * Check, whether this is a modern or a first generation APIC
143 static int modern_apic(void)
145 /* AMD systems use old APIC versions, so check the CPU */
146 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
147 boot_cpu_data
.x86
>= 0xf)
149 return lapic_get_version() >= 0x14;
153 * Paravirt kernels also might be using these below ops. So we still
154 * use generic apic_read()/apic_write(), which might be pointing to different
155 * ops in PARAVIRT case.
157 void xapic_wait_icr_idle(void)
159 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
163 u32
safe_xapic_wait_icr_idle(void)
170 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
174 } while (timeout
++ < 1000);
179 void xapic_icr_write(u32 low
, u32 id
)
181 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
182 apic_write(APIC_ICR
, low
);
185 u64
xapic_icr_read(void)
189 icr2
= apic_read(APIC_ICR2
);
190 icr1
= apic_read(APIC_ICR
);
192 return icr1
| ((u64
)icr2
<< 32);
195 static struct apic_ops xapic_ops
= {
196 .read
= native_apic_mem_read
,
197 .write
= native_apic_mem_write
,
198 .icr_read
= xapic_icr_read
,
199 .icr_write
= xapic_icr_write
,
200 .wait_icr_idle
= xapic_wait_icr_idle
,
201 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
204 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
205 EXPORT_SYMBOL_GPL(apic_ops
);
208 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
210 void __cpuinit
enable_NMI_through_LVT0(void)
214 /* unmask and set to NMI */
217 /* Level triggered for 82489DX (32bit mode) */
218 if (!lapic_is_integrated())
219 v
|= APIC_LVT_LEVEL_TRIGGER
;
221 apic_write(APIC_LVT0
, v
);
225 * get_physical_broadcast - Get number of physical broadcast IDs
227 int get_physical_broadcast(void)
229 return modern_apic() ? 0xff : 0xf;
233 * lapic_get_maxlvt - get the maximum number of local vector table entries
235 int lapic_get_maxlvt(void)
239 v
= apic_read(APIC_LVR
);
241 * - we always have APIC integrated on 64bit mode
242 * - 82489DXs do not report # of LVT entries
244 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
253 #define APIC_DIVISOR 1
255 #define APIC_DIVISOR 16
259 * This function sets up the local APIC timer, with a timeout of
260 * 'clocks' APIC bus clock. During calibration we actually call
261 * this function twice on the boot CPU, once with a bogus timeout
262 * value, second time for real. The other (noncalibrating) CPUs
263 * call this function only once, with the real, calibrated value.
265 * We do reads before writes even if unnecessary, to get around the
266 * P5 APIC double write bug.
268 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
270 unsigned int lvtt_value
, tmp_value
;
272 lvtt_value
= LOCAL_TIMER_VECTOR
;
274 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
275 if (!lapic_is_integrated())
276 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
279 lvtt_value
|= APIC_LVT_MASKED
;
281 apic_write(APIC_LVTT
, lvtt_value
);
286 tmp_value
= apic_read(APIC_TDCR
);
287 apic_write(APIC_TDCR
,
288 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
292 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
296 * Setup extended LVT, AMD specific (K8, family 10h)
298 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
299 * MCE interrupts are supported. Thus MCE offset must be set to 0.
302 #define APIC_EILVT_LVTOFF_MCE 0
303 #define APIC_EILVT_LVTOFF_IBS 1
305 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
307 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
308 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
313 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
315 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
316 return APIC_EILVT_LVTOFF_MCE
;
319 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
321 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
322 return APIC_EILVT_LVTOFF_IBS
;
326 * Program the next event, relative to now
328 static int lapic_next_event(unsigned long delta
,
329 struct clock_event_device
*evt
)
331 apic_write(APIC_TMICT
, delta
);
336 * Setup the lapic timer in periodic or oneshot mode
338 static void lapic_timer_setup(enum clock_event_mode mode
,
339 struct clock_event_device
*evt
)
344 /* Lapic used as dummy for broadcast ? */
345 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
348 local_irq_save(flags
);
351 case CLOCK_EVT_MODE_PERIODIC
:
352 case CLOCK_EVT_MODE_ONESHOT
:
353 __setup_APIC_LVTT(calibration_result
,
354 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
356 case CLOCK_EVT_MODE_UNUSED
:
357 case CLOCK_EVT_MODE_SHUTDOWN
:
358 v
= apic_read(APIC_LVTT
);
359 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
360 apic_write(APIC_LVTT
, v
);
362 case CLOCK_EVT_MODE_RESUME
:
363 /* Nothing to do here */
367 local_irq_restore(flags
);
371 * Local APIC timer broadcast function
373 static void lapic_timer_broadcast(cpumask_t mask
)
376 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
381 * Setup the local APIC timer for this CPU. Copy the initilized values
382 * of the boot CPU and register the clock event in the framework.
384 static void __devinit
setup_APIC_timer(void)
386 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
388 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
389 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
391 clockevents_register_device(levt
);
395 * In this functions we calibrate APIC bus clocks to the external timer.
397 * We want to do the calibration only once since we want to have local timer
398 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
401 * This was previously done by reading the PIT/HPET and waiting for a wrap
402 * around to find out, that a tick has elapsed. I have a box, where the PIT
403 * readout is broken, so it never gets out of the wait loop again. This was
404 * also reported by others.
406 * Monitoring the jiffies value is inaccurate and the clockevents
407 * infrastructure allows us to do a simple substitution of the interrupt
410 * The calibration routine also uses the pm_timer when possible, as the PIT
411 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
412 * back to normal later in the boot process).
415 #define LAPIC_CAL_LOOPS (HZ/10)
417 static __initdata
int lapic_cal_loops
= -1;
418 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
419 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
420 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
421 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
424 * Temporary interrupt handler.
426 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
428 unsigned long long tsc
= 0;
429 long tapic
= apic_read(APIC_TMCCT
);
430 unsigned long pm
= acpi_pm_read_early();
435 switch (lapic_cal_loops
++) {
437 lapic_cal_t1
= tapic
;
438 lapic_cal_tsc1
= tsc
;
440 lapic_cal_j1
= jiffies
;
443 case LAPIC_CAL_LOOPS
:
444 lapic_cal_t2
= tapic
;
445 lapic_cal_tsc2
= tsc
;
446 if (pm
< lapic_cal_pm1
)
447 pm
+= ACPI_PM_OVRRUN
;
449 lapic_cal_j2
= jiffies
;
454 static int __init
calibrate_APIC_clock(void)
456 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
457 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
458 const long pm_thresh
= pm_100ms
/100;
459 void (*real_handler
)(struct clock_event_device
*dev
);
460 unsigned long deltaj
;
462 int pm_referenced
= 0;
466 /* Replace the global interrupt handler */
467 real_handler
= global_clock_event
->event_handler
;
468 global_clock_event
->event_handler
= lapic_cal_handler
;
471 * Setup the APIC counter to 1e9. There is no way the lapic
472 * can underflow in the 100ms detection time frame
474 __setup_APIC_LVTT(1000000000, 0, 0);
476 /* Let the interrupts run */
479 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
484 /* Restore the real event handler */
485 global_clock_event
->event_handler
= real_handler
;
487 /* Build delta t1-t2 as apic timer counts down */
488 delta
= lapic_cal_t1
- lapic_cal_t2
;
489 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
491 /* Check, if the PM timer is available */
492 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
493 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
499 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
501 if (deltapm
> (pm_100ms
- pm_thresh
) &&
502 deltapm
< (pm_100ms
+ pm_thresh
)) {
503 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
505 res
= (((u64
) deltapm
) * mult
) >> 22;
506 do_div(res
, 1000000);
507 printk(KERN_WARNING
"APIC calibration not consistent "
508 "with PM Timer: %ldms instead of 100ms\n",
510 /* Correct the lapic counter value */
511 res
= (((u64
) delta
) * pm_100ms
);
512 do_div(res
, deltapm
);
513 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
514 "%lu (%ld)\n", (unsigned long) res
, delta
);
520 /* Calculate the scaled math multiplication factor */
521 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
522 lapic_clockevent
.shift
);
523 lapic_clockevent
.max_delta_ns
=
524 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
525 lapic_clockevent
.min_delta_ns
=
526 clockevent_delta2ns(0xF, &lapic_clockevent
);
528 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
530 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
531 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
532 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
536 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
537 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
539 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
540 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
543 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
545 calibration_result
/ (1000000 / HZ
),
546 calibration_result
% (1000000 / HZ
));
549 * Do a sanity check on the APIC calibration result
551 if (calibration_result
< (1000000 / HZ
)) {
554 "APIC frequency too slow, disabling apic timer\n");
558 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
560 /* We trust the pm timer based calibration */
561 if (!pm_referenced
) {
562 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
565 * Setup the apic timer manually
567 levt
->event_handler
= lapic_cal_handler
;
568 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
569 lapic_cal_loops
= -1;
571 /* Let the interrupts run */
574 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
579 /* Stop the lapic timer */
580 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
585 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
586 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
588 /* Check, if the jiffies result is consistent */
589 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
590 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
592 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
596 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
598 "APIC timer disabled due to verification failure.\n");
606 * Setup the boot APIC
608 * Calibrate and verify the result.
610 void __init
setup_boot_APIC_clock(void)
613 * The local apic timer can be disabled via the kernel
614 * commandline or from the CPU detection code. Register the lapic
615 * timer as a dummy clock event source on SMP systems, so the
616 * broadcast mechanism is used. On UP systems simply ignore it.
618 if (disable_apic_timer
) {
619 printk(KERN_INFO
"Disabling APIC timer\n");
620 /* No broadcast on UP ! */
621 if (num_possible_cpus() > 1) {
622 lapic_clockevent
.mult
= 1;
628 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
629 "calibrating APIC timer ...\n");
631 if (calibrate_APIC_clock()) {
632 /* No broadcast on UP ! */
633 if (num_possible_cpus() > 1)
639 * If nmi_watchdog is set to IO_APIC, we need the
640 * PIT/HPET going. Otherwise register lapic as a dummy
643 if (nmi_watchdog
!= NMI_IO_APIC
)
644 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
646 printk(KERN_WARNING
"APIC timer registered as dummy,"
647 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
649 /* Setup the lapic or request the broadcast */
653 void __devinit
setup_secondary_APIC_clock(void)
659 * The guts of the apic timer interrupt
661 static void local_apic_timer_interrupt(void)
663 int cpu
= smp_processor_id();
664 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
667 * Normally we should not be here till LAPIC has been initialized but
668 * in some cases like kdump, its possible that there is a pending LAPIC
669 * timer interrupt from previous kernel's context and is delivered in
670 * new kernel the moment interrupts are enabled.
672 * Interrupts are enabled early and LAPIC is setup much later, hence
673 * its possible that when we get here evt->event_handler is NULL.
674 * Check for event_handler being NULL and discard the interrupt as
677 if (!evt
->event_handler
) {
679 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
681 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
686 * the NMI deadlock-detector uses this.
688 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
690 evt
->event_handler(evt
);
694 * Local APIC timer interrupt. This is the most natural way for doing
695 * local interrupts, but local timer interrupts can be emulated by
696 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
698 * [ if a single-CPU system runs an SMP kernel then we call the local
699 * interrupt as well. Thus we cannot inline the local irq ... ]
701 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
703 struct pt_regs
*old_regs
= set_irq_regs(regs
);
706 * NOTE! We'd better ACK the irq immediately,
707 * because timer handling can be slow.
711 * update_process_times() expects us to have done irq_enter().
712 * Besides, if we don't timer interrupts ignore the global
713 * interrupt lock, which is the WrongThing (tm) to do.
716 local_apic_timer_interrupt();
719 set_irq_regs(old_regs
);
722 int setup_profiling_timer(unsigned int multiplier
)
728 * Local APIC start and shutdown
732 * clear_local_APIC - shutdown the local APIC
734 * This is called, when a CPU is disabled and before rebooting, so the state of
735 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
736 * leftovers during boot.
738 void clear_local_APIC(void)
743 /* APIC hasn't been mapped yet */
747 maxlvt
= lapic_get_maxlvt();
749 * Masking an LVT entry can trigger a local APIC error
750 * if the vector is zero. Mask LVTERR first to prevent this.
753 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
754 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
757 * Careful: we have to set masks only first to deassert
758 * any level-triggered sources.
760 v
= apic_read(APIC_LVTT
);
761 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
762 v
= apic_read(APIC_LVT0
);
763 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
764 v
= apic_read(APIC_LVT1
);
765 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
767 v
= apic_read(APIC_LVTPC
);
768 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
771 /* lets not touch this if we didn't frob it */
772 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
774 v
= apic_read(APIC_LVTTHMR
);
775 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
779 * Clean APIC state for other OSs:
781 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
782 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
783 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
785 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
787 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
789 /* Integrated APIC (!82489DX) ? */
790 if (lapic_is_integrated()) {
792 /* Clear ESR due to Pentium errata 3AP and 11AP */
793 apic_write(APIC_ESR
, 0);
799 * disable_local_APIC - clear and disable the local APIC
801 void disable_local_APIC(void)
808 * Disable APIC (implies clearing of registers
811 value
= apic_read(APIC_SPIV
);
812 value
&= ~APIC_SPIV_APIC_ENABLED
;
813 apic_write(APIC_SPIV
, value
);
817 * When LAPIC was disabled by the BIOS and enabled by the kernel,
818 * restore the disabled state.
820 if (enabled_via_apicbase
) {
823 rdmsr(MSR_IA32_APICBASE
, l
, h
);
824 l
&= ~MSR_IA32_APICBASE_ENABLE
;
825 wrmsr(MSR_IA32_APICBASE
, l
, h
);
831 * If Linux enabled the LAPIC against the BIOS default disable it down before
832 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
833 * not power-off. Additionally clear all LVT entries before disable_local_APIC
834 * for the case where Linux didn't enable the LAPIC.
836 void lapic_shutdown(void)
843 local_irq_save(flags
);
846 if (!enabled_via_apicbase
)
850 disable_local_APIC();
853 local_irq_restore(flags
);
857 * This is to verify that we're looking at a real local APIC.
858 * Check these against your board if the CPUs aren't getting
859 * started for no apparent reason.
861 int __init
verify_local_APIC(void)
863 unsigned int reg0
, reg1
;
866 * The version register is read-only in a real APIC.
868 reg0
= apic_read(APIC_LVR
);
869 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
870 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
871 reg1
= apic_read(APIC_LVR
);
872 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
875 * The two version reads above should print the same
876 * numbers. If the second one is different, then we
877 * poke at a non-APIC.
883 * Check if the version looks reasonably.
885 reg1
= GET_APIC_VERSION(reg0
);
886 if (reg1
== 0x00 || reg1
== 0xff)
888 reg1
= lapic_get_maxlvt();
889 if (reg1
< 0x02 || reg1
== 0xff)
893 * The ID register is read/write in a real APIC.
895 reg0
= apic_read(APIC_ID
);
896 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
897 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
898 reg1
= apic_read(APIC_ID
);
899 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
900 apic_write(APIC_ID
, reg0
);
901 if (reg1
!= (reg0
^ APIC_ID_MASK
))
905 * The next two are just to see if we have sane values.
906 * They're only really relevant if we're in Virtual Wire
907 * compatibility mode, but most boxes are anymore.
909 reg0
= apic_read(APIC_LVT0
);
910 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
911 reg1
= apic_read(APIC_LVT1
);
912 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
918 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
920 void __init
sync_Arb_IDs(void)
923 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
926 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
932 apic_wait_icr_idle();
934 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
935 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
936 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
940 * An initial setup of the virtual wire mode.
942 void __init
init_bsp_APIC(void)
947 * Don't do the setup now if we have a SMP BIOS as the
948 * through-I/O-APIC virtual wire mode might be active.
950 if (smp_found_config
|| !cpu_has_apic
)
954 * Do not trust the local APIC being empty at bootup.
961 value
= apic_read(APIC_SPIV
);
962 value
&= ~APIC_VECTOR_MASK
;
963 value
|= APIC_SPIV_APIC_ENABLED
;
966 /* This bit is reserved on P4/Xeon and should be cleared */
967 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
968 (boot_cpu_data
.x86
== 15))
969 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
972 value
|= APIC_SPIV_FOCUS_DISABLED
;
973 value
|= SPURIOUS_APIC_VECTOR
;
974 apic_write(APIC_SPIV
, value
);
977 * Set up the virtual wire mode.
979 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
981 if (!lapic_is_integrated()) /* 82489DX */
982 value
|= APIC_LVT_LEVEL_TRIGGER
;
983 apic_write(APIC_LVT1
, value
);
986 static void __cpuinit
lapic_setup_esr(void)
988 unsigned long oldvalue
, value
, maxlvt
;
989 if (lapic_is_integrated() && !esr_disable
) {
992 * Something untraceable is creating bad interrupts on
993 * secondary quads ... for the moment, just leave the
994 * ESR disabled - we can't do anything useful with the
995 * errors anyway - mbligh
997 printk(KERN_INFO
"Leaving ESR disabled.\n");
1001 maxlvt
= lapic_get_maxlvt();
1002 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1003 apic_write(APIC_ESR
, 0);
1004 oldvalue
= apic_read(APIC_ESR
);
1006 /* enables sending errors */
1007 value
= ERROR_APIC_VECTOR
;
1008 apic_write(APIC_LVTERR
, value
);
1010 * spec says clear errors after enabling vector.
1013 apic_write(APIC_ESR
, 0);
1014 value
= apic_read(APIC_ESR
);
1015 if (value
!= oldvalue
)
1016 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1017 "vector: 0x%08lx after: 0x%08lx\n",
1020 printk(KERN_INFO
"No ESR for 82489DX.\n");
1026 * setup_local_APIC - setup the local APIC
1028 void __cpuinit
setup_local_APIC(void)
1030 unsigned long value
, integrated
;
1033 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1035 apic_write(APIC_ESR
, 0);
1036 apic_write(APIC_ESR
, 0);
1037 apic_write(APIC_ESR
, 0);
1038 apic_write(APIC_ESR
, 0);
1041 integrated
= lapic_is_integrated();
1044 * Double-check whether this APIC is really registered.
1046 if (!apic_id_registered())
1050 * Intel recommends to set DFR, LDR and TPR before enabling
1051 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1052 * document number 292116). So here it goes...
1057 * Set Task Priority to 'accept all'. We never change this
1060 value
= apic_read(APIC_TASKPRI
);
1061 value
&= ~APIC_TPRI_MASK
;
1062 apic_write(APIC_TASKPRI
, value
);
1065 * After a crash, we no longer service the interrupts and a pending
1066 * interrupt from previous kernel might still have ISR bit set.
1068 * Most probably by now CPU has serviced that pending interrupt and
1069 * it might not have done the ack_APIC_irq() because it thought,
1070 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1071 * does not clear the ISR bit and cpu thinks it has already serivced
1072 * the interrupt. Hence a vector might get locked. It was noticed
1073 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1075 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1076 value
= apic_read(APIC_ISR
+ i
*0x10);
1077 for (j
= 31; j
>= 0; j
--) {
1084 * Now that we are all set up, enable the APIC
1086 value
= apic_read(APIC_SPIV
);
1087 value
&= ~APIC_VECTOR_MASK
;
1091 value
|= APIC_SPIV_APIC_ENABLED
;
1094 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1095 * certain networking cards. If high frequency interrupts are
1096 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1097 * entry is masked/unmasked at a high rate as well then sooner or
1098 * later IOAPIC line gets 'stuck', no more interrupts are received
1099 * from the device. If focus CPU is disabled then the hang goes
1102 * [ This bug can be reproduced easily with a level-triggered
1103 * PCI Ne2000 networking cards and PII/PIII processors, dual
1107 * Actually disabling the focus CPU check just makes the hang less
1108 * frequent as it makes the interrupt distributon model be more
1109 * like LRU than MRU (the short-term load is more even across CPUs).
1110 * See also the comment in end_level_ioapic_irq(). --macro
1113 /* Enable focus processor (bit==0) */
1114 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1117 * Set spurious IRQ vector
1119 value
|= SPURIOUS_APIC_VECTOR
;
1120 apic_write(APIC_SPIV
, value
);
1123 * Set up LVT0, LVT1:
1125 * set up through-local-APIC on the BP's LINT0. This is not
1126 * strictly necessary in pure symmetric-IO mode, but sometimes
1127 * we delegate interrupts to the 8259A.
1130 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1132 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1133 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1134 value
= APIC_DM_EXTINT
;
1135 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1136 smp_processor_id());
1138 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1139 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1140 smp_processor_id());
1142 apic_write(APIC_LVT0
, value
);
1145 * only the BP should see the LINT1 NMI signal, obviously.
1147 if (!smp_processor_id())
1148 value
= APIC_DM_NMI
;
1150 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1151 if (!integrated
) /* 82489DX */
1152 value
|= APIC_LVT_LEVEL_TRIGGER
;
1153 apic_write(APIC_LVT1
, value
);
1156 void __cpuinit
end_local_APIC_setup(void)
1158 unsigned long value
;
1161 /* Disable the local apic timer */
1162 value
= apic_read(APIC_LVTT
);
1163 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1164 apic_write(APIC_LVTT
, value
);
1166 setup_apic_nmi_watchdog(NULL
);
1171 * Detect and initialize APIC
1173 static int __init
detect_init_APIC(void)
1177 /* Disabled by kernel option? */
1181 switch (boot_cpu_data
.x86_vendor
) {
1182 case X86_VENDOR_AMD
:
1183 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1184 (boot_cpu_data
.x86
== 15))
1187 case X86_VENDOR_INTEL
:
1188 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1189 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1196 if (!cpu_has_apic
) {
1198 * Over-ride BIOS and try to enable the local APIC only if
1199 * "lapic" specified.
1201 if (!force_enable_local_apic
) {
1202 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1203 "you can enable it with \"lapic\"\n");
1207 * Some BIOSes disable the local APIC in the APIC_BASE
1208 * MSR. This can only be done in software for Intel P6 or later
1209 * and AMD K7 (Model > 1) or later.
1211 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1212 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1214 "Local APIC disabled by BIOS -- reenabling.\n");
1215 l
&= ~MSR_IA32_APICBASE_BASE
;
1216 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1217 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1218 enabled_via_apicbase
= 1;
1222 * The APIC feature bit should now be enabled
1225 features
= cpuid_edx(1);
1226 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1227 printk(KERN_WARNING
"Could not enable APIC!\n");
1230 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1231 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1233 /* The BIOS may have set up the APIC at some other address */
1234 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1235 if (l
& MSR_IA32_APICBASE_ENABLE
)
1236 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1238 printk(KERN_INFO
"Found and enabled local APIC!\n");
1245 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1250 * init_apic_mappings - initialize APIC mappings
1252 void __init
init_apic_mappings(void)
1255 * If no local APIC can be found then set up a fake all
1256 * zeroes page to simulate the local APIC and another
1257 * one for the IO-APIC.
1259 if (!smp_found_config
&& detect_init_APIC()) {
1260 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1261 apic_phys
= __pa(apic_phys
);
1263 apic_phys
= mp_lapic_addr
;
1265 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1266 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1270 * Fetch the APIC ID of the BSP in case we have a
1271 * default configuration (or the MP table is broken).
1273 if (boot_cpu_physical_apicid
== -1U)
1274 boot_cpu_physical_apicid
= read_apic_id();
1279 * This initializes the IO-APIC and APIC hardware if this is
1283 int apic_version
[MAX_APICS
];
1285 int __init
APIC_init_uniprocessor(void)
1287 if (!smp_found_config
&& !cpu_has_apic
)
1291 * Complain if the BIOS pretends there is one.
1293 if (!cpu_has_apic
&&
1294 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1295 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1296 boot_cpu_physical_apicid
);
1297 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1301 verify_local_APIC();
1306 * Hack: In case of kdump, after a crash, kernel might be booting
1307 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1308 * might be zero if read from MP tables. Get it from LAPIC.
1310 #ifdef CONFIG_CRASH_DUMP
1311 boot_cpu_physical_apicid
= read_apic_id();
1313 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1317 #ifdef CONFIG_X86_IO_APIC
1318 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1320 localise_nmi_watchdog();
1321 end_local_APIC_setup();
1322 #ifdef CONFIG_X86_IO_APIC
1323 if (smp_found_config
)
1324 if (!skip_ioapic_setup
&& nr_ioapics
)
1333 * Local APIC interrupts
1337 * This interrupt should _never_ happen with our APIC/SMP architecture
1339 void smp_spurious_interrupt(struct pt_regs
*regs
)
1345 * Check if this really is a spurious interrupt and ACK it
1346 * if it is a vectored one. Just in case...
1347 * Spurious interrupts should not be ACKed.
1349 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1350 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1353 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1354 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1355 "should never happen.\n", smp_processor_id());
1356 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1361 * This interrupt should never happen with our APIC/SMP architecture
1363 void smp_error_interrupt(struct pt_regs
*regs
)
1365 unsigned long v
, v1
;
1368 /* First tickle the hardware, only then report what went on. -- REW */
1369 v
= apic_read(APIC_ESR
);
1370 apic_write(APIC_ESR
, 0);
1371 v1
= apic_read(APIC_ESR
);
1373 atomic_inc(&irq_err_count
);
1375 /* Here is what the APIC error bits mean:
1378 2: Send accept error
1379 3: Receive accept error
1381 5: Send illegal vector
1382 6: Received illegal vector
1383 7: Illegal register address
1385 printk(KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1386 smp_processor_id(), v
, v1
);
1391 * connect_bsp_APIC - attach the APIC to the interrupt system
1393 void __init
connect_bsp_APIC(void)
1395 #ifdef CONFIG_X86_32
1398 * Do not trust the local APIC being empty at bootup.
1402 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1403 * local APIC to INT and NMI lines.
1405 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1406 "enabling APIC mode.\n");
1415 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1416 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1418 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1421 void disconnect_bsp_APIC(int virt_wire_setup
)
1423 #ifdef CONFIG_X86_32
1426 * Put the board back into PIC mode (has an effect only on
1427 * certain older boards). Note that APIC interrupts, including
1428 * IPIs, won't work beyond this point! The only exception are
1431 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1432 "entering PIC mode.\n");
1439 /* Go back to Virtual Wire compatibility mode */
1442 /* For the spurious interrupt use vector F, and enable it */
1443 value
= apic_read(APIC_SPIV
);
1444 value
&= ~APIC_VECTOR_MASK
;
1445 value
|= APIC_SPIV_APIC_ENABLED
;
1447 apic_write(APIC_SPIV
, value
);
1449 if (!virt_wire_setup
) {
1451 * For LVT0 make it edge triggered, active high,
1452 * external and enabled
1454 value
= apic_read(APIC_LVT0
);
1455 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1456 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1457 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1458 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1459 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1460 apic_write(APIC_LVT0
, value
);
1463 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1467 * For LVT1 make it edge triggered, active high,
1470 value
= apic_read(APIC_LVT1
);
1471 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1472 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1473 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1474 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1475 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1476 apic_write(APIC_LVT1
, value
);
1479 void __cpuinit
generic_processor_info(int apicid
, int version
)
1487 if (version
== 0x0) {
1488 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1489 "fixing up to 0x10. (tell your hw vendor)\n",
1493 apic_version
[apicid
] = version
;
1495 if (num_processors
>= NR_CPUS
) {
1496 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1497 " Processor ignored.\n", NR_CPUS
);
1501 if (num_processors
>= maxcpus
) {
1502 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1503 " Processor ignored.\n", maxcpus
);
1508 cpus_complement(tmp_map
, cpu_present_map
);
1509 cpu
= first_cpu(tmp_map
);
1511 physid_set(apicid
, phys_cpu_present_map
);
1512 if (apicid
== boot_cpu_physical_apicid
) {
1514 * x86_bios_cpu_apicid is required to have processors listed
1515 * in same order as logical cpu numbers. Hence the first
1516 * entry is BSP, and so on.
1520 if (apicid
> max_physical_apicid
)
1521 max_physical_apicid
= apicid
;
1523 #ifdef CONFIG_X86_32
1525 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1526 * but we need to work other dependencies like SMP_SUSPEND etc
1527 * before this can be done without some confusion.
1528 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1529 * - Ashok Raj <ashok.raj@intel.com>
1531 if (max_physical_apicid
>= 8) {
1532 switch (boot_cpu_data
.x86_vendor
) {
1533 case X86_VENDOR_INTEL
:
1534 if (!APIC_XAPIC(version
)) {
1538 /* If P4 and above fall through */
1539 case X86_VENDOR_AMD
:
1545 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1546 /* are we being called early in kernel startup? */
1547 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1548 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1549 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1551 cpu_to_apicid
[cpu
] = apicid
;
1552 bios_cpu_apicid
[cpu
] = apicid
;
1554 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1555 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1559 cpu_set(cpu
, cpu_possible_map
);
1560 cpu_set(cpu
, cpu_present_map
);
1570 * 'active' is true if the local APIC was enabled by us and
1571 * not the BIOS; this signifies that we are also responsible
1572 * for disabling it before entering apm/acpi suspend
1575 /* r/w apic fields */
1576 unsigned int apic_id
;
1577 unsigned int apic_taskpri
;
1578 unsigned int apic_ldr
;
1579 unsigned int apic_dfr
;
1580 unsigned int apic_spiv
;
1581 unsigned int apic_lvtt
;
1582 unsigned int apic_lvtpc
;
1583 unsigned int apic_lvt0
;
1584 unsigned int apic_lvt1
;
1585 unsigned int apic_lvterr
;
1586 unsigned int apic_tmict
;
1587 unsigned int apic_tdcr
;
1588 unsigned int apic_thmr
;
1591 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1593 unsigned long flags
;
1596 if (!apic_pm_state
.active
)
1599 maxlvt
= lapic_get_maxlvt();
1601 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1602 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1603 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1604 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1605 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1606 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1608 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1609 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1610 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1611 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1612 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1613 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1614 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1616 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1619 local_irq_save(flags
);
1620 disable_local_APIC();
1621 local_irq_restore(flags
);
1625 static int lapic_resume(struct sys_device
*dev
)
1628 unsigned long flags
;
1631 if (!apic_pm_state
.active
)
1634 maxlvt
= lapic_get_maxlvt();
1636 local_irq_save(flags
);
1638 #ifdef CONFIG_X86_64
1644 * Make sure the APICBASE points to the right address
1646 * FIXME! This will be wrong if we ever support suspend on
1647 * SMP! We'll need to do this as part of the CPU restore!
1649 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1650 l
&= ~MSR_IA32_APICBASE_BASE
;
1651 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1652 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1654 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1655 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1656 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1657 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1658 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1659 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1660 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1661 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1662 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1664 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1667 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1668 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1669 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1670 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1671 apic_write(APIC_ESR
, 0);
1672 apic_read(APIC_ESR
);
1673 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1674 apic_write(APIC_ESR
, 0);
1675 apic_read(APIC_ESR
);
1677 local_irq_restore(flags
);
1683 * This device has no shutdown method - fully functioning local APICs
1684 * are needed on every CPU up until machine_halt/restart/poweroff.
1687 static struct sysdev_class lapic_sysclass
= {
1689 .resume
= lapic_resume
,
1690 .suspend
= lapic_suspend
,
1693 static struct sys_device device_lapic
= {
1695 .cls
= &lapic_sysclass
,
1698 static void __devinit
apic_pm_activate(void)
1700 apic_pm_state
.active
= 1;
1703 static int __init
init_lapic_sysfs(void)
1709 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1711 error
= sysdev_class_register(&lapic_sysclass
);
1713 error
= sysdev_register(&device_lapic
);
1716 device_initcall(init_lapic_sysfs
);
1718 #else /* CONFIG_PM */
1720 static void apic_pm_activate(void) { }
1722 #endif /* CONFIG_PM */
1725 * APIC command line parameters
1727 static int __init
parse_lapic(char *arg
)
1729 force_enable_local_apic
= 1;
1732 early_param("lapic", parse_lapic
);
1734 static int __init
parse_nolapic(char *arg
)
1737 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1740 early_param("nolapic", parse_nolapic
);
1742 static int __init
parse_disable_apic_timer(char *arg
)
1744 disable_apic_timer
= 1;
1747 early_param("noapictimer", parse_disable_apic_timer
);
1749 static int __init
parse_nolapic_timer(char *arg
)
1751 disable_apic_timer
= 1;
1754 early_param("nolapic_timer", parse_nolapic_timer
);
1756 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1758 local_apic_timer_c2_ok
= 1;
1761 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1763 static int __init
apic_set_verbosity(char *arg
)
1768 if (strcmp(arg
, "debug") == 0)
1769 apic_verbosity
= APIC_DEBUG
;
1770 else if (strcmp(arg
, "verbose") == 0)
1771 apic_verbosity
= APIC_VERBOSE
;
1775 early_param("apic", apic_set_verbosity
);
1777 static int __init
lapic_insert_resource(void)
1782 /* Put local APIC into the resource map. */
1783 lapic_resource
.start
= apic_phys
;
1784 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1785 insert_resource(&iomem_resource
, &lapic_resource
);
1791 * need call insert after e820_reserve_resources()
1792 * that is using request_resource
1794 late_initcall(lapic_insert_resource
);