include/asm-x86/ipi.h

   1 #ifndef __ASM_IPI_H
   2 #define __ASM_IPI_H
   3
   4 /*
   5  * Copyright 2004 James Cleverdon, IBM.
   6  * Subject to the GNU Public License, v.2
   7  *
   8  * Generic APIC InterProcessor Interrupt code.
   9  *
  10  * Moved to include file by James Cleverdon from
  11  * arch/x86-64/kernel/smp.c
  12  *
  13  * Copyrights from kernel/smp.c:
  14  *
  15  * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
  16  * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
  17  * (c) 2002,2003 Andi Kleen, SuSE Labs.
  18  * Subject to the GNU Public License, v.2
  19  */
  20
  21 #include <asm/hw_irq.h>
  22 #include <asm/apic.h>
  23
  24 /*
  25  * the following functions deal with sending IPIs between CPUs.
  26  *
  27  * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
  28  */
  29
  30 static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector,
  31                                          unsigned int dest)
  32 {
  33         unsigned int icr = shortcut | dest;
  34
  35         switch (vector) {
  36         default:
  37                 icr |= APIC_DM_FIXED | vector;
  38                 break;
  39         case NMI_VECTOR:
  40                 icr |= APIC_DM_NMI;
  41                 break;
  42         }
  43         return icr;
  44 }
  45
  46 static inline int __prepare_ICR2(unsigned int mask)
  47 {
  48         return SET_APIC_DEST_FIELD(mask);
  49 }
  50
  51 static inline void __send_IPI_shortcut(unsigned int shortcut, int vector,
  52                                        unsigned int dest)
  53 {
  54         /*
  55          * Subtle. In the case of the 'never do double writes' workaround
  56          * we have to lock out interrupts to be safe.  As we don't care
  57          * of the value read we use an atomic rmw access to avoid costly
  58          * cli/sti.  Otherwise we use an even cheaper single atomic write
  59          * to the APIC.
  60          */
  61         unsigned int cfg;
  62
  63         /*
  64          * Wait for idle.
  65          */
  66         apic_wait_icr_idle();
  67
  68         /*
  69          * No need to touch the target chip field
  70          */
  71         cfg = __prepare_ICR(shortcut, vector, dest);
  72
  73         /*
  74          * Send the IPI. The write to APIC_ICR fires this off.
  75          */
  76         apic_write(APIC_ICR, cfg);
  77 }
  78
  79 /*
  80  * This is used to send an IPI with no shorthand notation (the destination is
  81  * specified in bits 56 to 63 of the ICR).
  82  */
  83 static inline void __send_IPI_dest_field(unsigned int mask, int vector,
  84                                          unsigned int dest)
  85 {
  86         unsigned long cfg;
  87
  88         /*
  89          * Wait for idle.
  90          */
  91         if (unlikely(vector == NMI_VECTOR))
  92                 safe_apic_wait_icr_idle();
  93         else
  94                 apic_wait_icr_idle();
  95
  96         /*
  97          * prepare target chip field
  98          */
  99         cfg = __prepare_ICR2(mask);
 100         apic_write(APIC_ICR2, cfg);
 101
 102         /*
 103          * program the ICR
 104          */
 105         cfg = __prepare_ICR(0, vector, dest);
 106
 107         /*
 108          * Send the IPI. The write to APIC_ICR fires this off.
 109          */
 110         apic_write(APIC_ICR, cfg);
 111 }
 112
 113 static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
 114 {
 115         unsigned long flags;
 116         unsigned long query_cpu;
 117
 118         /*
 119          * Hack. The clustered APIC addressing mode doesn't allow us to send
 120          * to an arbitrary mask, so I do a unicast to each CPU instead.
 121          * - mbligh
 122          */
 123         local_irq_save(flags);
 124         for_each_cpu_mask(query_cpu, mask) {
 125                 __send_IPI_dest_field(per_cpu(x86_cpu_to_apicid, query_cpu),
 126                                       vector, APIC_DEST_PHYSICAL);
 127         }
 128         local_irq_restore(flags);
 129 }
 130
 131 #endif /* __ASM_IPI_H */