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intel-gtt: move chipset flush to the gtt driver struct
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mfd / max8925-core.c
blob04028a9ee082735278557b606840619ade7e29a9
1 /*
2 * Base driver for Maxim MAX8925
3 *
4 * Copyright (C) 2009-2010 Marvell International Ltd.
5 * Haojian Zhuang <haojian.zhuang@marvell.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/i2c.h>
15 #include <linux/irq.h>
16 #include <linux/interrupt.h>
17 #include <linux/platform_device.h>
18 #include <linux/mfd/core.h>
19 #include <linux/mfd/max8925.h>
20
21 static struct resource backlight_resources[] = {
22 {
23 .name = "max8925-backlight",
24 .start = MAX8925_WLED_MODE_CNTL,
25 .end = MAX8925_WLED_CNTL,
26 .flags = IORESOURCE_IO,
27 },
28 };
29
30 static struct mfd_cell backlight_devs[] = {
31 {
32 .name = "max8925-backlight",
33 .num_resources = 1,
34 .resources = &backlight_resources[0],
35 .id = -1,
36 },
37 };
38
39 static struct resource touch_resources[] = {
40 {
41 .name = "max8925-tsc",
42 .start = MAX8925_TSC_IRQ,
43 .end = MAX8925_ADC_RES_END,
44 .flags = IORESOURCE_IO,
45 },
46 };
47
48 static struct mfd_cell touch_devs[] = {
49 {
50 .name = "max8925-touch",
51 .num_resources = 1,
52 .resources = &touch_resources[0],
53 .id = -1,
54 },
55 };
56
57 static struct resource power_supply_resources[] = {
58 {
59 .name = "max8925-power",
60 .start = MAX8925_CHG_IRQ1,
61 .end = MAX8925_CHG_IRQ1_MASK,
62 .flags = IORESOURCE_IO,
63 },
64 };
65
66 static struct mfd_cell power_devs[] = {
67 {
68 .name = "max8925-power",
69 .num_resources = 1,
70 .resources = &power_supply_resources[0],
71 .id = -1,
72 },
73 };
74
75 static struct resource rtc_resources[] = {
76 {
77 .name = "max8925-rtc",
78 .start = MAX8925_RTC_IRQ,
79 .end = MAX8925_RTC_IRQ_MASK,
80 .flags = IORESOURCE_IO,
81 },
82 };
83
84 static struct mfd_cell rtc_devs[] = {
85 {
86 .name = "max8925-rtc",
87 .num_resources = 1,
88 .resources = &rtc_resources[0],
89 .id = -1,
90 },
91 };
92
93 static struct resource onkey_resources[] = {
94 {
95 .name = "max8925-onkey",
96 .start = MAX8925_IRQ_GPM_SW_3SEC,
97 .end = MAX8925_IRQ_GPM_SW_3SEC,
98 .flags = IORESOURCE_IRQ,
99 },
100 };
101
102 static struct mfd_cell onkey_devs[] = {
103 {
104 .name = "max8925-onkey",
105 .num_resources = 1,
106 .resources = &onkey_resources[0],
107 .id = -1,
108 },
109 };
110
111 #define MAX8925_REG_RESOURCE(_start, _end) \
112 { \
113 .start = MAX8925_##_start, \
114 .end = MAX8925_##_end, \
115 .flags = IORESOURCE_IO, \
116 }
117
118 static struct resource regulator_resources[] = {
119 MAX8925_REG_RESOURCE(SDCTL1, SDCTL1),
120 MAX8925_REG_RESOURCE(SDCTL2, SDCTL2),
121 MAX8925_REG_RESOURCE(SDCTL3, SDCTL3),
122 MAX8925_REG_RESOURCE(LDOCTL1, LDOCTL1),
123 MAX8925_REG_RESOURCE(LDOCTL2, LDOCTL2),
124 MAX8925_REG_RESOURCE(LDOCTL3, LDOCTL3),
125 MAX8925_REG_RESOURCE(LDOCTL4, LDOCTL4),
126 MAX8925_REG_RESOURCE(LDOCTL5, LDOCTL5),
127 MAX8925_REG_RESOURCE(LDOCTL6, LDOCTL6),
128 MAX8925_REG_RESOURCE(LDOCTL7, LDOCTL7),
129 MAX8925_REG_RESOURCE(LDOCTL8, LDOCTL8),
130 MAX8925_REG_RESOURCE(LDOCTL9, LDOCTL9),
131 MAX8925_REG_RESOURCE(LDOCTL10, LDOCTL10),
132 MAX8925_REG_RESOURCE(LDOCTL11, LDOCTL11),
133 MAX8925_REG_RESOURCE(LDOCTL12, LDOCTL12),
134 MAX8925_REG_RESOURCE(LDOCTL13, LDOCTL13),
135 MAX8925_REG_RESOURCE(LDOCTL14, LDOCTL14),
136 MAX8925_REG_RESOURCE(LDOCTL15, LDOCTL15),
137 MAX8925_REG_RESOURCE(LDOCTL16, LDOCTL16),
138 MAX8925_REG_RESOURCE(LDOCTL17, LDOCTL17),
139 MAX8925_REG_RESOURCE(LDOCTL18, LDOCTL18),
140 MAX8925_REG_RESOURCE(LDOCTL19, LDOCTL19),
141 MAX8925_REG_RESOURCE(LDOCTL20, LDOCTL20),
142 };
143
144 #define MAX8925_REG_DEVS(_id) \
145 { \
146 .name = "max8925-regulator", \
147 .num_resources = 1, \
148 .resources = &regulator_resources[MAX8925_ID_##_id], \
149 .id = MAX8925_ID_##_id, \
150 }
151
152 static struct mfd_cell regulator_devs[] = {
153 MAX8925_REG_DEVS(SD1),
154 MAX8925_REG_DEVS(SD2),
155 MAX8925_REG_DEVS(SD3),
156 MAX8925_REG_DEVS(LDO1),
157 MAX8925_REG_DEVS(LDO2),
158 MAX8925_REG_DEVS(LDO3),
159 MAX8925_REG_DEVS(LDO4),
160 MAX8925_REG_DEVS(LDO5),
161 MAX8925_REG_DEVS(LDO6),
162 MAX8925_REG_DEVS(LDO7),
163 MAX8925_REG_DEVS(LDO8),
164 MAX8925_REG_DEVS(LDO9),
165 MAX8925_REG_DEVS(LDO10),
166 MAX8925_REG_DEVS(LDO11),
167 MAX8925_REG_DEVS(LDO12),
168 MAX8925_REG_DEVS(LDO13),
169 MAX8925_REG_DEVS(LDO14),
170 MAX8925_REG_DEVS(LDO15),
171 MAX8925_REG_DEVS(LDO16),
172 MAX8925_REG_DEVS(LDO17),
173 MAX8925_REG_DEVS(LDO18),
174 MAX8925_REG_DEVS(LDO19),
175 MAX8925_REG_DEVS(LDO20),
176 };
177
178 enum {
179 FLAGS_ADC = 1, /* register in ADC component */
180 FLAGS_RTC, /* register in RTC component */
181 };
182
183 struct max8925_irq_data {
184 int reg;
185 int mask_reg;
186 int enable; /* enable or not */
187 int offs; /* bit offset in mask register */
188 int flags;
189 int tsc_irq;
190 };
191
192 static struct max8925_irq_data max8925_irqs[] = {
193 [MAX8925_IRQ_VCHG_DC_OVP] = {
194 .reg = MAX8925_CHG_IRQ1,
195 .mask_reg = MAX8925_CHG_IRQ1_MASK,
196 .offs = 1 << 0,
197 },
198 [MAX8925_IRQ_VCHG_DC_F] = {
199 .reg = MAX8925_CHG_IRQ1,
200 .mask_reg = MAX8925_CHG_IRQ1_MASK,
201 .offs = 1 << 1,
202 },
203 [MAX8925_IRQ_VCHG_DC_R] = {
204 .reg = MAX8925_CHG_IRQ1,
205 .mask_reg = MAX8925_CHG_IRQ1_MASK,
206 .offs = 1 << 2,
207 },
208 [MAX8925_IRQ_VCHG_USB_OVP] = {
209 .reg = MAX8925_CHG_IRQ1,
210 .mask_reg = MAX8925_CHG_IRQ1_MASK,
211 .offs = 1 << 3,
212 },
213 [MAX8925_IRQ_VCHG_USB_F] = {
214 .reg = MAX8925_CHG_IRQ1,
215 .mask_reg = MAX8925_CHG_IRQ1_MASK,
216 .offs = 1 << 4,
217 },
218 [MAX8925_IRQ_VCHG_USB_R] = {
219 .reg = MAX8925_CHG_IRQ1,
220 .mask_reg = MAX8925_CHG_IRQ1_MASK,
221 .offs = 1 << 5,
222 },
223 [MAX8925_IRQ_VCHG_THM_OK_R] = {
224 .reg = MAX8925_CHG_IRQ2,
225 .mask_reg = MAX8925_CHG_IRQ2_MASK,
226 .offs = 1 << 0,
227 },
228 [MAX8925_IRQ_VCHG_THM_OK_F] = {
229 .reg = MAX8925_CHG_IRQ2,
230 .mask_reg = MAX8925_CHG_IRQ2_MASK,
231 .offs = 1 << 1,
232 },
233 [MAX8925_IRQ_VCHG_SYSLOW_F] = {
234 .reg = MAX8925_CHG_IRQ2,
235 .mask_reg = MAX8925_CHG_IRQ2_MASK,
236 .offs = 1 << 2,
237 },
238 [MAX8925_IRQ_VCHG_SYSLOW_R] = {
239 .reg = MAX8925_CHG_IRQ2,
240 .mask_reg = MAX8925_CHG_IRQ2_MASK,
241 .offs = 1 << 3,
242 },
243 [MAX8925_IRQ_VCHG_RST] = {
244 .reg = MAX8925_CHG_IRQ2,
245 .mask_reg = MAX8925_CHG_IRQ2_MASK,
246 .offs = 1 << 4,
247 },
248 [MAX8925_IRQ_VCHG_DONE] = {
249 .reg = MAX8925_CHG_IRQ2,
250 .mask_reg = MAX8925_CHG_IRQ2_MASK,
251 .offs = 1 << 5,
252 },
253 [MAX8925_IRQ_VCHG_TOPOFF] = {
254 .reg = MAX8925_CHG_IRQ2,
255 .mask_reg = MAX8925_CHG_IRQ2_MASK,
256 .offs = 1 << 6,
257 },
258 [MAX8925_IRQ_VCHG_TMR_FAULT] = {
259 .reg = MAX8925_CHG_IRQ2,
260 .mask_reg = MAX8925_CHG_IRQ2_MASK,
261 .offs = 1 << 7,
262 },
263 [MAX8925_IRQ_GPM_RSTIN] = {
264 .reg = MAX8925_ON_OFF_IRQ1,
265 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
266 .offs = 1 << 0,
267 },
268 [MAX8925_IRQ_GPM_MPL] = {
269 .reg = MAX8925_ON_OFF_IRQ1,
270 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
271 .offs = 1 << 1,
272 },
273 [MAX8925_IRQ_GPM_SW_3SEC] = {
274 .reg = MAX8925_ON_OFF_IRQ1,
275 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
276 .offs = 1 << 2,
277 },
278 [MAX8925_IRQ_GPM_EXTON_F] = {
279 .reg = MAX8925_ON_OFF_IRQ1,
280 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
281 .offs = 1 << 3,
282 },
283 [MAX8925_IRQ_GPM_EXTON_R] = {
284 .reg = MAX8925_ON_OFF_IRQ1,
285 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
286 .offs = 1 << 4,
287 },
288 [MAX8925_IRQ_GPM_SW_1SEC] = {
289 .reg = MAX8925_ON_OFF_IRQ1,
290 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
291 .offs = 1 << 5,
292 },
293 [MAX8925_IRQ_GPM_SW_F] = {
294 .reg = MAX8925_ON_OFF_IRQ1,
295 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
296 .offs = 1 << 6,
297 },
298 [MAX8925_IRQ_GPM_SW_R] = {
299 .reg = MAX8925_ON_OFF_IRQ1,
300 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
301 .offs = 1 << 7,
302 },
303 [MAX8925_IRQ_GPM_SYSCKEN_F] = {
304 .reg = MAX8925_ON_OFF_IRQ2,
305 .mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
306 .offs = 1 << 0,
307 },
308 [MAX8925_IRQ_GPM_SYSCKEN_R] = {
309 .reg = MAX8925_ON_OFF_IRQ2,
310 .mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
311 .offs = 1 << 1,
312 },
313 [MAX8925_IRQ_RTC_ALARM1] = {
314 .reg = MAX8925_RTC_IRQ,
315 .mask_reg = MAX8925_RTC_IRQ_MASK,
316 .offs = 1 << 2,
317 .flags = FLAGS_RTC,
318 },
319 [MAX8925_IRQ_RTC_ALARM0] = {
320 .reg = MAX8925_RTC_IRQ,
321 .mask_reg = MAX8925_RTC_IRQ_MASK,
322 .offs = 1 << 3,
323 .flags = FLAGS_RTC,
324 },
325 [MAX8925_IRQ_TSC_STICK] = {
326 .reg = MAX8925_TSC_IRQ,
327 .mask_reg = MAX8925_TSC_IRQ_MASK,
328 .offs = 1 << 0,
329 .flags = FLAGS_ADC,
330 .tsc_irq = 1,
331 },
332 [MAX8925_IRQ_TSC_NSTICK] = {
333 .reg = MAX8925_TSC_IRQ,
334 .mask_reg = MAX8925_TSC_IRQ_MASK,
335 .offs = 1 << 1,
336 .flags = FLAGS_ADC,
337 .tsc_irq = 1,
338 },
339 };
340
341 static inline struct max8925_irq_data *irq_to_max8925(struct max8925_chip *chip,
342 int irq)
343 {
344 return &max8925_irqs[irq - chip->irq_base];
345 }
346
347 static irqreturn_t max8925_irq(int irq, void *data)
348 {
349 struct max8925_chip *chip = data;
350 struct max8925_irq_data *irq_data;
351 struct i2c_client *i2c;
352 int read_reg = -1, value = 0;
353 int i;
354
355 for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
356 irq_data = &max8925_irqs[i];
357 /* TSC IRQ should be serviced in max8925_tsc_irq() */
358 if (irq_data->tsc_irq)
359 continue;
360 if (irq_data->flags == FLAGS_RTC)
361 i2c = chip->rtc;
362 else if (irq_data->flags == FLAGS_ADC)
363 i2c = chip->adc;
364 else
365 i2c = chip->i2c;
366 if (read_reg != irq_data->reg) {
367 read_reg = irq_data->reg;
368 value = max8925_reg_read(i2c, irq_data->reg);
369 }
370 if (value & irq_data->enable)
371 handle_nested_irq(chip->irq_base + i);
372 }
373 return IRQ_HANDLED;
374 }
375
376 static irqreturn_t max8925_tsc_irq(int irq, void *data)
377 {
378 struct max8925_chip *chip = data;
379 struct max8925_irq_data *irq_data;
380 struct i2c_client *i2c;
381 int read_reg = -1, value = 0;
382 int i;
383
384 for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
385 irq_data = &max8925_irqs[i];
386 /* non TSC IRQ should be serviced in max8925_irq() */
387 if (!irq_data->tsc_irq)
388 continue;
389 if (irq_data->flags == FLAGS_RTC)
390 i2c = chip->rtc;
391 else if (irq_data->flags == FLAGS_ADC)
392 i2c = chip->adc;
393 else
394 i2c = chip->i2c;
395 if (read_reg != irq_data->reg) {
396 read_reg = irq_data->reg;
397 value = max8925_reg_read(i2c, irq_data->reg);
398 }
399 if (value & irq_data->enable)
400 handle_nested_irq(chip->irq_base + i);
401 }
402 return IRQ_HANDLED;
403 }
404
405 static void max8925_irq_lock(unsigned int irq)
406 {
407 struct max8925_chip *chip = get_irq_chip_data(irq);
408
409 mutex_lock(&chip->irq_lock);
410 }
411
412 static void max8925_irq_sync_unlock(unsigned int irq)
413 {
414 struct max8925_chip *chip = get_irq_chip_data(irq);
415 struct max8925_irq_data *irq_data;
416 static unsigned char cache_chg[2] = {0xff, 0xff};
417 static unsigned char cache_on[2] = {0xff, 0xff};
418 static unsigned char cache_rtc = 0xff, cache_tsc = 0xff;
419 unsigned char irq_chg[2], irq_on[2];
420 unsigned char irq_rtc, irq_tsc;
421 int i;
422
423 /* Load cached value. In initial, all IRQs are masked */
424 irq_chg[0] = cache_chg[0];
425 irq_chg[1] = cache_chg[1];
426 irq_on[0] = cache_on[0];
427 irq_on[1] = cache_on[1];
428 irq_rtc = cache_rtc;
429 irq_tsc = cache_tsc;
430 for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
431 irq_data = &max8925_irqs[i];
432 switch (irq_data->mask_reg) {
433 case MAX8925_CHG_IRQ1_MASK:
434 irq_chg[0] &= irq_data->enable;
435 break;
436 case MAX8925_CHG_IRQ2_MASK:
437 irq_chg[1] &= irq_data->enable;
438 break;
439 case MAX8925_ON_OFF_IRQ1_MASK:
440 irq_on[0] &= irq_data->enable;
441 break;
442 case MAX8925_ON_OFF_IRQ2_MASK:
443 irq_on[1] &= irq_data->enable;
444 break;
445 case MAX8925_RTC_IRQ_MASK:
446 irq_rtc &= irq_data->enable;
447 break;
448 case MAX8925_TSC_IRQ_MASK:
449 irq_tsc &= irq_data->enable;
450 break;
451 default:
452 dev_err(chip->dev, "wrong IRQ\n");
453 break;
454 }
455 }
456 /* update mask into registers */
457 if (cache_chg[0] != irq_chg[0]) {
458 cache_chg[0] = irq_chg[0];
459 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK,
460 irq_chg[0]);
461 }
462 if (cache_chg[1] != irq_chg[1]) {
463 cache_chg[1] = irq_chg[1];
464 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK,
465 irq_chg[1]);
466 }
467 if (cache_on[0] != irq_on[0]) {
468 cache_on[0] = irq_on[0];
469 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK,
470 irq_on[0]);
471 }
472 if (cache_on[1] != irq_on[1]) {
473 cache_on[1] = irq_on[1];
474 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK,
475 irq_on[1]);
476 }
477 if (cache_rtc != irq_rtc) {
478 cache_rtc = irq_rtc;
479 max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, irq_rtc);
480 }
481 if (cache_tsc != irq_tsc) {
482 cache_tsc = irq_tsc;
483 max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, irq_tsc);
484 }
485
486 mutex_unlock(&chip->irq_lock);
487 }
488
489 static void max8925_irq_enable(unsigned int irq)
490 {
491 struct max8925_chip *chip = get_irq_chip_data(irq);
492 max8925_irqs[irq - chip->irq_base].enable
493 = max8925_irqs[irq - chip->irq_base].offs;
494 }
495
496 static void max8925_irq_disable(unsigned int irq)
497 {
498 struct max8925_chip *chip = get_irq_chip_data(irq);
499 max8925_irqs[irq - chip->irq_base].enable = 0;
500 }
501
502 static struct irq_chip max8925_irq_chip = {
503 .name = "max8925",
504 .bus_lock = max8925_irq_lock,
505 .bus_sync_unlock = max8925_irq_sync_unlock,
506 .enable = max8925_irq_enable,
507 .disable = max8925_irq_disable,
508 };
509
510 static int max8925_irq_init(struct max8925_chip *chip, int irq,
511 struct max8925_platform_data *pdata)
512 {
513 unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
514 struct irq_desc *desc;
515 int i, ret;
516 int __irq;
517
518 if (!pdata || !pdata->irq_base) {
519 dev_warn(chip->dev, "No interrupt support on IRQ base\n");
520 return -EINVAL;
521 }
522 /* clear all interrupts */
523 max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ1);
524 max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ2);
525 max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ1);
526 max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2);
527 max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ);
528 max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
529 /* mask all interrupts except for TSC */
530 max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0);
531 max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0);
532 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff);
533 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, 0xff);
534 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff);
535 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff);
536 max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff);
537
538 mutex_init(&chip->irq_lock);
539 chip->core_irq = irq;
540 chip->irq_base = pdata->irq_base;
541 desc = irq_to_desc(chip->core_irq);
542
543 /* register with genirq */
544 for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
545 __irq = i + chip->irq_base;
546 set_irq_chip_data(__irq, chip);
547 set_irq_chip_and_handler(__irq, &max8925_irq_chip,
548 handle_edge_irq);
549 set_irq_nested_thread(__irq, 1);
550 #ifdef CONFIG_ARM
551 set_irq_flags(__irq, IRQF_VALID);
552 #else
553 set_irq_noprobe(__irq);
554 #endif
555 }
556 if (!irq) {
557 dev_warn(chip->dev, "No interrupt support on core IRQ\n");
558 goto tsc_irq;
559 }
560
561 ret = request_threaded_irq(irq, NULL, max8925_irq, flags,
562 "max8925", chip);
563 if (ret) {
564 dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret);
565 chip->core_irq = 0;
566 }
567
568 tsc_irq:
569 /* mask TSC interrupt */
570 max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0x0f);
571
572 if (!pdata->tsc_irq) {
573 dev_warn(chip->dev, "No interrupt support on TSC IRQ\n");
574 return 0;
575 }
576 chip->tsc_irq = pdata->tsc_irq;
577
578 ret = request_threaded_irq(chip->tsc_irq, NULL, max8925_tsc_irq,
579 flags, "max8925-tsc", chip);
580 if (ret) {
581 dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret);
582 chip->tsc_irq = 0;
583 }
584 return 0;
585 }
586
587 int __devinit max8925_device_init(struct max8925_chip *chip,
588 struct max8925_platform_data *pdata)
589 {
590 int ret;
591
592 max8925_irq_init(chip, chip->i2c->irq, pdata);
593
594 if (pdata && (pdata->power || pdata->touch)) {
595 /* enable ADC to control internal reference */
596 max8925_set_bits(chip->i2c, MAX8925_RESET_CNFG, 1, 1);
597 /* enable internal reference for ADC */
598 max8925_set_bits(chip->adc, MAX8925_TSC_CNFG1, 3, 2);
599 /* check for internal reference IRQ */
600 do {
601 ret = max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
602 } while (ret & MAX8925_NREF_OK);
603 /* enaable ADC scheduler, interval is 1 second */
604 max8925_set_bits(chip->adc, MAX8925_ADC_SCHED, 3, 2);
605 }
606
607 /* enable Momentary Power Loss */
608 max8925_set_bits(chip->rtc, MAX8925_MPL_CNTL, 1 << 4, 1 << 4);
609
610 ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
611 ARRAY_SIZE(rtc_devs),
612 &rtc_resources[0], 0);
613 if (ret < 0) {
614 dev_err(chip->dev, "Failed to add rtc subdev\n");
615 goto out;
616 }
617
618 ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
619 ARRAY_SIZE(onkey_devs),
620 &onkey_resources[0], 0);
621 if (ret < 0) {
622 dev_err(chip->dev, "Failed to add onkey subdev\n");
623 goto out_dev;
624 }
625
626 if (pdata && pdata->regulator[0]) {
627 ret = mfd_add_devices(chip->dev, 0, &regulator_devs[0],
628 ARRAY_SIZE(regulator_devs),
629 &regulator_resources[0], 0);
630 if (ret < 0) {
631 dev_err(chip->dev, "Failed to add regulator subdev\n");
632 goto out_dev;
633 }
634 }
635
636 if (pdata && pdata->backlight) {
637 ret = mfd_add_devices(chip->dev, 0, &backlight_devs[0],
638 ARRAY_SIZE(backlight_devs),
639 &backlight_resources[0], 0);
640 if (ret < 0) {
641 dev_err(chip->dev, "Failed to add backlight subdev\n");
642 goto out_dev;
643 }
644 }
645
646 if (pdata && pdata->power) {
647 ret = mfd_add_devices(chip->dev, 0, &power_devs[0],
648 ARRAY_SIZE(power_devs),
649 &power_supply_resources[0], 0);
650 if (ret < 0) {
651 dev_err(chip->dev, "Failed to add power supply "
652 "subdev\n");
653 goto out_dev;
654 }
655 }
656
657 if (pdata && pdata->touch) {
658 ret = mfd_add_devices(chip->dev, 0, &touch_devs[0],
659 ARRAY_SIZE(touch_devs),
660 &touch_resources[0], 0);
661 if (ret < 0) {
662 dev_err(chip->dev, "Failed to add touch subdev\n");
663 goto out_dev;
664 }
665 }
666
667 return 0;
668 out_dev:
669 mfd_remove_devices(chip->dev);
670 out:
671 return ret;
672 }
673
674 void __devexit max8925_device_exit(struct max8925_chip *chip)
675 {
676 if (chip->core_irq)
677 free_irq(chip->core_irq, chip);
678 if (chip->tsc_irq)
679 free_irq(chip->tsc_irq, chip);
680 mfd_remove_devices(chip->dev);
681 }
682
683
684 MODULE_DESCRIPTION("PMIC Driver for Maxim MAX8925");
685 MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com");
686 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree