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ALSA: hda - Fix beep frequency on IDT 92HD73xx and 92HD71Bxx codecs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / 8139too.c
blob4ba72933f0da57b72f069e4d95a29fc1ad8da1f1
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
93
94 #define DRV_NAME "8139too"
95 #define DRV_VERSION "0.9.28"
96
97
98 #include <linux/module.h>
99 #include <linux/kernel.h>
100 #include <linux/compiler.h>
101 #include <linux/pci.h>
102 #include <linux/init.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/rtnetlink.h>
106 #include <linux/delay.h>
107 #include <linux/ethtool.h>
108 #include <linux/mii.h>
109 #include <linux/completion.h>
110 #include <linux/crc32.h>
111 #include <linux/io.h>
112 #include <linux/uaccess.h>
113 #include <linux/gfp.h>
114 #include <asm/irq.h>
115
116 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
117
118 /* Default Message level */
119 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
120 NETIF_MSG_PROBE | \
121 NETIF_MSG_LINK)
122
123
124 /* define to 1, 2 or 3 to enable copious debugging info */
125 #define RTL8139_DEBUG 0
126
127 /* define to 1 to disable lightweight runtime debugging checks */
128 #undef RTL8139_NDEBUG
129
130
131 #ifdef RTL8139_NDEBUG
132 # define assert(expr) do {} while (0)
133 #else
134 # define assert(expr) \
135 if (unlikely(!(expr))) { \
136 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
137 #expr, __FILE__, __func__, __LINE__); \
138 }
139 #endif
140
141
142 /* A few user-configurable values. */
143 /* media options */
144 #define MAX_UNITS 8
145 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
146 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
147
148 /* Whether to use MMIO or PIO. Default to MMIO. */
149 #ifdef CONFIG_8139TOO_PIO
150 static int use_io = 1;
151 #else
152 static int use_io = 0;
153 #endif
154
155 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
156 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
157 static int multicast_filter_limit = 32;
158
159 /* bitmapped message enable number */
160 static int debug = -1;
161
162 /*
163 * Receive ring size
164 * Warning: 64K ring has hardware issues and may lock up.
165 */
166 #if defined(CONFIG_SH_DREAMCAST)
167 #define RX_BUF_IDX 0 /* 8K ring */
168 #else
169 #define RX_BUF_IDX 2 /* 32K ring */
170 #endif
171 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
172 #define RX_BUF_PAD 16
173 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
174
175 #if RX_BUF_LEN == 65536
176 #define RX_BUF_TOT_LEN RX_BUF_LEN
177 #else
178 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
179 #endif
180
181 /* Number of Tx descriptor registers. */
182 #define NUM_TX_DESC 4
183
184 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
185 #define MAX_ETH_FRAME_SIZE 1536
186
187 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
188 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
189 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
190
191 /* PCI Tuning Parameters
192 Threshold is bytes transferred to chip before transmission starts. */
193 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
194
195 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
196 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
197 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
198 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
199 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
200
201 /* Operational parameters that usually are not changed. */
202 /* Time in jiffies before concluding the transmitter is hung. */
203 #define TX_TIMEOUT (6*HZ)
204
205
206 enum {
207 HAS_MII_XCVR = 0x010000,
208 HAS_CHIP_XCVR = 0x020000,
209 HAS_LNK_CHNG = 0x040000,
210 };
211
212 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
213 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
214 #define RTL_MIN_IO_SIZE 0x80
215 #define RTL8139B_IO_SIZE 256
216
217 #define RTL8129_CAPS HAS_MII_XCVR
218 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
219
220 typedef enum {
221 RTL8139 = 0,
222 RTL8129,
223 } board_t;
224
225
226 /* indexed by board_t, above */
227 static const struct {
228 const char *name;
229 u32 hw_flags;
230 } board_info[] __devinitdata = {
231 { "RealTek RTL8139", RTL8139_CAPS },
232 { "RealTek RTL8129", RTL8129_CAPS },
233 };
234
235
236 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {
237 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
238 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
239 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
240 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
241 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256
257 #ifdef CONFIG_SH_SECUREEDGE5410
258 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
259 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 #endif
261 #ifdef CONFIG_8139TOO_8129
262 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
263 #endif
264
265 /* some crazy cards report invalid vendor ids like
266 * 0x0001 here. The other ids are valid and constant,
267 * so we simply don't match on the main vendor id.
268 */
269 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
270 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
271 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
272
273 {0,}
274 };
275 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
276
277 static struct {
278 const char str[ETH_GSTRING_LEN];
279 } ethtool_stats_keys[] = {
280 { "early_rx" },
281 { "tx_buf_mapped" },
282 { "tx_timeouts" },
283 { "rx_lost_in_ring" },
284 };
285
286 /* The rest of these values should never change. */
287
288 /* Symbolic offsets to registers. */
289 enum RTL8139_registers {
290 MAC0 = 0, /* Ethernet hardware address. */
291 MAR0 = 8, /* Multicast filter. */
292 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
293 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
294 RxBuf = 0x30,
295 ChipCmd = 0x37,
296 RxBufPtr = 0x38,
297 RxBufAddr = 0x3A,
298 IntrMask = 0x3C,
299 IntrStatus = 0x3E,
300 TxConfig = 0x40,
301 RxConfig = 0x44,
302 Timer = 0x48, /* A general-purpose counter. */
303 RxMissed = 0x4C, /* 24 bits valid, write clears. */
304 Cfg9346 = 0x50,
305 Config0 = 0x51,
306 Config1 = 0x52,
307 TimerInt = 0x54,
308 MediaStatus = 0x58,
309 Config3 = 0x59,
310 Config4 = 0x5A, /* absent on RTL-8139A */
311 HltClk = 0x5B,
312 MultiIntr = 0x5C,
313 TxSummary = 0x60,
314 BasicModeCtrl = 0x62,
315 BasicModeStatus = 0x64,
316 NWayAdvert = 0x66,
317 NWayLPAR = 0x68,
318 NWayExpansion = 0x6A,
319 /* Undocumented registers, but required for proper operation. */
320 FIFOTMS = 0x70, /* FIFO Control and test. */
321 CSCR = 0x74, /* Chip Status and Configuration Register. */
322 PARA78 = 0x78,
323 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
324 PARA7c = 0x7c, /* Magic transceiver parameter register. */
325 Config5 = 0xD8, /* absent on RTL-8139A */
326 };
327
328 enum ClearBitMasks {
329 MultiIntrClear = 0xF000,
330 ChipCmdClear = 0xE2,
331 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
332 };
333
334 enum ChipCmdBits {
335 CmdReset = 0x10,
336 CmdRxEnb = 0x08,
337 CmdTxEnb = 0x04,
338 RxBufEmpty = 0x01,
339 };
340
341 /* Interrupt register bits, using my own meaningful names. */
342 enum IntrStatusBits {
343 PCIErr = 0x8000,
344 PCSTimeout = 0x4000,
345 RxFIFOOver = 0x40,
346 RxUnderrun = 0x20,
347 RxOverflow = 0x10,
348 TxErr = 0x08,
349 TxOK = 0x04,
350 RxErr = 0x02,
351 RxOK = 0x01,
352
353 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
354 };
355
356 enum TxStatusBits {
357 TxHostOwns = 0x2000,
358 TxUnderrun = 0x4000,
359 TxStatOK = 0x8000,
360 TxOutOfWindow = 0x20000000,
361 TxAborted = 0x40000000,
362 TxCarrierLost = 0x80000000,
363 };
364 enum RxStatusBits {
365 RxMulticast = 0x8000,
366 RxPhysical = 0x4000,
367 RxBroadcast = 0x2000,
368 RxBadSymbol = 0x0020,
369 RxRunt = 0x0010,
370 RxTooLong = 0x0008,
371 RxCRCErr = 0x0004,
372 RxBadAlign = 0x0002,
373 RxStatusOK = 0x0001,
374 };
375
376 /* Bits in RxConfig. */
377 enum rx_mode_bits {
378 AcceptErr = 0x20,
379 AcceptRunt = 0x10,
380 AcceptBroadcast = 0x08,
381 AcceptMulticast = 0x04,
382 AcceptMyPhys = 0x02,
383 AcceptAllPhys = 0x01,
384 };
385
386 /* Bits in TxConfig. */
387 enum tx_config_bits {
388 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
389 TxIFGShift = 24,
390 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
391 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
392 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
393 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
394
395 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
396 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
397 TxClearAbt = (1 << 0), /* Clear abort (WO) */
398 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
399 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
400
401 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
402 };
403
404 /* Bits in Config1 */
405 enum Config1Bits {
406 Cfg1_PM_Enable = 0x01,
407 Cfg1_VPD_Enable = 0x02,
408 Cfg1_PIO = 0x04,
409 Cfg1_MMIO = 0x08,
410 LWAKE = 0x10, /* not on 8139, 8139A */
411 Cfg1_Driver_Load = 0x20,
412 Cfg1_LED0 = 0x40,
413 Cfg1_LED1 = 0x80,
414 SLEEP = (1 << 1), /* only on 8139, 8139A */
415 PWRDN = (1 << 0), /* only on 8139, 8139A */
416 };
417
418 /* Bits in Config3 */
419 enum Config3Bits {
420 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
421 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
422 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
423 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
424 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
425 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
426 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
427 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
428 };
429
430 /* Bits in Config4 */
431 enum Config4Bits {
432 LWPTN = (1 << 2), /* not on 8139, 8139A */
433 };
434
435 /* Bits in Config5 */
436 enum Config5Bits {
437 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
438 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
439 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
440 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
441 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
442 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
443 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
444 };
445
446 enum RxConfigBits {
447 /* rx fifo threshold */
448 RxCfgFIFOShift = 13,
449 RxCfgFIFONone = (7 << RxCfgFIFOShift),
450
451 /* Max DMA burst */
452 RxCfgDMAShift = 8,
453 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
454
455 /* rx ring buffer length */
456 RxCfgRcv8K = 0,
457 RxCfgRcv16K = (1 << 11),
458 RxCfgRcv32K = (1 << 12),
459 RxCfgRcv64K = (1 << 11) | (1 << 12),
460
461 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
462 RxNoWrap = (1 << 7),
463 };
464
465 /* Twister tuning parameters from RealTek.
466 Completely undocumented, but required to tune bad links on some boards. */
467 enum CSCRBits {
468 CSCR_LinkOKBit = 0x0400,
469 CSCR_LinkChangeBit = 0x0800,
470 CSCR_LinkStatusBits = 0x0f000,
471 CSCR_LinkDownOffCmd = 0x003c0,
472 CSCR_LinkDownCmd = 0x0f3c0,
473 };
474
475 enum Cfg9346Bits {
476 Cfg9346_Lock = 0x00,
477 Cfg9346_Unlock = 0xC0,
478 };
479
480 typedef enum {
481 CH_8139 = 0,
482 CH_8139_K,
483 CH_8139A,
484 CH_8139A_G,
485 CH_8139B,
486 CH_8130,
487 CH_8139C,
488 CH_8100,
489 CH_8100B_8139D,
490 CH_8101,
491 } chip_t;
492
493 enum chip_flags {
494 HasHltClk = (1 << 0),
495 HasLWake = (1 << 1),
496 };
497
498 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
499 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
500 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
501
502 /* directly indexed by chip_t, above */
503 static const struct {
504 const char *name;
505 u32 version; /* from RTL8139C/RTL8139D docs */
506 u32 flags;
507 } rtl_chip_info[] = {
508 { "RTL-8139",
509 HW_REVID(1, 0, 0, 0, 0, 0, 0),
510 HasHltClk,
511 },
512
513 { "RTL-8139 rev K",
514 HW_REVID(1, 1, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139A",
519 HW_REVID(1, 1, 1, 0, 0, 0, 0),
520 HasHltClk, /* XXX undocumented? */
521 },
522
523 { "RTL-8139A rev G",
524 HW_REVID(1, 1, 1, 0, 0, 1, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139B",
529 HW_REVID(1, 1, 1, 1, 0, 0, 0),
530 HasLWake,
531 },
532
533 { "RTL-8130",
534 HW_REVID(1, 1, 1, 1, 1, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8139C",
539 HW_REVID(1, 1, 1, 0, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8100",
544 HW_REVID(1, 1, 1, 1, 0, 1, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100B/8139D",
549 HW_REVID(1, 1, 1, 0, 1, 0, 1),
550 HasHltClk /* XXX undocumented? */
551 | HasLWake,
552 },
553
554 { "RTL-8101",
555 HW_REVID(1, 1, 1, 0, 1, 1, 1),
556 HasLWake,
557 },
558 };
559
560 struct rtl_extra_stats {
561 unsigned long early_rx;
562 unsigned long tx_buf_mapped;
563 unsigned long tx_timeouts;
564 unsigned long rx_lost_in_ring;
565 };
566
567 struct rtl8139_private {
568 void __iomem *mmio_addr;
569 int drv_flags;
570 struct pci_dev *pci_dev;
571 u32 msg_enable;
572 struct napi_struct napi;
573 struct net_device *dev;
574
575 unsigned char *rx_ring;
576 unsigned int cur_rx; /* RX buf index of next pkt */
577 dma_addr_t rx_ring_dma;
578
579 unsigned int tx_flag;
580 unsigned long cur_tx;
581 unsigned long dirty_tx;
582 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
583 unsigned char *tx_bufs; /* Tx bounce buffer region. */
584 dma_addr_t tx_bufs_dma;
585
586 signed char phys[4]; /* MII device addresses. */
587
588 /* Twister tune state. */
589 char twistie, twist_row, twist_col;
590
591 unsigned int watchdog_fired : 1;
592 unsigned int default_port : 4; /* Last dev->if_port value. */
593 unsigned int have_thread : 1;
594
595 spinlock_t lock;
596 spinlock_t rx_lock;
597
598 chip_t chipset;
599 u32 rx_config;
600 struct rtl_extra_stats xstats;
601
602 struct delayed_work thread;
603
604 struct mii_if_info mii;
605 unsigned int regs_len;
606 unsigned long fifo_copy_timeout;
607 };
608
609 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
610 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
611 MODULE_LICENSE("GPL");
612 MODULE_VERSION(DRV_VERSION);
613
614 module_param(use_io, int, 0);
615 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
616 module_param(multicast_filter_limit, int, 0);
617 module_param_array(media, int, NULL, 0);
618 module_param_array(full_duplex, int, NULL, 0);
619 module_param(debug, int, 0);
620 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
621 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
622 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
623 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
624
625 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
626 static int rtl8139_open (struct net_device *dev);
627 static int mdio_read (struct net_device *dev, int phy_id, int location);
628 static void mdio_write (struct net_device *dev, int phy_id, int location,
629 int val);
630 static void rtl8139_start_thread(struct rtl8139_private *tp);
631 static void rtl8139_tx_timeout (struct net_device *dev);
632 static void rtl8139_init_ring (struct net_device *dev);
633 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
634 struct net_device *dev);
635 #ifdef CONFIG_NET_POLL_CONTROLLER
636 static void rtl8139_poll_controller(struct net_device *dev);
637 #endif
638 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
639 static int rtl8139_poll(struct napi_struct *napi, int budget);
640 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
641 static int rtl8139_close (struct net_device *dev);
642 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
643 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
644 static void rtl8139_set_rx_mode (struct net_device *dev);
645 static void __set_rx_mode (struct net_device *dev);
646 static void rtl8139_hw_start (struct net_device *dev);
647 static void rtl8139_thread (struct work_struct *work);
648 static void rtl8139_tx_timeout_task(struct work_struct *work);
649 static const struct ethtool_ops rtl8139_ethtool_ops;
650
651 /* write MMIO register, with flush */
652 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
653 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
654 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
655 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
656
657 /* write MMIO register */
658 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
659 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
660 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
661
662 /* read MMIO register */
663 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
664 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
665 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
666
667
668 static const u16 rtl8139_intr_mask =
669 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
670 TxErr | TxOK | RxErr | RxOK;
671
672 static const u16 rtl8139_norx_intr_mask =
673 PCIErr | PCSTimeout | RxUnderrun |
674 TxErr | TxOK | RxErr ;
675
676 #if RX_BUF_IDX == 0
677 static const unsigned int rtl8139_rx_config =
678 RxCfgRcv8K | RxNoWrap |
679 (RX_FIFO_THRESH << RxCfgFIFOShift) |
680 (RX_DMA_BURST << RxCfgDMAShift);
681 #elif RX_BUF_IDX == 1
682 static const unsigned int rtl8139_rx_config =
683 RxCfgRcv16K | RxNoWrap |
684 (RX_FIFO_THRESH << RxCfgFIFOShift) |
685 (RX_DMA_BURST << RxCfgDMAShift);
686 #elif RX_BUF_IDX == 2
687 static const unsigned int rtl8139_rx_config =
688 RxCfgRcv32K | RxNoWrap |
689 (RX_FIFO_THRESH << RxCfgFIFOShift) |
690 (RX_DMA_BURST << RxCfgDMAShift);
691 #elif RX_BUF_IDX == 3
692 static const unsigned int rtl8139_rx_config =
693 RxCfgRcv64K |
694 (RX_FIFO_THRESH << RxCfgFIFOShift) |
695 (RX_DMA_BURST << RxCfgDMAShift);
696 #else
697 #error "Invalid configuration for 8139_RXBUF_IDX"
698 #endif
699
700 static const unsigned int rtl8139_tx_config =
701 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
702
703 static void __rtl8139_cleanup_dev (struct net_device *dev)
704 {
705 struct rtl8139_private *tp = netdev_priv(dev);
706 struct pci_dev *pdev;
707
708 assert (dev != NULL);
709 assert (tp->pci_dev != NULL);
710 pdev = tp->pci_dev;
711
712 if (tp->mmio_addr)
713 pci_iounmap (pdev, tp->mmio_addr);
714
715 /* it's ok to call this even if we have no regions to free */
716 pci_release_regions (pdev);
717
718 free_netdev(dev);
719 pci_set_drvdata (pdev, NULL);
720 }
721
722
723 static void rtl8139_chip_reset (void __iomem *ioaddr)
724 {
725 int i;
726
727 /* Soft reset the chip. */
728 RTL_W8 (ChipCmd, CmdReset);
729
730 /* Check that the chip has finished the reset. */
731 for (i = 1000; i > 0; i--) {
732 barrier();
733 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
734 break;
735 udelay (10);
736 }
737 }
738
739
740 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)
741 {
742 void __iomem *ioaddr;
743 struct net_device *dev;
744 struct rtl8139_private *tp;
745 u8 tmp8;
746 int rc, disable_dev_on_err = 0;
747 unsigned int i;
748 unsigned long pio_start, pio_end, pio_flags, pio_len;
749 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
750 u32 version;
751
752 assert (pdev != NULL);
753
754 /* dev and priv zeroed in alloc_etherdev */
755 dev = alloc_etherdev (sizeof (*tp));
756 if (dev == NULL) {
757 dev_err(&pdev->dev, "Unable to alloc new net device\n");
758 return ERR_PTR(-ENOMEM);
759 }
760 SET_NETDEV_DEV(dev, &pdev->dev);
761
762 tp = netdev_priv(dev);
763 tp->pci_dev = pdev;
764
765 /* enable device (incl. PCI PM wakeup and hotplug setup) */
766 rc = pci_enable_device (pdev);
767 if (rc)
768 goto err_out;
769
770 pio_start = pci_resource_start (pdev, 0);
771 pio_end = pci_resource_end (pdev, 0);
772 pio_flags = pci_resource_flags (pdev, 0);
773 pio_len = pci_resource_len (pdev, 0);
774
775 mmio_start = pci_resource_start (pdev, 1);
776 mmio_end = pci_resource_end (pdev, 1);
777 mmio_flags = pci_resource_flags (pdev, 1);
778 mmio_len = pci_resource_len (pdev, 1);
779
780 /* set this immediately, we need to know before
781 * we talk to the chip directly */
782 pr_debug("PIO region size == 0x%02lX\n", pio_len);
783 pr_debug("MMIO region size == 0x%02lX\n", mmio_len);
784
785 retry:
786 if (use_io) {
787 /* make sure PCI base addr 0 is PIO */
788 if (!(pio_flags & IORESOURCE_IO)) {
789 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
790 rc = -ENODEV;
791 goto err_out;
792 }
793 /* check for weird/broken PCI region reporting */
794 if (pio_len < RTL_MIN_IO_SIZE) {
795 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
796 rc = -ENODEV;
797 goto err_out;
798 }
799 } else {
800 /* make sure PCI base addr 1 is MMIO */
801 if (!(mmio_flags & IORESOURCE_MEM)) {
802 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
803 rc = -ENODEV;
804 goto err_out;
805 }
806 if (mmio_len < RTL_MIN_IO_SIZE) {
807 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
808 rc = -ENODEV;
809 goto err_out;
810 }
811 }
812
813 rc = pci_request_regions (pdev, DRV_NAME);
814 if (rc)
815 goto err_out;
816 disable_dev_on_err = 1;
817
818 /* enable PCI bus-mastering */
819 pci_set_master (pdev);
820
821 if (use_io) {
822 ioaddr = pci_iomap(pdev, 0, 0);
823 if (!ioaddr) {
824 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
825 rc = -EIO;
826 goto err_out;
827 }
828 dev->base_addr = pio_start;
829 tp->regs_len = pio_len;
830 } else {
831 /* ioremap MMIO region */
832 ioaddr = pci_iomap(pdev, 1, 0);
833 if (ioaddr == NULL) {
834 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");
835 pci_release_regions(pdev);
836 use_io = 1;
837 goto retry;
838 }
839 dev->base_addr = (long) ioaddr;
840 tp->regs_len = mmio_len;
841 }
842 tp->mmio_addr = ioaddr;
843
844 /* Bring old chips out of low-power mode. */
845 RTL_W8 (HltClk, 'R');
846
847 /* check for missing/broken hardware */
848 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
849 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
850 rc = -EIO;
851 goto err_out;
852 }
853
854 /* identify chip attached to board */
855 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
856 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
857 if (version == rtl_chip_info[i].version) {
858 tp->chipset = i;
859 goto match;
860 }
861
862 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
863 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
864 dev_dbg(&pdev->dev, "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
865 tp->chipset = 0;
866
867 match:
868 pr_debug("chipset id (%d) == index %d, '%s'\n",
869 version, i, rtl_chip_info[i].name);
870
871 if (tp->chipset >= CH_8139B) {
872 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
873 pr_debug("PCI PM wakeup\n");
874 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
875 (tmp8 & LWAKE))
876 new_tmp8 &= ~LWAKE;
877 new_tmp8 |= Cfg1_PM_Enable;
878 if (new_tmp8 != tmp8) {
879 RTL_W8 (Cfg9346, Cfg9346_Unlock);
880 RTL_W8 (Config1, tmp8);
881 RTL_W8 (Cfg9346, Cfg9346_Lock);
882 }
883 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
884 tmp8 = RTL_R8 (Config4);
885 if (tmp8 & LWPTN) {
886 RTL_W8 (Cfg9346, Cfg9346_Unlock);
887 RTL_W8 (Config4, tmp8 & ~LWPTN);
888 RTL_W8 (Cfg9346, Cfg9346_Lock);
889 }
890 }
891 } else {
892 pr_debug("Old chip wakeup\n");
893 tmp8 = RTL_R8 (Config1);
894 tmp8 &= ~(SLEEP | PWRDN);
895 RTL_W8 (Config1, tmp8);
896 }
897
898 rtl8139_chip_reset (ioaddr);
899
900 return dev;
901
902 err_out:
903 __rtl8139_cleanup_dev (dev);
904 if (disable_dev_on_err)
905 pci_disable_device (pdev);
906 return ERR_PTR(rc);
907 }
908
909 static const struct net_device_ops rtl8139_netdev_ops = {
910 .ndo_open = rtl8139_open,
911 .ndo_stop = rtl8139_close,
912 .ndo_get_stats = rtl8139_get_stats,
913 .ndo_change_mtu = eth_change_mtu,
914 .ndo_validate_addr = eth_validate_addr,
915 .ndo_set_mac_address = rtl8139_set_mac_address,
916 .ndo_start_xmit = rtl8139_start_xmit,
917 .ndo_set_multicast_list = rtl8139_set_rx_mode,
918 .ndo_do_ioctl = netdev_ioctl,
919 .ndo_tx_timeout = rtl8139_tx_timeout,
920 #ifdef CONFIG_NET_POLL_CONTROLLER
921 .ndo_poll_controller = rtl8139_poll_controller,
922 #endif
923 };
924
925 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
926 const struct pci_device_id *ent)
927 {
928 struct net_device *dev = NULL;
929 struct rtl8139_private *tp;
930 int i, addr_len, option;
931 void __iomem *ioaddr;
932 static int board_idx = -1;
933
934 assert (pdev != NULL);
935 assert (ent != NULL);
936
937 board_idx++;
938
939 /* when we're built into the kernel, the driver version message
940 * is only printed if at least one 8139 board has been found
941 */
942 #ifndef MODULE
943 {
944 static int printed_version;
945 if (!printed_version++)
946 pr_info(RTL8139_DRIVER_NAME "\n");
947 }
948 #endif
949
950 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
951 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
952 dev_info(&pdev->dev,
953 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
954 pdev->vendor, pdev->device, pdev->revision);
955 return -ENODEV;
956 }
957
958 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
959 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
960 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
961 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
962 pr_info("OQO Model 2 detected. Forcing PIO\n");
963 use_io = 1;
964 }
965
966 dev = rtl8139_init_board (pdev);
967 if (IS_ERR(dev))
968 return PTR_ERR(dev);
969
970 assert (dev != NULL);
971 tp = netdev_priv(dev);
972 tp->dev = dev;
973
974 ioaddr = tp->mmio_addr;
975 assert (ioaddr != NULL);
976
977 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
978 for (i = 0; i < 3; i++)
979 ((__le16 *) (dev->dev_addr))[i] =
980 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
981 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
982
983 /* The Rtl8139-specific entries in the device structure. */
984 dev->netdev_ops = &rtl8139_netdev_ops;
985 dev->ethtool_ops = &rtl8139_ethtool_ops;
986 dev->watchdog_timeo = TX_TIMEOUT;
987 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
988
989 /* note: the hardware is not capable of sg/csum/highdma, however
990 * through the use of skb_copy_and_csum_dev we enable these
991 * features
992 */
993 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
994
995 dev->irq = pdev->irq;
996
997 /* tp zeroed and aligned in alloc_etherdev */
998 tp = netdev_priv(dev);
999
1000 /* note: tp->chipset set in rtl8139_init_board */
1001 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1002 tp->mmio_addr = ioaddr;
1003 tp->msg_enable =
1004 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1005 spin_lock_init (&tp->lock);
1006 spin_lock_init (&tp->rx_lock);
1007 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1008 tp->mii.dev = dev;
1009 tp->mii.mdio_read = mdio_read;
1010 tp->mii.mdio_write = mdio_write;
1011 tp->mii.phy_id_mask = 0x3f;
1012 tp->mii.reg_num_mask = 0x1f;
1013
1014 /* dev is fully set up and ready to use now */
1015 pr_debug("about to register device named %s (%p)...\n",
1016 dev->name, dev);
1017 i = register_netdev (dev);
1018 if (i) goto err_out;
1019
1020 pci_set_drvdata (pdev, dev);
1021
1022 netdev_info(dev, "%s at 0x%lx, %pM, IRQ %d\n",
1023 board_info[ent->driver_data].name,
1024 dev->base_addr, dev->dev_addr, dev->irq);
1025
1026 netdev_dbg(dev, "Identified 8139 chip type '%s'\n",
1027 rtl_chip_info[tp->chipset].name);
1028
1029 /* Find the connected MII xcvrs.
1030 Doing this in open() would allow detecting external xcvrs later, but
1031 takes too much time. */
1032 #ifdef CONFIG_8139TOO_8129
1033 if (tp->drv_flags & HAS_MII_XCVR) {
1034 int phy, phy_idx = 0;
1035 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1036 int mii_status = mdio_read(dev, phy, 1);
1037 if (mii_status != 0xffff && mii_status != 0x0000) {
1038 u16 advertising = mdio_read(dev, phy, 4);
1039 tp->phys[phy_idx++] = phy;
1040 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n",
1041 phy, mii_status, advertising);
1042 }
1043 }
1044 if (phy_idx == 0) {
1045 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n");
1046 tp->phys[0] = 32;
1047 }
1048 } else
1049 #endif
1050 tp->phys[0] = 32;
1051 tp->mii.phy_id = tp->phys[0];
1052
1053 /* The lower four bits are the media type. */
1054 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1055 if (option > 0) {
1056 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1057 tp->default_port = option & 0xFF;
1058 if (tp->default_port)
1059 tp->mii.force_media = 1;
1060 }
1061 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1062 tp->mii.full_duplex = full_duplex[board_idx];
1063 if (tp->mii.full_duplex) {
1064 netdev_info(dev, "Media type forced to Full Duplex\n");
1065 /* Changing the MII-advertised media because might prevent
1066 re-connection. */
1067 tp->mii.force_media = 1;
1068 }
1069 if (tp->default_port) {
1070 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n",
1071 (option & 0x20 ? 100 : 10),
1072 (option & 0x10 ? "full" : "half"));
1073 mdio_write(dev, tp->phys[0], 0,
1074 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1075 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1076 }
1077
1078 /* Put the chip into low-power mode. */
1079 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1080 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1081
1082 return 0;
1083
1084 err_out:
1085 __rtl8139_cleanup_dev (dev);
1086 pci_disable_device (pdev);
1087 return i;
1088 }
1089
1090
1091 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1092 {
1093 struct net_device *dev = pci_get_drvdata (pdev);
1094
1095 assert (dev != NULL);
1096
1097 flush_scheduled_work();
1098
1099 unregister_netdev (dev);
1100
1101 __rtl8139_cleanup_dev (dev);
1102 pci_disable_device (pdev);
1103 }
1104
1105
1106 /* Serial EEPROM section. */
1107
1108 /* EEPROM_Ctrl bits. */
1109 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1110 #define EE_CS 0x08 /* EEPROM chip select. */
1111 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1112 #define EE_WRITE_0 0x00
1113 #define EE_WRITE_1 0x02
1114 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1115 #define EE_ENB (0x80 | EE_CS)
1116
1117 /* Delay between EEPROM clock transitions.
1118 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1119 */
1120
1121 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1122
1123 /* The EEPROM commands include the alway-set leading bit. */
1124 #define EE_WRITE_CMD (5)
1125 #define EE_READ_CMD (6)
1126 #define EE_ERASE_CMD (7)
1127
1128 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1129 {
1130 int i;
1131 unsigned retval = 0;
1132 int read_cmd = location | (EE_READ_CMD << addr_len);
1133
1134 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1135 RTL_W8 (Cfg9346, EE_ENB);
1136 eeprom_delay ();
1137
1138 /* Shift the read command bits out. */
1139 for (i = 4 + addr_len; i >= 0; i--) {
1140 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1141 RTL_W8 (Cfg9346, EE_ENB | dataval);
1142 eeprom_delay ();
1143 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1144 eeprom_delay ();
1145 }
1146 RTL_W8 (Cfg9346, EE_ENB);
1147 eeprom_delay ();
1148
1149 for (i = 16; i > 0; i--) {
1150 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1151 eeprom_delay ();
1152 retval =
1153 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1154 0);
1155 RTL_W8 (Cfg9346, EE_ENB);
1156 eeprom_delay ();
1157 }
1158
1159 /* Terminate the EEPROM access. */
1160 RTL_W8 (Cfg9346, ~EE_CS);
1161 eeprom_delay ();
1162
1163 return retval;
1164 }
1165
1166 /* MII serial management: mostly bogus for now. */
1167 /* Read and write the MII management registers using software-generated
1168 serial MDIO protocol.
1169 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1170 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1171 "overclocking" issues. */
1172 #define MDIO_DIR 0x80
1173 #define MDIO_DATA_OUT 0x04
1174 #define MDIO_DATA_IN 0x02
1175 #define MDIO_CLK 0x01
1176 #define MDIO_WRITE0 (MDIO_DIR)
1177 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1178
1179 #define mdio_delay() RTL_R8(Config4)
1180
1181
1182 static const char mii_2_8139_map[8] = {
1183 BasicModeCtrl,
1184 BasicModeStatus,
1185 0,
1186 0,
1187 NWayAdvert,
1188 NWayLPAR,
1189 NWayExpansion,
1190 0
1191 };
1192
1193
1194 #ifdef CONFIG_8139TOO_8129
1195 /* Syncronize the MII management interface by shifting 32 one bits out. */
1196 static void mdio_sync (void __iomem *ioaddr)
1197 {
1198 int i;
1199
1200 for (i = 32; i >= 0; i--) {
1201 RTL_W8 (Config4, MDIO_WRITE1);
1202 mdio_delay ();
1203 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1204 mdio_delay ();
1205 }
1206 }
1207 #endif
1208
1209 static int mdio_read (struct net_device *dev, int phy_id, int location)
1210 {
1211 struct rtl8139_private *tp = netdev_priv(dev);
1212 int retval = 0;
1213 #ifdef CONFIG_8139TOO_8129
1214 void __iomem *ioaddr = tp->mmio_addr;
1215 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1216 int i;
1217 #endif
1218
1219 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1220 void __iomem *ioaddr = tp->mmio_addr;
1221 return location < 8 && mii_2_8139_map[location] ?
1222 RTL_R16 (mii_2_8139_map[location]) : 0;
1223 }
1224
1225 #ifdef CONFIG_8139TOO_8129
1226 mdio_sync (ioaddr);
1227 /* Shift the read command bits out. */
1228 for (i = 15; i >= 0; i--) {
1229 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1230
1231 RTL_W8 (Config4, MDIO_DIR | dataval);
1232 mdio_delay ();
1233 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1234 mdio_delay ();
1235 }
1236
1237 /* Read the two transition, 16 data, and wire-idle bits. */
1238 for (i = 19; i > 0; i--) {
1239 RTL_W8 (Config4, 0);
1240 mdio_delay ();
1241 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1242 RTL_W8 (Config4, MDIO_CLK);
1243 mdio_delay ();
1244 }
1245 #endif
1246
1247 return (retval >> 1) & 0xffff;
1248 }
1249
1250
1251 static void mdio_write (struct net_device *dev, int phy_id, int location,
1252 int value)
1253 {
1254 struct rtl8139_private *tp = netdev_priv(dev);
1255 #ifdef CONFIG_8139TOO_8129
1256 void __iomem *ioaddr = tp->mmio_addr;
1257 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1258 int i;
1259 #endif
1260
1261 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1262 void __iomem *ioaddr = tp->mmio_addr;
1263 if (location == 0) {
1264 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1265 RTL_W16 (BasicModeCtrl, value);
1266 RTL_W8 (Cfg9346, Cfg9346_Lock);
1267 } else if (location < 8 && mii_2_8139_map[location])
1268 RTL_W16 (mii_2_8139_map[location], value);
1269 return;
1270 }
1271
1272 #ifdef CONFIG_8139TOO_8129
1273 mdio_sync (ioaddr);
1274
1275 /* Shift the command bits out. */
1276 for (i = 31; i >= 0; i--) {
1277 int dataval =
1278 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1279 RTL_W8 (Config4, dataval);
1280 mdio_delay ();
1281 RTL_W8 (Config4, dataval | MDIO_CLK);
1282 mdio_delay ();
1283 }
1284 /* Clear out extra bits. */
1285 for (i = 2; i > 0; i--) {
1286 RTL_W8 (Config4, 0);
1287 mdio_delay ();
1288 RTL_W8 (Config4, MDIO_CLK);
1289 mdio_delay ();
1290 }
1291 #endif
1292 }
1293
1294
1295 static int rtl8139_open (struct net_device *dev)
1296 {
1297 struct rtl8139_private *tp = netdev_priv(dev);
1298 int retval;
1299 void __iomem *ioaddr = tp->mmio_addr;
1300
1301 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1302 if (retval)
1303 return retval;
1304
1305 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1306 &tp->tx_bufs_dma, GFP_KERNEL);
1307 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1308 &tp->rx_ring_dma, GFP_KERNEL);
1309 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1310 free_irq(dev->irq, dev);
1311
1312 if (tp->tx_bufs)
1313 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1314 tp->tx_bufs, tp->tx_bufs_dma);
1315 if (tp->rx_ring)
1316 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1317 tp->rx_ring, tp->rx_ring_dma);
1318
1319 return -ENOMEM;
1320
1321 }
1322
1323 napi_enable(&tp->napi);
1324
1325 tp->mii.full_duplex = tp->mii.force_media;
1326 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1327
1328 rtl8139_init_ring (dev);
1329 rtl8139_hw_start (dev);
1330 netif_start_queue (dev);
1331
1332 netif_dbg(tp, ifup, dev,
1333 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
1334 __func__,
1335 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1336 dev->irq, RTL_R8 (MediaStatus),
1337 tp->mii.full_duplex ? "full" : "half");
1338
1339 rtl8139_start_thread(tp);
1340
1341 return 0;
1342 }
1343
1344
1345 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1346 {
1347 struct rtl8139_private *tp = netdev_priv(dev);
1348
1349 if (tp->phys[0] >= 0) {
1350 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1351 }
1352 }
1353
1354 /* Start the hardware at open or resume. */
1355 static void rtl8139_hw_start (struct net_device *dev)
1356 {
1357 struct rtl8139_private *tp = netdev_priv(dev);
1358 void __iomem *ioaddr = tp->mmio_addr;
1359 u32 i;
1360 u8 tmp;
1361
1362 /* Bring old chips out of low-power mode. */
1363 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1364 RTL_W8 (HltClk, 'R');
1365
1366 rtl8139_chip_reset (ioaddr);
1367
1368 /* unlock Config[01234] and BMCR register writes */
1369 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1370 /* Restore our idea of the MAC address. */
1371 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1372 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1373
1374 tp->cur_rx = 0;
1375
1376 /* init Rx ring buffer DMA address */
1377 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1378
1379 /* Must enable Tx/Rx before setting transfer thresholds! */
1380 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1381
1382 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1383 RTL_W32 (RxConfig, tp->rx_config);
1384 RTL_W32 (TxConfig, rtl8139_tx_config);
1385
1386 rtl_check_media (dev, 1);
1387
1388 if (tp->chipset >= CH_8139B) {
1389 /* Disable magic packet scanning, which is enabled
1390 * when PM is enabled in Config1. It can be reenabled
1391 * via ETHTOOL_SWOL if desired. */
1392 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1393 }
1394
1395 netdev_dbg(dev, "init buffer addresses\n");
1396
1397 /* Lock Config[01234] and BMCR register writes */
1398 RTL_W8 (Cfg9346, Cfg9346_Lock);
1399
1400 /* init Tx buffer DMA addresses */
1401 for (i = 0; i < NUM_TX_DESC; i++)
1402 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1403
1404 RTL_W32 (RxMissed, 0);
1405
1406 rtl8139_set_rx_mode (dev);
1407
1408 /* no early-rx interrupts */
1409 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1410
1411 /* make sure RxTx has started */
1412 tmp = RTL_R8 (ChipCmd);
1413 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1414 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1415
1416 /* Enable all known interrupts by setting the interrupt mask. */
1417 RTL_W16 (IntrMask, rtl8139_intr_mask);
1418 }
1419
1420
1421 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1422 static void rtl8139_init_ring (struct net_device *dev)
1423 {
1424 struct rtl8139_private *tp = netdev_priv(dev);
1425 int i;
1426
1427 tp->cur_rx = 0;
1428 tp->cur_tx = 0;
1429 tp->dirty_tx = 0;
1430
1431 for (i = 0; i < NUM_TX_DESC; i++)
1432 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1433 }
1434
1435
1436 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1437 static int next_tick = 3 * HZ;
1438
1439 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1440 static inline void rtl8139_tune_twister (struct net_device *dev,
1441 struct rtl8139_private *tp) {}
1442 #else
1443 enum TwisterParamVals {
1444 PARA78_default = 0x78fa8388,
1445 PARA7c_default = 0xcb38de43, /* param[0][3] */
1446 PARA7c_xxx = 0xcb38de43,
1447 };
1448
1449 static const unsigned long param[4][4] = {
1450 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1451 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1452 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1453 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1454 };
1455
1456 static void rtl8139_tune_twister (struct net_device *dev,
1457 struct rtl8139_private *tp)
1458 {
1459 int linkcase;
1460 void __iomem *ioaddr = tp->mmio_addr;
1461
1462 /* This is a complicated state machine to configure the "twister" for
1463 impedance/echos based on the cable length.
1464 All of this is magic and undocumented.
1465 */
1466 switch (tp->twistie) {
1467 case 1:
1468 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1469 /* We have link beat, let us tune the twister. */
1470 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1471 tp->twistie = 2; /* Change to state 2. */
1472 next_tick = HZ / 10;
1473 } else {
1474 /* Just put in some reasonable defaults for when beat returns. */
1475 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1476 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1477 RTL_W32 (PARA78, PARA78_default);
1478 RTL_W32 (PARA7c, PARA7c_default);
1479 tp->twistie = 0; /* Bail from future actions. */
1480 }
1481 break;
1482 case 2:
1483 /* Read how long it took to hear the echo. */
1484 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1485 if (linkcase == 0x7000)
1486 tp->twist_row = 3;
1487 else if (linkcase == 0x3000)
1488 tp->twist_row = 2;
1489 else if (linkcase == 0x1000)
1490 tp->twist_row = 1;
1491 else
1492 tp->twist_row = 0;
1493 tp->twist_col = 0;
1494 tp->twistie = 3; /* Change to state 2. */
1495 next_tick = HZ / 10;
1496 break;
1497 case 3:
1498 /* Put out four tuning parameters, one per 100msec. */
1499 if (tp->twist_col == 0)
1500 RTL_W16 (FIFOTMS, 0);
1501 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1502 [(int) tp->twist_col]);
1503 next_tick = HZ / 10;
1504 if (++tp->twist_col >= 4) {
1505 /* For short cables we are done.
1506 For long cables (row == 3) check for mistune. */
1507 tp->twistie =
1508 (tp->twist_row == 3) ? 4 : 0;
1509 }
1510 break;
1511 case 4:
1512 /* Special case for long cables: check for mistune. */
1513 if ((RTL_R16 (CSCR) &
1514 CSCR_LinkStatusBits) == 0x7000) {
1515 tp->twistie = 0;
1516 break;
1517 } else {
1518 RTL_W32 (PARA7c, 0xfb38de03);
1519 tp->twistie = 5;
1520 next_tick = HZ / 10;
1521 }
1522 break;
1523 case 5:
1524 /* Retune for shorter cable (column 2). */
1525 RTL_W32 (FIFOTMS, 0x20);
1526 RTL_W32 (PARA78, PARA78_default);
1527 RTL_W32 (PARA7c, PARA7c_default);
1528 RTL_W32 (FIFOTMS, 0x00);
1529 tp->twist_row = 2;
1530 tp->twist_col = 0;
1531 tp->twistie = 3;
1532 next_tick = HZ / 10;
1533 break;
1534
1535 default:
1536 /* do nothing */
1537 break;
1538 }
1539 }
1540 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1541
1542 static inline void rtl8139_thread_iter (struct net_device *dev,
1543 struct rtl8139_private *tp,
1544 void __iomem *ioaddr)
1545 {
1546 int mii_lpa;
1547
1548 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1549
1550 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1551 int duplex = ((mii_lpa & LPA_100FULL) ||
1552 (mii_lpa & 0x01C0) == 0x0040);
1553 if (tp->mii.full_duplex != duplex) {
1554 tp->mii.full_duplex = duplex;
1555
1556 if (mii_lpa) {
1557 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
1558 tp->mii.full_duplex ? "full" : "half",
1559 tp->phys[0], mii_lpa);
1560 } else {
1561 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
1562 }
1563 #if 0
1564 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1565 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1566 RTL_W8 (Cfg9346, Cfg9346_Lock);
1567 #endif
1568 }
1569 }
1570
1571 next_tick = HZ * 60;
1572
1573 rtl8139_tune_twister (dev, tp);
1574
1575 netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
1576 RTL_R16(NWayLPAR));
1577 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
1578 RTL_R16(IntrMask), RTL_R16(IntrStatus));
1579 netdev_dbg(dev, "Chip config %02x %02x\n",
1580 RTL_R8(Config0), RTL_R8(Config1));
1581 }
1582
1583 static void rtl8139_thread (struct work_struct *work)
1584 {
1585 struct rtl8139_private *tp =
1586 container_of(work, struct rtl8139_private, thread.work);
1587 struct net_device *dev = tp->mii.dev;
1588 unsigned long thr_delay = next_tick;
1589
1590 rtnl_lock();
1591
1592 if (!netif_running(dev))
1593 goto out_unlock;
1594
1595 if (tp->watchdog_fired) {
1596 tp->watchdog_fired = 0;
1597 rtl8139_tx_timeout_task(work);
1598 } else
1599 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1600
1601 if (tp->have_thread)
1602 schedule_delayed_work(&tp->thread, thr_delay);
1603 out_unlock:
1604 rtnl_unlock ();
1605 }
1606
1607 static void rtl8139_start_thread(struct rtl8139_private *tp)
1608 {
1609 tp->twistie = 0;
1610 if (tp->chipset == CH_8139_K)
1611 tp->twistie = 1;
1612 else if (tp->drv_flags & HAS_LNK_CHNG)
1613 return;
1614
1615 tp->have_thread = 1;
1616 tp->watchdog_fired = 0;
1617
1618 schedule_delayed_work(&tp->thread, next_tick);
1619 }
1620
1621 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1622 {
1623 tp->cur_tx = 0;
1624 tp->dirty_tx = 0;
1625
1626 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1627 }
1628
1629 static void rtl8139_tx_timeout_task (struct work_struct *work)
1630 {
1631 struct rtl8139_private *tp =
1632 container_of(work, struct rtl8139_private, thread.work);
1633 struct net_device *dev = tp->mii.dev;
1634 void __iomem *ioaddr = tp->mmio_addr;
1635 int i;
1636 u8 tmp8;
1637
1638 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
1639 RTL_R8(ChipCmd), RTL_R16(IntrStatus),
1640 RTL_R16(IntrMask), RTL_R8(MediaStatus));
1641 /* Emit info to figure out what went wrong. */
1642 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n",
1643 tp->cur_tx, tp->dirty_tx);
1644 for (i = 0; i < NUM_TX_DESC; i++)
1645 netdev_dbg(dev, "Tx descriptor %d is %08lx%s\n",
1646 i, RTL_R32(TxStatus0 + (i * 4)),
1647 i == tp->dirty_tx % NUM_TX_DESC ?
1648 " (queue head)" : "");
1649
1650 tp->xstats.tx_timeouts++;
1651
1652 /* disable Tx ASAP, if not already */
1653 tmp8 = RTL_R8 (ChipCmd);
1654 if (tmp8 & CmdTxEnb)
1655 RTL_W8 (ChipCmd, CmdRxEnb);
1656
1657 spin_lock_bh(&tp->rx_lock);
1658 /* Disable interrupts by clearing the interrupt mask. */
1659 RTL_W16 (IntrMask, 0x0000);
1660
1661 /* Stop a shared interrupt from scavenging while we are. */
1662 spin_lock_irq(&tp->lock);
1663 rtl8139_tx_clear (tp);
1664 spin_unlock_irq(&tp->lock);
1665
1666 /* ...and finally, reset everything */
1667 if (netif_running(dev)) {
1668 rtl8139_hw_start (dev);
1669 netif_wake_queue (dev);
1670 }
1671 spin_unlock_bh(&tp->rx_lock);
1672 }
1673
1674 static void rtl8139_tx_timeout (struct net_device *dev)
1675 {
1676 struct rtl8139_private *tp = netdev_priv(dev);
1677
1678 tp->watchdog_fired = 1;
1679 if (!tp->have_thread) {
1680 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1681 schedule_delayed_work(&tp->thread, next_tick);
1682 }
1683 }
1684
1685 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
1686 struct net_device *dev)
1687 {
1688 struct rtl8139_private *tp = netdev_priv(dev);
1689 void __iomem *ioaddr = tp->mmio_addr;
1690 unsigned int entry;
1691 unsigned int len = skb->len;
1692 unsigned long flags;
1693
1694 /* Calculate the next Tx descriptor entry. */
1695 entry = tp->cur_tx % NUM_TX_DESC;
1696
1697 /* Note: the chip doesn't have auto-pad! */
1698 if (likely(len < TX_BUF_SIZE)) {
1699 if (len < ETH_ZLEN)
1700 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1701 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1702 dev_kfree_skb(skb);
1703 } else {
1704 dev_kfree_skb(skb);
1705 dev->stats.tx_dropped++;
1706 return NETDEV_TX_OK;
1707 }
1708
1709 spin_lock_irqsave(&tp->lock, flags);
1710 /*
1711 * Writing to TxStatus triggers a DMA transfer of the data
1712 * copied to tp->tx_buf[entry] above. Use a memory barrier
1713 * to make sure that the device sees the updated data.
1714 */
1715 wmb();
1716 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1717 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1718
1719 tp->cur_tx++;
1720
1721 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1722 netif_stop_queue (dev);
1723 spin_unlock_irqrestore(&tp->lock, flags);
1724
1725 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
1726 len, entry);
1727
1728 return NETDEV_TX_OK;
1729 }
1730
1731
1732 static void rtl8139_tx_interrupt (struct net_device *dev,
1733 struct rtl8139_private *tp,
1734 void __iomem *ioaddr)
1735 {
1736 unsigned long dirty_tx, tx_left;
1737
1738 assert (dev != NULL);
1739 assert (ioaddr != NULL);
1740
1741 dirty_tx = tp->dirty_tx;
1742 tx_left = tp->cur_tx - dirty_tx;
1743 while (tx_left > 0) {
1744 int entry = dirty_tx % NUM_TX_DESC;
1745 int txstatus;
1746
1747 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1748
1749 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1750 break; /* It still hasn't been Txed */
1751
1752 /* Note: TxCarrierLost is always asserted at 100mbps. */
1753 if (txstatus & (TxOutOfWindow | TxAborted)) {
1754 /* There was an major error, log it. */
1755 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
1756 txstatus);
1757 dev->stats.tx_errors++;
1758 if (txstatus & TxAborted) {
1759 dev->stats.tx_aborted_errors++;
1760 RTL_W32 (TxConfig, TxClearAbt);
1761 RTL_W16 (IntrStatus, TxErr);
1762 wmb();
1763 }
1764 if (txstatus & TxCarrierLost)
1765 dev->stats.tx_carrier_errors++;
1766 if (txstatus & TxOutOfWindow)
1767 dev->stats.tx_window_errors++;
1768 } else {
1769 if (txstatus & TxUnderrun) {
1770 /* Add 64 to the Tx FIFO threshold. */
1771 if (tp->tx_flag < 0x00300000)
1772 tp->tx_flag += 0x00020000;
1773 dev->stats.tx_fifo_errors++;
1774 }
1775 dev->stats.collisions += (txstatus >> 24) & 15;
1776 dev->stats.tx_bytes += txstatus & 0x7ff;
1777 dev->stats.tx_packets++;
1778 }
1779
1780 dirty_tx++;
1781 tx_left--;
1782 }
1783
1784 #ifndef RTL8139_NDEBUG
1785 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1786 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n",
1787 dirty_tx, tp->cur_tx);
1788 dirty_tx += NUM_TX_DESC;
1789 }
1790 #endif /* RTL8139_NDEBUG */
1791
1792 /* only wake the queue if we did work, and the queue is stopped */
1793 if (tp->dirty_tx != dirty_tx) {
1794 tp->dirty_tx = dirty_tx;
1795 mb();
1796 netif_wake_queue (dev);
1797 }
1798 }
1799
1800
1801 /* TODO: clean this up! Rx reset need not be this intensive */
1802 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1803 struct rtl8139_private *tp, void __iomem *ioaddr)
1804 {
1805 u8 tmp8;
1806 #ifdef CONFIG_8139_OLD_RX_RESET
1807 int tmp_work;
1808 #endif
1809
1810 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n",
1811 rx_status);
1812 dev->stats.rx_errors++;
1813 if (!(rx_status & RxStatusOK)) {
1814 if (rx_status & RxTooLong) {
1815 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n",
1816 rx_status);
1817 /* A.C.: The chip hangs here. */
1818 }
1819 if (rx_status & (RxBadSymbol | RxBadAlign))
1820 dev->stats.rx_frame_errors++;
1821 if (rx_status & (RxRunt | RxTooLong))
1822 dev->stats.rx_length_errors++;
1823 if (rx_status & RxCRCErr)
1824 dev->stats.rx_crc_errors++;
1825 } else {
1826 tp->xstats.rx_lost_in_ring++;
1827 }
1828
1829 #ifndef CONFIG_8139_OLD_RX_RESET
1830 tmp8 = RTL_R8 (ChipCmd);
1831 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1832 RTL_W8 (ChipCmd, tmp8);
1833 RTL_W32 (RxConfig, tp->rx_config);
1834 tp->cur_rx = 0;
1835 #else
1836 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1837
1838 /* disable receive */
1839 RTL_W8_F (ChipCmd, CmdTxEnb);
1840 tmp_work = 200;
1841 while (--tmp_work > 0) {
1842 udelay(1);
1843 tmp8 = RTL_R8 (ChipCmd);
1844 if (!(tmp8 & CmdRxEnb))
1845 break;
1846 }
1847 if (tmp_work <= 0)
1848 netdev_warn(dev, "rx stop wait too long\n");
1849 /* restart receive */
1850 tmp_work = 200;
1851 while (--tmp_work > 0) {
1852 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1853 udelay(1);
1854 tmp8 = RTL_R8 (ChipCmd);
1855 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1856 break;
1857 }
1858 if (tmp_work <= 0)
1859 netdev_warn(dev, "tx/rx enable wait too long\n");
1860
1861 /* and reinitialize all rx related registers */
1862 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1863 /* Must enable Tx/Rx before setting transfer thresholds! */
1864 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1865
1866 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1867 RTL_W32 (RxConfig, tp->rx_config);
1868 tp->cur_rx = 0;
1869
1870 netdev_dbg(dev, "init buffer addresses\n");
1871
1872 /* Lock Config[01234] and BMCR register writes */
1873 RTL_W8 (Cfg9346, Cfg9346_Lock);
1874
1875 /* init Rx ring buffer DMA address */
1876 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1877
1878 /* A.C.: Reset the multicast list. */
1879 __set_rx_mode (dev);
1880 #endif
1881 }
1882
1883 #if RX_BUF_IDX == 3
1884 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1885 u32 offset, unsigned int size)
1886 {
1887 u32 left = RX_BUF_LEN - offset;
1888
1889 if (size > left) {
1890 skb_copy_to_linear_data(skb, ring + offset, left);
1891 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1892 } else
1893 skb_copy_to_linear_data(skb, ring + offset, size);
1894 }
1895 #endif
1896
1897 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1898 {
1899 void __iomem *ioaddr = tp->mmio_addr;
1900 u16 status;
1901
1902 status = RTL_R16 (IntrStatus) & RxAckBits;
1903
1904 /* Clear out errors and receive interrupts */
1905 if (likely(status != 0)) {
1906 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1907 tp->dev->stats.rx_errors++;
1908 if (status & RxFIFOOver)
1909 tp->dev->stats.rx_fifo_errors++;
1910 }
1911 RTL_W16_F (IntrStatus, RxAckBits);
1912 }
1913 }
1914
1915 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1916 int budget)
1917 {
1918 void __iomem *ioaddr = tp->mmio_addr;
1919 int received = 0;
1920 unsigned char *rx_ring = tp->rx_ring;
1921 unsigned int cur_rx = tp->cur_rx;
1922 unsigned int rx_size = 0;
1923
1924 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1925 __func__, (u16)cur_rx,
1926 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
1927
1928 while (netif_running(dev) && received < budget &&
1929 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1930 u32 ring_offset = cur_rx % RX_BUF_LEN;
1931 u32 rx_status;
1932 unsigned int pkt_size;
1933 struct sk_buff *skb;
1934
1935 rmb();
1936
1937 /* read size+status of next frame from DMA ring buffer */
1938 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1939 rx_size = rx_status >> 16;
1940 pkt_size = rx_size - 4;
1941
1942 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n",
1943 __func__, rx_status, rx_size, cur_rx);
1944 #if RTL8139_DEBUG > 2
1945 print_hex_dump(KERN_DEBUG, "Frame contents: ",
1946 DUMP_PREFIX_OFFSET, 16, 1,
1947 &rx_ring[ring_offset], 70, true);
1948 #endif
1949
1950 /* Packet copy from FIFO still in progress.
1951 * Theoretically, this should never happen
1952 * since EarlyRx is disabled.
1953 */
1954 if (unlikely(rx_size == 0xfff0)) {
1955 if (!tp->fifo_copy_timeout)
1956 tp->fifo_copy_timeout = jiffies + 2;
1957 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1958 netdev_dbg(dev, "hung FIFO. Reset\n");
1959 rx_size = 0;
1960 goto no_early_rx;
1961 }
1962 netif_dbg(tp, intr, dev, "fifo copy in progress\n");
1963 tp->xstats.early_rx++;
1964 break;
1965 }
1966
1967 no_early_rx:
1968 tp->fifo_copy_timeout = 0;
1969
1970 /* If Rx err or invalid rx_size/rx_status received
1971 * (which happens if we get lost in the ring),
1972 * Rx process gets reset, so we abort any further
1973 * Rx processing.
1974 */
1975 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1976 (rx_size < 8) ||
1977 (!(rx_status & RxStatusOK)))) {
1978 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
1979 received = -1;
1980 goto out;
1981 }
1982
1983 /* Malloc up new buffer, compatible with net-2e. */
1984 /* Omit the four octet CRC from the length. */
1985
1986 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
1987 if (likely(skb)) {
1988 #if RX_BUF_IDX == 3
1989 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
1990 #else
1991 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
1992 #endif
1993 skb_put (skb, pkt_size);
1994
1995 skb->protocol = eth_type_trans (skb, dev);
1996
1997 dev->stats.rx_bytes += pkt_size;
1998 dev->stats.rx_packets++;
1999
2000 netif_receive_skb (skb);
2001 } else {
2002 if (net_ratelimit())
2003 netdev_warn(dev, "Memory squeeze, dropping packet\n");
2004 dev->stats.rx_dropped++;
2005 }
2006 received++;
2007
2008 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2009 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2010
2011 rtl8139_isr_ack(tp);
2012 }
2013
2014 if (unlikely(!received || rx_size == 0xfff0))
2015 rtl8139_isr_ack(tp);
2016
2017 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
2018 __func__, cur_rx,
2019 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
2020
2021 tp->cur_rx = cur_rx;
2022
2023 /*
2024 * The receive buffer should be mostly empty.
2025 * Tell NAPI to reenable the Rx irq.
2026 */
2027 if (tp->fifo_copy_timeout)
2028 received = budget;
2029
2030 out:
2031 return received;
2032 }
2033
2034
2035 static void rtl8139_weird_interrupt (struct net_device *dev,
2036 struct rtl8139_private *tp,
2037 void __iomem *ioaddr,
2038 int status, int link_changed)
2039 {
2040 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status);
2041
2042 assert (dev != NULL);
2043 assert (tp != NULL);
2044 assert (ioaddr != NULL);
2045
2046 /* Update the error count. */
2047 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2048 RTL_W32 (RxMissed, 0);
2049
2050 if ((status & RxUnderrun) && link_changed &&
2051 (tp->drv_flags & HAS_LNK_CHNG)) {
2052 rtl_check_media(dev, 0);
2053 status &= ~RxUnderrun;
2054 }
2055
2056 if (status & (RxUnderrun | RxErr))
2057 dev->stats.rx_errors++;
2058
2059 if (status & PCSTimeout)
2060 dev->stats.rx_length_errors++;
2061 if (status & RxUnderrun)
2062 dev->stats.rx_fifo_errors++;
2063 if (status & PCIErr) {
2064 u16 pci_cmd_status;
2065 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2066 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2067
2068 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status);
2069 }
2070 }
2071
2072 static int rtl8139_poll(struct napi_struct *napi, int budget)
2073 {
2074 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2075 struct net_device *dev = tp->dev;
2076 void __iomem *ioaddr = tp->mmio_addr;
2077 int work_done;
2078
2079 spin_lock(&tp->rx_lock);
2080 work_done = 0;
2081 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2082 work_done += rtl8139_rx(dev, tp, budget);
2083
2084 if (work_done < budget) {
2085 unsigned long flags;
2086 /*
2087 * Order is important since data can get interrupted
2088 * again when we think we are done.
2089 */
2090 spin_lock_irqsave(&tp->lock, flags);
2091 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2092 __napi_complete(napi);
2093 spin_unlock_irqrestore(&tp->lock, flags);
2094 }
2095 spin_unlock(&tp->rx_lock);
2096
2097 return work_done;
2098 }
2099
2100 /* The interrupt handler does all of the Rx thread work and cleans up
2101 after the Tx thread. */
2102 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2103 {
2104 struct net_device *dev = (struct net_device *) dev_instance;
2105 struct rtl8139_private *tp = netdev_priv(dev);
2106 void __iomem *ioaddr = tp->mmio_addr;
2107 u16 status, ackstat;
2108 int link_changed = 0; /* avoid bogus "uninit" warning */
2109 int handled = 0;
2110
2111 spin_lock (&tp->lock);
2112 status = RTL_R16 (IntrStatus);
2113
2114 /* shared irq? */
2115 if (unlikely((status & rtl8139_intr_mask) == 0))
2116 goto out;
2117
2118 handled = 1;
2119
2120 /* h/w no longer present (hotplug?) or major error, bail */
2121 if (unlikely(status == 0xFFFF))
2122 goto out;
2123
2124 /* close possible race's with dev_close */
2125 if (unlikely(!netif_running(dev))) {
2126 RTL_W16 (IntrMask, 0);
2127 goto out;
2128 }
2129
2130 /* Acknowledge all of the current interrupt sources ASAP, but
2131 an first get an additional status bit from CSCR. */
2132 if (unlikely(status & RxUnderrun))
2133 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2134
2135 ackstat = status & ~(RxAckBits | TxErr);
2136 if (ackstat)
2137 RTL_W16 (IntrStatus, ackstat);
2138
2139 /* Receive packets are processed by poll routine.
2140 If not running start it now. */
2141 if (status & RxAckBits){
2142 if (napi_schedule_prep(&tp->napi)) {
2143 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2144 __napi_schedule(&tp->napi);
2145 }
2146 }
2147
2148 /* Check uncommon events with one test. */
2149 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2150 rtl8139_weird_interrupt (dev, tp, ioaddr,
2151 status, link_changed);
2152
2153 if (status & (TxOK | TxErr)) {
2154 rtl8139_tx_interrupt (dev, tp, ioaddr);
2155 if (status & TxErr)
2156 RTL_W16 (IntrStatus, TxErr);
2157 }
2158 out:
2159 spin_unlock (&tp->lock);
2160
2161 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n",
2162 RTL_R16(IntrStatus));
2163 return IRQ_RETVAL(handled);
2164 }
2165
2166 #ifdef CONFIG_NET_POLL_CONTROLLER
2167 /*
2168 * Polling receive - used by netconsole and other diagnostic tools
2169 * to allow network i/o with interrupts disabled.
2170 */
2171 static void rtl8139_poll_controller(struct net_device *dev)
2172 {
2173 disable_irq(dev->irq);
2174 rtl8139_interrupt(dev->irq, dev);
2175 enable_irq(dev->irq);
2176 }
2177 #endif
2178
2179 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2180 {
2181 struct rtl8139_private *tp = netdev_priv(dev);
2182 void __iomem *ioaddr = tp->mmio_addr;
2183 struct sockaddr *addr = p;
2184
2185 if (!is_valid_ether_addr(addr->sa_data))
2186 return -EADDRNOTAVAIL;
2187
2188 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2189
2190 spin_lock_irq(&tp->lock);
2191
2192 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2193 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2194 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2195 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2196
2197 spin_unlock_irq(&tp->lock);
2198
2199 return 0;
2200 }
2201
2202 static int rtl8139_close (struct net_device *dev)
2203 {
2204 struct rtl8139_private *tp = netdev_priv(dev);
2205 void __iomem *ioaddr = tp->mmio_addr;
2206 unsigned long flags;
2207
2208 netif_stop_queue(dev);
2209 napi_disable(&tp->napi);
2210
2211 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n",
2212 RTL_R16(IntrStatus));
2213
2214 spin_lock_irqsave (&tp->lock, flags);
2215
2216 /* Stop the chip's Tx and Rx DMA processes. */
2217 RTL_W8 (ChipCmd, 0);
2218
2219 /* Disable interrupts by clearing the interrupt mask. */
2220 RTL_W16 (IntrMask, 0);
2221
2222 /* Update the error counts. */
2223 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2224 RTL_W32 (RxMissed, 0);
2225
2226 spin_unlock_irqrestore (&tp->lock, flags);
2227
2228 free_irq (dev->irq, dev);
2229
2230 rtl8139_tx_clear (tp);
2231
2232 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2233 tp->rx_ring, tp->rx_ring_dma);
2234 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2235 tp->tx_bufs, tp->tx_bufs_dma);
2236 tp->rx_ring = NULL;
2237 tp->tx_bufs = NULL;
2238
2239 /* Green! Put the chip in low-power mode. */
2240 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2241
2242 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2243 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2244
2245 return 0;
2246 }
2247
2248
2249 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2250 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2251 other threads or interrupts aren't messing with the 8139. */
2252 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2253 {
2254 struct rtl8139_private *tp = netdev_priv(dev);
2255 void __iomem *ioaddr = tp->mmio_addr;
2256
2257 spin_lock_irq(&tp->lock);
2258 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2259 u8 cfg3 = RTL_R8 (Config3);
2260 u8 cfg5 = RTL_R8 (Config5);
2261
2262 wol->supported = WAKE_PHY | WAKE_MAGIC
2263 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2264
2265 wol->wolopts = 0;
2266 if (cfg3 & Cfg3_LinkUp)
2267 wol->wolopts |= WAKE_PHY;
2268 if (cfg3 & Cfg3_Magic)
2269 wol->wolopts |= WAKE_MAGIC;
2270 /* (KON)FIXME: See how netdev_set_wol() handles the
2271 following constants. */
2272 if (cfg5 & Cfg5_UWF)
2273 wol->wolopts |= WAKE_UCAST;
2274 if (cfg5 & Cfg5_MWF)
2275 wol->wolopts |= WAKE_MCAST;
2276 if (cfg5 & Cfg5_BWF)
2277 wol->wolopts |= WAKE_BCAST;
2278 }
2279 spin_unlock_irq(&tp->lock);
2280 }
2281
2282
2283 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2284 that wol points to kernel memory and other threads or interrupts
2285 aren't messing with the 8139. */
2286 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2287 {
2288 struct rtl8139_private *tp = netdev_priv(dev);
2289 void __iomem *ioaddr = tp->mmio_addr;
2290 u32 support;
2291 u8 cfg3, cfg5;
2292
2293 support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2294 ? (WAKE_PHY | WAKE_MAGIC
2295 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2296 : 0);
2297 if (wol->wolopts & ~support)
2298 return -EINVAL;
2299
2300 spin_lock_irq(&tp->lock);
2301 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2302 if (wol->wolopts & WAKE_PHY)
2303 cfg3 |= Cfg3_LinkUp;
2304 if (wol->wolopts & WAKE_MAGIC)
2305 cfg3 |= Cfg3_Magic;
2306 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2307 RTL_W8 (Config3, cfg3);
2308 RTL_W8 (Cfg9346, Cfg9346_Lock);
2309
2310 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2311 /* (KON)FIXME: These are untested. We may have to set the
2312 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2313 documentation. */
2314 if (wol->wolopts & WAKE_UCAST)
2315 cfg5 |= Cfg5_UWF;
2316 if (wol->wolopts & WAKE_MCAST)
2317 cfg5 |= Cfg5_MWF;
2318 if (wol->wolopts & WAKE_BCAST)
2319 cfg5 |= Cfg5_BWF;
2320 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2321 spin_unlock_irq(&tp->lock);
2322
2323 return 0;
2324 }
2325
2326 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2327 {
2328 struct rtl8139_private *tp = netdev_priv(dev);
2329 strcpy(info->driver, DRV_NAME);
2330 strcpy(info->version, DRV_VERSION);
2331 strcpy(info->bus_info, pci_name(tp->pci_dev));
2332 info->regdump_len = tp->regs_len;
2333 }
2334
2335 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2336 {
2337 struct rtl8139_private *tp = netdev_priv(dev);
2338 spin_lock_irq(&tp->lock);
2339 mii_ethtool_gset(&tp->mii, cmd);
2340 spin_unlock_irq(&tp->lock);
2341 return 0;
2342 }
2343
2344 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2345 {
2346 struct rtl8139_private *tp = netdev_priv(dev);
2347 int rc;
2348 spin_lock_irq(&tp->lock);
2349 rc = mii_ethtool_sset(&tp->mii, cmd);
2350 spin_unlock_irq(&tp->lock);
2351 return rc;
2352 }
2353
2354 static int rtl8139_nway_reset(struct net_device *dev)
2355 {
2356 struct rtl8139_private *tp = netdev_priv(dev);
2357 return mii_nway_restart(&tp->mii);
2358 }
2359
2360 static u32 rtl8139_get_link(struct net_device *dev)
2361 {
2362 struct rtl8139_private *tp = netdev_priv(dev);
2363 return mii_link_ok(&tp->mii);
2364 }
2365
2366 static u32 rtl8139_get_msglevel(struct net_device *dev)
2367 {
2368 struct rtl8139_private *tp = netdev_priv(dev);
2369 return tp->msg_enable;
2370 }
2371
2372 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2373 {
2374 struct rtl8139_private *tp = netdev_priv(dev);
2375 tp->msg_enable = datum;
2376 }
2377
2378 static int rtl8139_get_regs_len(struct net_device *dev)
2379 {
2380 struct rtl8139_private *tp;
2381 /* TODO: we are too slack to do reg dumping for pio, for now */
2382 if (use_io)
2383 return 0;
2384 tp = netdev_priv(dev);
2385 return tp->regs_len;
2386 }
2387
2388 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2389 {
2390 struct rtl8139_private *tp;
2391
2392 /* TODO: we are too slack to do reg dumping for pio, for now */
2393 if (use_io)
2394 return;
2395 tp = netdev_priv(dev);
2396
2397 regs->version = RTL_REGS_VER;
2398
2399 spin_lock_irq(&tp->lock);
2400 memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2401 spin_unlock_irq(&tp->lock);
2402 }
2403
2404 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2405 {
2406 switch (sset) {
2407 case ETH_SS_STATS:
2408 return RTL_NUM_STATS;
2409 default:
2410 return -EOPNOTSUPP;
2411 }
2412 }
2413
2414 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2415 {
2416 struct rtl8139_private *tp = netdev_priv(dev);
2417
2418 data[0] = tp->xstats.early_rx;
2419 data[1] = tp->xstats.tx_buf_mapped;
2420 data[2] = tp->xstats.tx_timeouts;
2421 data[3] = tp->xstats.rx_lost_in_ring;
2422 }
2423
2424 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2425 {
2426 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2427 }
2428
2429 static const struct ethtool_ops rtl8139_ethtool_ops = {
2430 .get_drvinfo = rtl8139_get_drvinfo,
2431 .get_settings = rtl8139_get_settings,
2432 .set_settings = rtl8139_set_settings,
2433 .get_regs_len = rtl8139_get_regs_len,
2434 .get_regs = rtl8139_get_regs,
2435 .nway_reset = rtl8139_nway_reset,
2436 .get_link = rtl8139_get_link,
2437 .get_msglevel = rtl8139_get_msglevel,
2438 .set_msglevel = rtl8139_set_msglevel,
2439 .get_wol = rtl8139_get_wol,
2440 .set_wol = rtl8139_set_wol,
2441 .get_strings = rtl8139_get_strings,
2442 .get_sset_count = rtl8139_get_sset_count,
2443 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2444 };
2445
2446 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2447 {
2448 struct rtl8139_private *tp = netdev_priv(dev);
2449 int rc;
2450
2451 if (!netif_running(dev))
2452 return -EINVAL;
2453
2454 spin_lock_irq(&tp->lock);
2455 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2456 spin_unlock_irq(&tp->lock);
2457
2458 return rc;
2459 }
2460
2461
2462 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2463 {
2464 struct rtl8139_private *tp = netdev_priv(dev);
2465 void __iomem *ioaddr = tp->mmio_addr;
2466 unsigned long flags;
2467
2468 if (netif_running(dev)) {
2469 spin_lock_irqsave (&tp->lock, flags);
2470 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2471 RTL_W32 (RxMissed, 0);
2472 spin_unlock_irqrestore (&tp->lock, flags);
2473 }
2474
2475 return &dev->stats;
2476 }
2477
2478 /* Set or clear the multicast filter for this adaptor.
2479 This routine is not state sensitive and need not be SMP locked. */
2480
2481 static void __set_rx_mode (struct net_device *dev)
2482 {
2483 struct rtl8139_private *tp = netdev_priv(dev);
2484 void __iomem *ioaddr = tp->mmio_addr;
2485 u32 mc_filter[2]; /* Multicast hash filter */
2486 int rx_mode;
2487 u32 tmp;
2488
2489 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08lx\n",
2490 dev->flags, RTL_R32(RxConfig));
2491
2492 /* Note: do not reorder, GCC is clever about common statements. */
2493 if (dev->flags & IFF_PROMISC) {
2494 rx_mode =
2495 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2496 AcceptAllPhys;
2497 mc_filter[1] = mc_filter[0] = 0xffffffff;
2498 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2499 (dev->flags & IFF_ALLMULTI)) {
2500 /* Too many to filter perfectly -- accept all multicasts. */
2501 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2502 mc_filter[1] = mc_filter[0] = 0xffffffff;
2503 } else {
2504 struct netdev_hw_addr *ha;
2505 rx_mode = AcceptBroadcast | AcceptMyPhys;
2506 mc_filter[1] = mc_filter[0] = 0;
2507 netdev_for_each_mc_addr(ha, dev) {
2508 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2509
2510 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2511 rx_mode |= AcceptMulticast;
2512 }
2513 }
2514
2515 /* We can safely update without stopping the chip. */
2516 tmp = rtl8139_rx_config | rx_mode;
2517 if (tp->rx_config != tmp) {
2518 RTL_W32_F (RxConfig, tmp);
2519 tp->rx_config = tmp;
2520 }
2521 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2522 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2523 }
2524
2525 static void rtl8139_set_rx_mode (struct net_device *dev)
2526 {
2527 unsigned long flags;
2528 struct rtl8139_private *tp = netdev_priv(dev);
2529
2530 spin_lock_irqsave (&tp->lock, flags);
2531 __set_rx_mode(dev);
2532 spin_unlock_irqrestore (&tp->lock, flags);
2533 }
2534
2535 #ifdef CONFIG_PM
2536
2537 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2538 {
2539 struct net_device *dev = pci_get_drvdata (pdev);
2540 struct rtl8139_private *tp = netdev_priv(dev);
2541 void __iomem *ioaddr = tp->mmio_addr;
2542 unsigned long flags;
2543
2544 pci_save_state (pdev);
2545
2546 if (!netif_running (dev))
2547 return 0;
2548
2549 netif_device_detach (dev);
2550
2551 spin_lock_irqsave (&tp->lock, flags);
2552
2553 /* Disable interrupts, stop Tx and Rx. */
2554 RTL_W16 (IntrMask, 0);
2555 RTL_W8 (ChipCmd, 0);
2556
2557 /* Update the error counts. */
2558 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2559 RTL_W32 (RxMissed, 0);
2560
2561 spin_unlock_irqrestore (&tp->lock, flags);
2562
2563 pci_set_power_state (pdev, PCI_D3hot);
2564
2565 return 0;
2566 }
2567
2568
2569 static int rtl8139_resume (struct pci_dev *pdev)
2570 {
2571 struct net_device *dev = pci_get_drvdata (pdev);
2572
2573 pci_restore_state (pdev);
2574 if (!netif_running (dev))
2575 return 0;
2576 pci_set_power_state (pdev, PCI_D0);
2577 rtl8139_init_ring (dev);
2578 rtl8139_hw_start (dev);
2579 netif_device_attach (dev);
2580 return 0;
2581 }
2582
2583 #endif /* CONFIG_PM */
2584
2585
2586 static struct pci_driver rtl8139_pci_driver = {
2587 .name = DRV_NAME,
2588 .id_table = rtl8139_pci_tbl,
2589 .probe = rtl8139_init_one,
2590 .remove = __devexit_p(rtl8139_remove_one),
2591 #ifdef CONFIG_PM
2592 .suspend = rtl8139_suspend,
2593 .resume = rtl8139_resume,
2594 #endif /* CONFIG_PM */
2595 };
2596
2597
2598 static int __init rtl8139_init_module (void)
2599 {
2600 /* when we're a module, we always print a version message,
2601 * even if no 8139 board is found.
2602 */
2603 #ifdef MODULE
2604 pr_info(RTL8139_DRIVER_NAME "\n");
2605 #endif
2606
2607 return pci_register_driver(&rtl8139_pci_driver);
2608 }
2609
2610
2611 static void __exit rtl8139_cleanup_module (void)
2612 {
2613 pci_unregister_driver (&rtl8139_pci_driver);
2614 }
2615
2616
2617 module_init(rtl8139_init_module);
2618 module_exit(rtl8139_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree