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ARM: S3C6410: Declare possible sources of audio-bus2
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / oss / au1550_ac97.c
blobc1070e33b32ff04a7ca3aed2f89f5532fd7ce7b0
1 /*
2 * au1550_ac97.c -- Sound driver for Alchemy Au1550 MIPS Internet Edge
3 * Processor.
4 *
5 * Copyright 2004 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * Mostly copied from the au1000.c driver and some from the
9 * PowerMac dbdma driver.
10 * We assume the processor can do memory coherent DMA.
11 *
12 * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
22 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 */
35
36 #undef DEBUG
37
38 #include <linux/module.h>
39 #include <linux/string.h>
40 #include <linux/ioport.h>
41 #include <linux/sched.h>
42 #include <linux/delay.h>
43 #include <linux/sound.h>
44 #include <linux/slab.h>
45 #include <linux/soundcard.h>
46 #include <linux/init.h>
47 #include <linux/interrupt.h>
48 #include <linux/kernel.h>
49 #include <linux/poll.h>
50 #include <linux/bitops.h>
51 #include <linux/spinlock.h>
52 #include <linux/smp_lock.h>
53 #include <linux/ac97_codec.h>
54 #include <linux/mutex.h>
55
56 #include <asm/io.h>
57 #include <asm/uaccess.h>
58 #include <asm/hardirq.h>
59 #include <asm/mach-au1x00/au1xxx_psc.h>
60 #include <asm/mach-au1x00/au1xxx_dbdma.h>
61 #include <asm/mach-au1x00/au1xxx.h>
62
63 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
64
65 /* misc stuff */
66 #define POLL_COUNT 0x50000
67 #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
68
69 /* The number of DBDMA ring descriptors to allocate. No sense making
70 * this too large....if you can't keep up with a few you aren't likely
71 * to be able to with lots of them, either.
72 */
73 #define NUM_DBDMA_DESCRIPTORS 4
74
75 #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
76
77 /* Boot options
78 * 0 = no VRA, 1 = use VRA if codec supports it
79 */
80 static int vra = 1;
81 module_param(vra, bool, 0);
82 MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
83
84 static struct au1550_state {
85 /* soundcore stuff */
86 int dev_audio;
87
88 struct ac97_codec *codec;
89 unsigned codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
90 unsigned codec_ext_caps; /* AC'97 reg 28h, "Extended Audio ID" */
91 int no_vra; /* do not use VRA */
92
93 spinlock_t lock;
94 struct mutex open_mutex;
95 struct mutex sem;
96 fmode_t open_mode;
97 wait_queue_head_t open_wait;
98
99 struct dmabuf {
100 u32 dmanr;
101 unsigned sample_rate;
102 unsigned src_factor;
103 unsigned sample_size;
104 int num_channels;
105 int dma_bytes_per_sample;
106 int user_bytes_per_sample;
107 int cnt_factor;
108
109 void *rawbuf;
110 unsigned buforder;
111 unsigned numfrag;
112 unsigned fragshift;
113 void *nextIn;
114 void *nextOut;
115 int count;
116 unsigned total_bytes;
117 unsigned error;
118 wait_queue_head_t wait;
119
120 /* redundant, but makes calculations easier */
121 unsigned fragsize;
122 unsigned dma_fragsize;
123 unsigned dmasize;
124 unsigned dma_qcount;
125
126 /* OSS stuff */
127 unsigned mapped:1;
128 unsigned ready:1;
129 unsigned stopped:1;
130 unsigned ossfragshift;
131 int ossmaxfrags;
132 unsigned subdivision;
133 } dma_dac, dma_adc;
134 } au1550_state;
135
136 static unsigned
137 ld2(unsigned int x)
138 {
139 unsigned r = 0;
140
141 if (x >= 0x10000) {
142 x >>= 16;
143 r += 16;
144 }
145 if (x >= 0x100) {
146 x >>= 8;
147 r += 8;
148 }
149 if (x >= 0x10) {
150 x >>= 4;
151 r += 4;
152 }
153 if (x >= 4) {
154 x >>= 2;
155 r += 2;
156 }
157 if (x >= 2)
158 r++;
159 return r;
160 }
161
162 static void
163 au1550_delay(int msec)
164 {
165 unsigned long tmo;
166 signed long tmo2;
167
168 if (in_interrupt())
169 return;
170
171 tmo = jiffies + (msec * HZ) / 1000;
172 for (;;) {
173 tmo2 = tmo - jiffies;
174 if (tmo2 <= 0)
175 break;
176 schedule_timeout(tmo2);
177 }
178 }
179
180 static u16
181 rdcodec(struct ac97_codec *codec, u8 addr)
182 {
183 struct au1550_state *s = (struct au1550_state *)codec->private_data;
184 unsigned long flags;
185 u32 cmd, val;
186 u16 data;
187 int i;
188
189 spin_lock_irqsave(&s->lock, flags);
190
191 for (i = 0; i < POLL_COUNT; i++) {
192 val = au_readl(PSC_AC97STAT);
193 au_sync();
194 if (!(val & PSC_AC97STAT_CP))
195 break;
196 }
197 if (i == POLL_COUNT)
198 err("rdcodec: codec cmd pending expired!");
199
200 cmd = (u32)PSC_AC97CDC_INDX(addr);
201 cmd |= PSC_AC97CDC_RD; /* read command */
202 au_writel(cmd, PSC_AC97CDC);
203 au_sync();
204
205 /* now wait for the data
206 */
207 for (i = 0; i < POLL_COUNT; i++) {
208 val = au_readl(PSC_AC97STAT);
209 au_sync();
210 if (!(val & PSC_AC97STAT_CP))
211 break;
212 }
213 if (i == POLL_COUNT) {
214 err("rdcodec: read poll expired!");
215 data = 0;
216 goto out;
217 }
218
219 /* wait for command done?
220 */
221 for (i = 0; i < POLL_COUNT; i++) {
222 val = au_readl(PSC_AC97EVNT);
223 au_sync();
224 if (val & PSC_AC97EVNT_CD)
225 break;
226 }
227 if (i == POLL_COUNT) {
228 err("rdcodec: read cmdwait expired!");
229 data = 0;
230 goto out;
231 }
232
233 data = au_readl(PSC_AC97CDC) & 0xffff;
234 au_sync();
235
236 /* Clear command done event.
237 */
238 au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
239 au_sync();
240
241 out:
242 spin_unlock_irqrestore(&s->lock, flags);
243
244 return data;
245 }
246
247
248 static void
249 wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
250 {
251 struct au1550_state *s = (struct au1550_state *)codec->private_data;
252 unsigned long flags;
253 u32 cmd, val;
254 int i;
255
256 spin_lock_irqsave(&s->lock, flags);
257
258 for (i = 0; i < POLL_COUNT; i++) {
259 val = au_readl(PSC_AC97STAT);
260 au_sync();
261 if (!(val & PSC_AC97STAT_CP))
262 break;
263 }
264 if (i == POLL_COUNT)
265 err("wrcodec: codec cmd pending expired!");
266
267 cmd = (u32)PSC_AC97CDC_INDX(addr);
268 cmd |= (u32)data;
269 au_writel(cmd, PSC_AC97CDC);
270 au_sync();
271
272 for (i = 0; i < POLL_COUNT; i++) {
273 val = au_readl(PSC_AC97STAT);
274 au_sync();
275 if (!(val & PSC_AC97STAT_CP))
276 break;
277 }
278 if (i == POLL_COUNT)
279 err("wrcodec: codec cmd pending expired!");
280
281 for (i = 0; i < POLL_COUNT; i++) {
282 val = au_readl(PSC_AC97EVNT);
283 au_sync();
284 if (val & PSC_AC97EVNT_CD)
285 break;
286 }
287 if (i == POLL_COUNT)
288 err("wrcodec: read cmdwait expired!");
289
290 /* Clear command done event.
291 */
292 au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
293 au_sync();
294
295 spin_unlock_irqrestore(&s->lock, flags);
296 }
297
298 static void
299 waitcodec(struct ac97_codec *codec)
300 {
301 u16 temp;
302 u32 val;
303 int i;
304
305 /* codec_wait is used to wait for a ready state after
306 * an AC97C_RESET.
307 */
308 au1550_delay(10);
309
310 /* first poll the CODEC_READY tag bit
311 */
312 for (i = 0; i < POLL_COUNT; i++) {
313 val = au_readl(PSC_AC97STAT);
314 au_sync();
315 if (val & PSC_AC97STAT_CR)
316 break;
317 }
318 if (i == POLL_COUNT) {
319 err("waitcodec: CODEC_READY poll expired!");
320 return;
321 }
322
323 /* get AC'97 powerdown control/status register
324 */
325 temp = rdcodec(codec, AC97_POWER_CONTROL);
326
327 /* If anything is powered down, power'em up
328 */
329 if (temp & 0x7f00) {
330 /* Power on
331 */
332 wrcodec(codec, AC97_POWER_CONTROL, 0);
333 au1550_delay(100);
334
335 /* Reread
336 */
337 temp = rdcodec(codec, AC97_POWER_CONTROL);
338 }
339
340 /* Check if Codec REF,ANL,DAC,ADC ready
341 */
342 if ((temp & 0x7f0f) != 0x000f)
343 err("codec reg 26 status (0x%x) not ready!!", temp);
344 }
345
346 /* stop the ADC before calling */
347 static void
348 set_adc_rate(struct au1550_state *s, unsigned rate)
349 {
350 struct dmabuf *adc = &s->dma_adc;
351 struct dmabuf *dac = &s->dma_dac;
352 unsigned adc_rate, dac_rate;
353 u16 ac97_extstat;
354
355 if (s->no_vra) {
356 /* calc SRC factor
357 */
358 adc->src_factor = ((96000 / rate) + 1) >> 1;
359 adc->sample_rate = 48000 / adc->src_factor;
360 return;
361 }
362
363 adc->src_factor = 1;
364
365 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
366
367 rate = rate > 48000 ? 48000 : rate;
368
369 /* enable VRA
370 */
371 wrcodec(s->codec, AC97_EXTENDED_STATUS,
372 ac97_extstat | AC97_EXTSTAT_VRA);
373
374 /* now write the sample rate
375 */
376 wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
377
378 /* read it back for actual supported rate
379 */
380 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
381
382 pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
383
384 /* some codec's don't allow unequal DAC and ADC rates, in which case
385 * writing one rate reg actually changes both.
386 */
387 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
388 if (dac->num_channels > 2)
389 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
390 if (dac->num_channels > 4)
391 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
392
393 adc->sample_rate = adc_rate;
394 dac->sample_rate = dac_rate;
395 }
396
397 /* stop the DAC before calling */
398 static void
399 set_dac_rate(struct au1550_state *s, unsigned rate)
400 {
401 struct dmabuf *dac = &s->dma_dac;
402 struct dmabuf *adc = &s->dma_adc;
403 unsigned adc_rate, dac_rate;
404 u16 ac97_extstat;
405
406 if (s->no_vra) {
407 /* calc SRC factor
408 */
409 dac->src_factor = ((96000 / rate) + 1) >> 1;
410 dac->sample_rate = 48000 / dac->src_factor;
411 return;
412 }
413
414 dac->src_factor = 1;
415
416 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
417
418 rate = rate > 48000 ? 48000 : rate;
419
420 /* enable VRA
421 */
422 wrcodec(s->codec, AC97_EXTENDED_STATUS,
423 ac97_extstat | AC97_EXTSTAT_VRA);
424
425 /* now write the sample rate
426 */
427 wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
428
429 /* I don't support different sample rates for multichannel,
430 * so make these channels the same.
431 */
432 if (dac->num_channels > 2)
433 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
434 if (dac->num_channels > 4)
435 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
436 /* read it back for actual supported rate
437 */
438 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
439
440 pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
441
442 /* some codec's don't allow unequal DAC and ADC rates, in which case
443 * writing one rate reg actually changes both.
444 */
445 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
446
447 dac->sample_rate = dac_rate;
448 adc->sample_rate = adc_rate;
449 }
450
451 static void
452 stop_dac(struct au1550_state *s)
453 {
454 struct dmabuf *db = &s->dma_dac;
455 u32 stat;
456 unsigned long flags;
457
458 if (db->stopped)
459 return;
460
461 spin_lock_irqsave(&s->lock, flags);
462
463 au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
464 au_sync();
465
466 /* Wait for Transmit Busy to show disabled.
467 */
468 do {
469 stat = au_readl(PSC_AC97STAT);
470 au_sync();
471 } while ((stat & PSC_AC97STAT_TB) != 0);
472
473 au1xxx_dbdma_reset(db->dmanr);
474
475 db->stopped = 1;
476
477 spin_unlock_irqrestore(&s->lock, flags);
478 }
479
480 static void
481 stop_adc(struct au1550_state *s)
482 {
483 struct dmabuf *db = &s->dma_adc;
484 unsigned long flags;
485 u32 stat;
486
487 if (db->stopped)
488 return;
489
490 spin_lock_irqsave(&s->lock, flags);
491
492 au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
493 au_sync();
494
495 /* Wait for Receive Busy to show disabled.
496 */
497 do {
498 stat = au_readl(PSC_AC97STAT);
499 au_sync();
500 } while ((stat & PSC_AC97STAT_RB) != 0);
501
502 au1xxx_dbdma_reset(db->dmanr);
503
504 db->stopped = 1;
505
506 spin_unlock_irqrestore(&s->lock, flags);
507 }
508
509
510 static void
511 set_xmit_slots(int num_channels)
512 {
513 u32 ac97_config, stat;
514
515 ac97_config = au_readl(PSC_AC97CFG);
516 au_sync();
517 ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
518 au_writel(ac97_config, PSC_AC97CFG);
519 au_sync();
520
521 switch (num_channels) {
522 case 6: /* stereo with surround and center/LFE,
523 * slots 3,4,6,7,8,9
524 */
525 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
526 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
527
528 case 4: /* stereo with surround, slots 3,4,7,8 */
529 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
530 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
531
532 case 2: /* stereo, slots 3,4 */
533 case 1: /* mono */
534 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
535 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
536 }
537
538 au_writel(ac97_config, PSC_AC97CFG);
539 au_sync();
540
541 ac97_config |= PSC_AC97CFG_DE_ENABLE;
542 au_writel(ac97_config, PSC_AC97CFG);
543 au_sync();
544
545 /* Wait for Device ready.
546 */
547 do {
548 stat = au_readl(PSC_AC97STAT);
549 au_sync();
550 } while ((stat & PSC_AC97STAT_DR) == 0);
551 }
552
553 static void
554 set_recv_slots(int num_channels)
555 {
556 u32 ac97_config, stat;
557
558 ac97_config = au_readl(PSC_AC97CFG);
559 au_sync();
560 ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
561 au_writel(ac97_config, PSC_AC97CFG);
562 au_sync();
563
564 /* Always enable slots 3 and 4 (stereo). Slot 6 is
565 * optional Mic ADC, which we don't support yet.
566 */
567 ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
568 ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
569
570 au_writel(ac97_config, PSC_AC97CFG);
571 au_sync();
572
573 ac97_config |= PSC_AC97CFG_DE_ENABLE;
574 au_writel(ac97_config, PSC_AC97CFG);
575 au_sync();
576
577 /* Wait for Device ready.
578 */
579 do {
580 stat = au_readl(PSC_AC97STAT);
581 au_sync();
582 } while ((stat & PSC_AC97STAT_DR) == 0);
583 }
584
585 /* Hold spinlock for both start_dac() and start_adc() calls */
586 static void
587 start_dac(struct au1550_state *s)
588 {
589 struct dmabuf *db = &s->dma_dac;
590
591 if (!db->stopped)
592 return;
593
594 set_xmit_slots(db->num_channels);
595 au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
596 au_sync();
597 au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
598 au_sync();
599
600 au1xxx_dbdma_start(db->dmanr);
601
602 db->stopped = 0;
603 }
604
605 static void
606 start_adc(struct au1550_state *s)
607 {
608 struct dmabuf *db = &s->dma_adc;
609 int i;
610
611 if (!db->stopped)
612 return;
613
614 /* Put two buffers on the ring to get things started.
615 */
616 for (i=0; i<2; i++) {
617 au1xxx_dbdma_put_dest(db->dmanr, virt_to_phys(db->nextIn),
618 db->dma_fragsize, DDMA_FLAGS_IE);
619
620 db->nextIn += db->dma_fragsize;
621 if (db->nextIn >= db->rawbuf + db->dmasize)
622 db->nextIn -= db->dmasize;
623 }
624
625 set_recv_slots(db->num_channels);
626 au1xxx_dbdma_start(db->dmanr);
627 au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
628 au_sync();
629 au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
630 au_sync();
631
632 db->stopped = 0;
633 }
634
635 static int
636 prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
637 {
638 unsigned user_bytes_per_sec;
639 unsigned bufs;
640 unsigned rate = db->sample_rate;
641
642 if (!db->rawbuf) {
643 db->ready = db->mapped = 0;
644 db->buforder = 5; /* 32 * PAGE_SIZE */
645 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
646 if (!db->rawbuf)
647 return -ENOMEM;
648 }
649
650 db->cnt_factor = 1;
651 if (db->sample_size == 8)
652 db->cnt_factor *= 2;
653 if (db->num_channels == 1)
654 db->cnt_factor *= 2;
655 db->cnt_factor *= db->src_factor;
656
657 db->count = 0;
658 db->dma_qcount = 0;
659 db->nextIn = db->nextOut = db->rawbuf;
660
661 db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
662 db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
663 2 : db->num_channels);
664
665 user_bytes_per_sec = rate * db->user_bytes_per_sample;
666 bufs = PAGE_SIZE << db->buforder;
667 if (db->ossfragshift) {
668 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
669 db->fragshift = ld2(user_bytes_per_sec/1000);
670 else
671 db->fragshift = db->ossfragshift;
672 } else {
673 db->fragshift = ld2(user_bytes_per_sec / 100 /
674 (db->subdivision ? db->subdivision : 1));
675 if (db->fragshift < 3)
676 db->fragshift = 3;
677 }
678
679 db->fragsize = 1 << db->fragshift;
680 db->dma_fragsize = db->fragsize * db->cnt_factor;
681 db->numfrag = bufs / db->dma_fragsize;
682
683 while (db->numfrag < 4 && db->fragshift > 3) {
684 db->fragshift--;
685 db->fragsize = 1 << db->fragshift;
686 db->dma_fragsize = db->fragsize * db->cnt_factor;
687 db->numfrag = bufs / db->dma_fragsize;
688 }
689
690 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
691 db->numfrag = db->ossmaxfrags;
692
693 db->dmasize = db->dma_fragsize * db->numfrag;
694 memset(db->rawbuf, 0, bufs);
695
696 pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
697 rate, db->sample_size, db->num_channels);
698 pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
699 db->fragsize, db->cnt_factor, db->dma_fragsize);
700 pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
701
702 db->ready = 1;
703 return 0;
704 }
705
706 static int
707 prog_dmabuf_adc(struct au1550_state *s)
708 {
709 stop_adc(s);
710 return prog_dmabuf(s, &s->dma_adc);
711
712 }
713
714 static int
715 prog_dmabuf_dac(struct au1550_state *s)
716 {
717 stop_dac(s);
718 return prog_dmabuf(s, &s->dma_dac);
719 }
720
721
722 static void dac_dma_interrupt(int irq, void *dev_id)
723 {
724 struct au1550_state *s = (struct au1550_state *) dev_id;
725 struct dmabuf *db = &s->dma_dac;
726 u32 ac97c_stat;
727
728 spin_lock(&s->lock);
729
730 ac97c_stat = au_readl(PSC_AC97STAT);
731 if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
732 pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
733 db->dma_qcount--;
734
735 if (db->count >= db->fragsize) {
736 if (au1xxx_dbdma_put_source(db->dmanr,
737 virt_to_phys(db->nextOut), db->fragsize,
738 DDMA_FLAGS_IE) == 0) {
739 err("qcount < 2 and no ring room!");
740 }
741 db->nextOut += db->fragsize;
742 if (db->nextOut >= db->rawbuf + db->dmasize)
743 db->nextOut -= db->dmasize;
744 db->count -= db->fragsize;
745 db->total_bytes += db->dma_fragsize;
746 db->dma_qcount++;
747 }
748
749 /* wake up anybody listening */
750 if (waitqueue_active(&db->wait))
751 wake_up(&db->wait);
752
753 spin_unlock(&s->lock);
754 }
755
756
757 static void adc_dma_interrupt(int irq, void *dev_id)
758 {
759 struct au1550_state *s = (struct au1550_state *)dev_id;
760 struct dmabuf *dp = &s->dma_adc;
761 u32 obytes;
762 char *obuf;
763
764 spin_lock(&s->lock);
765
766 /* Pull the buffer from the dma queue.
767 */
768 au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
769
770 if ((dp->count + obytes) > dp->dmasize) {
771 /* Overrun. Stop ADC and log the error
772 */
773 spin_unlock(&s->lock);
774 stop_adc(s);
775 dp->error++;
776 err("adc overrun");
777 return;
778 }
779
780 /* Put a new empty buffer on the destination DMA.
781 */
782 au1xxx_dbdma_put_dest(dp->dmanr, virt_to_phys(dp->nextIn),
783 dp->dma_fragsize, DDMA_FLAGS_IE);
784
785 dp->nextIn += dp->dma_fragsize;
786 if (dp->nextIn >= dp->rawbuf + dp->dmasize)
787 dp->nextIn -= dp->dmasize;
788
789 dp->count += obytes;
790 dp->total_bytes += obytes;
791
792 /* wake up anybody listening
793 */
794 if (waitqueue_active(&dp->wait))
795 wake_up(&dp->wait);
796
797 spin_unlock(&s->lock);
798 }
799
800 static loff_t
801 au1550_llseek(struct file *file, loff_t offset, int origin)
802 {
803 return -ESPIPE;
804 }
805
806
807 static int
808 au1550_open_mixdev(struct inode *inode, struct file *file)
809 {
810 file->private_data = &au1550_state;
811 return 0;
812 }
813
814 static int
815 au1550_release_mixdev(struct inode *inode, struct file *file)
816 {
817 return 0;
818 }
819
820 static int
821 mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
822 unsigned long arg)
823 {
824 return codec->mixer_ioctl(codec, cmd, arg);
825 }
826
827 static int
828 au1550_ioctl_mixdev(struct inode *inode, struct file *file,
829 unsigned int cmd, unsigned long arg)
830 {
831 struct au1550_state *s = (struct au1550_state *)file->private_data;
832 struct ac97_codec *codec = s->codec;
833
834 return mixdev_ioctl(codec, cmd, arg);
835 }
836
837 static /*const */ struct file_operations au1550_mixer_fops = {
838 owner:THIS_MODULE,
839 llseek:au1550_llseek,
840 ioctl:au1550_ioctl_mixdev,
841 open:au1550_open_mixdev,
842 release:au1550_release_mixdev,
843 };
844
845 static int
846 drain_dac(struct au1550_state *s, int nonblock)
847 {
848 unsigned long flags;
849 int count, tmo;
850
851 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
852 return 0;
853
854 for (;;) {
855 spin_lock_irqsave(&s->lock, flags);
856 count = s->dma_dac.count;
857 spin_unlock_irqrestore(&s->lock, flags);
858 if (count <= s->dma_dac.fragsize)
859 break;
860 if (signal_pending(current))
861 break;
862 if (nonblock)
863 return -EBUSY;
864 tmo = 1000 * count / (s->no_vra ?
865 48000 : s->dma_dac.sample_rate);
866 tmo /= s->dma_dac.dma_bytes_per_sample;
867 au1550_delay(tmo);
868 }
869 if (signal_pending(current))
870 return -ERESTARTSYS;
871 return 0;
872 }
873
874 static inline u8 S16_TO_U8(s16 ch)
875 {
876 return (u8) (ch >> 8) + 0x80;
877 }
878 static inline s16 U8_TO_S16(u8 ch)
879 {
880 return (s16) (ch - 0x80) << 8;
881 }
882
883 /*
884 * Translates user samples to dma buffer suitable for AC'97 DAC data:
885 * If mono, copy left channel to right channel in dma buffer.
886 * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
887 * If interpolating (no VRA), duplicate every audio frame src_factor times.
888 */
889 static int
890 translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
891 int dmacount)
892 {
893 int sample, i;
894 int interp_bytes_per_sample;
895 int num_samples;
896 int mono = (db->num_channels == 1);
897 char usersample[12];
898 s16 ch, dmasample[6];
899
900 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
901 /* no translation necessary, just copy
902 */
903 if (copy_from_user(dmabuf, userbuf, dmacount))
904 return -EFAULT;
905 return dmacount;
906 }
907
908 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
909 num_samples = dmacount / interp_bytes_per_sample;
910
911 for (sample = 0; sample < num_samples; sample++) {
912 if (copy_from_user(usersample, userbuf,
913 db->user_bytes_per_sample)) {
914 return -EFAULT;
915 }
916
917 for (i = 0; i < db->num_channels; i++) {
918 if (db->sample_size == 8)
919 ch = U8_TO_S16(usersample[i]);
920 else
921 ch = *((s16 *) (&usersample[i * 2]));
922 dmasample[i] = ch;
923 if (mono)
924 dmasample[i + 1] = ch; /* right channel */
925 }
926
927 /* duplicate every audio frame src_factor times
928 */
929 for (i = 0; i < db->src_factor; i++)
930 memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
931
932 userbuf += db->user_bytes_per_sample;
933 dmabuf += interp_bytes_per_sample;
934 }
935
936 return num_samples * interp_bytes_per_sample;
937 }
938
939 /*
940 * Translates AC'97 ADC samples to user buffer:
941 * If mono, send only left channel to user buffer.
942 * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
943 * If decimating (no VRA), skip over src_factor audio frames.
944 */
945 static int
946 translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
947 int dmacount)
948 {
949 int sample, i;
950 int interp_bytes_per_sample;
951 int num_samples;
952 int mono = (db->num_channels == 1);
953 char usersample[12];
954
955 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
956 /* no translation necessary, just copy
957 */
958 if (copy_to_user(userbuf, dmabuf, dmacount))
959 return -EFAULT;
960 return dmacount;
961 }
962
963 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
964 num_samples = dmacount / interp_bytes_per_sample;
965
966 for (sample = 0; sample < num_samples; sample++) {
967 for (i = 0; i < db->num_channels; i++) {
968 if (db->sample_size == 8)
969 usersample[i] =
970 S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
971 else
972 *((s16 *) (&usersample[i * 2])) =
973 *((s16 *) (&dmabuf[i * 2]));
974 }
975
976 if (copy_to_user(userbuf, usersample,
977 db->user_bytes_per_sample)) {
978 return -EFAULT;
979 }
980
981 userbuf += db->user_bytes_per_sample;
982 dmabuf += interp_bytes_per_sample;
983 }
984
985 return num_samples * interp_bytes_per_sample;
986 }
987
988 /*
989 * Copy audio data to/from user buffer from/to dma buffer, taking care
990 * that we wrap when reading/writing the dma buffer. Returns actual byte
991 * count written to or read from the dma buffer.
992 */
993 static int
994 copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
995 {
996 char *bufptr = to_user ? db->nextOut : db->nextIn;
997 char *bufend = db->rawbuf + db->dmasize;
998 int cnt, ret;
999
1000 if (bufptr + count > bufend) {
1001 int partial = (int) (bufend - bufptr);
1002 if (to_user) {
1003 if ((cnt = translate_to_user(db, userbuf,
1004 bufptr, partial)) < 0)
1005 return cnt;
1006 ret = cnt;
1007 if ((cnt = translate_to_user(db, userbuf + partial,
1008 db->rawbuf,
1009 count - partial)) < 0)
1010 return cnt;
1011 ret += cnt;
1012 } else {
1013 if ((cnt = translate_from_user(db, bufptr, userbuf,
1014 partial)) < 0)
1015 return cnt;
1016 ret = cnt;
1017 if ((cnt = translate_from_user(db, db->rawbuf,
1018 userbuf + partial,
1019 count - partial)) < 0)
1020 return cnt;
1021 ret += cnt;
1022 }
1023 } else {
1024 if (to_user)
1025 ret = translate_to_user(db, userbuf, bufptr, count);
1026 else
1027 ret = translate_from_user(db, bufptr, userbuf, count);
1028 }
1029
1030 return ret;
1031 }
1032
1033
1034 static ssize_t
1035 au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1036 {
1037 struct au1550_state *s = (struct au1550_state *)file->private_data;
1038 struct dmabuf *db = &s->dma_adc;
1039 DECLARE_WAITQUEUE(wait, current);
1040 ssize_t ret;
1041 unsigned long flags;
1042 int cnt, usercnt, avail;
1043
1044 if (db->mapped)
1045 return -ENXIO;
1046 if (!access_ok(VERIFY_WRITE, buffer, count))
1047 return -EFAULT;
1048 ret = 0;
1049
1050 count *= db->cnt_factor;
1051
1052 mutex_lock(&s->sem);
1053 add_wait_queue(&db->wait, &wait);
1054
1055 while (count > 0) {
1056 /* wait for samples in ADC dma buffer
1057 */
1058 do {
1059 spin_lock_irqsave(&s->lock, flags);
1060 if (db->stopped)
1061 start_adc(s);
1062 avail = db->count;
1063 if (avail <= 0)
1064 __set_current_state(TASK_INTERRUPTIBLE);
1065 spin_unlock_irqrestore(&s->lock, flags);
1066 if (avail <= 0) {
1067 if (file->f_flags & O_NONBLOCK) {
1068 if (!ret)
1069 ret = -EAGAIN;
1070 goto out;
1071 }
1072 mutex_unlock(&s->sem);
1073 schedule();
1074 if (signal_pending(current)) {
1075 if (!ret)
1076 ret = -ERESTARTSYS;
1077 goto out2;
1078 }
1079 mutex_lock(&s->sem);
1080 }
1081 } while (avail <= 0);
1082
1083 /* copy from nextOut to user
1084 */
1085 if ((cnt = copy_dmabuf_user(db, buffer,
1086 count > avail ?
1087 avail : count, 1)) < 0) {
1088 if (!ret)
1089 ret = -EFAULT;
1090 goto out;
1091 }
1092
1093 spin_lock_irqsave(&s->lock, flags);
1094 db->count -= cnt;
1095 db->nextOut += cnt;
1096 if (db->nextOut >= db->rawbuf + db->dmasize)
1097 db->nextOut -= db->dmasize;
1098 spin_unlock_irqrestore(&s->lock, flags);
1099
1100 count -= cnt;
1101 usercnt = cnt / db->cnt_factor;
1102 buffer += usercnt;
1103 ret += usercnt;
1104 } /* while (count > 0) */
1105
1106 out:
1107 mutex_unlock(&s->sem);
1108 out2:
1109 remove_wait_queue(&db->wait, &wait);
1110 set_current_state(TASK_RUNNING);
1111 return ret;
1112 }
1113
1114 static ssize_t
1115 au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
1116 {
1117 struct au1550_state *s = (struct au1550_state *)file->private_data;
1118 struct dmabuf *db = &s->dma_dac;
1119 DECLARE_WAITQUEUE(wait, current);
1120 ssize_t ret = 0;
1121 unsigned long flags;
1122 int cnt, usercnt, avail;
1123
1124 pr_debug("write: count=%d\n", count);
1125
1126 if (db->mapped)
1127 return -ENXIO;
1128 if (!access_ok(VERIFY_READ, buffer, count))
1129 return -EFAULT;
1130
1131 count *= db->cnt_factor;
1132
1133 mutex_lock(&s->sem);
1134 add_wait_queue(&db->wait, &wait);
1135
1136 while (count > 0) {
1137 /* wait for space in playback buffer
1138 */
1139 do {
1140 spin_lock_irqsave(&s->lock, flags);
1141 avail = (int) db->dmasize - db->count;
1142 if (avail <= 0)
1143 __set_current_state(TASK_INTERRUPTIBLE);
1144 spin_unlock_irqrestore(&s->lock, flags);
1145 if (avail <= 0) {
1146 if (file->f_flags & O_NONBLOCK) {
1147 if (!ret)
1148 ret = -EAGAIN;
1149 goto out;
1150 }
1151 mutex_unlock(&s->sem);
1152 schedule();
1153 if (signal_pending(current)) {
1154 if (!ret)
1155 ret = -ERESTARTSYS;
1156 goto out2;
1157 }
1158 mutex_lock(&s->sem);
1159 }
1160 } while (avail <= 0);
1161
1162 /* copy from user to nextIn
1163 */
1164 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1165 count > avail ?
1166 avail : count, 0)) < 0) {
1167 if (!ret)
1168 ret = -EFAULT;
1169 goto out;
1170 }
1171
1172 spin_lock_irqsave(&s->lock, flags);
1173 db->count += cnt;
1174 db->nextIn += cnt;
1175 if (db->nextIn >= db->rawbuf + db->dmasize)
1176 db->nextIn -= db->dmasize;
1177
1178 /* If the data is available, we want to keep two buffers
1179 * on the dma queue. If the queue count reaches zero,
1180 * we know the dma has stopped.
1181 */
1182 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
1183 if (au1xxx_dbdma_put_source(db->dmanr,
1184 virt_to_phys(db->nextOut), db->fragsize,
1185 DDMA_FLAGS_IE) == 0) {
1186 err("qcount < 2 and no ring room!");
1187 }
1188 db->nextOut += db->fragsize;
1189 if (db->nextOut >= db->rawbuf + db->dmasize)
1190 db->nextOut -= db->dmasize;
1191 db->total_bytes += db->dma_fragsize;
1192 if (db->dma_qcount == 0)
1193 start_dac(s);
1194 db->dma_qcount++;
1195 }
1196 spin_unlock_irqrestore(&s->lock, flags);
1197
1198 count -= cnt;
1199 usercnt = cnt / db->cnt_factor;
1200 buffer += usercnt;
1201 ret += usercnt;
1202 } /* while (count > 0) */
1203
1204 out:
1205 mutex_unlock(&s->sem);
1206 out2:
1207 remove_wait_queue(&db->wait, &wait);
1208 set_current_state(TASK_RUNNING);
1209 return ret;
1210 }
1211
1212
1213 /* No kernel lock - we have our own spinlock */
1214 static unsigned int
1215 au1550_poll(struct file *file, struct poll_table_struct *wait)
1216 {
1217 struct au1550_state *s = (struct au1550_state *)file->private_data;
1218 unsigned long flags;
1219 unsigned int mask = 0;
1220
1221 if (file->f_mode & FMODE_WRITE) {
1222 if (!s->dma_dac.ready)
1223 return 0;
1224 poll_wait(file, &s->dma_dac.wait, wait);
1225 }
1226 if (file->f_mode & FMODE_READ) {
1227 if (!s->dma_adc.ready)
1228 return 0;
1229 poll_wait(file, &s->dma_adc.wait, wait);
1230 }
1231
1232 spin_lock_irqsave(&s->lock, flags);
1233
1234 if (file->f_mode & FMODE_READ) {
1235 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1236 mask |= POLLIN | POLLRDNORM;
1237 }
1238 if (file->f_mode & FMODE_WRITE) {
1239 if (s->dma_dac.mapped) {
1240 if (s->dma_dac.count >=
1241 (signed)s->dma_dac.dma_fragsize)
1242 mask |= POLLOUT | POLLWRNORM;
1243 } else {
1244 if ((signed) s->dma_dac.dmasize >=
1245 s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1246 mask |= POLLOUT | POLLWRNORM;
1247 }
1248 }
1249 spin_unlock_irqrestore(&s->lock, flags);
1250 return mask;
1251 }
1252
1253 static int
1254 au1550_mmap(struct file *file, struct vm_area_struct *vma)
1255 {
1256 struct au1550_state *s = (struct au1550_state *)file->private_data;
1257 struct dmabuf *db;
1258 unsigned long size;
1259 int ret = 0;
1260
1261 lock_kernel();
1262 mutex_lock(&s->sem);
1263 if (vma->vm_flags & VM_WRITE)
1264 db = &s->dma_dac;
1265 else if (vma->vm_flags & VM_READ)
1266 db = &s->dma_adc;
1267 else {
1268 ret = -EINVAL;
1269 goto out;
1270 }
1271 if (vma->vm_pgoff != 0) {
1272 ret = -EINVAL;
1273 goto out;
1274 }
1275 size = vma->vm_end - vma->vm_start;
1276 if (size > (PAGE_SIZE << db->buforder)) {
1277 ret = -EINVAL;
1278 goto out;
1279 }
1280 if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
1281 size, vma->vm_page_prot)) {
1282 ret = -EAGAIN;
1283 goto out;
1284 }
1285 vma->vm_flags &= ~VM_IO;
1286 db->mapped = 1;
1287 out:
1288 mutex_unlock(&s->sem);
1289 unlock_kernel();
1290 return ret;
1291 }
1292
1293 #ifdef DEBUG
1294 static struct ioctl_str_t {
1295 unsigned int cmd;
1296 const char *str;
1297 } ioctl_str[] = {
1298 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1299 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1300 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1301 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1302 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1303 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1304 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1305 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1306 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1307 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1308 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1309 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1310 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1311 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1312 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1313 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1314 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1315 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1316 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1317 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1318 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1319 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1320 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1321 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1322 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1323 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1324 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1325 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1326 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1327 {OSS_GETVERSION, "OSS_GETVERSION"},
1328 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1329 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1330 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1331 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1332 };
1333 #endif
1334
1335 static int
1336 dma_count_done(struct dmabuf *db)
1337 {
1338 if (db->stopped)
1339 return 0;
1340
1341 return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1342 }
1343
1344
1345 static int
1346 au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
1347 unsigned long arg)
1348 {
1349 struct au1550_state *s = (struct au1550_state *)file->private_data;
1350 unsigned long flags;
1351 audio_buf_info abinfo;
1352 count_info cinfo;
1353 int count;
1354 int val, mapped, ret, diff;
1355
1356 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1357 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1358
1359 #ifdef DEBUG
1360 for (count = 0; count < ARRAY_SIZE(ioctl_str); count++) {
1361 if (ioctl_str[count].cmd == cmd)
1362 break;
1363 }
1364 if (count < ARRAY_SIZE(ioctl_str))
1365 pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
1366 else
1367 pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
1368 #endif
1369
1370 switch (cmd) {
1371 case OSS_GETVERSION:
1372 return put_user(SOUND_VERSION, (int *) arg);
1373
1374 case SNDCTL_DSP_SYNC:
1375 if (file->f_mode & FMODE_WRITE)
1376 return drain_dac(s, file->f_flags & O_NONBLOCK);
1377 return 0;
1378
1379 case SNDCTL_DSP_SETDUPLEX:
1380 return 0;
1381
1382 case SNDCTL_DSP_GETCAPS:
1383 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1384 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1385
1386 case SNDCTL_DSP_RESET:
1387 if (file->f_mode & FMODE_WRITE) {
1388 stop_dac(s);
1389 synchronize_irq();
1390 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1391 s->dma_dac.nextIn = s->dma_dac.nextOut =
1392 s->dma_dac.rawbuf;
1393 }
1394 if (file->f_mode & FMODE_READ) {
1395 stop_adc(s);
1396 synchronize_irq();
1397 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1398 s->dma_adc.nextIn = s->dma_adc.nextOut =
1399 s->dma_adc.rawbuf;
1400 }
1401 return 0;
1402
1403 case SNDCTL_DSP_SPEED:
1404 if (get_user(val, (int *) arg))
1405 return -EFAULT;
1406 if (val >= 0) {
1407 if (file->f_mode & FMODE_READ) {
1408 stop_adc(s);
1409 set_adc_rate(s, val);
1410 }
1411 if (file->f_mode & FMODE_WRITE) {
1412 stop_dac(s);
1413 set_dac_rate(s, val);
1414 }
1415 if (s->open_mode & FMODE_READ)
1416 if ((ret = prog_dmabuf_adc(s)))
1417 return ret;
1418 if (s->open_mode & FMODE_WRITE)
1419 if ((ret = prog_dmabuf_dac(s)))
1420 return ret;
1421 }
1422 return put_user((file->f_mode & FMODE_READ) ?
1423 s->dma_adc.sample_rate :
1424 s->dma_dac.sample_rate,
1425 (int *)arg);
1426
1427 case SNDCTL_DSP_STEREO:
1428 if (get_user(val, (int *) arg))
1429 return -EFAULT;
1430 if (file->f_mode & FMODE_READ) {
1431 stop_adc(s);
1432 s->dma_adc.num_channels = val ? 2 : 1;
1433 if ((ret = prog_dmabuf_adc(s)))
1434 return ret;
1435 }
1436 if (file->f_mode & FMODE_WRITE) {
1437 stop_dac(s);
1438 s->dma_dac.num_channels = val ? 2 : 1;
1439 if (s->codec_ext_caps & AC97_EXT_DACS) {
1440 /* disable surround and center/lfe in AC'97
1441 */
1442 u16 ext_stat = rdcodec(s->codec,
1443 AC97_EXTENDED_STATUS);
1444 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1445 ext_stat | (AC97_EXTSTAT_PRI |
1446 AC97_EXTSTAT_PRJ |
1447 AC97_EXTSTAT_PRK));
1448 }
1449 if ((ret = prog_dmabuf_dac(s)))
1450 return ret;
1451 }
1452 return 0;
1453
1454 case SNDCTL_DSP_CHANNELS:
1455 if (get_user(val, (int *) arg))
1456 return -EFAULT;
1457 if (val != 0) {
1458 if (file->f_mode & FMODE_READ) {
1459 if (val < 0 || val > 2)
1460 return -EINVAL;
1461 stop_adc(s);
1462 s->dma_adc.num_channels = val;
1463 if ((ret = prog_dmabuf_adc(s)))
1464 return ret;
1465 }
1466 if (file->f_mode & FMODE_WRITE) {
1467 switch (val) {
1468 case 1:
1469 case 2:
1470 break;
1471 case 3:
1472 case 5:
1473 return -EINVAL;
1474 case 4:
1475 if (!(s->codec_ext_caps &
1476 AC97_EXTID_SDAC))
1477 return -EINVAL;
1478 break;
1479 case 6:
1480 if ((s->codec_ext_caps &
1481 AC97_EXT_DACS) != AC97_EXT_DACS)
1482 return -EINVAL;
1483 break;
1484 default:
1485 return -EINVAL;
1486 }
1487
1488 stop_dac(s);
1489 if (val <= 2 &&
1490 (s->codec_ext_caps & AC97_EXT_DACS)) {
1491 /* disable surround and center/lfe
1492 * channels in AC'97
1493 */
1494 u16 ext_stat =
1495 rdcodec(s->codec,
1496 AC97_EXTENDED_STATUS);
1497 wrcodec(s->codec,
1498 AC97_EXTENDED_STATUS,
1499 ext_stat | (AC97_EXTSTAT_PRI |
1500 AC97_EXTSTAT_PRJ |
1501 AC97_EXTSTAT_PRK));
1502 } else if (val >= 4) {
1503 /* enable surround, center/lfe
1504 * channels in AC'97
1505 */
1506 u16 ext_stat =
1507 rdcodec(s->codec,
1508 AC97_EXTENDED_STATUS);
1509 ext_stat &= ~AC97_EXTSTAT_PRJ;
1510 if (val == 6)
1511 ext_stat &=
1512 ~(AC97_EXTSTAT_PRI |
1513 AC97_EXTSTAT_PRK);
1514 wrcodec(s->codec,
1515 AC97_EXTENDED_STATUS,
1516 ext_stat);
1517 }
1518
1519 s->dma_dac.num_channels = val;
1520 if ((ret = prog_dmabuf_dac(s)))
1521 return ret;
1522 }
1523 }
1524 return put_user(val, (int *) arg);
1525
1526 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1527 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1528
1529 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1530 if (get_user(val, (int *) arg))
1531 return -EFAULT;
1532 if (val != AFMT_QUERY) {
1533 if (file->f_mode & FMODE_READ) {
1534 stop_adc(s);
1535 if (val == AFMT_S16_LE)
1536 s->dma_adc.sample_size = 16;
1537 else {
1538 val = AFMT_U8;
1539 s->dma_adc.sample_size = 8;
1540 }
1541 if ((ret = prog_dmabuf_adc(s)))
1542 return ret;
1543 }
1544 if (file->f_mode & FMODE_WRITE) {
1545 stop_dac(s);
1546 if (val == AFMT_S16_LE)
1547 s->dma_dac.sample_size = 16;
1548 else {
1549 val = AFMT_U8;
1550 s->dma_dac.sample_size = 8;
1551 }
1552 if ((ret = prog_dmabuf_dac(s)))
1553 return ret;
1554 }
1555 } else {
1556 if (file->f_mode & FMODE_READ)
1557 val = (s->dma_adc.sample_size == 16) ?
1558 AFMT_S16_LE : AFMT_U8;
1559 else
1560 val = (s->dma_dac.sample_size == 16) ?
1561 AFMT_S16_LE : AFMT_U8;
1562 }
1563 return put_user(val, (int *) arg);
1564
1565 case SNDCTL_DSP_POST:
1566 return 0;
1567
1568 case SNDCTL_DSP_GETTRIGGER:
1569 val = 0;
1570 spin_lock_irqsave(&s->lock, flags);
1571 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1572 val |= PCM_ENABLE_INPUT;
1573 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1574 val |= PCM_ENABLE_OUTPUT;
1575 spin_unlock_irqrestore(&s->lock, flags);
1576 return put_user(val, (int *) arg);
1577
1578 case SNDCTL_DSP_SETTRIGGER:
1579 if (get_user(val, (int *) arg))
1580 return -EFAULT;
1581 if (file->f_mode & FMODE_READ) {
1582 if (val & PCM_ENABLE_INPUT) {
1583 spin_lock_irqsave(&s->lock, flags);
1584 start_adc(s);
1585 spin_unlock_irqrestore(&s->lock, flags);
1586 } else
1587 stop_adc(s);
1588 }
1589 if (file->f_mode & FMODE_WRITE) {
1590 if (val & PCM_ENABLE_OUTPUT) {
1591 spin_lock_irqsave(&s->lock, flags);
1592 start_dac(s);
1593 spin_unlock_irqrestore(&s->lock, flags);
1594 } else
1595 stop_dac(s);
1596 }
1597 return 0;
1598
1599 case SNDCTL_DSP_GETOSPACE:
1600 if (!(file->f_mode & FMODE_WRITE))
1601 return -EINVAL;
1602 abinfo.fragsize = s->dma_dac.fragsize;
1603 spin_lock_irqsave(&s->lock, flags);
1604 count = s->dma_dac.count;
1605 count -= dma_count_done(&s->dma_dac);
1606 spin_unlock_irqrestore(&s->lock, flags);
1607 if (count < 0)
1608 count = 0;
1609 abinfo.bytes = (s->dma_dac.dmasize - count) /
1610 s->dma_dac.cnt_factor;
1611 abinfo.fragstotal = s->dma_dac.numfrag;
1612 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1613 pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
1614 return copy_to_user((void *) arg, &abinfo,
1615 sizeof(abinfo)) ? -EFAULT : 0;
1616
1617 case SNDCTL_DSP_GETISPACE:
1618 if (!(file->f_mode & FMODE_READ))
1619 return -EINVAL;
1620 abinfo.fragsize = s->dma_adc.fragsize;
1621 spin_lock_irqsave(&s->lock, flags);
1622 count = s->dma_adc.count;
1623 count += dma_count_done(&s->dma_adc);
1624 spin_unlock_irqrestore(&s->lock, flags);
1625 if (count < 0)
1626 count = 0;
1627 abinfo.bytes = count / s->dma_adc.cnt_factor;
1628 abinfo.fragstotal = s->dma_adc.numfrag;
1629 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1630 return copy_to_user((void *) arg, &abinfo,
1631 sizeof(abinfo)) ? -EFAULT : 0;
1632
1633 case SNDCTL_DSP_NONBLOCK:
1634 spin_lock(&file->f_lock);
1635 file->f_flags |= O_NONBLOCK;
1636 spin_unlock(&file->f_lock);
1637 return 0;
1638
1639 case SNDCTL_DSP_GETODELAY:
1640 if (!(file->f_mode & FMODE_WRITE))
1641 return -EINVAL;
1642 spin_lock_irqsave(&s->lock, flags);
1643 count = s->dma_dac.count;
1644 count -= dma_count_done(&s->dma_dac);
1645 spin_unlock_irqrestore(&s->lock, flags);
1646 if (count < 0)
1647 count = 0;
1648 count /= s->dma_dac.cnt_factor;
1649 return put_user(count, (int *) arg);
1650
1651 case SNDCTL_DSP_GETIPTR:
1652 if (!(file->f_mode & FMODE_READ))
1653 return -EINVAL;
1654 spin_lock_irqsave(&s->lock, flags);
1655 cinfo.bytes = s->dma_adc.total_bytes;
1656 count = s->dma_adc.count;
1657 if (!s->dma_adc.stopped) {
1658 diff = dma_count_done(&s->dma_adc);
1659 count += diff;
1660 cinfo.bytes += diff;
1661 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
1662 virt_to_phys(s->dma_adc.rawbuf);
1663 } else
1664 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1665 virt_to_phys(s->dma_adc.rawbuf);
1666 if (s->dma_adc.mapped)
1667 s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1668 spin_unlock_irqrestore(&s->lock, flags);
1669 if (count < 0)
1670 count = 0;
1671 cinfo.blocks = count >> s->dma_adc.fragshift;
1672 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1673
1674 case SNDCTL_DSP_GETOPTR:
1675 if (!(file->f_mode & FMODE_READ))
1676 return -EINVAL;
1677 spin_lock_irqsave(&s->lock, flags);
1678 cinfo.bytes = s->dma_dac.total_bytes;
1679 count = s->dma_dac.count;
1680 if (!s->dma_dac.stopped) {
1681 diff = dma_count_done(&s->dma_dac);
1682 count -= diff;
1683 cinfo.bytes += diff;
1684 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1685 virt_to_phys(s->dma_dac.rawbuf);
1686 } else
1687 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1688 virt_to_phys(s->dma_dac.rawbuf);
1689 if (s->dma_dac.mapped)
1690 s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1691 spin_unlock_irqrestore(&s->lock, flags);
1692 if (count < 0)
1693 count = 0;
1694 cinfo.blocks = count >> s->dma_dac.fragshift;
1695 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1696
1697 case SNDCTL_DSP_GETBLKSIZE:
1698 if (file->f_mode & FMODE_WRITE)
1699 return put_user(s->dma_dac.fragsize, (int *) arg);
1700 else
1701 return put_user(s->dma_adc.fragsize, (int *) arg);
1702
1703 case SNDCTL_DSP_SETFRAGMENT:
1704 if (get_user(val, (int *) arg))
1705 return -EFAULT;
1706 if (file->f_mode & FMODE_READ) {
1707 stop_adc(s);
1708 s->dma_adc.ossfragshift = val & 0xffff;
1709 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1710 if (s->dma_adc.ossfragshift < 4)
1711 s->dma_adc.ossfragshift = 4;
1712 if (s->dma_adc.ossfragshift > 15)
1713 s->dma_adc.ossfragshift = 15;
1714 if (s->dma_adc.ossmaxfrags < 4)
1715 s->dma_adc.ossmaxfrags = 4;
1716 if ((ret = prog_dmabuf_adc(s)))
1717 return ret;
1718 }
1719 if (file->f_mode & FMODE_WRITE) {
1720 stop_dac(s);
1721 s->dma_dac.ossfragshift = val & 0xffff;
1722 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1723 if (s->dma_dac.ossfragshift < 4)
1724 s->dma_dac.ossfragshift = 4;
1725 if (s->dma_dac.ossfragshift > 15)
1726 s->dma_dac.ossfragshift = 15;
1727 if (s->dma_dac.ossmaxfrags < 4)
1728 s->dma_dac.ossmaxfrags = 4;
1729 if ((ret = prog_dmabuf_dac(s)))
1730 return ret;
1731 }
1732 return 0;
1733
1734 case SNDCTL_DSP_SUBDIVIDE:
1735 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1736 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1737 return -EINVAL;
1738 if (get_user(val, (int *) arg))
1739 return -EFAULT;
1740 if (val != 1 && val != 2 && val != 4)
1741 return -EINVAL;
1742 if (file->f_mode & FMODE_READ) {
1743 stop_adc(s);
1744 s->dma_adc.subdivision = val;
1745 if ((ret = prog_dmabuf_adc(s)))
1746 return ret;
1747 }
1748 if (file->f_mode & FMODE_WRITE) {
1749 stop_dac(s);
1750 s->dma_dac.subdivision = val;
1751 if ((ret = prog_dmabuf_dac(s)))
1752 return ret;
1753 }
1754 return 0;
1755
1756 case SOUND_PCM_READ_RATE:
1757 return put_user((file->f_mode & FMODE_READ) ?
1758 s->dma_adc.sample_rate :
1759 s->dma_dac.sample_rate,
1760 (int *)arg);
1761
1762 case SOUND_PCM_READ_CHANNELS:
1763 if (file->f_mode & FMODE_READ)
1764 return put_user(s->dma_adc.num_channels, (int *)arg);
1765 else
1766 return put_user(s->dma_dac.num_channels, (int *)arg);
1767
1768 case SOUND_PCM_READ_BITS:
1769 if (file->f_mode & FMODE_READ)
1770 return put_user(s->dma_adc.sample_size, (int *)arg);
1771 else
1772 return put_user(s->dma_dac.sample_size, (int *)arg);
1773
1774 case SOUND_PCM_WRITE_FILTER:
1775 case SNDCTL_DSP_SETSYNCRO:
1776 case SOUND_PCM_READ_FILTER:
1777 return -EINVAL;
1778 }
1779
1780 return mixdev_ioctl(s->codec, cmd, arg);
1781 }
1782
1783
1784 static int
1785 au1550_open(struct inode *inode, struct file *file)
1786 {
1787 int minor = MINOR(inode->i_rdev);
1788 DECLARE_WAITQUEUE(wait, current);
1789 struct au1550_state *s = &au1550_state;
1790 int ret;
1791
1792 #ifdef DEBUG
1793 if (file->f_flags & O_NONBLOCK)
1794 pr_debug("open: non-blocking\n");
1795 else
1796 pr_debug("open: blocking\n");
1797 #endif
1798
1799 file->private_data = s;
1800 /* wait for device to become free */
1801 mutex_lock(&s->open_mutex);
1802 while (s->open_mode & file->f_mode) {
1803 if (file->f_flags & O_NONBLOCK) {
1804 mutex_unlock(&s->open_mutex);
1805 return -EBUSY;
1806 }
1807 add_wait_queue(&s->open_wait, &wait);
1808 __set_current_state(TASK_INTERRUPTIBLE);
1809 mutex_unlock(&s->open_mutex);
1810 schedule();
1811 remove_wait_queue(&s->open_wait, &wait);
1812 set_current_state(TASK_RUNNING);
1813 if (signal_pending(current))
1814 return -ERESTARTSYS;
1815 mutex_lock(&s->open_mutex);
1816 }
1817
1818 stop_dac(s);
1819 stop_adc(s);
1820
1821 if (file->f_mode & FMODE_READ) {
1822 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1823 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1824 s->dma_adc.num_channels = 1;
1825 s->dma_adc.sample_size = 8;
1826 set_adc_rate(s, 8000);
1827 if ((minor & 0xf) == SND_DEV_DSP16)
1828 s->dma_adc.sample_size = 16;
1829 }
1830
1831 if (file->f_mode & FMODE_WRITE) {
1832 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1833 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1834 s->dma_dac.num_channels = 1;
1835 s->dma_dac.sample_size = 8;
1836 set_dac_rate(s, 8000);
1837 if ((minor & 0xf) == SND_DEV_DSP16)
1838 s->dma_dac.sample_size = 16;
1839 }
1840
1841 if (file->f_mode & FMODE_READ) {
1842 if ((ret = prog_dmabuf_adc(s)))
1843 return ret;
1844 }
1845 if (file->f_mode & FMODE_WRITE) {
1846 if ((ret = prog_dmabuf_dac(s)))
1847 return ret;
1848 }
1849
1850 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1851 mutex_unlock(&s->open_mutex);
1852 mutex_init(&s->sem);
1853 return 0;
1854 }
1855
1856 static int
1857 au1550_release(struct inode *inode, struct file *file)
1858 {
1859 struct au1550_state *s = (struct au1550_state *)file->private_data;
1860
1861 lock_kernel();
1862
1863 if (file->f_mode & FMODE_WRITE) {
1864 unlock_kernel();
1865 drain_dac(s, file->f_flags & O_NONBLOCK);
1866 lock_kernel();
1867 }
1868
1869 mutex_lock(&s->open_mutex);
1870 if (file->f_mode & FMODE_WRITE) {
1871 stop_dac(s);
1872 kfree(s->dma_dac.rawbuf);
1873 s->dma_dac.rawbuf = NULL;
1874 }
1875 if (file->f_mode & FMODE_READ) {
1876 stop_adc(s);
1877 kfree(s->dma_adc.rawbuf);
1878 s->dma_adc.rawbuf = NULL;
1879 }
1880 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1881 mutex_unlock(&s->open_mutex);
1882 wake_up(&s->open_wait);
1883 unlock_kernel();
1884 return 0;
1885 }
1886
1887 static /*const */ struct file_operations au1550_audio_fops = {
1888 owner: THIS_MODULE,
1889 llseek: au1550_llseek,
1890 read: au1550_read,
1891 write: au1550_write,
1892 poll: au1550_poll,
1893 ioctl: au1550_ioctl,
1894 mmap: au1550_mmap,
1895 open: au1550_open,
1896 release: au1550_release,
1897 };
1898
1899 MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
1900 MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
1901 MODULE_LICENSE("GPL");
1902
1903
1904 static int __devinit
1905 au1550_probe(void)
1906 {
1907 struct au1550_state *s = &au1550_state;
1908 int val;
1909
1910 memset(s, 0, sizeof(struct au1550_state));
1911
1912 init_waitqueue_head(&s->dma_adc.wait);
1913 init_waitqueue_head(&s->dma_dac.wait);
1914 init_waitqueue_head(&s->open_wait);
1915 mutex_init(&s->open_mutex);
1916 spin_lock_init(&s->lock);
1917
1918 s->codec = ac97_alloc_codec();
1919 if(s->codec == NULL) {
1920 err("Out of memory");
1921 return -1;
1922 }
1923 s->codec->private_data = s;
1924 s->codec->id = 0;
1925 s->codec->codec_read = rdcodec;
1926 s->codec->codec_write = wrcodec;
1927 s->codec->codec_wait = waitcodec;
1928
1929 if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
1930 0x30, "Au1550 AC97")) {
1931 err("AC'97 ports in use");
1932 }
1933
1934 /* Allocate the DMA Channels
1935 */
1936 if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1937 DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1938 err("Can't get DAC DMA");
1939 goto err_dma1;
1940 }
1941 au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1942 if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1943 NUM_DBDMA_DESCRIPTORS) == 0) {
1944 err("Can't get DAC DMA descriptors");
1945 goto err_dma1;
1946 }
1947
1948 if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
1949 DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1950 err("Can't get ADC DMA");
1951 goto err_dma2;
1952 }
1953 au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1954 if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1955 NUM_DBDMA_DESCRIPTORS) == 0) {
1956 err("Can't get ADC DMA descriptors");
1957 goto err_dma2;
1958 }
1959
1960 pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
1961
1962 /* register devices */
1963
1964 if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1965 goto err_dev1;
1966 if ((s->codec->dev_mixer =
1967 register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1968 goto err_dev2;
1969
1970 /* The GPIO for the appropriate PSC was configured by the
1971 * board specific start up.
1972 *
1973 * configure PSC for AC'97
1974 */
1975 au_writel(0, AC97_PSC_CTRL); /* Disable PSC */
1976 au_sync();
1977 au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
1978 au_sync();
1979
1980 /* cold reset the AC'97
1981 */
1982 au_writel(PSC_AC97RST_RST, PSC_AC97RST);
1983 au_sync();
1984 au1550_delay(10);
1985 au_writel(0, PSC_AC97RST);
1986 au_sync();
1987
1988 /* need to delay around 500msec(bleech) to give
1989 some CODECs enough time to wakeup */
1990 au1550_delay(500);
1991
1992 /* warm reset the AC'97 to start the bitclk
1993 */
1994 au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
1995 au_sync();
1996 udelay(100);
1997 au_writel(0, PSC_AC97RST);
1998 au_sync();
1999
2000 /* Enable PSC
2001 */
2002 au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
2003 au_sync();
2004
2005 /* Wait for PSC ready.
2006 */
2007 do {
2008 val = au_readl(PSC_AC97STAT);
2009 au_sync();
2010 } while ((val & PSC_AC97STAT_SR) == 0);
2011
2012 /* Configure AC97 controller.
2013 * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
2014 */
2015 val = PSC_AC97CFG_SET_LEN(16);
2016 val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
2017
2018 /* Enable device so we can at least
2019 * talk over the AC-link.
2020 */
2021 au_writel(val, PSC_AC97CFG);
2022 au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
2023 au_sync();
2024 val |= PSC_AC97CFG_DE_ENABLE;
2025 au_writel(val, PSC_AC97CFG);
2026 au_sync();
2027
2028 /* Wait for Device ready.
2029 */
2030 do {
2031 val = au_readl(PSC_AC97STAT);
2032 au_sync();
2033 } while ((val & PSC_AC97STAT_DR) == 0);
2034
2035 /* codec init */
2036 if (!ac97_probe_codec(s->codec))
2037 goto err_dev3;
2038
2039 s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
2040 s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
2041 pr_info("AC'97 Base/Extended ID = %04x/%04x",
2042 s->codec_base_caps, s->codec_ext_caps);
2043
2044 if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2045 /* codec does not support VRA
2046 */
2047 s->no_vra = 1;
2048 } else if (!vra) {
2049 /* Boot option says disable VRA
2050 */
2051 u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
2052 wrcodec(s->codec, AC97_EXTENDED_STATUS,
2053 ac97_extstat & ~AC97_EXTSTAT_VRA);
2054 s->no_vra = 1;
2055 }
2056 if (s->no_vra)
2057 pr_info("no VRA, interpolating and decimating");
2058
2059 /* set mic to be the recording source */
2060 val = SOUND_MASK_MIC;
2061 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2062 (unsigned long) &val);
2063
2064 return 0;
2065
2066 err_dev3:
2067 unregister_sound_mixer(s->codec->dev_mixer);
2068 err_dev2:
2069 unregister_sound_dsp(s->dev_audio);
2070 err_dev1:
2071 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2072 err_dma2:
2073 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2074 err_dma1:
2075 release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2076
2077 ac97_release_codec(s->codec);
2078 return -1;
2079 }
2080
2081 static void __devinit
2082 au1550_remove(void)
2083 {
2084 struct au1550_state *s = &au1550_state;
2085
2086 if (!s)
2087 return;
2088 synchronize_irq();
2089 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2090 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2091 release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2092 unregister_sound_dsp(s->dev_audio);
2093 unregister_sound_mixer(s->codec->dev_mixer);
2094 ac97_release_codec(s->codec);
2095 }
2096
2097 static int __init
2098 init_au1550(void)
2099 {
2100 return au1550_probe();
2101 }
2102
2103 static void __exit
2104 cleanup_au1550(void)
2105 {
2106 au1550_remove();
2107 }
2108
2109 module_init(init_au1550);
2110 module_exit(cleanup_au1550);
2111
2112 #ifndef MODULE
2113
2114 static int __init
2115 au1550_setup(char *options)
2116 {
2117 char *this_opt;
2118
2119 if (!options || !*options)
2120 return 0;
2121
2122 while ((this_opt = strsep(&options, ","))) {
2123 if (!*this_opt)
2124 continue;
2125 if (!strncmp(this_opt, "vra", 3)) {
2126 vra = 1;
2127 }
2128 }
2129
2130 return 1;
2131 }
2132
2133 __setup("au1550_audio=", au1550_setup);
2134
2135 #endif /* MODULE */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree