2 * linux/include/linux/mtd/nand.h
4 * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
26 /* Scan and identify a NAND device */
27 extern int nand_scan (struct mtd_info
*mtd
, int max_chips
);
28 /* Separate phases of nand_scan(), allowing board driver to intervene
29 * and override command or ECC setup according to flash type */
30 extern int nand_scan_ident(struct mtd_info
*mtd
, int max_chips
);
31 extern int nand_scan_tail(struct mtd_info
*mtd
);
33 /* Free resources held by the NAND device */
34 extern void nand_release (struct mtd_info
*mtd
);
36 /* Internal helper for board drivers which need to override command function */
37 extern void nand_wait_ready(struct mtd_info
*mtd
);
39 /* The maximum number of NAND chips in an array */
40 #define NAND_MAX_CHIPS 8
42 /* This constant declares the max. oobsize / page, which
43 * is supported now. If you add a chip with bigger oobsize/page
44 * adjust this accordingly.
46 #define NAND_MAX_OOBSIZE 64
47 #define NAND_MAX_PAGESIZE 2048
50 * Constants for hardware specific CLE/ALE/NCE function
52 * These are bits which can be or'ed to set/clear multiple
55 /* Select the chip by setting nCE to low */
57 /* Select the command latch by setting CLE to high */
59 /* Select the address latch by setting ALE to high */
62 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
63 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
64 #define NAND_CTRL_CHANGE 0x80
67 * Standard NAND flash commands
69 #define NAND_CMD_READ0 0
70 #define NAND_CMD_READ1 1
71 #define NAND_CMD_RNDOUT 5
72 #define NAND_CMD_PAGEPROG 0x10
73 #define NAND_CMD_READOOB 0x50
74 #define NAND_CMD_ERASE1 0x60
75 #define NAND_CMD_STATUS 0x70
76 #define NAND_CMD_STATUS_MULTI 0x71
77 #define NAND_CMD_SEQIN 0x80
78 #define NAND_CMD_RNDIN 0x85
79 #define NAND_CMD_READID 0x90
80 #define NAND_CMD_ERASE2 0xd0
81 #define NAND_CMD_RESET 0xff
83 /* Extended commands for large page devices */
84 #define NAND_CMD_READSTART 0x30
85 #define NAND_CMD_RNDOUTSTART 0xE0
86 #define NAND_CMD_CACHEDPROG 0x15
88 /* Extended commands for AG-AND device */
90 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
91 * there is no way to distinguish that from NAND_CMD_READ0
92 * until the remaining sequence of commands has been completed
93 * so add a high order bit and mask it off in the command.
95 #define NAND_CMD_DEPLETE1 0x100
96 #define NAND_CMD_DEPLETE2 0x38
97 #define NAND_CMD_STATUS_MULTI 0x71
98 #define NAND_CMD_STATUS_ERROR 0x72
99 /* multi-bank error status (banks 0-3) */
100 #define NAND_CMD_STATUS_ERROR0 0x73
101 #define NAND_CMD_STATUS_ERROR1 0x74
102 #define NAND_CMD_STATUS_ERROR2 0x75
103 #define NAND_CMD_STATUS_ERROR3 0x76
104 #define NAND_CMD_STATUS_RESET 0x7f
105 #define NAND_CMD_STATUS_CLEAR 0xff
107 #define NAND_CMD_NONE -1
110 #define NAND_STATUS_FAIL 0x01
111 #define NAND_STATUS_FAIL_N1 0x02
112 #define NAND_STATUS_TRUE_READY 0x20
113 #define NAND_STATUS_READY 0x40
114 #define NAND_STATUS_WP 0x80
117 * Constants for ECC_MODES
123 NAND_ECC_HW_SYNDROME
,
127 * Constants for Hardware ECC
129 /* Reset Hardware ECC for read */
130 #define NAND_ECC_READ 0
131 /* Reset Hardware ECC for write */
132 #define NAND_ECC_WRITE 1
133 /* Enable Hardware ECC before syndrom is read back from flash */
134 #define NAND_ECC_READSYN 2
136 /* Bit mask for flags passed to do_nand_read_ecc */
137 #define NAND_GET_DEVICE 0x80
140 /* Option constants for bizarre disfunctionality and real
143 /* Chip can not auto increment pages */
144 #define NAND_NO_AUTOINCR 0x00000001
145 /* Buswitdh is 16 bit */
146 #define NAND_BUSWIDTH_16 0x00000002
147 /* Device supports partial programming without padding */
148 #define NAND_NO_PADDING 0x00000004
149 /* Chip has cache program function */
150 #define NAND_CACHEPRG 0x00000008
151 /* Chip has copy back function */
152 #define NAND_COPYBACK 0x00000010
153 /* AND Chip which has 4 banks and a confusing page / block
154 * assignment. See Renesas datasheet for further information */
155 #define NAND_IS_AND 0x00000020
156 /* Chip has a array of 4 pages which can be read without
157 * additional ready /busy waits */
158 #define NAND_4PAGE_ARRAY 0x00000040
159 /* Chip requires that BBT is periodically rewritten to prevent
160 * bits from adjacent blocks from 'leaking' in altering data.
161 * This happens with the Renesas AG-AND chips, possibly others. */
162 #define BBT_AUTO_REFRESH 0x00000080
163 /* Chip does not require ready check on read. True
164 * for all large page devices, as they do not support
166 #define NAND_NO_READRDY 0x00000100
167 /* Chip does not allow subpage writes */
168 #define NAND_NO_SUBPAGE_WRITE 0x00000200
171 /* Options valid for Samsung large page devices */
172 #define NAND_SAMSUNG_LP_OPTIONS \
173 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
175 /* Macros to identify the above */
176 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
177 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
178 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
179 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
180 /* Large page NAND with SOFT_ECC should support subpage reads */
181 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
182 && (chip->page_shift > 9))
184 /* Mask to zero out the chip options, which come from the id table */
185 #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
187 /* Non chip related options */
188 /* Use a flash based bad block table. This option is passed to the
189 * default bad block table function. */
190 #define NAND_USE_FLASH_BBT 0x00010000
191 /* This option skips the bbt scan during initialization. */
192 #define NAND_SKIP_BBTSCAN 0x00020000
193 /* This option is defined if the board driver allocates its own buffers
194 (e.g. because it needs them DMA-coherent */
195 #define NAND_OWN_BUFFERS 0x00040000
196 /* Options set by nand scan */
197 /* Nand scan has allocated controller struct */
198 #define NAND_CONTROLLER_ALLOC 0x80000000
200 /* Cell info constants */
201 #define NAND_CI_CHIPNR_MSK 0x03
202 #define NAND_CI_CELLTYPE_MSK 0x0C
205 * nand_state_t - chip states
206 * Enumeration for NAND flash chip state
222 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
223 * @lock: protection lock
224 * @active: the mtd device which holds the controller currently
225 * @wq: wait queue to sleep on if a NAND operation is in progress
226 * used instead of the per chip wait queue when a hw controller is available
228 struct nand_hw_control
{
230 struct nand_chip
*active
;
231 wait_queue_head_t wq
;
235 * struct nand_ecc_ctrl - Control structure for ecc
237 * @steps: number of ecc steps per page
238 * @size: data bytes per ecc step
239 * @bytes: ecc bytes per step
240 * @total: total number of ecc bytes per page
241 * @prepad: padding information for syndrome based ecc generators
242 * @postpad: padding information for syndrome based ecc generators
243 * @layout: ECC layout control struct pointer
244 * @hwctl: function to control hardware ecc generator. Must only
245 * be provided if an hardware ECC is available
246 * @calculate: function for ecc calculation or readback from ecc hardware
247 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
248 * @read_page_raw: function to read a raw page without ECC
249 * @write_page_raw: function to write a raw page without ECC
250 * @read_page: function to read a page according to the ecc generator requirements
251 * @write_page: function to write a page according to the ecc generator requirements
252 * @read_oob: function to read chip OOB data
253 * @write_oob: function to write chip OOB data
255 struct nand_ecc_ctrl
{
256 nand_ecc_modes_t mode
;
263 struct nand_ecclayout
*layout
;
264 void (*hwctl
)(struct mtd_info
*mtd
, int mode
);
265 int (*calculate
)(struct mtd_info
*mtd
,
268 int (*correct
)(struct mtd_info
*mtd
, uint8_t *dat
,
271 int (*read_page_raw
)(struct mtd_info
*mtd
,
272 struct nand_chip
*chip
,
274 void (*write_page_raw
)(struct mtd_info
*mtd
,
275 struct nand_chip
*chip
,
277 int (*read_page
)(struct mtd_info
*mtd
,
278 struct nand_chip
*chip
,
280 int (*read_subpage
)(struct mtd_info
*mtd
,
281 struct nand_chip
*chip
,
282 uint32_t offs
, uint32_t len
,
284 void (*write_page
)(struct mtd_info
*mtd
,
285 struct nand_chip
*chip
,
287 int (*read_oob
)(struct mtd_info
*mtd
,
288 struct nand_chip
*chip
,
291 int (*write_oob
)(struct mtd_info
*mtd
,
292 struct nand_chip
*chip
,
297 * struct nand_buffers - buffer structure for read/write
298 * @ecccalc: buffer for calculated ecc
299 * @ecccode: buffer for ecc read from flash
300 * @databuf: buffer for data - dynamically sized
302 * Do not change the order of buffers. databuf and oobrbuf must be in
305 struct nand_buffers
{
306 uint8_t ecccalc
[NAND_MAX_OOBSIZE
];
307 uint8_t ecccode
[NAND_MAX_OOBSIZE
];
308 uint8_t databuf
[NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
];
312 * struct nand_chip - NAND Private Flash Chip Data
313 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
314 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
315 * @read_byte: [REPLACEABLE] read one byte from the chip
316 * @read_word: [REPLACEABLE] read one word from the chip
317 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
318 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
319 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
320 * @select_chip: [REPLACEABLE] select chip nr
321 * @block_bad: [REPLACEABLE] check, if the block is bad
322 * @block_markbad: [REPLACEABLE] mark the block bad
323 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
324 * ALE/CLE/nCE. Also used to write command and address
325 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
326 * If set to NULL no access to ready/busy is available and the ready/busy information
327 * is read from the chip status register
328 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
329 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
330 * @ecc: [BOARDSPECIFIC] ecc control ctructure
331 * @buffers: buffer structure for read/write
332 * @hwcontrol: platform-specific hardware control structure
333 * @ops: oob operation operands
334 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
335 * @scan_bbt: [REPLACEABLE] function to scan bad block table
336 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
337 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
338 * @state: [INTERN] the current state of the NAND device
339 * @oob_poi: poison value buffer
340 * @page_shift: [INTERN] number of address bits in a page (column address bits)
341 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
342 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
343 * @chip_shift: [INTERN] number of address bits in one chip
344 * @datbuf: [INTERN] internal buffer for one page + oob
345 * @oobbuf: [INTERN] oob buffer for one eraseblock
346 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
347 * @data_poi: [INTERN] pointer to a data buffer
348 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
349 * special functionality. See the defines for further explanation
350 * @badblockpos: [INTERN] position of the bad block marker in the oob area
351 * @cellinfo: [INTERN] MLC/multichip data from chip ident
352 * @numchips: [INTERN] number of physical chips
353 * @chipsize: [INTERN] the size of one chip for multichip arrays
354 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
355 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
356 * @subpagesize: [INTERN] holds the subpagesize
357 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
358 * @bbt: [INTERN] bad block table pointer
359 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
360 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
361 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
362 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
363 * which is shared among multiple independend devices
364 * @priv: [OPTIONAL] pointer to private chip date
365 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
366 * (determine if errors are correctable)
367 * @write_page: [REPLACEABLE] High-level page write function
371 void __iomem
*IO_ADDR_R
;
372 void __iomem
*IO_ADDR_W
;
374 uint8_t (*read_byte
)(struct mtd_info
*mtd
);
375 u16 (*read_word
)(struct mtd_info
*mtd
);
376 void (*write_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
377 void (*read_buf
)(struct mtd_info
*mtd
, uint8_t *buf
, int len
);
378 int (*verify_buf
)(struct mtd_info
*mtd
, const uint8_t *buf
, int len
);
379 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
380 int (*block_bad
)(struct mtd_info
*mtd
, loff_t ofs
, int getchip
);
381 int (*block_markbad
)(struct mtd_info
*mtd
, loff_t ofs
);
382 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
,
384 int (*dev_ready
)(struct mtd_info
*mtd
);
385 void (*cmdfunc
)(struct mtd_info
*mtd
, unsigned command
, int column
, int page_addr
);
386 int (*waitfunc
)(struct mtd_info
*mtd
, struct nand_chip
*this);
387 void (*erase_cmd
)(struct mtd_info
*mtd
, int page
);
388 int (*scan_bbt
)(struct mtd_info
*mtd
);
389 int (*errstat
)(struct mtd_info
*mtd
, struct nand_chip
*this, int state
, int status
, int page
);
390 int (*write_page
)(struct mtd_info
*mtd
, struct nand_chip
*chip
,
391 const uint8_t *buf
, int page
, int cached
, int raw
);
394 unsigned int options
;
397 int phys_erase_shift
;
401 unsigned long chipsize
;
411 struct nand_hw_control
*controller
;
412 struct nand_ecclayout
*ecclayout
;
414 struct nand_ecc_ctrl ecc
;
415 struct nand_buffers
*buffers
;
416 struct nand_hw_control hwcontrol
;
418 struct mtd_oob_ops ops
;
421 struct nand_bbt_descr
*bbt_td
;
422 struct nand_bbt_descr
*bbt_md
;
424 struct nand_bbt_descr
*badblock_pattern
;
430 * NAND Flash Manufacturer ID Codes
432 #define NAND_MFR_TOSHIBA 0x98
433 #define NAND_MFR_SAMSUNG 0xec
434 #define NAND_MFR_FUJITSU 0x04
435 #define NAND_MFR_NATIONAL 0x8f
436 #define NAND_MFR_RENESAS 0x07
437 #define NAND_MFR_STMICRO 0x20
438 #define NAND_MFR_HYNIX 0xad
439 #define NAND_MFR_MICRON 0x2c
440 #define NAND_MFR_AMD 0x01
443 * struct nand_flash_dev - NAND Flash Device ID Structure
444 * @name: Identify the device type
445 * @id: device ID code
446 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
447 * If the pagesize is 0, then the real pagesize
448 * and the eraseize are determined from the
449 * extended id bytes in the chip
450 * @erasesize: Size of an erase block in the flash device.
451 * @chipsize: Total chipsize in Mega Bytes
452 * @options: Bitfield to store chip relevant options
454 struct nand_flash_dev
{
457 unsigned long pagesize
;
458 unsigned long chipsize
;
459 unsigned long erasesize
;
460 unsigned long options
;
464 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
465 * @name: Manufacturer name
466 * @id: manufacturer ID code of device.
468 struct nand_manufacturers
{
473 extern struct nand_flash_dev nand_flash_ids
[];
474 extern struct nand_manufacturers nand_manuf_ids
[];
477 * struct nand_bbt_descr - bad block table descriptor
478 * @options: options for this descriptor
479 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
480 * when bbt is searched, then we store the found bbts pages here.
481 * Its an array and supports up to 8 chips now
482 * @offs: offset of the pattern in the oob area of the page
483 * @veroffs: offset of the bbt version counter in the oob are of the page
484 * @version: version read from the bbt page during scan
485 * @len: length of the pattern, if 0 no pattern check is performed
486 * @maxblocks: maximum number of blocks to search for a bbt. This number of
487 * blocks is reserved at the end of the device where the tables are
489 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
490 * bad) block in the stored bbt
491 * @pattern: pattern to identify bad block table or factory marked good /
492 * bad blocks, can be NULL, if len = 0
494 * Descriptor for the bad block table marker and the descriptor for the
495 * pattern which identifies good and bad blocks. The assumption is made
496 * that the pattern and the version count are always located in the oob area
497 * of the first block.
499 struct nand_bbt_descr
{
501 int pages
[NAND_MAX_CHIPS
];
504 uint8_t version
[NAND_MAX_CHIPS
];
507 int reserved_block_code
;
511 /* Options for the bad block table descriptors */
513 /* The number of bits used per block in the bbt on the device */
514 #define NAND_BBT_NRBITS_MSK 0x0000000F
515 #define NAND_BBT_1BIT 0x00000001
516 #define NAND_BBT_2BIT 0x00000002
517 #define NAND_BBT_4BIT 0x00000004
518 #define NAND_BBT_8BIT 0x00000008
519 /* The bad block table is in the last good block of the device */
520 #define NAND_BBT_LASTBLOCK 0x00000010
521 /* The bbt is at the given page, else we must scan for the bbt */
522 #define NAND_BBT_ABSPAGE 0x00000020
523 /* The bbt is at the given page, else we must scan for the bbt */
524 #define NAND_BBT_SEARCH 0x00000040
525 /* bbt is stored per chip on multichip devices */
526 #define NAND_BBT_PERCHIP 0x00000080
527 /* bbt has a version counter at offset veroffs */
528 #define NAND_BBT_VERSION 0x00000100
529 /* Create a bbt if none axists */
530 #define NAND_BBT_CREATE 0x00000200
531 /* Search good / bad pattern through all pages of a block */
532 #define NAND_BBT_SCANALLPAGES 0x00000400
533 /* Scan block empty during good / bad block scan */
534 #define NAND_BBT_SCANEMPTY 0x00000800
535 /* Write bbt if neccecary */
536 #define NAND_BBT_WRITE 0x00001000
537 /* Read and write back block contents when writing bbt */
538 #define NAND_BBT_SAVECONTENT 0x00002000
539 /* Search good / bad pattern on the first and the second page */
540 #define NAND_BBT_SCAN2NDPAGE 0x00004000
542 /* The maximum number of blocks to scan for a bbt */
543 #define NAND_BBT_SCAN_MAXBLOCKS 4
545 extern int nand_scan_bbt(struct mtd_info
*mtd
, struct nand_bbt_descr
*bd
);
546 extern int nand_update_bbt(struct mtd_info
*mtd
, loff_t offs
);
547 extern int nand_default_bbt(struct mtd_info
*mtd
);
548 extern int nand_isbad_bbt(struct mtd_info
*mtd
, loff_t offs
, int allowbbt
);
549 extern int nand_erase_nand(struct mtd_info
*mtd
, struct erase_info
*instr
,
551 extern int nand_do_read(struct mtd_info
*mtd
, loff_t from
, size_t len
,
552 size_t * retlen
, uint8_t * buf
);
555 * Constants for oob configuration
557 #define NAND_SMALL_BADBLOCK_POS 5
558 #define NAND_LARGE_BADBLOCK_POS 0
561 * struct platform_nand_chip - chip level device structure
562 * @nr_chips: max. number of chips to scan for
563 * @chip_offset: chip number offset
564 * @nr_partitions: number of partitions pointed to by partitions (or zero)
565 * @partitions: mtd partition list
566 * @chip_delay: R/B delay value in us
567 * @options: Option flags, e.g. 16bit buswidth
568 * @ecclayout: ecc layout info structure
569 * @part_probe_types: NULL-terminated array of probe types
570 * @priv: hardware controller specific settings
572 struct platform_nand_chip
{
576 struct mtd_partition
*partitions
;
577 struct nand_ecclayout
*ecclayout
;
579 unsigned int options
;
580 const char **part_probe_types
;
585 * struct platform_nand_ctrl - controller level device structure
586 * @hwcontrol: platform specific hardware control structure
587 * @dev_ready: platform specific function to read ready/busy pin
588 * @select_chip: platform specific chip select function
589 * @cmd_ctrl: platform specific function for controlling
590 * ALE/CLE/nCE. Also used to write command and address
591 * @priv: private data to transport driver specific settings
593 * All fields are optional and depend on the hardware driver requirements
595 struct platform_nand_ctrl
{
596 void (*hwcontrol
)(struct mtd_info
*mtd
, int cmd
);
597 int (*dev_ready
)(struct mtd_info
*mtd
);
598 void (*select_chip
)(struct mtd_info
*mtd
, int chip
);
599 void (*cmd_ctrl
)(struct mtd_info
*mtd
, int dat
,
605 * struct platform_nand_data - container structure for platform-specific data
606 * @chip: chip level chip structure
607 * @ctrl: controller level device structure
609 struct platform_nand_data
{
610 struct platform_nand_chip chip
;
611 struct platform_nand_ctrl ctrl
;
614 /* Some helpers to access the data structures */
616 struct platform_nand_chip
*get_platform_nandchip(struct mtd_info
*mtd
)
618 struct nand_chip
*chip
= mtd
->priv
;
623 #endif /* __LINUX_MTD_NAND_H */