2 * Intel GTT (Graphics Translation Table) routines
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
15 * /fairy-tale-mode off
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
26 #include "intel-agp.h"
27 #include <linux/intel-gtt.h>
28 #include <drm/intel-gtt.h>
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
37 #define USE_PCI_DMA_API 1
40 /* Max amount of stolen space, anything above will be returned to Linux */
41 int intel_max_stolen
= 32 * 1024 * 1024;
42 EXPORT_SYMBOL(intel_max_stolen
);
44 static const struct aper_size_info_fixed intel_i810_sizes
[] =
47 /* The 32M mode still requires a 64k gatt */
51 #define AGP_DCACHE_MEMORY 1
52 #define AGP_PHYS_MEMORY 2
53 #define INTEL_AGP_CACHED_MEMORY 3
55 static struct gatt_mask intel_i810_masks
[] =
57 {.mask
= I810_PTE_VALID
, .type
= 0},
58 {.mask
= (I810_PTE_VALID
| I810_PTE_LOCAL
), .type
= AGP_DCACHE_MEMORY
},
59 {.mask
= I810_PTE_VALID
, .type
= 0},
60 {.mask
= I810_PTE_VALID
| I830_PTE_SYSTEM_CACHED
,
61 .type
= INTEL_AGP_CACHED_MEMORY
}
64 #define INTEL_AGP_UNCACHED_MEMORY 0
65 #define INTEL_AGP_CACHED_MEMORY_LLC 1
66 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
67 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
70 static struct gatt_mask intel_gen6_masks
[] =
72 {.mask
= I810_PTE_VALID
| GEN6_PTE_UNCACHED
,
73 .type
= INTEL_AGP_UNCACHED_MEMORY
},
74 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC
,
75 .type
= INTEL_AGP_CACHED_MEMORY_LLC
},
76 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC
| GEN6_PTE_GFDT
,
77 .type
= INTEL_AGP_CACHED_MEMORY_LLC_GFDT
},
78 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC_MLC
,
79 .type
= INTEL_AGP_CACHED_MEMORY_LLC_MLC
},
80 {.mask
= I810_PTE_VALID
| GEN6_PTE_LLC_MLC
| GEN6_PTE_GFDT
,
81 .type
= INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT
},
84 struct intel_gtt_driver
{
86 unsigned int is_g33
: 1;
87 unsigned int is_pineview
: 1;
88 unsigned int is_ironlake
: 1;
91 static struct _intel_private
{
92 struct intel_gtt base
;
93 const struct intel_gtt_driver
*driver
;
94 struct pci_dev
*pcidev
; /* device one */
95 struct pci_dev
*bridge_dev
;
96 u8 __iomem
*registers
;
97 u32 __iomem
*gtt
; /* I915G */
98 int num_dcache_entries
;
100 void __iomem
*i9xx_flush_page
;
101 void *i8xx_flush_page
;
103 struct page
*i8xx_page
;
104 struct resource ifp_resource
;
108 #define INTEL_GTT_GEN intel_private.driver->gen
109 #define IS_G33 intel_private.driver->is_g33
110 #define IS_PINEVIEW intel_private.driver->is_pineview
111 #define IS_IRONLAKE intel_private.driver->is_ironlake
113 #ifdef USE_PCI_DMA_API
114 static int intel_agp_map_page(struct page
*page
, dma_addr_t
*ret
)
116 *ret
= pci_map_page(intel_private
.pcidev
, page
, 0,
117 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
118 if (pci_dma_mapping_error(intel_private
.pcidev
, *ret
))
123 static void intel_agp_unmap_page(struct page
*page
, dma_addr_t dma
)
125 pci_unmap_page(intel_private
.pcidev
, dma
,
126 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
129 static void intel_agp_free_sglist(struct agp_memory
*mem
)
133 st
.sgl
= mem
->sg_list
;
134 st
.orig_nents
= st
.nents
= mem
->page_count
;
142 static int intel_agp_map_memory(struct agp_memory
*mem
)
145 struct scatterlist
*sg
;
148 DBG("try mapping %lu pages\n", (unsigned long)mem
->page_count
);
150 if (sg_alloc_table(&st
, mem
->page_count
, GFP_KERNEL
))
153 mem
->sg_list
= sg
= st
.sgl
;
155 for (i
= 0 ; i
< mem
->page_count
; i
++, sg
= sg_next(sg
))
156 sg_set_page(sg
, mem
->pages
[i
], PAGE_SIZE
, 0);
158 mem
->num_sg
= pci_map_sg(intel_private
.pcidev
, mem
->sg_list
,
159 mem
->page_count
, PCI_DMA_BIDIRECTIONAL
);
160 if (unlikely(!mem
->num_sg
))
170 static void intel_agp_unmap_memory(struct agp_memory
*mem
)
172 DBG("try unmapping %lu pages\n", (unsigned long)mem
->page_count
);
174 pci_unmap_sg(intel_private
.pcidev
, mem
->sg_list
,
175 mem
->page_count
, PCI_DMA_BIDIRECTIONAL
);
176 intel_agp_free_sglist(mem
);
179 static void intel_agp_insert_sg_entries(struct agp_memory
*mem
,
180 off_t pg_start
, int mask_type
)
182 struct scatterlist
*sg
;
187 WARN_ON(!mem
->num_sg
);
189 if (mem
->num_sg
== mem
->page_count
) {
190 for_each_sg(mem
->sg_list
, sg
, mem
->page_count
, i
) {
191 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
192 sg_dma_address(sg
), mask_type
),
193 intel_private
.gtt
+j
);
197 /* sg may merge pages, but we have to separate
198 * per-page addr for GTT */
201 for_each_sg(mem
->sg_list
, sg
, mem
->num_sg
, i
) {
202 len
= sg_dma_len(sg
) / PAGE_SIZE
;
203 for (m
= 0; m
< len
; m
++) {
204 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
205 sg_dma_address(sg
) + m
* PAGE_SIZE
,
207 intel_private
.gtt
+j
);
212 readl(intel_private
.gtt
+j
-1);
217 static void intel_agp_insert_sg_entries(struct agp_memory
*mem
,
218 off_t pg_start
, int mask_type
)
222 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
223 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
224 page_to_phys(mem
->pages
[i
]), mask_type
),
225 intel_private
.gtt
+j
);
228 readl(intel_private
.gtt
+j
-1);
233 static int intel_i810_fetch_size(void)
236 struct aper_size_info_fixed
*values
;
238 pci_read_config_dword(intel_private
.bridge_dev
,
239 I810_SMRAM_MISCC
, &smram_miscc
);
240 values
= A_SIZE_FIX(agp_bridge
->driver
->aperture_sizes
);
242 if ((smram_miscc
& I810_GMS
) == I810_GMS_DISABLE
) {
243 dev_warn(&intel_private
.bridge_dev
->dev
, "i810 is disabled\n");
246 if ((smram_miscc
& I810_GFX_MEM_WIN_SIZE
) == I810_GFX_MEM_WIN_32M
) {
247 agp_bridge
->current_size
= (void *) (values
+ 1);
248 agp_bridge
->aperture_size_idx
= 1;
249 return values
[1].size
;
251 agp_bridge
->current_size
= (void *) (values
);
252 agp_bridge
->aperture_size_idx
= 0;
253 return values
[0].size
;
259 static int intel_i810_configure(void)
261 struct aper_size_info_fixed
*current_size
;
265 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
267 if (!intel_private
.registers
) {
268 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, &temp
);
271 intel_private
.registers
= ioremap(temp
, 128 * 4096);
272 if (!intel_private
.registers
) {
273 dev_err(&intel_private
.pcidev
->dev
,
274 "can't remap memory\n");
279 if ((readl(intel_private
.registers
+I810_DRAM_CTL
)
280 & I810_DRAM_ROW_0
) == I810_DRAM_ROW_0_SDRAM
) {
281 /* This will need to be dynamically assigned */
282 dev_info(&intel_private
.pcidev
->dev
,
283 "detected 4MB dedicated video ram\n");
284 intel_private
.num_dcache_entries
= 1024;
286 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
, &temp
);
287 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
288 writel(agp_bridge
->gatt_bus_addr
| I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
289 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
291 if (agp_bridge
->driver
->needs_scratch_page
) {
292 for (i
= 0; i
< current_size
->num_entries
; i
++) {
293 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
295 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4)); /* PCI posting. */
297 global_cache_flush();
301 static void intel_i810_cleanup(void)
303 writel(0, intel_private
.registers
+I810_PGETBL_CTL
);
304 readl(intel_private
.registers
); /* PCI Posting. */
305 iounmap(intel_private
.registers
);
308 static void intel_fake_agp_enable(struct agp_bridge_data
*bridge
, u32 mode
)
313 /* Exists to support ARGB cursors */
314 static struct page
*i8xx_alloc_pages(void)
318 page
= alloc_pages(GFP_KERNEL
| GFP_DMA32
, 2);
322 if (set_pages_uc(page
, 4) < 0) {
323 set_pages_wb(page
, 4);
324 __free_pages(page
, 2);
328 atomic_inc(&agp_bridge
->current_memory_agp
);
332 static void i8xx_destroy_pages(struct page
*page
)
337 set_pages_wb(page
, 4);
339 __free_pages(page
, 2);
340 atomic_dec(&agp_bridge
->current_memory_agp
);
343 static int intel_i830_type_to_mask_type(struct agp_bridge_data
*bridge
,
346 if (type
< AGP_USER_TYPES
)
348 else if (type
== AGP_USER_CACHED_MEMORY
)
349 return INTEL_AGP_CACHED_MEMORY
;
354 static int intel_gen6_type_to_mask_type(struct agp_bridge_data
*bridge
,
357 unsigned int type_mask
= type
& ~AGP_USER_CACHED_MEMORY_GFDT
;
358 unsigned int gfdt
= type
& AGP_USER_CACHED_MEMORY_GFDT
;
360 if (type_mask
== AGP_USER_UNCACHED_MEMORY
)
361 return INTEL_AGP_UNCACHED_MEMORY
;
362 else if (type_mask
== AGP_USER_CACHED_MEMORY_LLC_MLC
)
363 return gfdt
? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT
:
364 INTEL_AGP_CACHED_MEMORY_LLC_MLC
;
365 else /* set 'normal'/'cached' to LLC by default */
366 return gfdt
? INTEL_AGP_CACHED_MEMORY_LLC_GFDT
:
367 INTEL_AGP_CACHED_MEMORY_LLC
;
371 static int intel_i810_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
374 int i
, j
, num_entries
;
379 if (mem
->page_count
== 0)
382 temp
= agp_bridge
->current_size
;
383 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
385 if ((pg_start
+ mem
->page_count
) > num_entries
)
389 for (j
= pg_start
; j
< (pg_start
+ mem
->page_count
); j
++) {
390 if (!PGE_EMPTY(agp_bridge
, readl(agp_bridge
->gatt_table
+j
))) {
396 if (type
!= mem
->type
)
399 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
402 case AGP_DCACHE_MEMORY
:
403 if (!mem
->is_flushed
)
404 global_cache_flush();
405 for (i
= pg_start
; i
< (pg_start
+ mem
->page_count
); i
++) {
406 writel((i
*4096)|I810_PTE_LOCAL
|I810_PTE_VALID
,
407 intel_private
.registers
+I810_PTE_BASE
+(i
*4));
409 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
411 case AGP_PHYS_MEMORY
:
412 case AGP_NORMAL_MEMORY
:
413 if (!mem
->is_flushed
)
414 global_cache_flush();
415 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
416 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
417 page_to_phys(mem
->pages
[i
]), mask_type
),
418 intel_private
.registers
+I810_PTE_BASE
+(j
*4));
420 readl(intel_private
.registers
+I810_PTE_BASE
+((j
-1)*4));
429 mem
->is_flushed
= true;
433 static int intel_i810_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
438 if (mem
->page_count
== 0)
441 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
442 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
444 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
450 * The i810/i830 requires a physical address to program its mouse
451 * pointer into hardware.
452 * However the Xserver still writes to it through the agp aperture.
454 static struct agp_memory
*alloc_agpphysmem_i8xx(size_t pg_count
, int type
)
456 struct agp_memory
*new;
460 case 1: page
= agp_bridge
->driver
->agp_alloc_page(agp_bridge
);
463 /* kludge to get 4 physical pages for ARGB cursor */
464 page
= i8xx_alloc_pages();
473 new = agp_create_memory(pg_count
);
477 new->pages
[0] = page
;
479 /* kludge to get 4 physical pages for ARGB cursor */
480 new->pages
[1] = new->pages
[0] + 1;
481 new->pages
[2] = new->pages
[1] + 1;
482 new->pages
[3] = new->pages
[2] + 1;
484 new->page_count
= pg_count
;
485 new->num_scratch_pages
= pg_count
;
486 new->type
= AGP_PHYS_MEMORY
;
487 new->physical
= page_to_phys(new->pages
[0]);
491 static struct agp_memory
*intel_i810_alloc_by_type(size_t pg_count
, int type
)
493 struct agp_memory
*new;
495 if (type
== AGP_DCACHE_MEMORY
) {
496 if (pg_count
!= intel_private
.num_dcache_entries
)
499 new = agp_create_memory(1);
503 new->type
= AGP_DCACHE_MEMORY
;
504 new->page_count
= pg_count
;
505 new->num_scratch_pages
= 0;
506 agp_free_page_array(new);
509 if (type
== AGP_PHYS_MEMORY
)
510 return alloc_agpphysmem_i8xx(pg_count
, type
);
514 static void intel_i810_free_by_type(struct agp_memory
*curr
)
516 agp_free_key(curr
->key
);
517 if (curr
->type
== AGP_PHYS_MEMORY
) {
518 if (curr
->page_count
== 4)
519 i8xx_destroy_pages(curr
->pages
[0]);
521 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
522 AGP_PAGE_DESTROY_UNMAP
);
523 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
524 AGP_PAGE_DESTROY_FREE
);
526 agp_free_page_array(curr
);
531 static unsigned long intel_i810_mask_memory(struct agp_bridge_data
*bridge
,
532 dma_addr_t addr
, int type
)
534 /* Type checking must be done elsewhere */
535 return addr
| bridge
->driver
->masks
[type
].mask
;
538 static struct aper_size_info_fixed intel_fake_agp_sizes
[] =
541 /* The 64M mode still requires a 128k gatt */
547 static unsigned int intel_gtt_stolen_entries(void)
552 static const int ddt
[4] = { 0, 16, 32, 64 };
553 unsigned int overhead_entries
, stolen_entries
;
554 unsigned int stolen_size
= 0;
556 pci_read_config_word(intel_private
.bridge_dev
,
557 I830_GMCH_CTRL
, &gmch_ctrl
);
559 if (INTEL_GTT_GEN
> 4 || IS_PINEVIEW
)
560 overhead_entries
= 0;
562 overhead_entries
= intel_private
.base
.gtt_mappable_entries
565 overhead_entries
+= 1; /* BIOS popup */
567 if (intel_private
.bridge_dev
->device
== PCI_DEVICE_ID_INTEL_82830_HB
||
568 intel_private
.bridge_dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
) {
569 switch (gmch_ctrl
& I830_GMCH_GMS_MASK
) {
570 case I830_GMCH_GMS_STOLEN_512
:
571 stolen_size
= KB(512);
573 case I830_GMCH_GMS_STOLEN_1024
:
576 case I830_GMCH_GMS_STOLEN_8192
:
579 case I830_GMCH_GMS_LOCAL
:
580 rdct
= readb(intel_private
.registers
+I830_RDRAM_CHANNEL_TYPE
);
581 stolen_size
= (I830_RDRAM_ND(rdct
) + 1) *
582 MB(ddt
[I830_RDRAM_DDT(rdct
)]);
589 } else if (INTEL_GTT_GEN
== 6) {
591 * SandyBridge has new memory control reg at 0x50.w
594 pci_read_config_word(intel_private
.pcidev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
595 switch (snb_gmch_ctl
& SNB_GMCH_GMS_STOLEN_MASK
) {
596 case SNB_GMCH_GMS_STOLEN_32M
:
597 stolen_size
= MB(32);
599 case SNB_GMCH_GMS_STOLEN_64M
:
600 stolen_size
= MB(64);
602 case SNB_GMCH_GMS_STOLEN_96M
:
603 stolen_size
= MB(96);
605 case SNB_GMCH_GMS_STOLEN_128M
:
606 stolen_size
= MB(128);
608 case SNB_GMCH_GMS_STOLEN_160M
:
609 stolen_size
= MB(160);
611 case SNB_GMCH_GMS_STOLEN_192M
:
612 stolen_size
= MB(192);
614 case SNB_GMCH_GMS_STOLEN_224M
:
615 stolen_size
= MB(224);
617 case SNB_GMCH_GMS_STOLEN_256M
:
618 stolen_size
= MB(256);
620 case SNB_GMCH_GMS_STOLEN_288M
:
621 stolen_size
= MB(288);
623 case SNB_GMCH_GMS_STOLEN_320M
:
624 stolen_size
= MB(320);
626 case SNB_GMCH_GMS_STOLEN_352M
:
627 stolen_size
= MB(352);
629 case SNB_GMCH_GMS_STOLEN_384M
:
630 stolen_size
= MB(384);
632 case SNB_GMCH_GMS_STOLEN_416M
:
633 stolen_size
= MB(416);
635 case SNB_GMCH_GMS_STOLEN_448M
:
636 stolen_size
= MB(448);
638 case SNB_GMCH_GMS_STOLEN_480M
:
639 stolen_size
= MB(480);
641 case SNB_GMCH_GMS_STOLEN_512M
:
642 stolen_size
= MB(512);
646 switch (gmch_ctrl
& I855_GMCH_GMS_MASK
) {
647 case I855_GMCH_GMS_STOLEN_1M
:
650 case I855_GMCH_GMS_STOLEN_4M
:
653 case I855_GMCH_GMS_STOLEN_8M
:
656 case I855_GMCH_GMS_STOLEN_16M
:
657 stolen_size
= MB(16);
659 case I855_GMCH_GMS_STOLEN_32M
:
660 stolen_size
= MB(32);
662 case I915_GMCH_GMS_STOLEN_48M
:
663 stolen_size
= MB(48);
665 case I915_GMCH_GMS_STOLEN_64M
:
666 stolen_size
= MB(64);
668 case G33_GMCH_GMS_STOLEN_128M
:
669 stolen_size
= MB(128);
671 case G33_GMCH_GMS_STOLEN_256M
:
672 stolen_size
= MB(256);
674 case INTEL_GMCH_GMS_STOLEN_96M
:
675 stolen_size
= MB(96);
677 case INTEL_GMCH_GMS_STOLEN_160M
:
678 stolen_size
= MB(160);
680 case INTEL_GMCH_GMS_STOLEN_224M
:
681 stolen_size
= MB(224);
683 case INTEL_GMCH_GMS_STOLEN_352M
:
684 stolen_size
= MB(352);
692 if (!local
&& stolen_size
> intel_max_stolen
) {
693 dev_info(&intel_private
.bridge_dev
->dev
,
694 "detected %dK stolen memory, trimming to %dK\n",
695 stolen_size
/ KB(1), intel_max_stolen
/ KB(1));
696 stolen_size
= intel_max_stolen
;
697 } else if (stolen_size
> 0) {
698 dev_info(&intel_private
.bridge_dev
->dev
, "detected %dK %s memory\n",
699 stolen_size
/ KB(1), local
? "local" : "stolen");
701 dev_info(&intel_private
.bridge_dev
->dev
,
702 "no pre-allocated video memory detected\n");
706 stolen_entries
= stolen_size
/KB(4) - overhead_entries
;
708 return stolen_entries
;
711 #if 0 /* extracted code in bad shape, needs some cleaning before use */
712 static unsigned int intel_gtt_total_entries(void)
716 if (IS_G33
|| INTEL_GTT_GEN
>= 4) {
718 pgetbl_ctl
= readl(intel_private
.registers
+I810_PGETBL_CTL
);
720 switch (pgetbl_ctl
& I965_PGETBL_SIZE_MASK
) {
721 case I965_PGETBL_SIZE_128KB
:
724 case I965_PGETBL_SIZE_256KB
:
727 case I965_PGETBL_SIZE_512KB
:
730 case I965_PGETBL_SIZE_1MB
:
733 case I965_PGETBL_SIZE_2MB
:
736 case I965_PGETBL_SIZE_1_5MB
:
737 size
= KB(1024 + 512);
740 dev_info(&intel_private
.pcidev
->dev
,
741 "unknown page table size, assuming 512KB\n");
747 /* On previous hardware, the GTT size was just what was
748 * required to map the aperture.
750 return intel_private
.base
.gtt_mappable_entries
;
755 static unsigned int intel_gtt_mappable_entries(void)
757 unsigned int aperture_size
;
760 aperture_size
= 1024 * 1024;
762 pci_read_config_word(intel_private
.bridge_dev
,
763 I830_GMCH_CTRL
, &gmch_ctrl
);
765 switch (intel_private
.pcidev
->device
) {
766 case PCI_DEVICE_ID_INTEL_82830_CGC
:
767 case PCI_DEVICE_ID_INTEL_82845G_IG
:
768 case PCI_DEVICE_ID_INTEL_82855GM_IG
:
769 case PCI_DEVICE_ID_INTEL_82865_IG
:
770 if ((gmch_ctrl
& I830_GMCH_MEM_MASK
) == I830_GMCH_MEM_64M
)
773 aperture_size
*= 128;
776 /* 9xx supports large sizes, just look at the length */
777 aperture_size
= pci_resource_len(intel_private
.pcidev
, 2);
781 return aperture_size
>> PAGE_SHIFT
;
784 static int intel_gtt_init(void)
786 /* we have to call this as early as possible after the MMIO base address is known */
787 intel_private
.base
.gtt_stolen_entries
= intel_gtt_stolen_entries();
788 if (intel_private
.base
.gtt_stolen_entries
== 0) {
789 iounmap(intel_private
.registers
);
796 static int intel_fake_agp_fetch_size(void)
798 unsigned int aper_size
;
800 int num_sizes
= ARRAY_SIZE(intel_fake_agp_sizes
);
802 aper_size
= (intel_private
.base
.gtt_mappable_entries
<< PAGE_SHIFT
)
805 for (i
= 0; i
< num_sizes
; i
++) {
806 if (aper_size
== intel_fake_agp_sizes
[i
].size
) {
807 agp_bridge
->current_size
= intel_fake_agp_sizes
+ i
;
815 static void intel_i830_fini_flush(void)
817 kunmap(intel_private
.i8xx_page
);
818 intel_private
.i8xx_flush_page
= NULL
;
819 unmap_page_from_agp(intel_private
.i8xx_page
);
821 __free_page(intel_private
.i8xx_page
);
822 intel_private
.i8xx_page
= NULL
;
825 static void intel_i830_setup_flush(void)
827 /* return if we've already set the flush mechanism up */
828 if (intel_private
.i8xx_page
)
831 intel_private
.i8xx_page
= alloc_page(GFP_KERNEL
| __GFP_ZERO
| GFP_DMA32
);
832 if (!intel_private
.i8xx_page
)
835 intel_private
.i8xx_flush_page
= kmap(intel_private
.i8xx_page
);
836 if (!intel_private
.i8xx_flush_page
)
837 intel_i830_fini_flush();
840 /* The chipset_flush interface needs to get data that has already been
841 * flushed out of the CPU all the way out to main memory, because the GPU
842 * doesn't snoop those buffers.
844 * The 8xx series doesn't have the same lovely interface for flushing the
845 * chipset write buffers that the later chips do. According to the 865
846 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
847 * that buffer out, we just fill 1KB and clflush it out, on the assumption
848 * that it'll push whatever was in there out. It appears to work.
850 static void intel_i830_chipset_flush(struct agp_bridge_data
*bridge
)
852 unsigned int *pg
= intel_private
.i8xx_flush_page
;
857 clflush_cache_range(pg
, 1024);
858 else if (wbinvd_on_all_cpus() != 0)
859 printk(KERN_ERR
"Timed out waiting for cache flush.\n");
862 /* The intel i830 automatically initializes the agp aperture during POST.
863 * Use the memory already set aside for in the GTT.
865 static int intel_i830_create_gatt_table(struct agp_bridge_data
*bridge
)
868 struct aper_size_info_fixed
*size
;
872 size
= agp_bridge
->current_size
;
873 page_order
= size
->page_order
;
874 num_entries
= size
->num_entries
;
875 agp_bridge
->gatt_table_real
= NULL
;
877 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, &temp
);
880 intel_private
.registers
= ioremap(temp
, 128 * 4096);
881 if (!intel_private
.registers
)
884 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
885 global_cache_flush(); /* FIXME: ?? */
887 ret
= intel_gtt_init();
891 agp_bridge
->gatt_table
= NULL
;
893 agp_bridge
->gatt_bus_addr
= temp
;
898 /* Return the gatt table to a sane state. Use the top of stolen
899 * memory for the GTT.
901 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data
*bridge
)
906 static int intel_i830_configure(void)
908 struct aper_size_info_fixed
*current_size
;
913 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
915 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
, &temp
);
916 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
918 pci_read_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
919 gmch_ctrl
|= I830_GMCH_ENABLED
;
920 pci_write_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, gmch_ctrl
);
922 writel(agp_bridge
->gatt_bus_addr
|I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
923 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
925 if (agp_bridge
->driver
->needs_scratch_page
) {
926 for (i
= intel_private
.base
.gtt_stolen_entries
; i
< current_size
->num_entries
; i
++) {
927 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
929 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4)); /* PCI Posting. */
932 global_cache_flush();
934 intel_i830_setup_flush();
938 static void intel_i830_cleanup(void)
940 iounmap(intel_private
.registers
);
943 static int intel_i830_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
946 int i
, j
, num_entries
;
951 if (mem
->page_count
== 0)
954 temp
= agp_bridge
->current_size
;
955 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
957 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
958 dev_printk(KERN_DEBUG
, &intel_private
.pcidev
->dev
,
959 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
960 pg_start
, intel_private
.base
.gtt_stolen_entries
);
962 dev_info(&intel_private
.pcidev
->dev
,
963 "trying to insert into local/stolen memory\n");
967 if ((pg_start
+ mem
->page_count
) > num_entries
)
970 /* The i830 can't check the GTT for entries since its read only,
971 * depend on the caller to make the correct offset decisions.
974 if (type
!= mem
->type
)
977 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
979 if (mask_type
!= 0 && mask_type
!= AGP_PHYS_MEMORY
&&
980 mask_type
!= INTEL_AGP_CACHED_MEMORY
)
983 if (!mem
->is_flushed
)
984 global_cache_flush();
986 for (i
= 0, j
= pg_start
; i
< mem
->page_count
; i
++, j
++) {
987 writel(agp_bridge
->driver
->mask_memory(agp_bridge
,
988 page_to_phys(mem
->pages
[i
]), mask_type
),
989 intel_private
.registers
+I810_PTE_BASE
+(j
*4));
991 readl(intel_private
.registers
+I810_PTE_BASE
+((j
-1)*4));
996 mem
->is_flushed
= true;
1000 static int intel_i830_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
1005 if (mem
->page_count
== 0)
1008 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
1009 dev_info(&intel_private
.pcidev
->dev
,
1010 "trying to disable local/stolen memory\n");
1014 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++) {
1015 writel(agp_bridge
->scratch_page
, intel_private
.registers
+I810_PTE_BASE
+(i
*4));
1017 readl(intel_private
.registers
+I810_PTE_BASE
+((i
-1)*4));
1022 static struct agp_memory
*intel_fake_agp_alloc_by_type(size_t pg_count
,
1025 if (type
== AGP_PHYS_MEMORY
)
1026 return alloc_agpphysmem_i8xx(pg_count
, type
);
1027 /* always return NULL for other allocation types for now */
1031 static int intel_alloc_chipset_flush_resource(void)
1034 ret
= pci_bus_alloc_resource(intel_private
.bridge_dev
->bus
, &intel_private
.ifp_resource
, PAGE_SIZE
,
1035 PAGE_SIZE
, PCIBIOS_MIN_MEM
, 0,
1036 pcibios_align_resource
, intel_private
.bridge_dev
);
1041 static void intel_i915_setup_chipset_flush(void)
1046 pci_read_config_dword(intel_private
.bridge_dev
, I915_IFPADDR
, &temp
);
1047 if (!(temp
& 0x1)) {
1048 intel_alloc_chipset_flush_resource();
1049 intel_private
.resource_valid
= 1;
1050 pci_write_config_dword(intel_private
.bridge_dev
, I915_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1054 intel_private
.resource_valid
= 1;
1055 intel_private
.ifp_resource
.start
= temp
;
1056 intel_private
.ifp_resource
.end
= temp
+ PAGE_SIZE
;
1057 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1058 /* some BIOSes reserve this area in a pnp some don't */
1060 intel_private
.resource_valid
= 0;
1064 static void intel_i965_g33_setup_chipset_flush(void)
1066 u32 temp_hi
, temp_lo
;
1069 pci_read_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
+ 4, &temp_hi
);
1070 pci_read_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
, &temp_lo
);
1072 if (!(temp_lo
& 0x1)) {
1074 intel_alloc_chipset_flush_resource();
1076 intel_private
.resource_valid
= 1;
1077 pci_write_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
+ 4,
1078 upper_32_bits(intel_private
.ifp_resource
.start
));
1079 pci_write_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1084 l64
= ((u64
)temp_hi
<< 32) | temp_lo
;
1086 intel_private
.resource_valid
= 1;
1087 intel_private
.ifp_resource
.start
= l64
;
1088 intel_private
.ifp_resource
.end
= l64
+ PAGE_SIZE
;
1089 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1090 /* some BIOSes reserve this area in a pnp some don't */
1092 intel_private
.resource_valid
= 0;
1096 static void intel_i9xx_setup_flush(void)
1098 /* return if already configured */
1099 if (intel_private
.ifp_resource
.start
)
1102 if (INTEL_GTT_GEN
== 6)
1105 /* setup a resource for this object */
1106 intel_private
.ifp_resource
.name
= "Intel Flush Page";
1107 intel_private
.ifp_resource
.flags
= IORESOURCE_MEM
;
1109 /* Setup chipset flush for 915 */
1110 if (IS_G33
|| INTEL_GTT_GEN
>= 4) {
1111 intel_i965_g33_setup_chipset_flush();
1113 intel_i915_setup_chipset_flush();
1116 if (intel_private
.ifp_resource
.start
)
1117 intel_private
.i9xx_flush_page
= ioremap_nocache(intel_private
.ifp_resource
.start
, PAGE_SIZE
);
1118 if (!intel_private
.i9xx_flush_page
)
1119 dev_err(&intel_private
.pcidev
->dev
,
1120 "can't ioremap flush page - no chipset flushing\n");
1123 static int intel_i9xx_configure(void)
1125 struct aper_size_info_fixed
*current_size
;
1130 current_size
= A_SIZE_FIX(agp_bridge
->current_size
);
1132 pci_read_config_dword(intel_private
.pcidev
, I915_GMADDR
, &temp
);
1134 agp_bridge
->gart_bus_addr
= (temp
& PCI_BASE_ADDRESS_MEM_MASK
);
1136 pci_read_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
1137 gmch_ctrl
|= I830_GMCH_ENABLED
;
1138 pci_write_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, gmch_ctrl
);
1140 writel(agp_bridge
->gatt_bus_addr
|I810_PGETBL_ENABLED
, intel_private
.registers
+I810_PGETBL_CTL
);
1141 readl(intel_private
.registers
+I810_PGETBL_CTL
); /* PCI Posting. */
1143 if (agp_bridge
->driver
->needs_scratch_page
) {
1144 for (i
= intel_private
.base
.gtt_stolen_entries
; i
<
1145 intel_private
.base
.gtt_total_entries
; i
++) {
1146 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
1148 readl(intel_private
.gtt
+i
-1); /* PCI Posting. */
1151 global_cache_flush();
1153 intel_i9xx_setup_flush();
1158 static void intel_i915_cleanup(void)
1160 if (intel_private
.i9xx_flush_page
)
1161 iounmap(intel_private
.i9xx_flush_page
);
1162 if (intel_private
.resource_valid
)
1163 release_resource(&intel_private
.ifp_resource
);
1164 intel_private
.ifp_resource
.start
= 0;
1165 intel_private
.resource_valid
= 0;
1166 iounmap(intel_private
.gtt
);
1167 iounmap(intel_private
.registers
);
1170 static void intel_i915_chipset_flush(struct agp_bridge_data
*bridge
)
1172 if (intel_private
.i9xx_flush_page
)
1173 writel(1, intel_private
.i9xx_flush_page
);
1176 static int intel_i915_insert_entries(struct agp_memory
*mem
, off_t pg_start
,
1184 if (mem
->page_count
== 0)
1187 temp
= agp_bridge
->current_size
;
1188 num_entries
= A_SIZE_FIX(temp
)->num_entries
;
1190 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
1191 dev_printk(KERN_DEBUG
, &intel_private
.pcidev
->dev
,
1192 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1193 pg_start
, intel_private
.base
.gtt_stolen_entries
);
1195 dev_info(&intel_private
.pcidev
->dev
,
1196 "trying to insert into local/stolen memory\n");
1200 if ((pg_start
+ mem
->page_count
) > num_entries
)
1203 /* The i915 can't check the GTT for entries since it's read only;
1204 * depend on the caller to make the correct offset decisions.
1207 if (type
!= mem
->type
)
1210 mask_type
= agp_bridge
->driver
->agp_type_to_mask_type(agp_bridge
, type
);
1212 if (INTEL_GTT_GEN
!= 6 && mask_type
!= 0 &&
1213 mask_type
!= AGP_PHYS_MEMORY
&&
1214 mask_type
!= INTEL_AGP_CACHED_MEMORY
)
1217 if (!mem
->is_flushed
)
1218 global_cache_flush();
1220 intel_agp_insert_sg_entries(mem
, pg_start
, mask_type
);
1225 mem
->is_flushed
= true;
1229 static int intel_i915_remove_entries(struct agp_memory
*mem
, off_t pg_start
,
1234 if (mem
->page_count
== 0)
1237 if (pg_start
< intel_private
.base
.gtt_stolen_entries
) {
1238 dev_info(&intel_private
.pcidev
->dev
,
1239 "trying to disable local/stolen memory\n");
1243 for (i
= pg_start
; i
< (mem
->page_count
+ pg_start
); i
++)
1244 writel(agp_bridge
->scratch_page
, intel_private
.gtt
+i
);
1246 readl(intel_private
.gtt
+i
-1);
1251 /* Return the aperture size by just checking the resource length. The effect
1252 * described in the spec of the MSAC registers is just changing of the
1255 static int intel_i915_get_gtt_size(void)
1262 /* G33's GTT size defined in gmch_ctrl */
1263 pci_read_config_word(intel_private
.bridge_dev
, I830_GMCH_CTRL
, &gmch_ctrl
);
1264 switch (gmch_ctrl
& I830_GMCH_GMS_MASK
) {
1265 case I830_GMCH_GMS_STOLEN_512
:
1268 case I830_GMCH_GMS_STOLEN_1024
:
1271 case I830_GMCH_GMS_STOLEN_8192
:
1275 dev_info(&intel_private
.bridge_dev
->dev
,
1276 "unknown page table size 0x%x, assuming 512KB\n",
1277 (gmch_ctrl
& I830_GMCH_GMS_MASK
));
1281 /* On previous hardware, the GTT size was just what was
1282 * required to map the aperture.
1284 size
= agp_bridge
->driver
->fetch_size();
1290 /* The intel i915 automatically initializes the agp aperture during POST.
1291 * Use the memory already set aside for in the GTT.
1293 static int intel_i915_create_gatt_table(struct agp_bridge_data
*bridge
)
1295 int page_order
, ret
;
1296 struct aper_size_info_fixed
*size
;
1301 size
= agp_bridge
->current_size
;
1302 page_order
= size
->page_order
;
1303 num_entries
= size
->num_entries
;
1304 agp_bridge
->gatt_table_real
= NULL
;
1306 pci_read_config_dword(intel_private
.pcidev
, I915_MMADDR
, &temp
);
1307 pci_read_config_dword(intel_private
.pcidev
, I915_PTEADDR
, &temp2
);
1309 gtt_map_size
= intel_i915_get_gtt_size();
1311 intel_private
.gtt
= ioremap(temp2
, gtt_map_size
);
1312 if (!intel_private
.gtt
)
1315 intel_private
.base
.gtt_total_entries
= gtt_map_size
/ 4;
1319 intel_private
.registers
= ioremap(temp
, 128 * 4096);
1320 if (!intel_private
.registers
) {
1321 iounmap(intel_private
.gtt
);
1325 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
1326 global_cache_flush(); /* FIXME: ? */
1328 ret
= intel_gtt_init();
1330 iounmap(intel_private
.gtt
);
1334 agp_bridge
->gatt_table
= NULL
;
1336 agp_bridge
->gatt_bus_addr
= temp
;
1342 * The i965 supports 36-bit physical addresses, but to keep
1343 * the format of the GTT the same, the bits that don't fit
1344 * in a 32-bit word are shifted down to bits 4..7.
1346 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1347 * is always zero on 32-bit architectures, so no need to make
1350 static unsigned long intel_i965_mask_memory(struct agp_bridge_data
*bridge
,
1351 dma_addr_t addr
, int type
)
1353 /* Shift high bits down */
1354 addr
|= (addr
>> 28) & 0xf0;
1356 /* Type checking must be done elsewhere */
1357 return addr
| bridge
->driver
->masks
[type
].mask
;
1360 static unsigned long intel_gen6_mask_memory(struct agp_bridge_data
*bridge
,
1361 dma_addr_t addr
, int type
)
1363 /* gen6 has bit11-4 for physical addr bit39-32 */
1364 addr
|= (addr
>> 28) & 0xff0;
1366 /* Type checking must be done elsewhere */
1367 return addr
| bridge
->driver
->masks
[type
].mask
;
1370 static void intel_i965_get_gtt_range(int *gtt_offset
, int *gtt_size
)
1374 switch (intel_private
.bridge_dev
->device
) {
1375 case PCI_DEVICE_ID_INTEL_GM45_HB
:
1376 case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB
:
1377 case PCI_DEVICE_ID_INTEL_Q45_HB
:
1378 case PCI_DEVICE_ID_INTEL_G45_HB
:
1379 case PCI_DEVICE_ID_INTEL_G41_HB
:
1380 case PCI_DEVICE_ID_INTEL_B43_HB
:
1381 case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB
:
1382 case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB
:
1383 case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB
:
1384 case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB
:
1385 *gtt_offset
= *gtt_size
= MB(2);
1387 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB
:
1388 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB
:
1389 case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB
:
1390 *gtt_offset
= MB(2);
1392 pci_read_config_word(intel_private
.pcidev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
1393 switch (snb_gmch_ctl
& SNB_GTT_SIZE_MASK
) {
1395 case SNB_GTT_SIZE_0M
:
1396 printk(KERN_ERR
"Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl
);
1399 case SNB_GTT_SIZE_1M
:
1402 case SNB_GTT_SIZE_2M
:
1408 *gtt_offset
= *gtt_size
= KB(512);
1412 /* The intel i965 automatically initializes the agp aperture during POST.
1413 * Use the memory already set aside for in the GTT.
1415 static int intel_i965_create_gatt_table(struct agp_bridge_data
*bridge
)
1417 int page_order
, ret
;
1418 struct aper_size_info_fixed
*size
;
1421 int gtt_offset
, gtt_size
;
1423 size
= agp_bridge
->current_size
;
1424 page_order
= size
->page_order
;
1425 num_entries
= size
->num_entries
;
1426 agp_bridge
->gatt_table_real
= NULL
;
1428 pci_read_config_dword(intel_private
.pcidev
, I915_MMADDR
, &temp
);
1432 intel_i965_get_gtt_range(>t_offset
, >t_size
);
1434 intel_private
.gtt
= ioremap((temp
+ gtt_offset
) , gtt_size
);
1436 if (!intel_private
.gtt
)
1439 intel_private
.base
.gtt_total_entries
= gtt_size
/ 4;
1441 intel_private
.registers
= ioremap(temp
, 128 * 4096);
1442 if (!intel_private
.registers
) {
1443 iounmap(intel_private
.gtt
);
1447 temp
= readl(intel_private
.registers
+I810_PGETBL_CTL
) & 0xfffff000;
1448 global_cache_flush(); /* FIXME: ? */
1450 ret
= intel_gtt_init();
1452 iounmap(intel_private
.gtt
);
1456 agp_bridge
->gatt_table
= NULL
;
1458 agp_bridge
->gatt_bus_addr
= temp
;
1463 static const struct agp_bridge_driver intel_810_driver
= {
1464 .owner
= THIS_MODULE
,
1465 .aperture_sizes
= intel_i810_sizes
,
1466 .size_type
= FIXED_APER_SIZE
,
1467 .num_aperture_sizes
= 2,
1468 .needs_scratch_page
= true,
1469 .configure
= intel_i810_configure
,
1470 .fetch_size
= intel_i810_fetch_size
,
1471 .cleanup
= intel_i810_cleanup
,
1472 .mask_memory
= intel_i810_mask_memory
,
1473 .masks
= intel_i810_masks
,
1474 .agp_enable
= intel_fake_agp_enable
,
1475 .cache_flush
= global_cache_flush
,
1476 .create_gatt_table
= agp_generic_create_gatt_table
,
1477 .free_gatt_table
= agp_generic_free_gatt_table
,
1478 .insert_memory
= intel_i810_insert_entries
,
1479 .remove_memory
= intel_i810_remove_entries
,
1480 .alloc_by_type
= intel_i810_alloc_by_type
,
1481 .free_by_type
= intel_i810_free_by_type
,
1482 .agp_alloc_page
= agp_generic_alloc_page
,
1483 .agp_alloc_pages
= agp_generic_alloc_pages
,
1484 .agp_destroy_page
= agp_generic_destroy_page
,
1485 .agp_destroy_pages
= agp_generic_destroy_pages
,
1486 .agp_type_to_mask_type
= agp_generic_type_to_mask_type
,
1489 static const struct agp_bridge_driver intel_830_driver
= {
1490 .owner
= THIS_MODULE
,
1491 .aperture_sizes
= intel_fake_agp_sizes
,
1492 .size_type
= FIXED_APER_SIZE
,
1493 .num_aperture_sizes
= 4,
1494 .needs_scratch_page
= true,
1495 .configure
= intel_i830_configure
,
1496 .fetch_size
= intel_fake_agp_fetch_size
,
1497 .cleanup
= intel_i830_cleanup
,
1498 .mask_memory
= intel_i810_mask_memory
,
1499 .masks
= intel_i810_masks
,
1500 .agp_enable
= intel_fake_agp_enable
,
1501 .cache_flush
= global_cache_flush
,
1502 .create_gatt_table
= intel_i830_create_gatt_table
,
1503 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1504 .insert_memory
= intel_i830_insert_entries
,
1505 .remove_memory
= intel_i830_remove_entries
,
1506 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1507 .free_by_type
= intel_i810_free_by_type
,
1508 .agp_alloc_page
= agp_generic_alloc_page
,
1509 .agp_alloc_pages
= agp_generic_alloc_pages
,
1510 .agp_destroy_page
= agp_generic_destroy_page
,
1511 .agp_destroy_pages
= agp_generic_destroy_pages
,
1512 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1513 .chipset_flush
= intel_i830_chipset_flush
,
1516 static const struct agp_bridge_driver intel_915_driver
= {
1517 .owner
= THIS_MODULE
,
1518 .aperture_sizes
= intel_fake_agp_sizes
,
1519 .size_type
= FIXED_APER_SIZE
,
1520 .num_aperture_sizes
= 4,
1521 .needs_scratch_page
= true,
1522 .configure
= intel_i9xx_configure
,
1523 .fetch_size
= intel_fake_agp_fetch_size
,
1524 .cleanup
= intel_i915_cleanup
,
1525 .mask_memory
= intel_i810_mask_memory
,
1526 .masks
= intel_i810_masks
,
1527 .agp_enable
= intel_fake_agp_enable
,
1528 .cache_flush
= global_cache_flush
,
1529 .create_gatt_table
= intel_i915_create_gatt_table
,
1530 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1531 .insert_memory
= intel_i915_insert_entries
,
1532 .remove_memory
= intel_i915_remove_entries
,
1533 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1534 .free_by_type
= intel_i810_free_by_type
,
1535 .agp_alloc_page
= agp_generic_alloc_page
,
1536 .agp_alloc_pages
= agp_generic_alloc_pages
,
1537 .agp_destroy_page
= agp_generic_destroy_page
,
1538 .agp_destroy_pages
= agp_generic_destroy_pages
,
1539 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1540 .chipset_flush
= intel_i915_chipset_flush
,
1541 #ifdef USE_PCI_DMA_API
1542 .agp_map_page
= intel_agp_map_page
,
1543 .agp_unmap_page
= intel_agp_unmap_page
,
1544 .agp_map_memory
= intel_agp_map_memory
,
1545 .agp_unmap_memory
= intel_agp_unmap_memory
,
1549 static const struct agp_bridge_driver intel_i965_driver
= {
1550 .owner
= THIS_MODULE
,
1551 .aperture_sizes
= intel_fake_agp_sizes
,
1552 .size_type
= FIXED_APER_SIZE
,
1553 .num_aperture_sizes
= 4,
1554 .needs_scratch_page
= true,
1555 .configure
= intel_i9xx_configure
,
1556 .fetch_size
= intel_fake_agp_fetch_size
,
1557 .cleanup
= intel_i915_cleanup
,
1558 .mask_memory
= intel_i965_mask_memory
,
1559 .masks
= intel_i810_masks
,
1560 .agp_enable
= intel_fake_agp_enable
,
1561 .cache_flush
= global_cache_flush
,
1562 .create_gatt_table
= intel_i965_create_gatt_table
,
1563 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1564 .insert_memory
= intel_i915_insert_entries
,
1565 .remove_memory
= intel_i915_remove_entries
,
1566 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1567 .free_by_type
= intel_i810_free_by_type
,
1568 .agp_alloc_page
= agp_generic_alloc_page
,
1569 .agp_alloc_pages
= agp_generic_alloc_pages
,
1570 .agp_destroy_page
= agp_generic_destroy_page
,
1571 .agp_destroy_pages
= agp_generic_destroy_pages
,
1572 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1573 .chipset_flush
= intel_i915_chipset_flush
,
1574 #ifdef USE_PCI_DMA_API
1575 .agp_map_page
= intel_agp_map_page
,
1576 .agp_unmap_page
= intel_agp_unmap_page
,
1577 .agp_map_memory
= intel_agp_map_memory
,
1578 .agp_unmap_memory
= intel_agp_unmap_memory
,
1582 static const struct agp_bridge_driver intel_gen6_driver
= {
1583 .owner
= THIS_MODULE
,
1584 .aperture_sizes
= intel_fake_agp_sizes
,
1585 .size_type
= FIXED_APER_SIZE
,
1586 .num_aperture_sizes
= 4,
1587 .needs_scratch_page
= true,
1588 .configure
= intel_i9xx_configure
,
1589 .fetch_size
= intel_fake_agp_fetch_size
,
1590 .cleanup
= intel_i915_cleanup
,
1591 .mask_memory
= intel_gen6_mask_memory
,
1592 .masks
= intel_gen6_masks
,
1593 .agp_enable
= intel_fake_agp_enable
,
1594 .cache_flush
= global_cache_flush
,
1595 .create_gatt_table
= intel_i965_create_gatt_table
,
1596 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1597 .insert_memory
= intel_i915_insert_entries
,
1598 .remove_memory
= intel_i915_remove_entries
,
1599 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1600 .free_by_type
= intel_i810_free_by_type
,
1601 .agp_alloc_page
= agp_generic_alloc_page
,
1602 .agp_alloc_pages
= agp_generic_alloc_pages
,
1603 .agp_destroy_page
= agp_generic_destroy_page
,
1604 .agp_destroy_pages
= agp_generic_destroy_pages
,
1605 .agp_type_to_mask_type
= intel_gen6_type_to_mask_type
,
1606 .chipset_flush
= intel_i915_chipset_flush
,
1607 #ifdef USE_PCI_DMA_API
1608 .agp_map_page
= intel_agp_map_page
,
1609 .agp_unmap_page
= intel_agp_unmap_page
,
1610 .agp_map_memory
= intel_agp_map_memory
,
1611 .agp_unmap_memory
= intel_agp_unmap_memory
,
1615 static const struct agp_bridge_driver intel_g33_driver
= {
1616 .owner
= THIS_MODULE
,
1617 .aperture_sizes
= intel_fake_agp_sizes
,
1618 .size_type
= FIXED_APER_SIZE
,
1619 .num_aperture_sizes
= 4,
1620 .needs_scratch_page
= true,
1621 .configure
= intel_i9xx_configure
,
1622 .fetch_size
= intel_fake_agp_fetch_size
,
1623 .cleanup
= intel_i915_cleanup
,
1624 .mask_memory
= intel_i965_mask_memory
,
1625 .masks
= intel_i810_masks
,
1626 .agp_enable
= intel_fake_agp_enable
,
1627 .cache_flush
= global_cache_flush
,
1628 .create_gatt_table
= intel_i915_create_gatt_table
,
1629 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1630 .insert_memory
= intel_i915_insert_entries
,
1631 .remove_memory
= intel_i915_remove_entries
,
1632 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1633 .free_by_type
= intel_i810_free_by_type
,
1634 .agp_alloc_page
= agp_generic_alloc_page
,
1635 .agp_alloc_pages
= agp_generic_alloc_pages
,
1636 .agp_destroy_page
= agp_generic_destroy_page
,
1637 .agp_destroy_pages
= agp_generic_destroy_pages
,
1638 .agp_type_to_mask_type
= intel_i830_type_to_mask_type
,
1639 .chipset_flush
= intel_i915_chipset_flush
,
1640 #ifdef USE_PCI_DMA_API
1641 .agp_map_page
= intel_agp_map_page
,
1642 .agp_unmap_page
= intel_agp_unmap_page
,
1643 .agp_map_memory
= intel_agp_map_memory
,
1644 .agp_unmap_memory
= intel_agp_unmap_memory
,
1648 static const struct intel_gtt_driver i8xx_gtt_driver
= {
1651 static const struct intel_gtt_driver i915_gtt_driver
= {
1654 static const struct intel_gtt_driver g33_gtt_driver
= {
1658 static const struct intel_gtt_driver pineview_gtt_driver
= {
1660 .is_pineview
= 1, .is_g33
= 1,
1662 static const struct intel_gtt_driver i965_gtt_driver
= {
1665 static const struct intel_gtt_driver g4x_gtt_driver
= {
1668 static const struct intel_gtt_driver ironlake_gtt_driver
= {
1672 static const struct intel_gtt_driver sandybridge_gtt_driver
= {
1676 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1677 * driver and gmch_driver must be non-null, and find_gmch will determine
1678 * which one should be used if a gmch_chip_id is present.
1680 static const struct intel_gtt_driver_description
{
1681 unsigned int gmch_chip_id
;
1683 const struct agp_bridge_driver
*gmch_driver
;
1684 const struct intel_gtt_driver
*gtt_driver
;
1685 } intel_gtt_chipsets
[] = {
1686 { PCI_DEVICE_ID_INTEL_82810_IG1
, "i810", &intel_810_driver
, NULL
},
1687 { PCI_DEVICE_ID_INTEL_82810_IG3
, "i810", &intel_810_driver
, NULL
},
1688 { PCI_DEVICE_ID_INTEL_82810E_IG
, "i810", &intel_810_driver
, NULL
},
1689 { PCI_DEVICE_ID_INTEL_82815_CGC
, "i815", &intel_810_driver
, NULL
},
1690 { PCI_DEVICE_ID_INTEL_82830_CGC
, "830M",
1691 &intel_830_driver
, &i8xx_gtt_driver
},
1692 { PCI_DEVICE_ID_INTEL_82845G_IG
, "830M",
1693 &intel_830_driver
, &i8xx_gtt_driver
},
1694 { PCI_DEVICE_ID_INTEL_82854_IG
, "854",
1695 &intel_830_driver
, &i8xx_gtt_driver
},
1696 { PCI_DEVICE_ID_INTEL_82855GM_IG
, "855GM",
1697 &intel_830_driver
, &i8xx_gtt_driver
},
1698 { PCI_DEVICE_ID_INTEL_82865_IG
, "865",
1699 &intel_830_driver
, &i8xx_gtt_driver
},
1700 { PCI_DEVICE_ID_INTEL_E7221_IG
, "E7221 (i915)",
1701 &intel_915_driver
, &i915_gtt_driver
},
1702 { PCI_DEVICE_ID_INTEL_82915G_IG
, "915G",
1703 &intel_915_driver
, &i915_gtt_driver
},
1704 { PCI_DEVICE_ID_INTEL_82915GM_IG
, "915GM",
1705 &intel_915_driver
, &i915_gtt_driver
},
1706 { PCI_DEVICE_ID_INTEL_82945G_IG
, "945G",
1707 &intel_915_driver
, &i915_gtt_driver
},
1708 { PCI_DEVICE_ID_INTEL_82945GM_IG
, "945GM",
1709 &intel_915_driver
, &i915_gtt_driver
},
1710 { PCI_DEVICE_ID_INTEL_82945GME_IG
, "945GME",
1711 &intel_915_driver
, &i915_gtt_driver
},
1712 { PCI_DEVICE_ID_INTEL_82946GZ_IG
, "946GZ",
1713 &intel_i965_driver
, &i965_gtt_driver
},
1714 { PCI_DEVICE_ID_INTEL_82G35_IG
, "G35",
1715 &intel_i965_driver
, &i965_gtt_driver
},
1716 { PCI_DEVICE_ID_INTEL_82965Q_IG
, "965Q",
1717 &intel_i965_driver
, &i965_gtt_driver
},
1718 { PCI_DEVICE_ID_INTEL_82965G_IG
, "965G",
1719 &intel_i965_driver
, &i965_gtt_driver
},
1720 { PCI_DEVICE_ID_INTEL_82965GM_IG
, "965GM",
1721 &intel_i965_driver
, &i965_gtt_driver
},
1722 { PCI_DEVICE_ID_INTEL_82965GME_IG
, "965GME/GLE",
1723 &intel_i965_driver
, &i965_gtt_driver
},
1724 { PCI_DEVICE_ID_INTEL_G33_IG
, "G33",
1725 &intel_g33_driver
, &g33_gtt_driver
},
1726 { PCI_DEVICE_ID_INTEL_Q35_IG
, "Q35",
1727 &intel_g33_driver
, &g33_gtt_driver
},
1728 { PCI_DEVICE_ID_INTEL_Q33_IG
, "Q33",
1729 &intel_g33_driver
, &g33_gtt_driver
},
1730 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG
, "GMA3150",
1731 &intel_g33_driver
, &pineview_gtt_driver
},
1732 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG
, "GMA3150",
1733 &intel_g33_driver
, &pineview_gtt_driver
},
1734 { PCI_DEVICE_ID_INTEL_GM45_IG
, "GM45",
1735 &intel_i965_driver
, &g4x_gtt_driver
},
1736 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG
, "Eaglelake",
1737 &intel_i965_driver
, &g4x_gtt_driver
},
1738 { PCI_DEVICE_ID_INTEL_Q45_IG
, "Q45/Q43",
1739 &intel_i965_driver
, &g4x_gtt_driver
},
1740 { PCI_DEVICE_ID_INTEL_G45_IG
, "G45/G43",
1741 &intel_i965_driver
, &g4x_gtt_driver
},
1742 { PCI_DEVICE_ID_INTEL_B43_IG
, "B43",
1743 &intel_i965_driver
, &g4x_gtt_driver
},
1744 { PCI_DEVICE_ID_INTEL_G41_IG
, "G41",
1745 &intel_i965_driver
, &g4x_gtt_driver
},
1746 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG
,
1747 "HD Graphics", &intel_i965_driver
, &ironlake_gtt_driver
},
1748 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG
,
1749 "HD Graphics", &intel_i965_driver
, &ironlake_gtt_driver
},
1750 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG
,
1751 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1752 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG
,
1753 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1754 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG
,
1755 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1756 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG
,
1757 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1758 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG
,
1759 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1760 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG
,
1761 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1762 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG
,
1763 "Sandybridge", &intel_gen6_driver
, &sandybridge_gtt_driver
},
1767 static int find_gmch(u16 device
)
1769 struct pci_dev
*gmch_device
;
1771 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
, device
, NULL
);
1772 if (gmch_device
&& PCI_FUNC(gmch_device
->devfn
) != 0) {
1773 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
,
1774 device
, gmch_device
);
1780 intel_private
.pcidev
= gmch_device
;
1784 int intel_gmch_probe(struct pci_dev
*pdev
,
1785 struct agp_bridge_data
*bridge
)
1788 bridge
->driver
= NULL
;
1790 for (i
= 0; intel_gtt_chipsets
[i
].name
!= NULL
; i
++) {
1791 if (find_gmch(intel_gtt_chipsets
[i
].gmch_chip_id
)) {
1793 intel_gtt_chipsets
[i
].gmch_driver
;
1794 intel_private
.driver
=
1795 intel_gtt_chipsets
[i
].gtt_driver
;
1800 if (!bridge
->driver
)
1803 bridge
->dev_private_data
= &intel_private
;
1806 intel_private
.bridge_dev
= pci_dev_get(pdev
);
1808 dev_info(&pdev
->dev
, "Intel %s Chipset\n", intel_gtt_chipsets
[i
].name
);
1810 if (bridge
->driver
->mask_memory
== intel_gen6_mask_memory
)
1812 else if (bridge
->driver
->mask_memory
== intel_i965_mask_memory
)
1817 if (pci_set_dma_mask(intel_private
.pcidev
, DMA_BIT_MASK(mask
)))
1818 dev_err(&intel_private
.pcidev
->dev
,
1819 "set gfx device dma mask %d-bit failed!\n", mask
);
1821 pci_set_consistent_dma_mask(intel_private
.pcidev
,
1822 DMA_BIT_MASK(mask
));
1824 if (bridge
->driver
== &intel_810_driver
)
1827 intel_private
.base
.gtt_mappable_entries
= intel_gtt_mappable_entries();
1831 EXPORT_SYMBOL(intel_gmch_probe
);
1833 void intel_gmch_remove(struct pci_dev
*pdev
)
1835 if (intel_private
.pcidev
)
1836 pci_dev_put(intel_private
.pcidev
);
1837 if (intel_private
.bridge_dev
)
1838 pci_dev_put(intel_private
.bridge_dev
);
1840 EXPORT_SYMBOL(intel_gmch_remove
);
1842 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1843 MODULE_LICENSE("GPL and additional rights");