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[media] cx231xx: add support for Hauppauge EXETER
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / media / video / cx231xx / cx231xx-avcore.c
blob64e07d335e77b755c99d53cf642ca940af4a1154
1 /*
2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102
3 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program contains the specific code to control the avdecoder chip and
8 other related usb control functions for cx231xx based chipset.
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/bitmap.h>
30 #include <linux/usb.h>
31 #include <linux/i2c.h>
32 #include <linux/mm.h>
33 #include <linux/mutex.h>
34 #include <media/tuner.h>
35
36 #include <media/v4l2-common.h>
37 #include <media/v4l2-ioctl.h>
38 #include <media/v4l2-chip-ident.h>
39
40 #include "cx231xx.h"
41 #include "cx231xx-dif.h"
42
43 #define TUNER_MODE_FM_RADIO 0
44 /******************************************************************************
45 -: BLOCK ARRANGEMENT :-
46 I2S block ----------------------|
47 [I2S audio] |
48 |
49 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
50 [video & audio] | [Audio]
51 |
52 |-> Cx25840 --> Video
53 [Video]
54
55 *******************************************************************************/
56 /******************************************************************************
57 * VERVE REGISTER *
58 * *
59 ******************************************************************************/
60 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data)
61 {
62 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS,
63 saddr, 1, data, 1);
64 }
65
66 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data)
67 {
68 int status;
69 u32 temp = 0;
70
71 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS,
72 saddr, 1, &temp, 1);
73 *data = (u8) temp;
74 return status;
75 }
76 void initGPIO(struct cx231xx *dev)
77 {
78 u32 _gpio_direction = 0;
79 u32 value = 0;
80 u8 val = 0;
81
82 _gpio_direction = _gpio_direction & 0xFC0003FF;
83 _gpio_direction = _gpio_direction | 0x03FDFC00;
84 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0);
85
86 verve_read_byte(dev, 0x07, &val);
87 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
88 verve_write_byte(dev, 0x07, 0xF4);
89 verve_read_byte(dev, 0x07, &val);
90 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val);
91
92 cx231xx_capture_start(dev, 1, 2);
93
94 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00);
95 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF);
96
97 }
98 void uninitGPIO(struct cx231xx *dev)
99 {
100 u8 value[4] = { 0, 0, 0, 0 };
101
102 cx231xx_capture_start(dev, 0, 2);
103 verve_write_byte(dev, 0x07, 0x14);
104 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
105 0x68, value, 4);
106 }
107
108 /******************************************************************************
109 * A F E - B L O C K C O N T R O L functions *
110 * [ANALOG FRONT END] *
111 ******************************************************************************/
112 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
113 {
114 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
115 saddr, 2, data, 1);
116 }
117
118 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
119 {
120 int status;
121 u32 temp = 0;
122
123 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
124 saddr, 2, &temp, 1);
125 *data = (u8) temp;
126 return status;
127 }
128
129 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
130 {
131 int status = 0;
132 u8 temp = 0;
133 u8 afe_power_status = 0;
134 int i = 0;
135
136 /* super block initialize */
137 temp = (u8) (ref_count & 0xff);
138 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
139 if (status < 0)
140 return status;
141
142 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
143 if (status < 0)
144 return status;
145
146 temp = (u8) ((ref_count & 0x300) >> 8);
147 temp |= 0x40;
148 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
149 if (status < 0)
150 return status;
151
152 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
153 if (status < 0)
154 return status;
155
156 /* enable pll */
157 while (afe_power_status != 0x18) {
158 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
159 if (status < 0) {
160 cx231xx_info(
161 ": Init Super Block failed in send cmd\n");
162 break;
163 }
164
165 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
166 afe_power_status &= 0xff;
167 if (status < 0) {
168 cx231xx_info(
169 ": Init Super Block failed in receive cmd\n");
170 break;
171 }
172 i++;
173 if (i == 10) {
174 cx231xx_info(
175 ": Init Super Block force break in loop !!!!\n");
176 status = -1;
177 break;
178 }
179 }
180
181 if (status < 0)
182 return status;
183
184 /* start tuning filter */
185 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
186 if (status < 0)
187 return status;
188
189 msleep(5);
190
191 /* exit tuning */
192 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
193
194 return status;
195 }
196
197 int cx231xx_afe_init_channels(struct cx231xx *dev)
198 {
199 int status = 0;
200
201 /* power up all 3 channels, clear pd_buffer */
202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
204 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
205
206 /* Enable quantizer calibration */
207 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
208
209 /* channel initialize, force modulator (fb) reset */
210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
213
214 /* start quantilizer calibration */
215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
217 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
218 msleep(5);
219
220 /* exit modulator (fb) reset */
221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
223 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
224
225 /* enable the pre_clamp in each channel for single-ended input */
226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
228 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
229
230 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
231 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
232 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
233 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
234 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
235 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
236 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
237
238 /* dynamic element matching off */
239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
241 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
242
243 return status;
244 }
245
246 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
247 {
248 u8 c_value = 0;
249 int status = 0;
250
251 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
252 c_value &= (~(0x50));
253 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
254
255 return status;
256 }
257
258 /*
259 The Analog Front End in Cx231xx has 3 channels. These
260 channels are used to share between different inputs
261 like tuner, s-video and composite inputs.
262
263 channel 1 ----- pin 1 to pin4(in reg is 1-4)
264 channel 2 ----- pin 5 to pin8(in reg is 5-8)
265 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
266 */
267 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
268 {
269 u8 ch1_setting = (u8) input_mux;
270 u8 ch2_setting = (u8) (input_mux >> 8);
271 u8 ch3_setting = (u8) (input_mux >> 16);
272 int status = 0;
273 u8 value = 0;
274
275 if (ch1_setting != 0) {
276 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
277 value &= (!INPUT_SEL_MASK);
278 value |= (ch1_setting - 1) << 4;
279 value &= 0xff;
280 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
281 }
282
283 if (ch2_setting != 0) {
284 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
285 value &= (!INPUT_SEL_MASK);
286 value |= (ch2_setting - 1) << 4;
287 value &= 0xff;
288 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
289 }
290
291 /* For ch3_setting, the value to put in the register is
292 7 less than the input number */
293 if (ch3_setting != 0) {
294 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
295 value &= (!INPUT_SEL_MASK);
296 value |= (ch3_setting - 1) << 4;
297 value &= 0xff;
298 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
299 }
300
301 return status;
302 }
303
304 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
305 {
306 int status = 0;
307
308 /*
309 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
310 * Currently, only baseband works.
311 */
312
313 switch (mode) {
314 case AFE_MODE_LOW_IF:
315 cx231xx_Setup_AFE_for_LowIF(dev);
316 break;
317 case AFE_MODE_BASEBAND:
318 status = cx231xx_afe_setup_AFE_for_baseband(dev);
319 break;
320 case AFE_MODE_EU_HI_IF:
321 /* SetupAFEforEuHiIF(); */
322 break;
323 case AFE_MODE_US_HI_IF:
324 /* SetupAFEforUsHiIF(); */
325 break;
326 case AFE_MODE_JAPAN_HI_IF:
327 /* SetupAFEforJapanHiIF(); */
328 break;
329 }
330
331 if ((mode != dev->afe_mode) &&
332 (dev->video_input == CX231XX_VMUX_TELEVISION))
333 status = cx231xx_afe_adjust_ref_count(dev,
334 CX231XX_VMUX_TELEVISION);
335
336 dev->afe_mode = mode;
337
338 return status;
339 }
340
341 int cx231xx_afe_update_power_control(struct cx231xx *dev,
342 enum AV_MODE avmode)
343 {
344 u8 afe_power_status = 0;
345 int status = 0;
346
347 switch (dev->model) {
348 case CX231XX_BOARD_CNXT_CARRAERA:
349 case CX231XX_BOARD_CNXT_RDE_250:
350 case CX231XX_BOARD_CNXT_SHELBY:
351 case CX231XX_BOARD_CNXT_RDU_250:
352 case CX231XX_BOARD_CNXT_RDE_253S:
353 case CX231XX_BOARD_CNXT_RDU_253S:
354 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
355 case CX231XX_BOARD_HAUPPAUGE_EXETER:
356 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
357 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
358 FLD_PWRDN_ENABLE_PLL)) {
359 status = afe_write_byte(dev, SUP_BLK_PWRDN,
360 FLD_PWRDN_TUNING_BIAS |
361 FLD_PWRDN_ENABLE_PLL);
362 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
363 &afe_power_status);
364 if (status < 0)
365 break;
366 }
367
368 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
369 0x00);
370 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
371 0x00);
372 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
373 0x00);
374 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
375 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
376 0x70);
377 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
378 0x70);
379 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
380 0x70);
381
382 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
383 &afe_power_status);
384 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
385 FLD_PWRDN_PD_BIAS |
386 FLD_PWRDN_PD_TUNECK;
387 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
388 afe_power_status);
389 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
390 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
391 FLD_PWRDN_ENABLE_PLL)) {
392 status = afe_write_byte(dev, SUP_BLK_PWRDN,
393 FLD_PWRDN_TUNING_BIAS |
394 FLD_PWRDN_ENABLE_PLL);
395 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
396 &afe_power_status);
397 if (status < 0)
398 break;
399 }
400
401 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
402 0x00);
403 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
404 0x00);
405 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
406 0x00);
407 } else {
408 cx231xx_info("Invalid AV mode input\n");
409 status = -1;
410 }
411 break;
412 default:
413 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
414 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
415 FLD_PWRDN_ENABLE_PLL)) {
416 status = afe_write_byte(dev, SUP_BLK_PWRDN,
417 FLD_PWRDN_TUNING_BIAS |
418 FLD_PWRDN_ENABLE_PLL);
419 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
420 &afe_power_status);
421 if (status < 0)
422 break;
423 }
424
425 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
426 0x40);
427 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
428 0x40);
429 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
430 0x00);
431 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
432 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
433 0x70);
434 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
435 0x70);
436 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
437 0x70);
438
439 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
440 &afe_power_status);
441 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
442 FLD_PWRDN_PD_BIAS |
443 FLD_PWRDN_PD_TUNECK;
444 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
445 afe_power_status);
446 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
447 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
448 FLD_PWRDN_ENABLE_PLL)) {
449 status = afe_write_byte(dev, SUP_BLK_PWRDN,
450 FLD_PWRDN_TUNING_BIAS |
451 FLD_PWRDN_ENABLE_PLL);
452 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
453 &afe_power_status);
454 if (status < 0)
455 break;
456 }
457
458 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
459 0x00);
460 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
461 0x00);
462 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
463 0x40);
464 } else {
465 cx231xx_info("Invalid AV mode input\n");
466 status = -1;
467 }
468 } /* switch */
469
470 return status;
471 }
472
473 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
474 {
475 u8 input_mode = 0;
476 u8 ntf_mode = 0;
477 int status = 0;
478
479 dev->video_input = video_input;
480
481 if (video_input == CX231XX_VMUX_TELEVISION) {
482 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
483 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
484 &ntf_mode);
485 } else {
486 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
487 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
488 &ntf_mode);
489 }
490
491 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
492
493 switch (input_mode) {
494 case SINGLE_ENDED:
495 dev->afe_ref_count = 0x23C;
496 break;
497 case LOW_IF:
498 dev->afe_ref_count = 0x24C;
499 break;
500 case EU_IF:
501 dev->afe_ref_count = 0x258;
502 break;
503 case US_IF:
504 dev->afe_ref_count = 0x260;
505 break;
506 default:
507 break;
508 }
509
510 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
511
512 return status;
513 }
514
515 /******************************************************************************
516 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
517 ******************************************************************************/
518 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
519 {
520 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
521 saddr, 2, data, 1);
522 }
523
524 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
525 {
526 int status;
527 u32 temp = 0;
528
529 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
530 saddr, 2, &temp, 1);
531 *data = (u8) temp;
532 return status;
533 }
534
535 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
536 {
537 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
538 saddr, 2, data, 4);
539 }
540
541 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
542 {
543 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
544 saddr, 2, data, 4);
545 }
546 int cx231xx_check_fw(struct cx231xx *dev)
547 {
548 u8 temp = 0;
549 int status = 0;
550 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp);
551 if (status < 0)
552 return status;
553 else
554 return temp;
555
556 }
557
558 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
559 {
560 int status = 0;
561
562 switch (INPUT(input)->type) {
563 case CX231XX_VMUX_COMPOSITE1:
564 case CX231XX_VMUX_SVIDEO:
565 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
566 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
567 /* External AV */
568 status = cx231xx_set_power_mode(dev,
569 POLARIS_AVMODE_ENXTERNAL_AV);
570 if (status < 0) {
571 cx231xx_errdev("%s: set_power_mode : Failed to"
572 " set Power - errCode [%d]!\n",
573 __func__, status);
574 return status;
575 }
576 }
577 status = cx231xx_set_decoder_video_input(dev,
578 INPUT(input)->type,
579 INPUT(input)->vmux);
580 break;
581 case CX231XX_VMUX_TELEVISION:
582 case CX231XX_VMUX_CABLE:
583 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
584 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
585 /* Tuner */
586 status = cx231xx_set_power_mode(dev,
587 POLARIS_AVMODE_ANALOGT_TV);
588 if (status < 0) {
589 cx231xx_errdev("%s: set_power_mode:Failed"
590 " to set Power - errCode [%d]!\n",
591 __func__, status);
592 return status;
593 }
594 }
595 if (dev->tuner_type == TUNER_NXP_TDA18271)
596 status = cx231xx_set_decoder_video_input(dev,
597 CX231XX_VMUX_TELEVISION,
598 INPUT(input)->vmux);
599 else
600 status = cx231xx_set_decoder_video_input(dev,
601 CX231XX_VMUX_COMPOSITE1,
602 INPUT(input)->vmux);
603
604 break;
605 default:
606 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
607 __func__, INPUT(input)->type);
608 break;
609 }
610
611 /* save the selection */
612 dev->video_input = input;
613
614 return status;
615 }
616
617 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
618 u8 pin_type, u8 input)
619 {
620 int status = 0;
621 u32 value = 0;
622
623 if (pin_type != dev->video_input) {
624 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
625 if (status < 0) {
626 cx231xx_errdev("%s: adjust_ref_count :Failed to set"
627 "AFE input mux - errCode [%d]!\n",
628 __func__, status);
629 return status;
630 }
631 }
632
633 /* call afe block to set video inputs */
634 status = cx231xx_afe_set_input_mux(dev, input);
635 if (status < 0) {
636 cx231xx_errdev("%s: set_input_mux :Failed to set"
637 " AFE input mux - errCode [%d]!\n",
638 __func__, status);
639 return status;
640 }
641
642 switch (pin_type) {
643 case CX231XX_VMUX_COMPOSITE1:
644 status = vid_blk_read_word(dev, AFE_CTRL, &value);
645 value |= (0 << 13) | (1 << 4);
646 value &= ~(1 << 5);
647
648 /* set [24:23] [22:15] to 0 */
649 value &= (~(0x1ff8000));
650 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
651 value |= 0x1000000;
652 status = vid_blk_write_word(dev, AFE_CTRL, value);
653
654 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
655 value |= (1 << 7);
656 status = vid_blk_write_word(dev, OUT_CTRL1, value);
657
658 /* Set vip 1.1 output mode */
659 status = cx231xx_read_modify_write_i2c_dword(dev,
660 VID_BLK_I2C_ADDRESS,
661 OUT_CTRL1,
662 FLD_OUT_MODE,
663 OUT_MODE_VIP11);
664
665 /* Tell DIF object to go to baseband mode */
666 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
667 if (status < 0) {
668 cx231xx_errdev("%s: cx231xx_dif set to By pass"
669 " mode- errCode [%d]!\n",
670 __func__, status);
671 return status;
672 }
673
674 /* Read the DFE_CTRL1 register */
675 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
676
677 /* enable the VBI_GATE_EN */
678 value |= FLD_VBI_GATE_EN;
679
680 /* Enable the auto-VGA enable */
681 value |= FLD_VGA_AUTO_EN;
682
683 /* Write it back */
684 status = vid_blk_write_word(dev, DFE_CTRL1, value);
685
686 /* Disable auto config of registers */
687 status = cx231xx_read_modify_write_i2c_dword(dev,
688 VID_BLK_I2C_ADDRESS,
689 MODE_CTRL, FLD_ACFG_DIS,
690 cx231xx_set_field(FLD_ACFG_DIS, 1));
691
692 /* Set CVBS input mode */
693 status = cx231xx_read_modify_write_i2c_dword(dev,
694 VID_BLK_I2C_ADDRESS,
695 MODE_CTRL, FLD_INPUT_MODE,
696 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
697 break;
698 case CX231XX_VMUX_SVIDEO:
699 /* Disable the use of DIF */
700
701 status = vid_blk_read_word(dev, AFE_CTRL, &value);
702
703 /* set [24:23] [22:15] to 0 */
704 value &= (~(0x1ff8000));
705 /* set FUNC_MODE[24:23] = 2
706 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
707 value |= 0x1000010;
708 status = vid_blk_write_word(dev, AFE_CTRL, value);
709
710 /* Tell DIF object to go to baseband mode */
711 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
712 if (status < 0) {
713 cx231xx_errdev("%s: cx231xx_dif set to By pass"
714 " mode- errCode [%d]!\n",
715 __func__, status);
716 return status;
717 }
718
719 /* Read the DFE_CTRL1 register */
720 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
721
722 /* enable the VBI_GATE_EN */
723 value |= FLD_VBI_GATE_EN;
724
725 /* Enable the auto-VGA enable */
726 value |= FLD_VGA_AUTO_EN;
727
728 /* Write it back */
729 status = vid_blk_write_word(dev, DFE_CTRL1, value);
730
731 /* Disable auto config of registers */
732 status = cx231xx_read_modify_write_i2c_dword(dev,
733 VID_BLK_I2C_ADDRESS,
734 MODE_CTRL, FLD_ACFG_DIS,
735 cx231xx_set_field(FLD_ACFG_DIS, 1));
736
737 /* Set YC input mode */
738 status = cx231xx_read_modify_write_i2c_dword(dev,
739 VID_BLK_I2C_ADDRESS,
740 MODE_CTRL,
741 FLD_INPUT_MODE,
742 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
743
744 /* Chroma to ADC2 */
745 status = vid_blk_read_word(dev, AFE_CTRL, &value);
746 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
747
748 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
749 This sets them to use video
750 rather than audio. Only one of the two will be in use. */
751 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
752
753 status = vid_blk_write_word(dev, AFE_CTRL, value);
754
755 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
756 break;
757 case CX231XX_VMUX_TELEVISION:
758 case CX231XX_VMUX_CABLE:
759 default:
760 switch (dev->model) {
761 case CX231XX_BOARD_CNXT_CARRAERA:
762 case CX231XX_BOARD_CNXT_RDE_250:
763 case CX231XX_BOARD_CNXT_SHELBY:
764 case CX231XX_BOARD_CNXT_RDU_250:
765 /* Disable the use of DIF */
766
767 status = vid_blk_read_word(dev, AFE_CTRL, &value);
768 value |= (0 << 13) | (1 << 4);
769 value &= ~(1 << 5);
770
771 /* set [24:23] [22:15] to 0 */
772 value &= (~(0x1FF8000));
773 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
774 value |= 0x1000000;
775 status = vid_blk_write_word(dev, AFE_CTRL, value);
776
777 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
778 value |= (1 << 7);
779 status = vid_blk_write_word(dev, OUT_CTRL1, value);
780
781 /* Set vip 1.1 output mode */
782 status = cx231xx_read_modify_write_i2c_dword(dev,
783 VID_BLK_I2C_ADDRESS,
784 OUT_CTRL1, FLD_OUT_MODE,
785 OUT_MODE_VIP11);
786
787 /* Tell DIF object to go to baseband mode */
788 status = cx231xx_dif_set_standard(dev,
789 DIF_USE_BASEBAND);
790 if (status < 0) {
791 cx231xx_errdev("%s: cx231xx_dif set to By pass"
792 " mode- errCode [%d]!\n",
793 __func__, status);
794 return status;
795 }
796
797 /* Read the DFE_CTRL1 register */
798 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
799
800 /* enable the VBI_GATE_EN */
801 value |= FLD_VBI_GATE_EN;
802
803 /* Enable the auto-VGA enable */
804 value |= FLD_VGA_AUTO_EN;
805
806 /* Write it back */
807 status = vid_blk_write_word(dev, DFE_CTRL1, value);
808
809 /* Disable auto config of registers */
810 status = cx231xx_read_modify_write_i2c_dword(dev,
811 VID_BLK_I2C_ADDRESS,
812 MODE_CTRL, FLD_ACFG_DIS,
813 cx231xx_set_field(FLD_ACFG_DIS, 1));
814
815 /* Set CVBS input mode */
816 status = cx231xx_read_modify_write_i2c_dword(dev,
817 VID_BLK_I2C_ADDRESS,
818 MODE_CTRL, FLD_INPUT_MODE,
819 cx231xx_set_field(FLD_INPUT_MODE,
820 INPUT_MODE_CVBS_0));
821 break;
822 default:
823 /* Enable the DIF for the tuner */
824
825 /* Reinitialize the DIF */
826 status = cx231xx_dif_set_standard(dev, dev->norm);
827 if (status < 0) {
828 cx231xx_errdev("%s: cx231xx_dif set to By pass"
829 " mode- errCode [%d]!\n",
830 __func__, status);
831 return status;
832 }
833
834 /* Make sure bypass is cleared */
835 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
836
837 /* Clear the bypass bit */
838 value &= ~FLD_DIF_DIF_BYPASS;
839
840 /* Enable the use of the DIF block */
841 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
842
843 /* Read the DFE_CTRL1 register */
844 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
845
846 /* Disable the VBI_GATE_EN */
847 value &= ~FLD_VBI_GATE_EN;
848
849 /* Enable the auto-VGA enable, AGC, and
850 set the skip count to 2 */
851 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
852
853 /* Write it back */
854 status = vid_blk_write_word(dev, DFE_CTRL1, value);
855
856 /* Wait until AGC locks up */
857 msleep(1);
858
859 /* Disable the auto-VGA enable AGC */
860 value &= ~(FLD_VGA_AUTO_EN);
861
862 /* Write it back */
863 status = vid_blk_write_word(dev, DFE_CTRL1, value);
864
865 /* Enable Polaris B0 AGC output */
866 status = vid_blk_read_word(dev, PIN_CTRL, &value);
867 value |= (FLD_OEF_AGC_RF) |
868 (FLD_OEF_AGC_IFVGA) |
869 (FLD_OEF_AGC_IF);
870 status = vid_blk_write_word(dev, PIN_CTRL, value);
871
872 /* Set vip 1.1 output mode */
873 status = cx231xx_read_modify_write_i2c_dword(dev,
874 VID_BLK_I2C_ADDRESS,
875 OUT_CTRL1, FLD_OUT_MODE,
876 OUT_MODE_VIP11);
877
878 /* Disable auto config of registers */
879 status = cx231xx_read_modify_write_i2c_dword(dev,
880 VID_BLK_I2C_ADDRESS,
881 MODE_CTRL, FLD_ACFG_DIS,
882 cx231xx_set_field(FLD_ACFG_DIS, 1));
883
884 /* Set CVBS input mode */
885 status = cx231xx_read_modify_write_i2c_dword(dev,
886 VID_BLK_I2C_ADDRESS,
887 MODE_CTRL, FLD_INPUT_MODE,
888 cx231xx_set_field(FLD_INPUT_MODE,
889 INPUT_MODE_CVBS_0));
890
891 /* Set some bits in AFE_CTRL so that channel 2 or 3
892 * is ready to receive audio */
893 /* Clear clamp for channels 2 and 3 (bit 16-17) */
894 /* Clear droop comp (bit 19-20) */
895 /* Set VGA_SEL (for audio control) (bit 7-8) */
896 status = vid_blk_read_word(dev, AFE_CTRL, &value);
897
898 /*Set Func mode:01-DIF 10-baseband 11-YUV*/
899 value &= (~(FLD_FUNC_MODE));
900 value |= 0x800000;
901
902 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
903
904 status = vid_blk_write_word(dev, AFE_CTRL, value);
905
906 if (dev->tuner_type == TUNER_NXP_TDA18271) {
907 status = vid_blk_read_word(dev, PIN_CTRL,
908 &value);
909 status = vid_blk_write_word(dev, PIN_CTRL,
910 (value & 0xFFFFFFEF));
911 }
912
913 break;
914
915 }
916 break;
917 }
918
919 /* Set raw VBI mode */
920 status = cx231xx_read_modify_write_i2c_dword(dev,
921 VID_BLK_I2C_ADDRESS,
922 OUT_CTRL1, FLD_VBIHACTRAW_EN,
923 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
924
925 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
926 if (value & 0x02) {
927 value |= (1 << 19);
928 status = vid_blk_write_word(dev, OUT_CTRL1, value);
929 }
930
931 return status;
932 }
933
934 void cx231xx_enable656(struct cx231xx *dev)
935 {
936 u8 temp = 0;
937 int status;
938 /*enable TS1 data[0:7] as output to export 656*/
939
940 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF);
941
942 /*enable TS1 clock as output to export 656*/
943
944 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
945 temp = temp|0x04;
946
947 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
948
949 }
950 EXPORT_SYMBOL_GPL(cx231xx_enable656);
951
952 void cx231xx_disable656(struct cx231xx *dev)
953 {
954 u8 temp = 0;
955 int status;
956
957
958 status = vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00);
959
960 status = vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp);
961 temp = temp&0xFB;
962
963 status = vid_blk_write_byte(dev, TS1_PIN_CTL1, temp);
964 }
965 EXPORT_SYMBOL_GPL(cx231xx_disable656);
966
967 /*
968 * Handle any video-mode specific overrides that are different
969 * on a per video standards basis after touching the MODE_CTRL
970 * register which resets many values for autodetect
971 */
972 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
973 {
974 int status = 0;
975
976 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
977 (unsigned int)dev->norm);
978
979 /* Change the DFE_CTRL3 bp_percent to fix flagging */
980 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
981
982 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
983 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
984
985 /* Move the close caption lines out of active video,
986 adjust the active video start point */
987 status = cx231xx_read_modify_write_i2c_dword(dev,
988 VID_BLK_I2C_ADDRESS,
989 VERT_TIM_CTRL,
990 FLD_VBLANK_CNT, 0x18);
991 status = cx231xx_read_modify_write_i2c_dword(dev,
992 VID_BLK_I2C_ADDRESS,
993 VERT_TIM_CTRL,
994 FLD_VACTIVE_CNT,
995 0x1E6000);
996 status = cx231xx_read_modify_write_i2c_dword(dev,
997 VID_BLK_I2C_ADDRESS,
998 VERT_TIM_CTRL,
999 FLD_V656BLANK_CNT,
1000 0x1C000000);
1001
1002 status = cx231xx_read_modify_write_i2c_dword(dev,
1003 VID_BLK_I2C_ADDRESS,
1004 HORIZ_TIM_CTRL,
1005 FLD_HBLANK_CNT,
1006 cx231xx_set_field
1007 (FLD_HBLANK_CNT, 0x79));
1008
1009 } else if (dev->norm & V4L2_STD_SECAM) {
1010 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1011 status = cx231xx_read_modify_write_i2c_dword(dev,
1012 VID_BLK_I2C_ADDRESS,
1013 VERT_TIM_CTRL,
1014 FLD_VBLANK_CNT, 0x24);
1015 status = cx231xx_read_modify_write_i2c_dword(dev,
1016 VID_BLK_I2C_ADDRESS,
1017 VERT_TIM_CTRL,
1018 FLD_V656BLANK_CNT,
1019 cx231xx_set_field
1020 (FLD_V656BLANK_CNT,
1021 0x28));
1022 /* Adjust the active video horizontal start point */
1023 status = cx231xx_read_modify_write_i2c_dword(dev,
1024 VID_BLK_I2C_ADDRESS,
1025 HORIZ_TIM_CTRL,
1026 FLD_HBLANK_CNT,
1027 cx231xx_set_field
1028 (FLD_HBLANK_CNT, 0x85));
1029 } else {
1030 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1031 status = cx231xx_read_modify_write_i2c_dword(dev,
1032 VID_BLK_I2C_ADDRESS,
1033 VERT_TIM_CTRL,
1034 FLD_VBLANK_CNT, 0x24);
1035 status = cx231xx_read_modify_write_i2c_dword(dev,
1036 VID_BLK_I2C_ADDRESS,
1037 VERT_TIM_CTRL,
1038 FLD_V656BLANK_CNT,
1039 cx231xx_set_field
1040 (FLD_V656BLANK_CNT,
1041 0x28));
1042 /* Adjust the active video horizontal start point */
1043 status = cx231xx_read_modify_write_i2c_dword(dev,
1044 VID_BLK_I2C_ADDRESS,
1045 HORIZ_TIM_CTRL,
1046 FLD_HBLANK_CNT,
1047 cx231xx_set_field
1048 (FLD_HBLANK_CNT, 0x85));
1049
1050 }
1051
1052 return status;
1053 }
1054
1055 int cx231xx_unmute_audio(struct cx231xx *dev)
1056 {
1057 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24);
1058 }
1059 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio);
1060
1061 int stopAudioFirmware(struct cx231xx *dev)
1062 {
1063 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03);
1064 }
1065
1066 int restartAudioFirmware(struct cx231xx *dev)
1067 {
1068 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13);
1069 }
1070
1071 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1072 {
1073 int status = 0;
1074 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1075
1076 switch (INPUT(input)->amux) {
1077 case CX231XX_AMUX_VIDEO:
1078 ainput = AUDIO_INPUT_TUNER_TV;
1079 break;
1080 case CX231XX_AMUX_LINE_IN:
1081 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1082 ainput = AUDIO_INPUT_LINE;
1083 break;
1084 default:
1085 break;
1086 }
1087
1088 status = cx231xx_set_audio_decoder_input(dev, ainput);
1089
1090 return status;
1091 }
1092
1093 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1094 enum AUDIO_INPUT audio_input)
1095 {
1096 u32 dwval;
1097 int status;
1098 u8 gen_ctrl;
1099 u32 value = 0;
1100
1101 /* Put it in soft reset */
1102 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1103 gen_ctrl |= 1;
1104 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1105
1106 switch (audio_input) {
1107 case AUDIO_INPUT_LINE:
1108 /* setup AUD_IO control from Merlin paralle output */
1109 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1110 AUD_CHAN_SRC_PARALLEL);
1111 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1112
1113 /* setup input to Merlin, SRC2 connect to AC97
1114 bypass upsample-by-2, slave mode, sony mode, left justify
1115 adr 091c, dat 01000000 */
1116 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1117
1118 status = vid_blk_write_word(dev, AC97_CTL,
1119 (dwval | FLD_AC97_UP2X_BYPASS));
1120
1121 /* select the parallel1 and SRC3 */
1122 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1123 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1124 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1125 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1126
1127 /* unmute all, AC97 in, independence mode
1128 adr 08d0, data 0x00063073 */
1129 status = vid_blk_write_word(dev, DL_CTL, 0x3000001);
1130 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1131
1132 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1133 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1134 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1135 (dwval | FLD_PATH1_AVC_THRESHOLD));
1136
1137 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1138 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1139 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1140 (dwval | FLD_PATH1_SC_THRESHOLD));
1141 break;
1142
1143 case AUDIO_INPUT_TUNER_TV:
1144 default:
1145 status = stopAudioFirmware(dev);
1146 /* Setup SRC sources and clocks */
1147 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1148 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1149 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1150 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
1151 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) |
1152 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) |
1153 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) |
1154 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) |
1155 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) |
1156 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1157 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1158 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1159 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1160 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1161
1162 /* Setup the AUD_IO control */
1163 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1164 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1165 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1166 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1167 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1168 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1169
1170 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1171
1172 /* setAudioStandard(_audio_standard); */
1173 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1174
1175 status = restartAudioFirmware(dev);
1176
1177 switch (dev->model) {
1178 case CX231XX_BOARD_CNXT_CARRAERA:
1179 case CX231XX_BOARD_CNXT_RDE_250:
1180 case CX231XX_BOARD_CNXT_SHELBY:
1181 case CX231XX_BOARD_CNXT_RDU_250:
1182 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1183 status = cx231xx_read_modify_write_i2c_dword(dev,
1184 VID_BLK_I2C_ADDRESS,
1185 CHIP_CTRL,
1186 FLD_SIF_EN,
1187 cx231xx_set_field(FLD_SIF_EN, 1));
1188 break;
1189 case CX231XX_BOARD_CNXT_RDE_253S:
1190 case CX231XX_BOARD_CNXT_RDU_253S:
1191 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1192 status = cx231xx_read_modify_write_i2c_dword(dev,
1193 VID_BLK_I2C_ADDRESS,
1194 CHIP_CTRL,
1195 FLD_SIF_EN,
1196 cx231xx_set_field(FLD_SIF_EN, 0));
1197 break;
1198 default:
1199 break;
1200 }
1201 break;
1202
1203 case AUDIO_INPUT_TUNER_FM:
1204 /* use SIF for FM radio
1205 setupFM();
1206 setAudioStandard(_audio_standard);
1207 */
1208 break;
1209
1210 case AUDIO_INPUT_MUTE:
1211 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1212 break;
1213 }
1214
1215 /* Take it out of soft reset */
1216 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1217 gen_ctrl &= ~1;
1218 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1219
1220 return status;
1221 }
1222
1223 /* Set resolution of the video */
1224 int cx231xx_resolution_set(struct cx231xx *dev)
1225 {
1226 /* set horzontal scale */
1227 int status = vid_blk_write_word(dev, HSCALE_CTRL, dev->hscale);
1228 if (status)
1229 return status;
1230
1231 /* set vertical scale */
1232 status = vid_blk_write_word(dev, VSCALE_CTRL, dev->vscale);
1233
1234 return status;
1235 }
1236
1237 /******************************************************************************
1238 * C H I P Specific C O N T R O L functions *
1239 ******************************************************************************/
1240 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1241 {
1242 u32 value;
1243 int status = 0;
1244
1245 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1246 value |= (~dev->board.ctl_pin_status_mask);
1247 status = vid_blk_write_word(dev, PIN_CTRL, value);
1248
1249 return status;
1250 }
1251
1252 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1253 u8 analog_or_digital)
1254 {
1255 int status = 0;
1256
1257 /* first set the direction to output */
1258 status = cx231xx_set_gpio_direction(dev,
1259 dev->board.
1260 agc_analog_digital_select_gpio, 1);
1261
1262 /* 0 - demod ; 1 - Analog mode */
1263 status = cx231xx_set_gpio_value(dev,
1264 dev->board.agc_analog_digital_select_gpio,
1265 analog_or_digital);
1266
1267 return status;
1268 }
1269
1270 int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1271 {
1272 u8 value[4] = { 0, 0, 0, 0 };
1273 int status = 0;
1274
1275 cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1276
1277 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1278 PWR_CTL_EN, value, 4);
1279 if (status < 0)
1280 return status;
1281
1282 if (I2CIndex == I2C_1) {
1283 if (value[0] & I2C_DEMOD_EN) {
1284 value[0] &= ~I2C_DEMOD_EN;
1285 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1286 PWR_CTL_EN, value, 4);
1287 }
1288 } else {
1289 if (!(value[0] & I2C_DEMOD_EN)) {
1290 value[0] |= I2C_DEMOD_EN;
1291 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1292 PWR_CTL_EN, value, 4);
1293 }
1294 }
1295
1296 return status;
1297
1298 }
1299 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_for_tuner);
1300 void update_HH_register_after_set_DIF(struct cx231xx *dev)
1301 {
1302 /*
1303 u8 status = 0;
1304 u32 value = 0;
1305
1306 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F);
1307 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11);
1308 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06);
1309
1310 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1311 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1312 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1313 */
1314 }
1315
1316 void cx231xx_dump_HH_reg(struct cx231xx *dev)
1317 {
1318 u8 status = 0;
1319 u32 value = 0;
1320 u16 i = 0;
1321
1322 value = 0x45005390;
1323 status = vid_blk_write_word(dev, 0x104, value);
1324
1325 for (i = 0x100; i < 0x140; i++) {
1326 status = vid_blk_read_word(dev, i, &value);
1327 cx231xx_info("reg0x%x=0x%x\n", i, value);
1328 i = i+3;
1329 }
1330
1331 for (i = 0x300; i < 0x400; i++) {
1332 status = vid_blk_read_word(dev, i, &value);
1333 cx231xx_info("reg0x%x=0x%x\n", i, value);
1334 i = i+3;
1335 }
1336
1337 for (i = 0x400; i < 0x440; i++) {
1338 status = vid_blk_read_word(dev, i, &value);
1339 cx231xx_info("reg0x%x=0x%x\n", i, value);
1340 i = i+3;
1341 }
1342
1343 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1344 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1345 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390);
1346 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value);
1347 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value);
1348
1349 }
1350 void cx231xx_dump_SC_reg(struct cx231xx *dev)
1351 {
1352 u8 value[4] = { 0, 0, 0, 0 };
1353 int status = 0;
1354 cx231xx_info("cx231xx_dump_SC_reg %s!\n", __TIME__);
1355
1356 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT,
1357 value, 4);
1358 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0],
1359 value[1], value[2], value[3]);
1360 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG,
1361 value, 4);
1362 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0],
1363 value[1], value[2], value[3]);
1364 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG,
1365 value, 4);
1366 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0],
1367 value[1], value[2], value[3]);
1368 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG,
1369 value, 4);
1370 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0],
1371 value[1], value[2], value[3]);
1372
1373 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG,
1374 value, 4);
1375 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0],
1376 value[1], value[2], value[3]);
1377 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG,
1378 value, 4);
1379 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0],
1380 value[1], value[2], value[3]);
1381 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1382 value, 4);
1383 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0],
1384 value[1], value[2], value[3]);
1385 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1,
1386 value, 4);
1387 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0],
1388 value[1], value[2], value[3]);
1389
1390 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2,
1391 value, 4);
1392 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0],
1393 value[1], value[2], value[3]);
1394 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3,
1395 value, 4);
1396 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0],
1397 value[1], value[2], value[3]);
1398 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0,
1399 value, 4);
1400 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0],
1401 value[1], value[2], value[3]);
1402 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1,
1403 value, 4);
1404 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0],
1405 value[1], value[2], value[3]);
1406
1407 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2,
1408 value, 4);
1409 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0],
1410 value[1], value[2], value[3]);
1411 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN,
1412 value, 4);
1413 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0],
1414 value[1], value[2], value[3]);
1415 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG,
1416 value, 4);
1417 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0],
1418 value[1], value[2], value[3]);
1419 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1,
1420 value, 4);
1421 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0],
1422 value[1], value[2], value[3]);
1423
1424 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2,
1425 value, 4);
1426 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0],
1427 value[1], value[2], value[3]);
1428 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1429 value, 4);
1430 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0],
1431 value[1], value[2], value[3]);
1432
1433
1434 }
1435
1436 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev)
1437
1438 {
1439 u8 status = 0;
1440 u8 value = 0;
1441
1442
1443
1444 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1445 value = (value & 0xFE)|0x01;
1446 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1447
1448 status = afe_read_byte(dev, ADC_STATUS2_CH3, &value);
1449 value = (value & 0xFE)|0x00;
1450 status = afe_write_byte(dev, ADC_STATUS2_CH3, value);
1451
1452
1453 /*
1454 config colibri to lo-if mode
1455
1456 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce
1457 the diff IF input by half,
1458
1459 for low-if agc defect
1460 */
1461
1462 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value);
1463 value = (value & 0xFC)|0x00;
1464 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value);
1465
1466 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
1467 value = (value & 0xF9)|0x02;
1468 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
1469
1470 status = afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value);
1471 value = (value & 0xFB)|0x04;
1472 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, value);
1473
1474 status = afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value);
1475 value = (value & 0xFC)|0x03;
1476 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value);
1477
1478 status = afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value);
1479 value = (value & 0xFB)|0x04;
1480 status = afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value);
1481
1482 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1483 value = (value & 0xF8)|0x06;
1484 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1485
1486 status = afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value);
1487 value = (value & 0x8F)|0x40;
1488 status = afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value);
1489
1490 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value);
1491 value = (value & 0xDF)|0x20;
1492 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value);
1493 }
1494
1495 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq,
1496 u8 spectral_invert, u32 mode)
1497 {
1498
1499 u32 colibri_carrier_offset = 0;
1500 u8 status = 0;
1501 u32 func_mode = 0;
1502 u32 standard = 0;
1503 u8 value[4] = { 0, 0, 0, 0 };
1504
1505 switch (dev->model) {
1506 case CX231XX_BOARD_CNXT_CARRAERA:
1507 case CX231XX_BOARD_CNXT_RDE_250:
1508 case CX231XX_BOARD_CNXT_SHELBY:
1509 case CX231XX_BOARD_CNXT_RDU_250:
1510 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1511 func_mode = 0x03;
1512 break;
1513 case CX231XX_BOARD_CNXT_RDE_253S:
1514 case CX231XX_BOARD_CNXT_RDU_253S:
1515 func_mode = 0x01;
1516 break;
1517
1518 default:
1519 func_mode = 0x01;
1520 }
1521
1522 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n");
1523 value[0] = (u8) 0x6F;
1524 value[1] = (u8) 0x6F;
1525 value[2] = (u8) 0x6F;
1526 value[3] = (u8) 0x6F;
1527 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1528 PWR_CTL_EN, value, 4);
1529 if (1) {
1530
1531 /*Set colibri for low IF*/
1532 status = cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF);
1533
1534
1535 /* Set C2HH for low IF operation.*/
1536 standard = dev->norm;
1537 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1538 func_mode, standard);
1539
1540
1541 /* Get colibri offsets.*/
1542 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode,
1543 standard);
1544
1545 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n",
1546 colibri_carrier_offset, standard);
1547
1548 /* Set the band Pass filter for DIF*/
1549 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset)
1550 , spectral_invert, mode);
1551 }
1552 }
1553
1554 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd)
1555 {
1556 u32 colibri_carrier_offset = 0;
1557
1558
1559 if (mode == TUNER_MODE_FM_RADIO) {
1560 colibri_carrier_offset = 1100000;
1561 } else if (standerd & (V4L2_STD_NTSC | V4L2_STD_NTSC_M_JP)) {
1562 colibri_carrier_offset = 4832000; /*4.83MHz */
1563 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1564 colibri_carrier_offset = 2700000; /*2.70MHz */
1565 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I
1566 | V4L2_STD_SECAM)) {
1567 colibri_carrier_offset = 2100000; /*2.10MHz */
1568 }
1569
1570
1571 return colibri_carrier_offset;
1572 }
1573
1574 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq,
1575 u8 spectral_invert, u32 mode)
1576 {
1577
1578 unsigned long pll_freq_word;
1579 int status = 0;
1580 u32 dif_misc_ctrl_value = 0;
1581 u64 pll_freq_u64 = 0;
1582 u32 i = 0;
1583
1584
1585 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n",
1586 if_freq, spectral_invert, mode);
1587
1588
1589 if (mode == TUNER_MODE_FM_RADIO) {
1590 pll_freq_word = 0x905A1CAC;
1591 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1592
1593 } else /*KSPROPERTY_TUNER_MODE_TV*/{
1594 /* Calculate the PLL frequency word based on the adjusted if_freq*/
1595 pll_freq_word = if_freq;
1596 pll_freq_u64 = (u64)pll_freq_word << 28L;
1597 do_div(pll_freq_u64, 50000000);
1598 pll_freq_word = (u32)pll_freq_u64;
1599 /*pll_freq_word = 0x3463497;*/
1600 status = vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word);
1601
1602 if (spectral_invert) {
1603 if_freq -= 400000;
1604 /* Enable Spectral Invert*/
1605 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1606 &dif_misc_ctrl_value);
1607 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000;
1608 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1609 dif_misc_ctrl_value);
1610 } else {
1611 if_freq += 400000;
1612 /* Disable Spectral Invert*/
1613 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1614 &dif_misc_ctrl_value);
1615 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF;
1616 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1617 dif_misc_ctrl_value);
1618 }
1619
1620 if_freq = (if_freq/100000)*100000;
1621
1622 if (if_freq < 3000000)
1623 if_freq = 3000000;
1624
1625 if (if_freq > 16000000)
1626 if_freq = 16000000;
1627 }
1628
1629 cx231xx_info("Enter IF=%d\n",
1630 sizeof(Dif_set_array)/sizeof(struct dif_settings));
1631 for (i = 0; i < sizeof(Dif_set_array)/sizeof(struct dif_settings); i++) {
1632 if (Dif_set_array[i].if_freq == if_freq) {
1633 status = vid_blk_write_word(dev,
1634 Dif_set_array[i].register_address, Dif_set_array[i].value);
1635 }
1636 }
1637
1638 }
1639
1640 /******************************************************************************
1641 * D I F - B L O C K C O N T R O L functions *
1642 ******************************************************************************/
1643 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1644 u32 function_mode, u32 standard)
1645 {
1646 int status = 0;
1647
1648
1649 if (mode == V4L2_TUNER_RADIO) {
1650 /* C2HH */
1651 /* lo if big signal */
1652 status = cx231xx_reg_mask_write(dev,
1653 VID_BLK_I2C_ADDRESS, 32,
1654 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1655 /* FUNC_MODE = DIF */
1656 status = cx231xx_reg_mask_write(dev,
1657 VID_BLK_I2C_ADDRESS, 32,
1658 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1659 /* IF_MODE */
1660 status = cx231xx_reg_mask_write(dev,
1661 VID_BLK_I2C_ADDRESS, 32,
1662 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1663 /* no inv */
1664 status = cx231xx_reg_mask_write(dev,
1665 VID_BLK_I2C_ADDRESS, 32,
1666 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1667 } else if (standard != DIF_USE_BASEBAND) {
1668 if (standard & V4L2_STD_MN) {
1669 /* lo if big signal */
1670 status = cx231xx_reg_mask_write(dev,
1671 VID_BLK_I2C_ADDRESS, 32,
1672 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1673 /* FUNC_MODE = DIF */
1674 status = cx231xx_reg_mask_write(dev,
1675 VID_BLK_I2C_ADDRESS, 32,
1676 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1677 function_mode);
1678 /* IF_MODE */
1679 status = cx231xx_reg_mask_write(dev,
1680 VID_BLK_I2C_ADDRESS, 32,
1681 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1682 /* no inv */
1683 status = cx231xx_reg_mask_write(dev,
1684 VID_BLK_I2C_ADDRESS, 32,
1685 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1686 /* 0x124, AUD_CHAN1_SRC = 0x3 */
1687 status = cx231xx_reg_mask_write(dev,
1688 VID_BLK_I2C_ADDRESS, 32,
1689 AUD_IO_CTRL, 0, 31, 0x00000003);
1690 } else if ((standard == V4L2_STD_PAL_I) |
1691 (standard & V4L2_STD_PAL_D) |
1692 (standard & V4L2_STD_SECAM)) {
1693 /* C2HH setup */
1694 /* lo if big signal */
1695 status = cx231xx_reg_mask_write(dev,
1696 VID_BLK_I2C_ADDRESS, 32,
1697 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1698 /* FUNC_MODE = DIF */
1699 status = cx231xx_reg_mask_write(dev,
1700 VID_BLK_I2C_ADDRESS, 32,
1701 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1702 function_mode);
1703 /* IF_MODE */
1704 status = cx231xx_reg_mask_write(dev,
1705 VID_BLK_I2C_ADDRESS, 32,
1706 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1707 /* no inv */
1708 status = cx231xx_reg_mask_write(dev,
1709 VID_BLK_I2C_ADDRESS, 32,
1710 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1711 } else {
1712 /* default PAL BG */
1713 /* C2HH setup */
1714 /* lo if big signal */
1715 status = cx231xx_reg_mask_write(dev,
1716 VID_BLK_I2C_ADDRESS, 32,
1717 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1718 /* FUNC_MODE = DIF */
1719 status = cx231xx_reg_mask_write(dev,
1720 VID_BLK_I2C_ADDRESS, 32,
1721 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1722 function_mode);
1723 /* IF_MODE */
1724 status = cx231xx_reg_mask_write(dev,
1725 VID_BLK_I2C_ADDRESS, 32,
1726 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1727 /* no inv */
1728 status = cx231xx_reg_mask_write(dev,
1729 VID_BLK_I2C_ADDRESS, 32,
1730 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1731 }
1732 }
1733
1734 return status;
1735 }
1736
1737 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1738 {
1739 int status = 0;
1740 u32 dif_misc_ctrl_value = 0;
1741 u32 func_mode = 0;
1742
1743 cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1744
1745 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1746 if (standard != DIF_USE_BASEBAND)
1747 dev->norm = standard;
1748
1749 switch (dev->model) {
1750 case CX231XX_BOARD_CNXT_CARRAERA:
1751 case CX231XX_BOARD_CNXT_RDE_250:
1752 case CX231XX_BOARD_CNXT_SHELBY:
1753 case CX231XX_BOARD_CNXT_RDU_250:
1754 case CX231XX_BOARD_CNXT_VIDEO_GRABBER:
1755 case CX231XX_BOARD_HAUPPAUGE_EXETER:
1756 func_mode = 0x03;
1757 break;
1758 case CX231XX_BOARD_CNXT_RDE_253S:
1759 case CX231XX_BOARD_CNXT_RDU_253S:
1760 func_mode = 0x01;
1761 break;
1762 default:
1763 func_mode = 0x01;
1764 }
1765
1766 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1767 func_mode, standard);
1768
1769 if (standard == DIF_USE_BASEBAND) { /* base band */
1770 /* There is a different SRC_PHASE_INC value
1771 for baseband vs. DIF */
1772 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1773 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1774 &dif_misc_ctrl_value);
1775 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1776 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1777 dif_misc_ctrl_value);
1778 } else if (standard & V4L2_STD_PAL_D) {
1779 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1780 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1781 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1782 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1783 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1784 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1785 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1786 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1787 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1788 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1789 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1790 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1791 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1792 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1793 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1794 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1796 DIF_AGC_IF_INT_CURRENT, 0, 31,
1797 0x26001700);
1798 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1799 DIF_AGC_RF_CURRENT, 0, 31,
1800 0x00002660);
1801 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1802 DIF_VIDEO_AGC_CTRL, 0, 31,
1803 0x72500800);
1804 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1805 DIF_VID_AUD_OVERRIDE, 0, 31,
1806 0x27000100);
1807 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1808 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1809 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1810 DIF_COMP_FLT_CTRL, 0, 31,
1811 0x00000000);
1812 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1813 DIF_SRC_PHASE_INC, 0, 31,
1814 0x1befbf06);
1815 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1816 DIF_SRC_GAIN_CONTROL, 0, 31,
1817 0x000035e8);
1818 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1819 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1820 /* Save the Spec Inversion value */
1821 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1822 dif_misc_ctrl_value |= 0x3a023F11;
1823 } else if (standard & V4L2_STD_PAL_I) {
1824 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1825 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1826 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1827 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1828 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1829 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1830 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1831 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1832 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1833 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1834 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1835 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1836 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1837 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1838 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1839 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1840 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1841 DIF_AGC_IF_INT_CURRENT, 0, 31,
1842 0x26001700);
1843 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1844 DIF_AGC_RF_CURRENT, 0, 31,
1845 0x00002660);
1846 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1847 DIF_VIDEO_AGC_CTRL, 0, 31,
1848 0x72500800);
1849 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1850 DIF_VID_AUD_OVERRIDE, 0, 31,
1851 0x27000100);
1852 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1853 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1854 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1855 DIF_COMP_FLT_CTRL, 0, 31,
1856 0x00000000);
1857 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1858 DIF_SRC_PHASE_INC, 0, 31,
1859 0x1befbf06);
1860 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1861 DIF_SRC_GAIN_CONTROL, 0, 31,
1862 0x000035e8);
1863 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1864 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1865 /* Save the Spec Inversion value */
1866 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1867 dif_misc_ctrl_value |= 0x3a033F11;
1868 } else if (standard & V4L2_STD_PAL_M) {
1869 /* improved Low Frequency Phase Noise */
1870 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1871 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1872 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1873 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1874 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1875 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1876 0x26001700);
1877 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1878 0x00002660);
1879 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1880 0x72500800);
1881 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1882 0x27000100);
1883 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1884 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1885 0x009f50c1);
1886 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1887 0x1befbf06);
1888 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1889 0x000035e8);
1890 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1891 0x00000000);
1892 /* Save the Spec Inversion value */
1893 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1894 dif_misc_ctrl_value |= 0x3A0A3F10;
1895 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1896 /* improved Low Frequency Phase Noise */
1897 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1898 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1899 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1900 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1901 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1902 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1903 0x26001700);
1904 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1905 0x00002660);
1906 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1907 0x72500800);
1908 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1909 0x27000100);
1910 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1911 0x012c405d);
1912 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1913 0x009f50c1);
1914 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1915 0x1befbf06);
1916 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1917 0x000035e8);
1918 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1919 0x00000000);
1920 /* Save the Spec Inversion value */
1921 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1922 dif_misc_ctrl_value = 0x3A093F10;
1923 } else if (standard &
1924 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1925 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1926
1927 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1928 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1929 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1930 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1931 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1932 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1933 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1934 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1935 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1936 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1937 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1938 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1939 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1940 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1941 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1942 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1943 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1944 DIF_AGC_IF_INT_CURRENT, 0, 31,
1945 0x26001700);
1946 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1947 DIF_AGC_RF_CURRENT, 0, 31,
1948 0x00002660);
1949 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1950 DIF_VID_AUD_OVERRIDE, 0, 31,
1951 0x27000100);
1952 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1953 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1954 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1955 DIF_COMP_FLT_CTRL, 0, 31,
1956 0x00000000);
1957 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1958 DIF_SRC_PHASE_INC, 0, 31,
1959 0x1befbf06);
1960 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1961 DIF_SRC_GAIN_CONTROL, 0, 31,
1962 0x000035e8);
1963 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1964 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1965 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1966 DIF_VIDEO_AGC_CTRL, 0, 31,
1967 0xf4000000);
1968
1969 /* Save the Spec Inversion value */
1970 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1971 dif_misc_ctrl_value |= 0x3a023F11;
1972 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1973 /* Is it SECAM_L1? */
1974 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1975 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1976 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1977 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1978 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1979 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1980 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1981 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1982 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1983 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1984 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1985 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1986 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1987 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1988 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1989 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1990 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1991 DIF_AGC_IF_INT_CURRENT, 0, 31,
1992 0x26001700);
1993 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1994 DIF_AGC_RF_CURRENT, 0, 31,
1995 0x00002660);
1996 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1997 DIF_VID_AUD_OVERRIDE, 0, 31,
1998 0x27000100);
1999 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2000 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
2001 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2002 DIF_COMP_FLT_CTRL, 0, 31,
2003 0x00000000);
2004 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2005 DIF_SRC_PHASE_INC, 0, 31,
2006 0x1befbf06);
2007 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2008 DIF_SRC_GAIN_CONTROL, 0, 31,
2009 0x000035e8);
2010 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2011 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2012 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2013 DIF_VIDEO_AGC_CTRL, 0, 31,
2014 0xf2560000);
2015
2016 /* Save the Spec Inversion value */
2017 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2018 dif_misc_ctrl_value |= 0x3a023F11;
2019
2020 } else if (standard & V4L2_STD_NTSC_M) {
2021 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
2022 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
2023
2024 /* For NTSC the centre frequency of video coming out of
2025 sidewinder is around 7.1MHz or 3.6MHz depending on the
2026 spectral inversion. so for a non spectrally inverted channel
2027 the pll freq word is 0x03420c49
2028 */
2029
2030 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
2031 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
2032 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
2033 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
2034 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
2035 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
2036 0x26001700);
2037 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
2038 0x00002660);
2039 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
2040 0x04000800);
2041 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
2042 0x27000100);
2043 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
2044
2045 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
2046 0x009f50c1);
2047 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
2048 0x1befbf06);
2049 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
2050 0x000035e8);
2051
2052 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
2053 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
2054 0xC2262600);
2055 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
2056
2057 /* Save the Spec Inversion value */
2058 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2059 dif_misc_ctrl_value |= 0x3a003F10;
2060 } else {
2061 /* default PAL BG */
2062 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2063 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
2064 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2065 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
2066 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2067 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
2068 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2069 DIF_PLL_CTRL3, 0, 31, 0x00008800);
2070 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2071 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
2072 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2073 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
2074 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2075 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
2076 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2077 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
2078 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2079 DIF_AGC_IF_INT_CURRENT, 0, 31,
2080 0x26001700);
2081 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2082 DIF_AGC_RF_CURRENT, 0, 31,
2083 0x00002660);
2084 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2085 DIF_VIDEO_AGC_CTRL, 0, 31,
2086 0x72500800);
2087 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2088 DIF_VID_AUD_OVERRIDE, 0, 31,
2089 0x27000100);
2090 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2091 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
2092 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2093 DIF_COMP_FLT_CTRL, 0, 31,
2094 0x00A653A8);
2095 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2096 DIF_SRC_PHASE_INC, 0, 31,
2097 0x1befbf06);
2098 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2099 DIF_SRC_GAIN_CONTROL, 0, 31,
2100 0x000035e8);
2101 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
2102 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
2103 /* Save the Spec Inversion value */
2104 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
2105 dif_misc_ctrl_value |= 0x3a013F11;
2106 }
2107
2108 /* The AGC values should be the same for all standards,
2109 AUD_SRC_SEL[19] should always be disabled */
2110 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
2111
2112 /* It is still possible to get Set Standard calls even when we
2113 are in FM mode.
2114 This is done to override the value for FM. */
2115 if (dev->active_mode == V4L2_TUNER_RADIO)
2116 dif_misc_ctrl_value = 0x7a080000;
2117
2118 /* Write the calculated value for misc ontrol register */
2119 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
2120
2121 return status;
2122 }
2123
2124 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
2125 {
2126 int status = 0;
2127 u32 dwval;
2128
2129 /* Set the RF and IF k_agc values to 3 */
2130 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2131 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2132 dwval |= 0x33000000;
2133
2134 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2135
2136 return status;
2137 }
2138
2139 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
2140 {
2141 int status = 0;
2142 u32 dwval;
2143 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n",
2144 dev->tuner_type);
2145 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
2146 * SECAM L/B/D standards */
2147 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
2148 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
2149
2150 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
2151 V4L2_STD_SECAM_D)) {
2152 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2153 dwval &= ~FLD_DIF_IF_REF;
2154 dwval |= 0x88000300;
2155 } else
2156 dwval |= 0x88000000;
2157 } else {
2158 if (dev->tuner_type == TUNER_NXP_TDA18271) {
2159 dwval &= ~FLD_DIF_IF_REF;
2160 dwval |= 0xCC000300;
2161 } else
2162 dwval |= 0x44000000;
2163 }
2164
2165 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
2166
2167 return status;
2168 }
2169
2170 /******************************************************************************
2171 * I 2 S - B L O C K C O N T R O L functions *
2172 ******************************************************************************/
2173 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
2174 {
2175 int status = 0;
2176 u32 value;
2177
2178 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2179 CH_PWR_CTRL1, 1, &value, 1);
2180 /* enables clock to delta-sigma and decimation filter */
2181 value |= 0x80;
2182 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2183 CH_PWR_CTRL1, 1, value, 1);
2184 /* power up all channel */
2185 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2186 CH_PWR_CTRL2, 1, 0x00, 1);
2187
2188 return status;
2189 }
2190
2191 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
2192 enum AV_MODE avmode)
2193 {
2194 int status = 0;
2195 u32 value = 0;
2196
2197 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
2198 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2199 CH_PWR_CTRL2, 1, &value, 1);
2200 value |= 0xfe;
2201 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2202 CH_PWR_CTRL2, 1, value, 1);
2203 } else {
2204 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2205 CH_PWR_CTRL2, 1, 0x00, 1);
2206 }
2207
2208 return status;
2209 }
2210
2211 /* set i2s_blk for audio input types */
2212 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
2213 {
2214 int status = 0;
2215
2216 switch (audio_input) {
2217 case CX231XX_AMUX_LINE_IN:
2218 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2219 CH_PWR_CTRL2, 1, 0x00, 1);
2220 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
2221 CH_PWR_CTRL1, 1, 0x80, 1);
2222 break;
2223 case CX231XX_AMUX_VIDEO:
2224 default:
2225 break;
2226 }
2227
2228 dev->ctl_ainput = audio_input;
2229
2230 return status;
2231 }
2232
2233 /******************************************************************************
2234 * P O W E R C O N T R O L functions *
2235 ******************************************************************************/
2236 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2237 {
2238 u8 value[4] = { 0, 0, 0, 0 };
2239 u32 tmp = 0;
2240 int status = 0;
2241
2242 if (dev->power_mode != mode)
2243 dev->power_mode = mode;
2244 else {
2245 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
2246 mode);
2247 return 0;
2248 }
2249
2250 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2251 4);
2252 if (status < 0)
2253 return status;
2254
2255 tmp = *((u32 *) value);
2256
2257 switch (mode) {
2258 case POLARIS_AVMODE_ENXTERNAL_AV:
2259
2260 tmp &= (~PWR_MODE_MASK);
2261
2262 tmp |= PWR_AV_EN;
2263 value[0] = (u8) tmp;
2264 value[1] = (u8) (tmp >> 8);
2265 value[2] = (u8) (tmp >> 16);
2266 value[3] = (u8) (tmp >> 24);
2267 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2268 PWR_CTL_EN, value, 4);
2269 msleep(PWR_SLEEP_INTERVAL);
2270
2271 tmp |= PWR_ISO_EN;
2272 value[0] = (u8) tmp;
2273 value[1] = (u8) (tmp >> 8);
2274 value[2] = (u8) (tmp >> 16);
2275 value[3] = (u8) (tmp >> 24);
2276 status =
2277 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2278 value, 4);
2279 msleep(PWR_SLEEP_INTERVAL);
2280
2281 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
2282 value[0] = (u8) tmp;
2283 value[1] = (u8) (tmp >> 8);
2284 value[2] = (u8) (tmp >> 16);
2285 value[3] = (u8) (tmp >> 24);
2286 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2287 PWR_CTL_EN, value, 4);
2288
2289 /* reset state of xceive tuner */
2290 dev->xc_fw_load_done = 0;
2291 break;
2292
2293 case POLARIS_AVMODE_ANALOGT_TV:
2294
2295 tmp |= PWR_DEMOD_EN;
2296 tmp |= (I2C_DEMOD_EN);
2297 value[0] = (u8) tmp;
2298 value[1] = (u8) (tmp >> 8);
2299 value[2] = (u8) (tmp >> 16);
2300 value[3] = (u8) (tmp >> 24);
2301 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2302 PWR_CTL_EN, value, 4);
2303 msleep(PWR_SLEEP_INTERVAL);
2304
2305 if (!(tmp & PWR_TUNER_EN)) {
2306 tmp |= (PWR_TUNER_EN);
2307 value[0] = (u8) tmp;
2308 value[1] = (u8) (tmp >> 8);
2309 value[2] = (u8) (tmp >> 16);
2310 value[3] = (u8) (tmp >> 24);
2311 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2312 PWR_CTL_EN, value, 4);
2313 msleep(PWR_SLEEP_INTERVAL);
2314 }
2315
2316 if (!(tmp & PWR_AV_EN)) {
2317 tmp |= PWR_AV_EN;
2318 value[0] = (u8) tmp;
2319 value[1] = (u8) (tmp >> 8);
2320 value[2] = (u8) (tmp >> 16);
2321 value[3] = (u8) (tmp >> 24);
2322 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2323 PWR_CTL_EN, value, 4);
2324 msleep(PWR_SLEEP_INTERVAL);
2325 }
2326 if (!(tmp & PWR_ISO_EN)) {
2327 tmp |= PWR_ISO_EN;
2328 value[0] = (u8) tmp;
2329 value[1] = (u8) (tmp >> 8);
2330 value[2] = (u8) (tmp >> 16);
2331 value[3] = (u8) (tmp >> 24);
2332 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2333 PWR_CTL_EN, value, 4);
2334 msleep(PWR_SLEEP_INTERVAL);
2335 }
2336
2337 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2338 tmp |= POLARIS_AVMODE_ANALOGT_TV;
2339 value[0] = (u8) tmp;
2340 value[1] = (u8) (tmp >> 8);
2341 value[2] = (u8) (tmp >> 16);
2342 value[3] = (u8) (tmp >> 24);
2343 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2344 PWR_CTL_EN, value, 4);
2345 msleep(PWR_SLEEP_INTERVAL);
2346 }
2347
2348 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2349 (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2350 (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2351 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2352 /* tuner path to channel 1 from port 3 */
2353 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2354
2355 /* reset the Tuner */
2356 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2357
2358 if (dev->cx231xx_reset_analog_tuner)
2359 dev->cx231xx_reset_analog_tuner(dev);
2360 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2361 (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2362 (dev->model == CX231XX_BOARD_CNXT_RDU_253S)) {
2363 /* tuner path to channel 1 from port 3 */
2364 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2365 if (dev->cx231xx_reset_analog_tuner)
2366 dev->cx231xx_reset_analog_tuner(dev);
2367 } else if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) {
2368 /* tuner path to channel 1 from port 1 ?? */
2369 cx231xx_enable_i2c_for_tuner(dev, I2C_1);
2370
2371 if (dev->cx231xx_reset_analog_tuner)
2372 dev->cx231xx_reset_analog_tuner(dev);
2373 }
2374
2375 break;
2376
2377 case POLARIS_AVMODE_DIGITAL:
2378 if (!(tmp & PWR_TUNER_EN)) {
2379 tmp |= (PWR_TUNER_EN);
2380 value[0] = (u8) tmp;
2381 value[1] = (u8) (tmp >> 8);
2382 value[2] = (u8) (tmp >> 16);
2383 value[3] = (u8) (tmp >> 24);
2384 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2385 PWR_CTL_EN, value, 4);
2386 msleep(PWR_SLEEP_INTERVAL);
2387 }
2388 if (!(tmp & PWR_AV_EN)) {
2389 tmp |= PWR_AV_EN;
2390 value[0] = (u8) tmp;
2391 value[1] = (u8) (tmp >> 8);
2392 value[2] = (u8) (tmp >> 16);
2393 value[3] = (u8) (tmp >> 24);
2394 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2395 PWR_CTL_EN, value, 4);
2396 msleep(PWR_SLEEP_INTERVAL);
2397 }
2398 if (!(tmp & PWR_ISO_EN)) {
2399 tmp |= PWR_ISO_EN;
2400 value[0] = (u8) tmp;
2401 value[1] = (u8) (tmp >> 8);
2402 value[2] = (u8) (tmp >> 16);
2403 value[3] = (u8) (tmp >> 24);
2404 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2405 PWR_CTL_EN, value, 4);
2406 msleep(PWR_SLEEP_INTERVAL);
2407 }
2408
2409 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
2410 value[0] = (u8) tmp;
2411 value[1] = (u8) (tmp >> 8);
2412 value[2] = (u8) (tmp >> 16);
2413 value[3] = (u8) (tmp >> 24);
2414 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2415 PWR_CTL_EN, value, 4);
2416 msleep(PWR_SLEEP_INTERVAL);
2417
2418 if (!(tmp & PWR_DEMOD_EN)) {
2419 tmp |= PWR_DEMOD_EN;
2420 value[0] = (u8) tmp;
2421 value[1] = (u8) (tmp >> 8);
2422 value[2] = (u8) (tmp >> 16);
2423 value[3] = (u8) (tmp >> 24);
2424 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2425 PWR_CTL_EN, value, 4);
2426 msleep(PWR_SLEEP_INTERVAL);
2427 }
2428
2429 if ((dev->model == CX231XX_BOARD_CNXT_CARRAERA) ||
2430 (dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2431 (dev->model == CX231XX_BOARD_CNXT_SHELBY) ||
2432 (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2433 /* tuner path to channel 1 from port 3 */
2434 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2435
2436 /* reset the Tuner */
2437 cx231xx_gpio_set(dev, dev->board.tuner_gpio);
2438
2439 if (dev->cx231xx_reset_analog_tuner)
2440 dev->cx231xx_reset_analog_tuner(dev);
2441 } else if ((dev->model == CX231XX_BOARD_CNXT_RDE_253S) ||
2442 (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) ||
2443 (dev->model == CX231XX_BOARD_CNXT_RDU_253S)) {
2444 /* tuner path to channel 1 from port 3 */
2445 cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2446 if (dev->cx231xx_reset_analog_tuner)
2447 dev->cx231xx_reset_analog_tuner(dev);
2448 } else if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) {
2449 /* tuner path to channel 1 from port 1 ?? */
2450 cx231xx_enable_i2c_for_tuner(dev, I2C_1);
2451
2452 if (dev->cx231xx_reset_analog_tuner)
2453 dev->cx231xx_reset_analog_tuner(dev);
2454 }
2455
2456 break;
2457
2458 default:
2459 break;
2460 }
2461
2462 msleep(PWR_SLEEP_INTERVAL);
2463
2464 /* For power saving, only enable Pwr_resetout_n
2465 when digital TV is selected. */
2466 if (mode == POLARIS_AVMODE_DIGITAL) {
2467 tmp |= PWR_RESETOUT_EN;
2468 value[0] = (u8) tmp;
2469 value[1] = (u8) (tmp >> 8);
2470 value[2] = (u8) (tmp >> 16);
2471 value[3] = (u8) (tmp >> 24);
2472 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2473 PWR_CTL_EN, value, 4);
2474 msleep(PWR_SLEEP_INTERVAL);
2475 }
2476
2477 /* update power control for afe */
2478 status = cx231xx_afe_update_power_control(dev, mode);
2479
2480 /* update power control for i2s_blk */
2481 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2482
2483 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2484 4);
2485
2486 return status;
2487 }
2488
2489 int cx231xx_power_suspend(struct cx231xx *dev)
2490 {
2491 u8 value[4] = { 0, 0, 0, 0 };
2492 u32 tmp = 0;
2493 int status = 0;
2494
2495 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2496 value, 4);
2497 if (status > 0)
2498 return status;
2499
2500 tmp = *((u32 *) value);
2501 tmp &= (~PWR_MODE_MASK);
2502
2503 value[0] = (u8) tmp;
2504 value[1] = (u8) (tmp >> 8);
2505 value[2] = (u8) (tmp >> 16);
2506 value[3] = (u8) (tmp >> 24);
2507 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2508 value, 4);
2509
2510 return status;
2511 }
2512
2513 /******************************************************************************
2514 * S T R E A M C O N T R O L functions *
2515 ******************************************************************************/
2516 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2517 {
2518 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2519 u32 tmp = 0;
2520 int status = 0;
2521
2522 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2523 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2524 value, 4);
2525 if (status < 0)
2526 return status;
2527
2528 tmp = *((u32 *) value);
2529 tmp |= ep_mask;
2530 value[0] = (u8) tmp;
2531 value[1] = (u8) (tmp >> 8);
2532 value[2] = (u8) (tmp >> 16);
2533 value[3] = (u8) (tmp >> 24);
2534
2535 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2536 value, 4);
2537
2538 return status;
2539 }
2540
2541 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2542 {
2543 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2544 u32 tmp = 0;
2545 int status = 0;
2546
2547 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2548 status =
2549 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2550 if (status < 0)
2551 return status;
2552
2553 tmp = *((u32 *) value);
2554 tmp &= (~ep_mask);
2555 value[0] = (u8) tmp;
2556 value[1] = (u8) (tmp >> 8);
2557 value[2] = (u8) (tmp >> 16);
2558 value[3] = (u8) (tmp >> 24);
2559
2560 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2561 value, 4);
2562
2563 return status;
2564 }
2565
2566 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2567 {
2568 int status = 0;
2569 u32 value = 0;
2570 u8 val[4] = { 0, 0, 0, 0 };
2571
2572 if (dev->udev->speed == USB_SPEED_HIGH) {
2573 switch (media_type) {
2574 case 81: /* audio */
2575 cx231xx_info("%s: Audio enter HANC\n", __func__);
2576 status =
2577 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2578 break;
2579
2580 case 2: /* vbi */
2581 cx231xx_info("%s: set vanc registers\n", __func__);
2582 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2583 break;
2584
2585 case 3: /* sliced cc */
2586 cx231xx_info("%s: set hanc registers\n", __func__);
2587 status =
2588 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2589 break;
2590
2591 case 0: /* video */
2592 cx231xx_info("%s: set video registers\n", __func__);
2593 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2594 break;
2595
2596 case 4: /* ts1 */
2597 cx231xx_info("%s: set ts1 registers", __func__);
2598
2599 if (dev->model == CX231XX_BOARD_CNXT_VIDEO_GRABBER) {
2600 cx231xx_info(" MPEG\n");
2601 value &= 0xFFFFFFFC;
2602 value |= 0x3;
2603
2604 status = cx231xx_mode_register(dev, TS_MODE_REG, value);
2605
2606 val[0] = 0x04;
2607 val[1] = 0xA3;
2608 val[2] = 0x3B;
2609 val[3] = 0x00;
2610 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2611 TS1_CFG_REG, val, 4);
2612
2613 val[0] = 0x00;
2614 val[1] = 0x08;
2615 val[2] = 0x00;
2616 val[3] = 0x08;
2617 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2618 TS1_LENGTH_REG, val, 4);
2619
2620 } else {
2621 cx231xx_info(" BDA\n");
2622 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2623 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010);
2624 }
2625 break;
2626
2627 case 6: /* ts1 parallel mode */
2628 cx231xx_info("%s: set ts1 parrallel mode registers\n",
2629 __func__);
2630 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2631 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2632 break;
2633 }
2634 } else {
2635 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2636 }
2637
2638 return status;
2639 }
2640
2641 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2642 {
2643 int rc = -1;
2644 u32 ep_mask = -1;
2645 struct pcb_config *pcb_config;
2646
2647 /* get EP for media type */
2648 pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2649
2650 if (pcb_config->config_num == 1) {
2651 switch (media_type) {
2652 case 0: /* Video */
2653 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2654 break;
2655 case 1: /* Audio */
2656 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2657 break;
2658 case 2: /* Vbi */
2659 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2660 break;
2661 case 3: /* Sliced_cc */
2662 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2663 break;
2664 case 4: /* ts1 */
2665 case 6: /* ts1 parallel mode */
2666 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2667 break;
2668 case 5: /* ts2 */
2669 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2670 break;
2671 }
2672
2673 } else if (pcb_config->config_num > 1) {
2674 switch (media_type) {
2675 case 0: /* Video */
2676 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */
2677 break;
2678 case 1: /* Audio */
2679 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */
2680 break;
2681 case 2: /* Vbi */
2682 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */
2683 break;
2684 case 3: /* Sliced_cc */
2685 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */
2686 break;
2687 case 4: /* ts1 */
2688 case 6: /* ts1 parallel mode */
2689 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */
2690 break;
2691 case 5: /* ts2 */
2692 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */
2693 break;
2694 }
2695
2696 }
2697
2698 if (start) {
2699 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2700
2701 if (rc < 0)
2702 return rc;
2703
2704 /* enable video capture */
2705 if (ep_mask > 0)
2706 rc = cx231xx_start_stream(dev, ep_mask);
2707 } else {
2708 /* disable video capture */
2709 if (ep_mask > 0)
2710 rc = cx231xx_stop_stream(dev, ep_mask);
2711 }
2712
2713 if (dev->mode == CX231XX_ANALOG_MODE)
2714 ;/* do any in Analog mode */
2715 else
2716 ;/* do any in digital mode */
2717
2718 return rc;
2719 }
2720 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2721
2722 /*****************************************************************************
2723 * G P I O B I T control functions *
2724 ******************************************************************************/
2725 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2726 {
2727 int status = 0;
2728
2729 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2730
2731 return status;
2732 }
2733
2734 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val)
2735 {
2736 int status = 0;
2737
2738 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2739
2740 return status;
2741 }
2742
2743 /*
2744 * cx231xx_set_gpio_direction
2745 * Sets the direction of the GPIO pin to input or output
2746 *
2747 * Parameters :
2748 * pin_number : The GPIO Pin number to program the direction for
2749 * from 0 to 31
2750 * pin_value : The Direction of the GPIO Pin under reference.
2751 * 0 = Input direction
2752 * 1 = Output direction
2753 */
2754 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2755 int pin_number, int pin_value)
2756 {
2757 int status = 0;
2758 u32 value = 0;
2759
2760 /* Check for valid pin_number - if 32 , bail out */
2761 if (pin_number >= 32)
2762 return -EINVAL;
2763
2764 /* input */
2765 if (pin_value == 0)
2766 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */
2767 else
2768 value = dev->gpio_dir | (1 << pin_number);
2769
2770 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2771
2772 /* cache the value for future */
2773 dev->gpio_dir = value;
2774
2775 return status;
2776 }
2777
2778 /*
2779 * cx231xx_set_gpio_value
2780 * Sets the value of the GPIO pin to Logic high or low. The Pin under
2781 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2782 *
2783 * Parameters :
2784 * pin_number : The GPIO Pin number to program the direction for
2785 * pin_value : The value of the GPIO Pin under reference.
2786 * 0 = set it to 0
2787 * 1 = set it to 1
2788 */
2789 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2790 {
2791 int status = 0;
2792 u32 value = 0;
2793
2794 /* Check for valid pin_number - if 0xFF , bail out */
2795 if (pin_number >= 32)
2796 return -EINVAL;
2797
2798 /* first do a sanity check - if the Pin is not output, make it output */
2799 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2800 /* It was in input mode */
2801 value = dev->gpio_dir | (1 << pin_number);
2802 dev->gpio_dir = value;
2803 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2804 (u8 *) &dev->gpio_val);
2805 value = 0;
2806 }
2807
2808 if (pin_value == 0)
2809 value = dev->gpio_val & (~(1 << pin_number));
2810 else
2811 value = dev->gpio_val | (1 << pin_number);
2812
2813 /* store the value */
2814 dev->gpio_val = value;
2815
2816 /* toggle bit0 of GP_IO */
2817 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2818
2819 return status;
2820 }
2821
2822 /*****************************************************************************
2823 * G P I O I2C related functions *
2824 ******************************************************************************/
2825 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2826 {
2827 int status = 0;
2828
2829 /* set SCL to output 1 ; set SDA to output 1 */
2830 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2831 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2832 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2833 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2834
2835 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2836 if (status < 0)
2837 return -EINVAL;
2838
2839 /* set SCL to output 1; set SDA to output 0 */
2840 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2841 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2842
2843 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2844 if (status < 0)
2845 return -EINVAL;
2846
2847 /* set SCL to output 0; set SDA to output 0 */
2848 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2849 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2850
2851 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2852 if (status < 0)
2853 return -EINVAL;
2854
2855 return status;
2856 }
2857
2858 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2859 {
2860 int status = 0;
2861
2862 /* set SCL to output 0; set SDA to output 0 */
2863 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2864 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2865
2866 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2867 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2868
2869 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2870 if (status < 0)
2871 return -EINVAL;
2872
2873 /* set SCL to output 1; set SDA to output 0 */
2874 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2875 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2876
2877 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2878 if (status < 0)
2879 return -EINVAL;
2880
2881 /* set SCL to input ,release SCL cable control
2882 set SDA to input ,release SDA cable control */
2883 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2884 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2885
2886 status =
2887 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2888 if (status < 0)
2889 return -EINVAL;
2890
2891 return status;
2892 }
2893
2894 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2895 {
2896 int status = 0;
2897 u8 i;
2898
2899 /* set SCL to output ; set SDA to output */
2900 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2901 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2902
2903 for (i = 0; i < 8; i++) {
2904 if (((data << i) & 0x80) == 0) {
2905 /* set SCL to output 0; set SDA to output 0 */
2906 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2907 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2908 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2909 (u8 *)&dev->gpio_val);
2910
2911 /* set SCL to output 1; set SDA to output 0 */
2912 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2913 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2914 (u8 *)&dev->gpio_val);
2915
2916 /* set SCL to output 0; set SDA to output 0 */
2917 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2918 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2919 (u8 *)&dev->gpio_val);
2920 } else {
2921 /* set SCL to output 0; set SDA to output 1 */
2922 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2923 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2924 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2925 (u8 *)&dev->gpio_val);
2926
2927 /* set SCL to output 1; set SDA to output 1 */
2928 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2929 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2930 (u8 *)&dev->gpio_val);
2931
2932 /* set SCL to output 0; set SDA to output 1 */
2933 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2934 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2935 (u8 *)&dev->gpio_val);
2936 }
2937 }
2938 return status;
2939 }
2940
2941 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf)
2942 {
2943 u8 value = 0;
2944 int status = 0;
2945 u32 gpio_logic_value = 0;
2946 u8 i;
2947
2948 /* read byte */
2949 for (i = 0; i < 8; i++) { /* send write I2c addr */
2950
2951 /* set SCL to output 0; set SDA to input */
2952 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2953 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2954 (u8 *)&dev->gpio_val);
2955
2956 /* set SCL to output 1; set SDA to input */
2957 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2958 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2959 (u8 *)&dev->gpio_val);
2960
2961 /* get SDA data bit */
2962 gpio_logic_value = dev->gpio_val;
2963 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2964 (u8 *)&dev->gpio_val);
2965 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2966 value |= (1 << (8 - i - 1));
2967
2968 dev->gpio_val = gpio_logic_value;
2969 }
2970
2971 /* set SCL to output 0,finish the read latest SCL signal.
2972 !!!set SDA to input, never to modify SDA direction at
2973 the same times */
2974 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2975 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2976
2977 /* store the value */
2978 *buf = value & 0xff;
2979
2980 return status;
2981 }
2982
2983 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2984 {
2985 int status = 0;
2986 u32 gpio_logic_value = 0;
2987 int nCnt = 10;
2988 int nInit = nCnt;
2989
2990 /* clock stretch; set SCL to input; set SDA to input;
2991 get SCL value till SCL = 1 */
2992 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2993 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2994
2995 gpio_logic_value = dev->gpio_val;
2996 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2997
2998 do {
2999 msleep(2);
3000 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
3001 (u8 *)&dev->gpio_val);
3002 nCnt--;
3003 } while (((dev->gpio_val &
3004 (1 << dev->board.tuner_scl_gpio)) == 0) &&
3005 (nCnt > 0));
3006
3007 if (nCnt == 0)
3008 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
3009 nInit * 10);
3010
3011 /*
3012 * readAck
3013 * through clock stretch, slave has given a SCL signal,
3014 * so the SDA data can be directly read.
3015 */
3016 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3017
3018 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
3019 dev->gpio_val = gpio_logic_value;
3020 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3021 status = 0;
3022 } else {
3023 dev->gpio_val = gpio_logic_value;
3024 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
3025 }
3026
3027 /* read SDA end, set the SCL to output 0, after this operation,
3028 SDA direction can be changed. */
3029 dev->gpio_val = gpio_logic_value;
3030 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
3031 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3032 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3033
3034 return status;
3035 }
3036
3037 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
3038 {
3039 int status = 0;
3040
3041 /* set SDA to ouput */
3042 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
3043 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3044
3045 /* set SCL = 0 (output); set SDA = 0 (output) */
3046 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
3047 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3048 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3049
3050 /* set SCL = 1 (output); set SDA = 0 (output) */
3051 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3052 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3053
3054 /* set SCL = 0 (output); set SDA = 0 (output) */
3055 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3056 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3057
3058 /* set SDA to input,and then the slave will read data from SDA. */
3059 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3060 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3061
3062 return status;
3063 }
3064
3065 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
3066 {
3067 int status = 0;
3068
3069 /* set scl to output ; set sda to input */
3070 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
3071 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
3072 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3073
3074 /* set scl to output 0; set sda to input */
3075 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
3076 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3077
3078 /* set scl to output 1; set sda to input */
3079 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
3080 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
3081
3082 return status;
3083 }
3084
3085 /*****************************************************************************
3086 * G P I O I2C related functions *
3087 ******************************************************************************/
3088 /* cx231xx_gpio_i2c_read
3089 * Function to read data from gpio based I2C interface
3090 */
3091 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3092 {
3093 int status = 0;
3094 int i = 0;
3095
3096 /* get the lock */
3097 mutex_lock(&dev->gpio_i2c_lock);
3098
3099 /* start */
3100 status = cx231xx_gpio_i2c_start(dev);
3101
3102 /* write dev_addr */
3103 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
3104
3105 /* readAck */
3106 status = cx231xx_gpio_i2c_read_ack(dev);
3107
3108 /* read data */
3109 for (i = 0; i < len; i++) {
3110 /* read data */
3111 buf[i] = 0;
3112 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
3113
3114 if ((i + 1) != len) {
3115 /* only do write ack if we more length */
3116 status = cx231xx_gpio_i2c_write_ack(dev);
3117 }
3118 }
3119
3120 /* write NAK - inform reads are complete */
3121 status = cx231xx_gpio_i2c_write_nak(dev);
3122
3123 /* write end */
3124 status = cx231xx_gpio_i2c_end(dev);
3125
3126 /* release the lock */
3127 mutex_unlock(&dev->gpio_i2c_lock);
3128
3129 return status;
3130 }
3131
3132 /* cx231xx_gpio_i2c_write
3133 * Function to write data to gpio based I2C interface
3134 */
3135 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len)
3136 {
3137 int status = 0;
3138 int i = 0;
3139
3140 /* get the lock */
3141 mutex_lock(&dev->gpio_i2c_lock);
3142
3143 /* start */
3144 status = cx231xx_gpio_i2c_start(dev);
3145
3146 /* write dev_addr */
3147 status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
3148
3149 /* read Ack */
3150 status = cx231xx_gpio_i2c_read_ack(dev);
3151
3152 for (i = 0; i < len; i++) {
3153 /* Write data */
3154 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
3155
3156 /* read Ack */
3157 status = cx231xx_gpio_i2c_read_ack(dev);
3158 }
3159
3160 /* write End */
3161 status = cx231xx_gpio_i2c_end(dev);
3162
3163 /* release the lock */
3164 mutex_unlock(&dev->gpio_i2c_lock);
3165
3166 return 0;
3167 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree