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usb-xhci: Handle COMP_TX_ERR for isoc tds
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / ahci.c
blobabf2f4e10fd67a6510fd9368f1a62dc94cf97d75
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 };
57
58 enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
63 board_ahci_yes_fbs,
64
65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
67 board_ahci_mcp77,
68 board_ahci_mcp89,
69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
79 };
80
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 #ifdef CONFIG_PM
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
91 #endif
92
93 static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95 };
96
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
100 };
101
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
105 };
106
107 static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
111 };
112
113 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114
115 static const struct ata_port_info ahci_port_info[] = {
116 /* by features */
117 [board_ahci] =
118 {
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_ign_iferr] =
125 {
126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_nosntf] =
133 {
134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 [board_ahci_yes_fbs] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
148 /* by chipsets */
149 [board_ahci_mcp65] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
152 AHCI_HFLAG_YES_NCQ),
153 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp77] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_mcp89] =
167 {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_mv] =
175 {
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
183 [board_ahci_sb600] =
184 {
185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_sb600_ops,
192 },
193 [board_ahci_sb700] = /* for SB700 and SB800 */
194 {
195 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_sb600_ops,
200 },
201 [board_ahci_vt8251] =
202 {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_vt8251_ops,
208 },
209 };
210
211 static const struct pci_device_id ahci_pci_tbl[] = {
212 /* Intel */
213 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
214 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
215 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
216 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
217 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
218 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
219 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
223 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
224 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
225 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
227 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
228 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
239 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
240 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
241 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
242 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
243 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
244 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
245 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
246 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
248 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
250 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
251 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
252 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
253 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
259 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
260 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
262 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
263 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
264 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
265 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
266 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
268 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
269 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
270 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
271
272 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
273 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
274 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
275
276 /* ATI */
277 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
278 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
283 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
284
285 /* AMD */
286 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
287 /* AMD is using RAID class only for ahci controllers */
288 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
289 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
290
291 /* VIA */
292 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
293 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
294
295 /* NVIDIA */
296 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
303 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
304 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
316 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
332 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
368 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
379 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
380
381 /* SiS */
382 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
383 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
384 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
385
386 /* Marvell */
387 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
388 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
389 { PCI_DEVICE(0x1b4b, 0x9123),
390 .class = PCI_CLASS_STORAGE_SATA_AHCI,
391 .class_mask = 0xffffff,
392 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
393 { PCI_DEVICE(0x1b4b, 0x9125),
394 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
395 { PCI_DEVICE(0x1b4b, 0x917a),
396 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
397 { PCI_DEVICE(0x1b4b, 0x91a3),
398 .driver_data = board_ahci_yes_fbs },
399
400 /* Promise */
401 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
402
403 /* Generic, PCI class code for AHCI */
404 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
405 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
406
407 { } /* terminate list */
408 };
409
410
411 static struct pci_driver ahci_pci_driver = {
412 .name = DRV_NAME,
413 .id_table = ahci_pci_tbl,
414 .probe = ahci_init_one,
415 .remove = ata_pci_remove_one,
416 #ifdef CONFIG_PM
417 .suspend = ahci_pci_device_suspend,
418 .resume = ahci_pci_device_resume,
419 #endif
420 };
421
422 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
423 static int marvell_enable;
424 #else
425 static int marvell_enable = 1;
426 #endif
427 module_param(marvell_enable, int, 0644);
428 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
429
430
431 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
432 struct ahci_host_priv *hpriv)
433 {
434 unsigned int force_port_map = 0;
435 unsigned int mask_port_map = 0;
436
437 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
438 dev_info(&pdev->dev, "JMB361 has only one port\n");
439 force_port_map = 1;
440 }
441
442 /*
443 * Temporary Marvell 6145 hack: PATA port presence
444 * is asserted through the standard AHCI port
445 * presence register, as bit 4 (counting from 0)
446 */
447 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
448 if (pdev->device == 0x6121)
449 mask_port_map = 0x3;
450 else
451 mask_port_map = 0xf;
452 dev_info(&pdev->dev,
453 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
454 }
455
456 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
457 mask_port_map);
458 }
459
460 static int ahci_pci_reset_controller(struct ata_host *host)
461 {
462 struct pci_dev *pdev = to_pci_dev(host->dev);
463
464 ahci_reset_controller(host);
465
466 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
467 struct ahci_host_priv *hpriv = host->private_data;
468 u16 tmp16;
469
470 /* configure PCS */
471 pci_read_config_word(pdev, 0x92, &tmp16);
472 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
473 tmp16 |= hpriv->port_map;
474 pci_write_config_word(pdev, 0x92, tmp16);
475 }
476 }
477
478 return 0;
479 }
480
481 static void ahci_pci_init_controller(struct ata_host *host)
482 {
483 struct ahci_host_priv *hpriv = host->private_data;
484 struct pci_dev *pdev = to_pci_dev(host->dev);
485 void __iomem *port_mmio;
486 u32 tmp;
487 int mv;
488
489 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
490 if (pdev->device == 0x6121)
491 mv = 2;
492 else
493 mv = 4;
494 port_mmio = __ahci_port_base(host, mv);
495
496 writel(0, port_mmio + PORT_IRQ_MASK);
497
498 /* clear port IRQ */
499 tmp = readl(port_mmio + PORT_IRQ_STAT);
500 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
501 if (tmp)
502 writel(tmp, port_mmio + PORT_IRQ_STAT);
503 }
504
505 ahci_init_controller(host);
506 }
507
508 static int ahci_sb600_check_ready(struct ata_link *link)
509 {
510 void __iomem *port_mmio = ahci_port_base(link->ap);
511 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
512 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
513
514 /*
515 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
516 * which can save timeout delay.
517 */
518 if (irq_status & PORT_IRQ_BAD_PMP)
519 return -EIO;
520
521 return ata_check_ready(status);
522 }
523
524 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
525 unsigned long deadline)
526 {
527 struct ata_port *ap = link->ap;
528 void __iomem *port_mmio = ahci_port_base(ap);
529 int pmp = sata_srst_pmp(link);
530 int rc;
531 u32 irq_sts;
532
533 DPRINTK("ENTER\n");
534
535 rc = ahci_do_softreset(link, class, pmp, deadline,
536 ahci_sb600_check_ready);
537
538 /*
539 * Soft reset fails on some ATI chips with IPMS set when PMP
540 * is enabled but SATA HDD/ODD is connected to SATA port,
541 * do soft reset again to port 0.
542 */
543 if (rc == -EIO) {
544 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
545 if (irq_sts & PORT_IRQ_BAD_PMP) {
546 ata_link_printk(link, KERN_WARNING,
547 "applying SB600 PMP SRST workaround "
548 "and retrying\n");
549 rc = ahci_do_softreset(link, class, 0, deadline,
550 ahci_check_ready);
551 }
552 }
553
554 return rc;
555 }
556
557 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
558 unsigned long deadline)
559 {
560 struct ata_port *ap = link->ap;
561 bool online;
562 int rc;
563
564 DPRINTK("ENTER\n");
565
566 ahci_stop_engine(ap);
567
568 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
569 deadline, &online, NULL);
570
571 ahci_start_engine(ap);
572
573 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
574
575 /* vt8251 doesn't clear BSY on signature FIS reception,
576 * request follow-up softreset.
577 */
578 return online ? -EAGAIN : rc;
579 }
580
581 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
582 unsigned long deadline)
583 {
584 struct ata_port *ap = link->ap;
585 struct ahci_port_priv *pp = ap->private_data;
586 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
587 struct ata_taskfile tf;
588 bool online;
589 int rc;
590
591 ahci_stop_engine(ap);
592
593 /* clear D2H reception area to properly wait for D2H FIS */
594 ata_tf_init(link->device, &tf);
595 tf.command = 0x80;
596 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
597
598 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
599 deadline, &online, NULL);
600
601 ahci_start_engine(ap);
602
603 /* The pseudo configuration device on SIMG4726 attached to
604 * ASUS P5W-DH Deluxe doesn't send signature FIS after
605 * hardreset if no device is attached to the first downstream
606 * port && the pseudo device locks up on SRST w/ PMP==0. To
607 * work around this, wait for !BSY only briefly. If BSY isn't
608 * cleared, perform CLO and proceed to IDENTIFY (achieved by
609 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
610 *
611 * Wait for two seconds. Devices attached to downstream port
612 * which can't process the following IDENTIFY after this will
613 * have to be reset again. For most cases, this should
614 * suffice while making probing snappish enough.
615 */
616 if (online) {
617 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
618 ahci_check_ready);
619 if (rc)
620 ahci_kick_engine(ap);
621 }
622 return rc;
623 }
624
625 #ifdef CONFIG_PM
626 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
627 {
628 struct ata_host *host = dev_get_drvdata(&pdev->dev);
629 struct ahci_host_priv *hpriv = host->private_data;
630 void __iomem *mmio = hpriv->mmio;
631 u32 ctl;
632
633 if (mesg.event & PM_EVENT_SUSPEND &&
634 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
635 dev_printk(KERN_ERR, &pdev->dev,
636 "BIOS update required for suspend/resume\n");
637 return -EIO;
638 }
639
640 if (mesg.event & PM_EVENT_SLEEP) {
641 /* AHCI spec rev1.1 section 8.3.3:
642 * Software must disable interrupts prior to requesting a
643 * transition of the HBA to D3 state.
644 */
645 ctl = readl(mmio + HOST_CTL);
646 ctl &= ~HOST_IRQ_EN;
647 writel(ctl, mmio + HOST_CTL);
648 readl(mmio + HOST_CTL); /* flush */
649 }
650
651 return ata_pci_device_suspend(pdev, mesg);
652 }
653
654 static int ahci_pci_device_resume(struct pci_dev *pdev)
655 {
656 struct ata_host *host = dev_get_drvdata(&pdev->dev);
657 int rc;
658
659 rc = ata_pci_device_do_resume(pdev);
660 if (rc)
661 return rc;
662
663 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
664 rc = ahci_pci_reset_controller(host);
665 if (rc)
666 return rc;
667
668 ahci_pci_init_controller(host);
669 }
670
671 ata_host_resume(host);
672
673 return 0;
674 }
675 #endif
676
677 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
678 {
679 int rc;
680
681 if (using_dac &&
682 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
683 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
684 if (rc) {
685 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
686 if (rc) {
687 dev_printk(KERN_ERR, &pdev->dev,
688 "64-bit DMA enable failed\n");
689 return rc;
690 }
691 }
692 } else {
693 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
694 if (rc) {
695 dev_printk(KERN_ERR, &pdev->dev,
696 "32-bit DMA enable failed\n");
697 return rc;
698 }
699 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
700 if (rc) {
701 dev_printk(KERN_ERR, &pdev->dev,
702 "32-bit consistent DMA enable failed\n");
703 return rc;
704 }
705 }
706 return 0;
707 }
708
709 static void ahci_pci_print_info(struct ata_host *host)
710 {
711 struct pci_dev *pdev = to_pci_dev(host->dev);
712 u16 cc;
713 const char *scc_s;
714
715 pci_read_config_word(pdev, 0x0a, &cc);
716 if (cc == PCI_CLASS_STORAGE_IDE)
717 scc_s = "IDE";
718 else if (cc == PCI_CLASS_STORAGE_SATA)
719 scc_s = "SATA";
720 else if (cc == PCI_CLASS_STORAGE_RAID)
721 scc_s = "RAID";
722 else
723 scc_s = "unknown";
724
725 ahci_print_info(host, scc_s);
726 }
727
728 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
729 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
730 * support PMP and the 4726 either directly exports the device
731 * attached to the first downstream port or acts as a hardware storage
732 * controller and emulate a single ATA device (can be RAID 0/1 or some
733 * other configuration).
734 *
735 * When there's no device attached to the first downstream port of the
736 * 4726, "Config Disk" appears, which is a pseudo ATA device to
737 * configure the 4726. However, ATA emulation of the device is very
738 * lame. It doesn't send signature D2H Reg FIS after the initial
739 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
740 *
741 * The following function works around the problem by always using
742 * hardreset on the port and not depending on receiving signature FIS
743 * afterward. If signature FIS isn't received soon, ATA class is
744 * assumed without follow-up softreset.
745 */
746 static void ahci_p5wdh_workaround(struct ata_host *host)
747 {
748 static struct dmi_system_id sysids[] = {
749 {
750 .ident = "P5W DH Deluxe",
751 .matches = {
752 DMI_MATCH(DMI_SYS_VENDOR,
753 "ASUSTEK COMPUTER INC"),
754 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
755 },
756 },
757 { }
758 };
759 struct pci_dev *pdev = to_pci_dev(host->dev);
760
761 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
762 dmi_check_system(sysids)) {
763 struct ata_port *ap = host->ports[1];
764
765 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
766 "Deluxe on-board SIMG4726 workaround\n");
767
768 ap->ops = &ahci_p5wdh_ops;
769 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
770 }
771 }
772
773 /* only some SB600 ahci controllers can do 64bit DMA */
774 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
775 {
776 static const struct dmi_system_id sysids[] = {
777 /*
778 * The oldest version known to be broken is 0901 and
779 * working is 1501 which was released on 2007-10-26.
780 * Enable 64bit DMA on 1501 and anything newer.
781 *
782 * Please read bko#9412 for more info.
783 */
784 {
785 .ident = "ASUS M2A-VM",
786 .matches = {
787 DMI_MATCH(DMI_BOARD_VENDOR,
788 "ASUSTeK Computer INC."),
789 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
790 },
791 .driver_data = "20071026", /* yyyymmdd */
792 },
793 /*
794 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
795 * support 64bit DMA.
796 *
797 * BIOS versions earlier than 1.5 had the Manufacturer DMI
798 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
799 * This spelling mistake was fixed in BIOS version 1.5, so
800 * 1.5 and later have the Manufacturer as
801 * "MICRO-STAR INTERNATIONAL CO.,LTD".
802 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
803 *
804 * BIOS versions earlier than 1.9 had a Board Product Name
805 * DMI field of "MS-7376". This was changed to be
806 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
807 * match on DMI_BOARD_NAME of "MS-7376".
808 */
809 {
810 .ident = "MSI K9A2 Platinum",
811 .matches = {
812 DMI_MATCH(DMI_BOARD_VENDOR,
813 "MICRO-STAR INTER"),
814 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
815 },
816 },
817 /*
818 * All BIOS versions for the Asus M3A support 64bit DMA.
819 * (all release versions from 0301 to 1206 were tested)
820 */
821 {
822 .ident = "ASUS M3A",
823 .matches = {
824 DMI_MATCH(DMI_BOARD_VENDOR,
825 "ASUSTeK Computer INC."),
826 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
827 },
828 },
829 { }
830 };
831 const struct dmi_system_id *match;
832 int year, month, date;
833 char buf[9];
834
835 match = dmi_first_match(sysids);
836 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
837 !match)
838 return false;
839
840 if (!match->driver_data)
841 goto enable_64bit;
842
843 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
844 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
845
846 if (strcmp(buf, match->driver_data) >= 0)
847 goto enable_64bit;
848 else {
849 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
850 "forcing 32bit DMA, update BIOS\n", match->ident);
851 return false;
852 }
853
854 enable_64bit:
855 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
856 match->ident);
857 return true;
858 }
859
860 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
861 {
862 static const struct dmi_system_id broken_systems[] = {
863 {
864 .ident = "HP Compaq nx6310",
865 .matches = {
866 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
867 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
868 },
869 /* PCI slot number of the controller */
870 .driver_data = (void *)0x1FUL,
871 },
872 {
873 .ident = "HP Compaq 6720s",
874 .matches = {
875 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
876 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
877 },
878 /* PCI slot number of the controller */
879 .driver_data = (void *)0x1FUL,
880 },
881
882 { } /* terminate list */
883 };
884 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
885
886 if (dmi) {
887 unsigned long slot = (unsigned long)dmi->driver_data;
888 /* apply the quirk only to on-board controllers */
889 return slot == PCI_SLOT(pdev->devfn);
890 }
891
892 return false;
893 }
894
895 static bool ahci_broken_suspend(struct pci_dev *pdev)
896 {
897 static const struct dmi_system_id sysids[] = {
898 /*
899 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
900 * to the harddisk doesn't become online after
901 * resuming from STR. Warn and fail suspend.
902 *
903 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
904 *
905 * Use dates instead of versions to match as HP is
906 * apparently recycling both product and version
907 * strings.
908 *
909 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
910 */
911 {
912 .ident = "dv4",
913 .matches = {
914 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
915 DMI_MATCH(DMI_PRODUCT_NAME,
916 "HP Pavilion dv4 Notebook PC"),
917 },
918 .driver_data = "20090105", /* F.30 */
919 },
920 {
921 .ident = "dv5",
922 .matches = {
923 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
924 DMI_MATCH(DMI_PRODUCT_NAME,
925 "HP Pavilion dv5 Notebook PC"),
926 },
927 .driver_data = "20090506", /* F.16 */
928 },
929 {
930 .ident = "dv6",
931 .matches = {
932 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
933 DMI_MATCH(DMI_PRODUCT_NAME,
934 "HP Pavilion dv6 Notebook PC"),
935 },
936 .driver_data = "20090423", /* F.21 */
937 },
938 {
939 .ident = "HDX18",
940 .matches = {
941 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
942 DMI_MATCH(DMI_PRODUCT_NAME,
943 "HP HDX18 Notebook PC"),
944 },
945 .driver_data = "20090430", /* F.23 */
946 },
947 /*
948 * Acer eMachines G725 has the same problem. BIOS
949 * V1.03 is known to be broken. V3.04 is known to
950 * work. Between, there are V1.06, V2.06 and V3.03
951 * that we don't have much idea about. For now,
952 * blacklist anything older than V3.04.
953 *
954 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
955 */
956 {
957 .ident = "G725",
958 .matches = {
959 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
960 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
961 },
962 .driver_data = "20091216", /* V3.04 */
963 },
964 { } /* terminate list */
965 };
966 const struct dmi_system_id *dmi = dmi_first_match(sysids);
967 int year, month, date;
968 char buf[9];
969
970 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
971 return false;
972
973 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
974 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
975
976 return strcmp(buf, dmi->driver_data) < 0;
977 }
978
979 static bool ahci_broken_online(struct pci_dev *pdev)
980 {
981 #define ENCODE_BUSDEVFN(bus, slot, func) \
982 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
983 static const struct dmi_system_id sysids[] = {
984 /*
985 * There are several gigabyte boards which use
986 * SIMG5723s configured as hardware RAID. Certain
987 * 5723 firmware revisions shipped there keep the link
988 * online but fail to answer properly to SRST or
989 * IDENTIFY when no device is attached downstream
990 * causing libata to retry quite a few times leading
991 * to excessive detection delay.
992 *
993 * As these firmwares respond to the second reset try
994 * with invalid device signature, considering unknown
995 * sig as offline works around the problem acceptably.
996 */
997 {
998 .ident = "EP45-DQ6",
999 .matches = {
1000 DMI_MATCH(DMI_BOARD_VENDOR,
1001 "Gigabyte Technology Co., Ltd."),
1002 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1003 },
1004 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1005 },
1006 {
1007 .ident = "EP45-DS5",
1008 .matches = {
1009 DMI_MATCH(DMI_BOARD_VENDOR,
1010 "Gigabyte Technology Co., Ltd."),
1011 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1012 },
1013 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1014 },
1015 { } /* terminate list */
1016 };
1017 #undef ENCODE_BUSDEVFN
1018 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1019 unsigned int val;
1020
1021 if (!dmi)
1022 return false;
1023
1024 val = (unsigned long)dmi->driver_data;
1025
1026 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1027 }
1028
1029 #ifdef CONFIG_ATA_ACPI
1030 static void ahci_gtf_filter_workaround(struct ata_host *host)
1031 {
1032 static const struct dmi_system_id sysids[] = {
1033 /*
1034 * Aspire 3810T issues a bunch of SATA enable commands
1035 * via _GTF including an invalid one and one which is
1036 * rejected by the device. Among the successful ones
1037 * is FPDMA non-zero offset enable which when enabled
1038 * only on the drive side leads to NCQ command
1039 * failures. Filter it out.
1040 */
1041 {
1042 .ident = "Aspire 3810T",
1043 .matches = {
1044 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1045 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1046 },
1047 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1048 },
1049 { }
1050 };
1051 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1052 unsigned int filter;
1053 int i;
1054
1055 if (!dmi)
1056 return;
1057
1058 filter = (unsigned long)dmi->driver_data;
1059 dev_printk(KERN_INFO, host->dev,
1060 "applying extra ACPI _GTF filter 0x%x for %s\n",
1061 filter, dmi->ident);
1062
1063 for (i = 0; i < host->n_ports; i++) {
1064 struct ata_port *ap = host->ports[i];
1065 struct ata_link *link;
1066 struct ata_device *dev;
1067
1068 ata_for_each_link(link, ap, EDGE)
1069 ata_for_each_dev(dev, link, ALL)
1070 dev->gtf_filter |= filter;
1071 }
1072 }
1073 #else
1074 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1075 {}
1076 #endif
1077
1078 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1079 {
1080 static int printed_version;
1081 unsigned int board_id = ent->driver_data;
1082 struct ata_port_info pi = ahci_port_info[board_id];
1083 const struct ata_port_info *ppi[] = { &pi, NULL };
1084 struct device *dev = &pdev->dev;
1085 struct ahci_host_priv *hpriv;
1086 struct ata_host *host;
1087 int n_ports, i, rc;
1088
1089 VPRINTK("ENTER\n");
1090
1091 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1092
1093 if (!printed_version++)
1094 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1095
1096 /* The AHCI driver can only drive the SATA ports, the PATA driver
1097 can drive them all so if both drivers are selected make sure
1098 AHCI stays out of the way */
1099 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1100 return -ENODEV;
1101
1102 /*
1103 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1104 * ahci, use ata_generic instead.
1105 */
1106 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1107 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1108 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1109 pdev->subsystem_device == 0xcb89)
1110 return -ENODEV;
1111
1112 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1113 * At the moment, we can only use the AHCI mode. Let the users know
1114 * that for SAS drives they're out of luck.
1115 */
1116 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1117 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1118 "can only drive SATA devices with this driver\n");
1119
1120 /* acquire resources */
1121 rc = pcim_enable_device(pdev);
1122 if (rc)
1123 return rc;
1124
1125 /* AHCI controllers often implement SFF compatible interface.
1126 * Grab all PCI BARs just in case.
1127 */
1128 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1129 if (rc == -EBUSY)
1130 pcim_pin_device(pdev);
1131 if (rc)
1132 return rc;
1133
1134 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1135 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1136 u8 map;
1137
1138 /* ICH6s share the same PCI ID for both piix and ahci
1139 * modes. Enabling ahci mode while MAP indicates
1140 * combined mode is a bad idea. Yield to ata_piix.
1141 */
1142 pci_read_config_byte(pdev, ICH_MAP, &map);
1143 if (map & 0x3) {
1144 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1145 "combined mode, can't enable AHCI mode\n");
1146 return -ENODEV;
1147 }
1148 }
1149
1150 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1151 if (!hpriv)
1152 return -ENOMEM;
1153 hpriv->flags |= (unsigned long)pi.private_data;
1154
1155 /* MCP65 revision A1 and A2 can't do MSI */
1156 if (board_id == board_ahci_mcp65 &&
1157 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1158 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1159
1160 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1161 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1162 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1163
1164 /* only some SB600s can do 64bit DMA */
1165 if (ahci_sb600_enable_64bit(pdev))
1166 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1167
1168 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1169 pci_intx(pdev, 1);
1170
1171 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1172
1173 /* save initial config */
1174 ahci_pci_save_initial_config(pdev, hpriv);
1175
1176 /* prepare host */
1177 if (hpriv->cap & HOST_CAP_NCQ) {
1178 pi.flags |= ATA_FLAG_NCQ;
1179 /*
1180 * Auto-activate optimization is supposed to be
1181 * supported on all AHCI controllers indicating NCQ
1182 * capability, but it seems to be broken on some
1183 * chipsets including NVIDIAs.
1184 */
1185 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1186 pi.flags |= ATA_FLAG_FPDMA_AA;
1187 }
1188
1189 if (hpriv->cap & HOST_CAP_PMP)
1190 pi.flags |= ATA_FLAG_PMP;
1191
1192 ahci_set_em_messages(hpriv, &pi);
1193
1194 if (ahci_broken_system_poweroff(pdev)) {
1195 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1196 dev_info(&pdev->dev,
1197 "quirky BIOS, skipping spindown on poweroff\n");
1198 }
1199
1200 if (ahci_broken_suspend(pdev)) {
1201 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1202 dev_printk(KERN_WARNING, &pdev->dev,
1203 "BIOS update required for suspend/resume\n");
1204 }
1205
1206 if (ahci_broken_online(pdev)) {
1207 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1208 dev_info(&pdev->dev,
1209 "online status unreliable, applying workaround\n");
1210 }
1211
1212 /* CAP.NP sometimes indicate the index of the last enabled
1213 * port, at other times, that of the last possible port, so
1214 * determining the maximum port number requires looking at
1215 * both CAP.NP and port_map.
1216 */
1217 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1218
1219 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1220 if (!host)
1221 return -ENOMEM;
1222 host->private_data = hpriv;
1223
1224 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1225 host->flags |= ATA_HOST_PARALLEL_SCAN;
1226 else
1227 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1228
1229 if (pi.flags & ATA_FLAG_EM)
1230 ahci_reset_em(host);
1231
1232 for (i = 0; i < host->n_ports; i++) {
1233 struct ata_port *ap = host->ports[i];
1234
1235 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1236 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1237 0x100 + ap->port_no * 0x80, "port");
1238
1239 /* set enclosure management message type */
1240 if (ap->flags & ATA_FLAG_EM)
1241 ap->em_message_type = hpriv->em_msg_type;
1242
1243
1244 /* disabled/not-implemented port */
1245 if (!(hpriv->port_map & (1 << i)))
1246 ap->ops = &ata_dummy_port_ops;
1247 }
1248
1249 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1250 ahci_p5wdh_workaround(host);
1251
1252 /* apply gtf filter quirk */
1253 ahci_gtf_filter_workaround(host);
1254
1255 /* initialize adapter */
1256 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1257 if (rc)
1258 return rc;
1259
1260 rc = ahci_pci_reset_controller(host);
1261 if (rc)
1262 return rc;
1263
1264 ahci_pci_init_controller(host);
1265 ahci_pci_print_info(host);
1266
1267 pci_set_master(pdev);
1268 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1269 &ahci_sht);
1270 }
1271
1272 static int __init ahci_init(void)
1273 {
1274 return pci_register_driver(&ahci_pci_driver);
1275 }
1276
1277 static void __exit ahci_exit(void)
1278 {
1279 pci_unregister_driver(&ahci_pci_driver);
1280 }
1281
1282
1283 MODULE_AUTHOR("Jeff Garzik");
1284 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1285 MODULE_LICENSE("GPL");
1286 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1287 MODULE_VERSION(DRV_VERSION);
1288
1289 module_init(ahci_init);
1290 module_exit(ahci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree