arch/ppc64/kernel/cputable.c

   1 /*
   2  *  arch/ppc64/kernel/cputable.c
   3  *
   4  *  Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
   5  *
   6  *  Modifications for ppc64:
   7  *      Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
   8  *
   9  *  This program is free software; you can redistribute it and/or
  10  *  modify it under the terms of the GNU General Public License
  11  *  as published by the Free Software Foundation; either version
  12  *  2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/string.h>
  17 #include <linux/sched.h>
  18 #include <linux/threads.h>
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21
  22 #include <asm/cputable.h>
  23
  24 struct cpu_spec* cur_cpu_spec = NULL;
  25 EXPORT_SYMBOL(cur_cpu_spec);
  26
  27 /* NOTE:
  28  * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  29  * the responsibility of the appropriate CPU save/restore functions to
  30  * eventually copy these settings over. Those save/restore aren't yet
  31  * part of the cputable though. That has to be fixed for both ppc32
  32  * and ppc64
  33  */
  34 extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
  35 extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
  36 extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  37 extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
  38
  39
  40 /* We only set the altivec features if the kernel was compiled with altivec
  41  * support
  42  */
  43 #ifdef CONFIG_ALTIVEC
  44 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
  45 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
  46 #else
  47 #define CPU_FTR_ALTIVEC_COMP    0
  48 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
  49 #endif
  50
  51 struct cpu_spec cpu_specs[] = {
  52         {       /* Power3 */
  53                 .pvr_mask               = 0xffff0000,
  54                 .pvr_value              = 0x00400000,
  55                 .cpu_name               = "POWER3 (630)",
  56                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  57                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
  58                 .cpu_user_features = COMMON_USER_PPC64,
  59                 .icache_bsize           = 128,
  60                 .dcache_bsize           = 128,
  61                 .num_pmcs               = 8,
  62                 .cpu_setup              = __setup_cpu_power3,
  63                 .oprofile_cpu_type      = "ppc64/power3",
  64         },
  65         {       /* Power3+ */
  66                 .pvr_mask               = 0xffff0000,
  67                 .pvr_value              = 0x00410000,
  68                 .cpu_name               = "POWER3 (630+)",
  69                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  70                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
  71                 .cpu_user_features      = COMMON_USER_PPC64,
  72                 .icache_bsize           = 128,
  73                 .dcache_bsize           = 128,
  74                 .num_pmcs               = 8,
  75                 .cpu_setup              = __setup_cpu_power3,
  76                 .oprofile_cpu_type      = "ppc64/power3",
  77         },
  78         {       /* Northstar */
  79                 .pvr_mask               = 0xffff0000,
  80                 .pvr_value              = 0x00330000,
  81                 .cpu_name               = "RS64-II (northstar)",
  82                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  83                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  84                         CPU_FTR_MMCRA | CPU_FTR_CTRL,
  85                 .cpu_user_features      = COMMON_USER_PPC64,
  86                 .icache_bsize           = 128,
  87                 .dcache_bsize           = 128,
  88                 .num_pmcs               = 8,
  89                 .cpu_setup              = __setup_cpu_power3,
  90                 .oprofile_cpu_type      = "ppc64/rs64",
  91         },
  92         {       /* Pulsar */
  93                 .pvr_mask               = 0xffff0000,
  94                 .pvr_value              = 0x00340000,
  95                 .cpu_name               = "RS64-III (pulsar)",
  96                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
  97                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
  98                         CPU_FTR_MMCRA | CPU_FTR_CTRL,
  99                 .cpu_user_features      = COMMON_USER_PPC64,
 100                 .icache_bsize           = 128,
 101                 .dcache_bsize           = 128,
 102                 .num_pmcs               = 8,
 103                 .cpu_setup              = __setup_cpu_power3,
 104                 .oprofile_cpu_type      = "ppc64/rs64",
 105         },
 106         {       /* I-star */
 107                 .pvr_mask               = 0xffff0000,
 108                 .pvr_value              = 0x00360000,
 109                 .cpu_name               = "RS64-III (icestar)",
 110                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 111                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
 112                         CPU_FTR_MMCRA | CPU_FTR_CTRL,
 113                 .cpu_user_features      = COMMON_USER_PPC64,
 114                 .icache_bsize           = 128,
 115                 .dcache_bsize           = 128,
 116                 .num_pmcs               = 8,
 117                 .cpu_setup              = __setup_cpu_power3,
 118                 .oprofile_cpu_type      = "ppc64/rs64",
 119         },
 120         {       /* S-star */
 121                 .pvr_mask               = 0xffff0000,
 122                 .pvr_value              = 0x00370000,
 123                 .cpu_name               = "RS64-IV (sstar)",
 124                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 125                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
 126                         CPU_FTR_MMCRA | CPU_FTR_CTRL,
 127                 .cpu_user_features      = COMMON_USER_PPC64,
 128                 .icache_bsize           = 128,
 129                 .dcache_bsize           = 128,
 130                 .num_pmcs               = 8,
 131                 .cpu_setup              = __setup_cpu_power3,
 132                 .oprofile_cpu_type      = "ppc64/rs64",
 133         },
 134         {       /* Power4 */
 135                 .pvr_mask               = 0xffff0000,
 136                 .pvr_value              = 0x00350000,
 137                 .cpu_name               = "POWER4 (gp)",
 138                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 139                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 140                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
 141                 .cpu_user_features      = COMMON_USER_PPC64,
 142                 .icache_bsize           = 128,
 143                 .dcache_bsize           = 128,
 144                 .num_pmcs               = 8,
 145                 .cpu_setup              = __setup_cpu_power4,
 146                 .oprofile_cpu_type      = "ppc64/power4",
 147         },
 148         {       /* Power4+ */
 149                 .pvr_mask               = 0xffff0000,
 150                 .pvr_value              = 0x00380000,
 151                 .cpu_name               = "POWER4+ (gq)",
 152                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 153                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 154                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
 155                 .cpu_user_features      = COMMON_USER_PPC64,
 156                 .icache_bsize           = 128,
 157                 .dcache_bsize           = 128,
 158                 .num_pmcs               = 8,
 159                 .cpu_setup              = __setup_cpu_power4,
 160                 .oprofile_cpu_type      = "ppc64/power4",
 161         },
 162         {       /* PPC970 */
 163                 .pvr_mask               = 0xffff0000,
 164                 .pvr_value              = 0x00390000,
 165                 .cpu_name               = "PPC970",
 166                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 167                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 168                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 169                         CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
 170                 .cpu_user_features      = COMMON_USER_PPC64 |
 171                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 172                 .icache_bsize           = 128,
 173                 .dcache_bsize           = 128,
 174                 .num_pmcs               = 8,
 175                 .cpu_setup              = __setup_cpu_ppc970,
 176                 .oprofile_cpu_type      = "ppc64/970",
 177         },
 178         {       /* PPC970FX */
 179                 .pvr_mask               = 0xffff0000,
 180                 .pvr_value              = 0x003c0000,
 181                 .cpu_name               = "PPC970FX",
 182                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 183                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 184                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 185                         CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
 186                 .cpu_user_features      = COMMON_USER_PPC64 |
 187                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 188                 .icache_bsize           = 128,
 189                 .dcache_bsize           = 128,
 190                 .num_pmcs               = 8,
 191                 .cpu_setup              = __setup_cpu_ppc970,
 192                 .oprofile_cpu_type      = "ppc64/970",
 193         },
 194         {       /* PPC970MP */
 195                 .pvr_mask               = 0xffff0000,
 196                 .pvr_value              = 0x00440000,
 197                 .cpu_name               = "PPC970MP",
 198                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 199                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 200                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 201                         CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
 202                 .cpu_user_features      = COMMON_USER_PPC64 |
 203                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 204                 .icache_bsize           = 128,
 205                 .dcache_bsize           = 128,
 206                 .cpu_setup              = __setup_cpu_ppc970,
 207                 .oprofile_cpu_type      = "ppc64/970",
 208         },
 209         {       /* Power5 */
 210                 .pvr_mask               = 0xffff0000,
 211                 .pvr_value              = 0x003a0000,
 212                 .cpu_name               = "POWER5 (gr)",
 213                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 214                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 215                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 216                         CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 217                         CPU_FTR_MMCRA_SIHV,
 218                 .cpu_user_features      = COMMON_USER_PPC64,
 219                 .icache_bsize           = 128,
 220                 .dcache_bsize           = 128,
 221                 .num_pmcs               = 6,
 222                 .cpu_setup              = __setup_cpu_power4,
 223                 .oprofile_cpu_type      = "ppc64/power5",
 224         },
 225         {       /* Power5 */
 226                 .pvr_mask               = 0xffff0000,
 227                 .pvr_value              = 0x003b0000,
 228                 .cpu_name               = "POWER5 (gs)",
 229                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 230                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 231                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
 232                         CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
 233                         CPU_FTR_MMCRA_SIHV,
 234                 .cpu_user_features      = COMMON_USER_PPC64,
 235                 .icache_bsize           = 128,
 236                 .dcache_bsize           = 128,
 237                 .num_pmcs               = 6,
 238                 .cpu_setup              = __setup_cpu_power4,
 239                 .oprofile_cpu_type      = "ppc64/power5",
 240         },
 241         {       /* BE DD1.x */
 242                 .pvr_mask               = 0xffff0000,
 243                 .pvr_value              = 0x00700000,
 244                 .cpu_name               = "Broadband Engine",
 245                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 246                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 247                         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
 248                         CPU_FTR_SMT,
 249                 .cpu_user_features      = COMMON_USER_PPC64 |
 250                         PPC_FEATURE_HAS_ALTIVEC_COMP,
 251                 .icache_bsize           = 128,
 252                 .dcache_bsize           = 128,
 253                 .cpu_setup              = __setup_cpu_be,
 254         },
 255         {       /* default match */
 256                 .pvr_mask               = 0x00000000,
 257                 .pvr_value              = 0x00000000,
 258                 .cpu_name               = "POWER4 (compatible)",
 259                 .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
 260                         CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
 261                         CPU_FTR_PPCAS_ARCH_V2,
 262                 .cpu_user_features      = COMMON_USER_PPC64,
 263                 .icache_bsize           = 128,
 264                 .dcache_bsize           = 128,
 265                 .num_pmcs               = 6,
 266                 .cpu_setup              = __setup_cpu_power4,
 267         }
 268 };