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sky2: remove unnecessary reads of PCI_CAP_ID_EXP
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / sky2.c
blobe14b86e27dc979c9c7a3451a0e240b32ebe93cf8
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/slab.h>
38 #include <net/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/in.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
47
48 #include <asm/irq.h>
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.28"
54
55 /*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
58 * similar to Tigon3.
59 */
60
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65
66 /* This is the worst case number of transmit list elements for a single skb:
67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
69 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
70 #define TX_MAX_PENDING 1024
71 #define TX_DEF_PENDING 127
72
73 #define TX_WATCHDOG (5 * HZ)
74 #define NAPI_WEIGHT 64
75 #define PHY_RETRIES 1000
76
77 #define SKY2_EEPROM_MAGIC 0x9955aabb
78
79 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
80
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
85
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
98 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
99 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
102 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
140 { 0 }
141 };
142
143 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145 /* Avoid conditionals by using array */
146 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
148 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149
150 static void sky2_set_multicast(struct net_device *dev);
151
152 /* Access to PHY via serial interconnect */
153 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
154 {
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
167 return 0;
168
169 udelay(10);
170 }
171
172 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
173 return -ETIMEDOUT;
174
175 io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
178 }
179
180 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
181 {
182 int i;
183
184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
197 udelay(10);
198 }
199
200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
201 return -ETIMEDOUT;
202 io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
205 }
206
207 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
208 {
209 u16 v;
210 __gm_phy_read(hw, port, reg, &v);
211 return v;
212 }
213
214
215 static void sky2_power_on(struct sky2_hw *hw)
216 {
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232
233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
234 u32 reg;
235
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237
238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
242
243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
247
248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
249
250 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
251
252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
253 reg = sky2_read32(hw, B2_GP_IO);
254 reg |= GLB_GPIO_STAT_RACE_DIS;
255 sky2_write32(hw, B2_GP_IO, reg);
256
257 sky2_read32(hw, B2_GP_IO);
258 }
259
260 /* Turn on "driver loaded" LED */
261 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
262 }
263
264 static void sky2_power_aux(struct sky2_hw *hw)
265 {
266 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
267 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
268 else
269 /* enable bits are inverted */
270 sky2_write8(hw, B2_Y2_CLK_GATE,
271 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
272 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
273 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
274
275 /* switch power to VAUX if supported and PME from D3cold */
276 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
277 pci_pme_capable(hw->pdev, PCI_D3cold))
278 sky2_write8(hw, B0_POWER_CTRL,
279 (PC_VAUX_ENA | PC_VCC_ENA |
280 PC_VAUX_ON | PC_VCC_OFF));
281
282 /* turn off "driver loaded LED" */
283 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
284 }
285
286 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
287 {
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
292
293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301 }
302
303 /* flow control to advertise bits */
304 static const u16 copper_fc_adv[] = {
305 [FC_NONE] = 0,
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
309 };
310
311 /* flow control to advertise bits when using 1000BaseX */
312 static const u16 fiber_fc_adv[] = {
313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
317 };
318
319 /* flow control to GMA disable bits */
320 static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
324 [FC_BOTH] = 0,
325 };
326
327
328 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
329 {
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
332
333 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
336
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
338 PHY_M_EC_MAC_S_MSK);
339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
340
341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
342 if (hw->chip_id == CHIP_ID_YUKON_EC)
343 /* set downshift counter to 3x and enable downshift */
344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
345 else
346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
348
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 if (sky2_is_copper(hw)) {
354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
357
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
360 u16 spec;
361
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
366 }
367 } else {
368 /* disable energy detect */
369 ctrl &= ~PHY_M_PC_EN_DET_MSK;
370
371 /* enable automatic crossover */
372 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
373
374 /* downshift on PHY 88E1112 and 88E1149 is changed */
375 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
376 (hw->flags & SKY2_HW_NEWER_PHY)) {
377 /* set downshift counter to 3x and enable downshift */
378 ctrl &= ~PHY_M_PC_DSC_MSK;
379 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
380 }
381 }
382 } else {
383 /* workaround for deviation #4.88 (CRC errors) */
384 /* disable Automatic Crossover */
385
386 ctrl &= ~PHY_M_PC_MDIX_MSK;
387 }
388
389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
390
391 /* special setup for PHY 88E1112 Fiber */
392 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
393 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
394
395 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
397 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
398 ctrl &= ~PHY_M_MAC_MD_MSK;
399 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401
402 if (hw->pmd_type == 'P') {
403 /* select page 1 to access Fiber registers */
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
405
406 /* for SFP-module set SIGDET polarity to low */
407 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
408 ctrl |= PHY_M_FIB_SIGD_POL;
409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
410 }
411
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
413 }
414
415 ctrl = PHY_CT_RESET;
416 ct1000 = 0;
417 adv = PHY_AN_CSMA;
418 reg = 0;
419
420 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
421 if (sky2_is_copper(hw)) {
422 if (sky2->advertising & ADVERTISED_1000baseT_Full)
423 ct1000 |= PHY_M_1000C_AFD;
424 if (sky2->advertising & ADVERTISED_1000baseT_Half)
425 ct1000 |= PHY_M_1000C_AHD;
426 if (sky2->advertising & ADVERTISED_100baseT_Full)
427 adv |= PHY_M_AN_100_FD;
428 if (sky2->advertising & ADVERTISED_100baseT_Half)
429 adv |= PHY_M_AN_100_HD;
430 if (sky2->advertising & ADVERTISED_10baseT_Full)
431 adv |= PHY_M_AN_10_FD;
432 if (sky2->advertising & ADVERTISED_10baseT_Half)
433 adv |= PHY_M_AN_10_HD;
434
435 } else { /* special defines for FIBER (88E1040S only) */
436 if (sky2->advertising & ADVERTISED_1000baseT_Full)
437 adv |= PHY_M_AN_1000X_AFD;
438 if (sky2->advertising & ADVERTISED_1000baseT_Half)
439 adv |= PHY_M_AN_1000X_AHD;
440 }
441
442 /* Restart Auto-negotiation */
443 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
444 } else {
445 /* forced speed/duplex settings */
446 ct1000 = PHY_M_1000C_MSE;
447
448 /* Disable auto update for duplex flow control and duplex */
449 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
450
451 switch (sky2->speed) {
452 case SPEED_1000:
453 ctrl |= PHY_CT_SP1000;
454 reg |= GM_GPCR_SPEED_1000;
455 break;
456 case SPEED_100:
457 ctrl |= PHY_CT_SP100;
458 reg |= GM_GPCR_SPEED_100;
459 break;
460 }
461
462 if (sky2->duplex == DUPLEX_FULL) {
463 reg |= GM_GPCR_DUP_FULL;
464 ctrl |= PHY_CT_DUP_MD;
465 } else if (sky2->speed < SPEED_1000)
466 sky2->flow_mode = FC_NONE;
467 }
468
469 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
470 if (sky2_is_copper(hw))
471 adv |= copper_fc_adv[sky2->flow_mode];
472 else
473 adv |= fiber_fc_adv[sky2->flow_mode];
474 } else {
475 reg |= GM_GPCR_AU_FCT_DIS;
476 reg |= gm_fc_disable[sky2->flow_mode];
477
478 /* Forward pause packets to GMAC? */
479 if (sky2->flow_mode & FC_RX)
480 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
481 else
482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
483 }
484
485 gma_write16(hw, port, GM_GP_CTRL, reg);
486
487 if (hw->flags & SKY2_HW_GIGABIT)
488 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
489
490 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
491 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
492
493 /* Setup Phy LED's */
494 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
495 ledover = 0;
496
497 switch (hw->chip_id) {
498 case CHIP_ID_YUKON_FE:
499 /* on 88E3082 these bits are at 11..9 (shifted left) */
500 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
501
502 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
503
504 /* delete ACT LED control bits */
505 ctrl &= ~PHY_M_FELP_LED1_MSK;
506 /* change ACT LED control to blink mode */
507 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
508 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
509 break;
510
511 case CHIP_ID_YUKON_FE_P:
512 /* Enable Link Partner Next Page */
513 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
514 ctrl |= PHY_M_PC_ENA_LIP_NP;
515
516 /* disable Energy Detect and enable scrambler */
517 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
518 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
519
520 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
521 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
522 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
523 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
524
525 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
526 break;
527
528 case CHIP_ID_YUKON_XL:
529 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
530
531 /* select page 3 to access LED control register */
532 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
533
534 /* set LED Function Control register */
535 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
536 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
537 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
538 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
539 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
540
541 /* set Polarity Control register */
542 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
543 (PHY_M_POLC_LS1_P_MIX(4) |
544 PHY_M_POLC_IS0_P_MIX(4) |
545 PHY_M_POLC_LOS_CTRL(2) |
546 PHY_M_POLC_INIT_CTRL(2) |
547 PHY_M_POLC_STA1_CTRL(2) |
548 PHY_M_POLC_STA0_CTRL(2)));
549
550 /* restore page register */
551 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
552 break;
553
554 case CHIP_ID_YUKON_EC_U:
555 case CHIP_ID_YUKON_EX:
556 case CHIP_ID_YUKON_SUPR:
557 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
558
559 /* select page 3 to access LED control register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
561
562 /* set LED Function Control register */
563 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
564 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
565 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
566 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
567 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
568
569 /* set Blink Rate in LED Timer Control Register */
570 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
571 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
572 /* restore page register */
573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
574 break;
575
576 default:
577 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
578 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
579
580 /* turn off the Rx LED (LED_RX) */
581 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
582 }
583
584 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
585 /* apply fixes in PHY AFE */
586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
587
588 /* increase differential signal amplitude in 10BASE-T */
589 gm_phy_write(hw, port, 0x18, 0xaa99);
590 gm_phy_write(hw, port, 0x17, 0x2011);
591
592 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
593 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
594 gm_phy_write(hw, port, 0x18, 0xa204);
595 gm_phy_write(hw, port, 0x17, 0x2002);
596 }
597
598 /* set page register to 0 */
599 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
600 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
601 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
602 /* apply workaround for integrated resistors calibration */
603 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
604 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
605 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
606 /* apply fixes in PHY AFE */
607 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
608
609 /* apply RDAC termination workaround */
610 gm_phy_write(hw, port, 24, 0x2800);
611 gm_phy_write(hw, port, 23, 0x2001);
612
613 /* set page register back to 0 */
614 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
615 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
616 hw->chip_id < CHIP_ID_YUKON_SUPR) {
617 /* no effect on Yukon-XL */
618 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
619
620 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
621 sky2->speed == SPEED_100) {
622 /* turn on 100 Mbps LED (LED_LINK100) */
623 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
624 }
625
626 if (ledover)
627 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
628
629 }
630
631 /* Enable phy interrupt on auto-negotiation complete (or link up) */
632 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
633 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
634 else
635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
636 }
637
638 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
639 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
640
641 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
642 {
643 u32 reg1;
644
645 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
646 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
647 reg1 &= ~phy_power[port];
648
649 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
650 reg1 |= coma_mode[port];
651
652 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
653 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
654 sky2_pci_read32(hw, PCI_DEV_REG1);
655
656 if (hw->chip_id == CHIP_ID_YUKON_FE)
657 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
658 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
659 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
660 }
661
662 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
663 {
664 u32 reg1;
665 u16 ctrl;
666
667 /* release GPHY Control reset */
668 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
669
670 /* release GMAC reset */
671 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
672
673 if (hw->flags & SKY2_HW_NEWER_PHY) {
674 /* select page 2 to access MAC control register */
675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
676
677 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
678 /* allow GMII Power Down */
679 ctrl &= ~PHY_M_MAC_GMIF_PUP;
680 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
681
682 /* set page register back to 0 */
683 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
684 }
685
686 /* setup General Purpose Control Register */
687 gma_write16(hw, port, GM_GP_CTRL,
688 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
689 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
690 GM_GPCR_AU_SPD_DIS);
691
692 if (hw->chip_id != CHIP_ID_YUKON_EC) {
693 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
694 /* select page 2 to access MAC control register */
695 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
696
697 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
698 /* enable Power Down */
699 ctrl |= PHY_M_PC_POW_D_ENA;
700 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
701
702 /* set page register back to 0 */
703 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
704 }
705
706 /* set IEEE compatible Power Down Mode (dev. #4.99) */
707 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
708 }
709
710 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
711 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
712 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
713 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
714 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
715 }
716
717 /* Enable Rx/Tx */
718 static void sky2_enable_rx_tx(struct sky2_port *sky2)
719 {
720 struct sky2_hw *hw = sky2->hw;
721 unsigned port = sky2->port;
722 u16 reg;
723
724 reg = gma_read16(hw, port, GM_GP_CTRL);
725 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
726 gma_write16(hw, port, GM_GP_CTRL, reg);
727 }
728
729 /* Force a renegotiation */
730 static void sky2_phy_reinit(struct sky2_port *sky2)
731 {
732 spin_lock_bh(&sky2->phy_lock);
733 sky2_phy_init(sky2->hw, sky2->port);
734 sky2_enable_rx_tx(sky2);
735 spin_unlock_bh(&sky2->phy_lock);
736 }
737
738 /* Put device in state to listen for Wake On Lan */
739 static void sky2_wol_init(struct sky2_port *sky2)
740 {
741 struct sky2_hw *hw = sky2->hw;
742 unsigned port = sky2->port;
743 enum flow_control save_mode;
744 u16 ctrl;
745
746 /* Bring hardware out of reset */
747 sky2_write16(hw, B0_CTST, CS_RST_CLR);
748 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
749
750 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
751 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
752
753 /* Force to 10/100
754 * sky2_reset will re-enable on resume
755 */
756 save_mode = sky2->flow_mode;
757 ctrl = sky2->advertising;
758
759 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
760 sky2->flow_mode = FC_NONE;
761
762 spin_lock_bh(&sky2->phy_lock);
763 sky2_phy_power_up(hw, port);
764 sky2_phy_init(hw, port);
765 spin_unlock_bh(&sky2->phy_lock);
766
767 sky2->flow_mode = save_mode;
768 sky2->advertising = ctrl;
769
770 /* Set GMAC to no flow control and auto update for speed/duplex */
771 gma_write16(hw, port, GM_GP_CTRL,
772 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
773 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
774
775 /* Set WOL address */
776 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
777 sky2->netdev->dev_addr, ETH_ALEN);
778
779 /* Turn on appropriate WOL control bits */
780 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
781 ctrl = 0;
782 if (sky2->wol & WAKE_PHY)
783 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
784 else
785 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
786
787 if (sky2->wol & WAKE_MAGIC)
788 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
789 else
790 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
791
792 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
793 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
794
795 /* Disable PiG firmware */
796 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
797
798 /* block receiver */
799 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
800 }
801
802 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
803 {
804 struct net_device *dev = hw->dev[port];
805
806 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
807 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
808 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
809 /* Yukon-Extreme B0 and further Extreme devices */
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
811 } else if (dev->mtu > ETH_DATA_LEN) {
812 /* set Tx GMAC FIFO Almost Empty Threshold */
813 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
814 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
815
816 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
817 } else
818 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
819 }
820
821 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
822 {
823 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
824 u16 reg;
825 u32 rx_reg;
826 int i;
827 const u8 *addr = hw->dev[port]->dev_addr;
828
829 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
830 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
831
832 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
833
834 if (hw->chip_id == CHIP_ID_YUKON_XL &&
835 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
836 port == 1) {
837 /* WA DEV_472 -- looks like crossed wires on port 2 */
838 /* clear GMAC 1 Control reset */
839 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
840 do {
841 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
842 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
843 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
844 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
845 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
846 }
847
848 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
849
850 /* Enable Transmit FIFO Underrun */
851 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
852
853 spin_lock_bh(&sky2->phy_lock);
854 sky2_phy_power_up(hw, port);
855 sky2_phy_init(hw, port);
856 spin_unlock_bh(&sky2->phy_lock);
857
858 /* MIB clear */
859 reg = gma_read16(hw, port, GM_PHY_ADDR);
860 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
861
862 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
863 gma_read16(hw, port, i);
864 gma_write16(hw, port, GM_PHY_ADDR, reg);
865
866 /* transmit control */
867 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
868
869 /* receive control reg: unicast + multicast + no FCS */
870 gma_write16(hw, port, GM_RX_CTRL,
871 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
872
873 /* transmit flow control */
874 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
875
876 /* transmit parameter */
877 gma_write16(hw, port, GM_TX_PARAM,
878 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
879 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
880 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
881 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
882
883 /* serial mode register */
884 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
885 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
886
887 if (hw->dev[port]->mtu > ETH_DATA_LEN)
888 reg |= GM_SMOD_JUMBO_ENA;
889
890 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
891 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
892 reg |= GM_NEW_FLOW_CTRL;
893
894 gma_write16(hw, port, GM_SERIAL_MODE, reg);
895
896 /* virtual address for data */
897 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
898
899 /* physical address: used for pause frames */
900 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
901
902 /* ignore counter overflows */
903 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
904 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
905 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
906
907 /* Configure Rx MAC FIFO */
908 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
909 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
910 if (hw->chip_id == CHIP_ID_YUKON_EX ||
911 hw->chip_id == CHIP_ID_YUKON_FE_P)
912 rx_reg |= GMF_RX_OVER_ON;
913
914 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
915
916 if (hw->chip_id == CHIP_ID_YUKON_XL) {
917 /* Hardware errata - clear flush mask */
918 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
919 } else {
920 /* Flush Rx MAC FIFO on any flow control or error */
921 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
922 }
923
924 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
925 reg = RX_GMF_FL_THR_DEF + 1;
926 /* Another magic mystery workaround from sk98lin */
927 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
928 hw->chip_rev == CHIP_REV_YU_FE2_A0)
929 reg = 0x178;
930 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
931
932 /* Configure Tx MAC FIFO */
933 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
934 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
935
936 /* On chips without ram buffer, pause is controlled by MAC level */
937 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
938 /* Pause threshold is scaled by 8 in bytes */
939 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
940 hw->chip_rev == CHIP_REV_YU_FE2_A0)
941 reg = 1568 / 8;
942 else
943 reg = 1024 / 8;
944 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
945 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
946
947 sky2_set_tx_stfwd(hw, port);
948 }
949
950 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
951 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
952 /* disable dynamic watermark */
953 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
954 reg &= ~TX_DYN_WM_ENA;
955 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
956 }
957 }
958
959 /* Assign Ram Buffer allocation to queue */
960 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
961 {
962 u32 end;
963
964 /* convert from K bytes to qwords used for hw register */
965 start *= 1024/8;
966 space *= 1024/8;
967 end = start + space - 1;
968
969 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
970 sky2_write32(hw, RB_ADDR(q, RB_START), start);
971 sky2_write32(hw, RB_ADDR(q, RB_END), end);
972 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
973 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
974
975 if (q == Q_R1 || q == Q_R2) {
976 u32 tp = space - space/4;
977
978 /* On receive queue's set the thresholds
979 * give receiver priority when > 3/4 full
980 * send pause when down to 2K
981 */
982 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
983 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
984
985 tp = space - 2048/8;
986 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
987 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
988 } else {
989 /* Enable store & forward on Tx queue's because
990 * Tx FIFO is only 1K on Yukon
991 */
992 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
993 }
994
995 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
996 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
997 }
998
999 /* Setup Bus Memory Interface */
1000 static void sky2_qset(struct sky2_hw *hw, u16 q)
1001 {
1002 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1003 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1004 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1005 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1006 }
1007
1008 /* Setup prefetch unit registers. This is the interface between
1009 * hardware and driver list elements
1010 */
1011 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1012 dma_addr_t addr, u32 last)
1013 {
1014 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1015 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1017 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1018 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1019 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1020
1021 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1022 }
1023
1024 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1025 {
1026 struct sky2_tx_le *le = sky2->tx_le + *slot;
1027
1028 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1029 le->ctrl = 0;
1030 return le;
1031 }
1032
1033 static void tx_init(struct sky2_port *sky2)
1034 {
1035 struct sky2_tx_le *le;
1036
1037 sky2->tx_prod = sky2->tx_cons = 0;
1038 sky2->tx_tcpsum = 0;
1039 sky2->tx_last_mss = 0;
1040
1041 le = get_tx_le(sky2, &sky2->tx_prod);
1042 le->addr = 0;
1043 le->opcode = OP_ADDR64 | HW_OWNER;
1044 sky2->tx_last_upper = 0;
1045 }
1046
1047 /* Update chip's next pointer */
1048 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1049 {
1050 /* Make sure write' to descriptors are complete before we tell hardware */
1051 wmb();
1052 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1053
1054 /* Synchronize I/O on since next processor may write to tail */
1055 mmiowb();
1056 }
1057
1058
1059 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1060 {
1061 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1062 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1063 le->ctrl = 0;
1064 return le;
1065 }
1066
1067 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1068 {
1069 unsigned size;
1070
1071 /* Space needed for frame data + headers rounded up */
1072 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1073
1074 /* Stopping point for hardware truncation */
1075 return (size - 8) / sizeof(u32);
1076 }
1077
1078 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1079 {
1080 struct rx_ring_info *re;
1081 unsigned size;
1082
1083 /* Space needed for frame data + headers rounded up */
1084 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1085
1086 sky2->rx_nfrags = size >> PAGE_SHIFT;
1087 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1088
1089 /* Compute residue after pages */
1090 size -= sky2->rx_nfrags << PAGE_SHIFT;
1091
1092 /* Optimize to handle small packets and headers */
1093 if (size < copybreak)
1094 size = copybreak;
1095 if (size < ETH_HLEN)
1096 size = ETH_HLEN;
1097
1098 return size;
1099 }
1100
1101 /* Build description to hardware for one receive segment */
1102 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1103 dma_addr_t map, unsigned len)
1104 {
1105 struct sky2_rx_le *le;
1106
1107 if (sizeof(dma_addr_t) > sizeof(u32)) {
1108 le = sky2_next_rx(sky2);
1109 le->addr = cpu_to_le32(upper_32_bits(map));
1110 le->opcode = OP_ADDR64 | HW_OWNER;
1111 }
1112
1113 le = sky2_next_rx(sky2);
1114 le->addr = cpu_to_le32(lower_32_bits(map));
1115 le->length = cpu_to_le16(len);
1116 le->opcode = op | HW_OWNER;
1117 }
1118
1119 /* Build description to hardware for one possibly fragmented skb */
1120 static void sky2_rx_submit(struct sky2_port *sky2,
1121 const struct rx_ring_info *re)
1122 {
1123 int i;
1124
1125 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1126
1127 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1128 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1129 }
1130
1131
1132 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1133 unsigned size)
1134 {
1135 struct sk_buff *skb = re->skb;
1136 int i;
1137
1138 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1139 if (pci_dma_mapping_error(pdev, re->data_addr))
1140 goto mapping_error;
1141
1142 dma_unmap_len_set(re, data_size, size);
1143
1144 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1145 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1146
1147 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1148 frag->page_offset,
1149 frag->size,
1150 PCI_DMA_FROMDEVICE);
1151
1152 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1153 goto map_page_error;
1154 }
1155 return 0;
1156
1157 map_page_error:
1158 while (--i >= 0) {
1159 pci_unmap_page(pdev, re->frag_addr[i],
1160 skb_shinfo(skb)->frags[i].size,
1161 PCI_DMA_FROMDEVICE);
1162 }
1163
1164 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1165 PCI_DMA_FROMDEVICE);
1166
1167 mapping_error:
1168 if (net_ratelimit())
1169 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1170 skb->dev->name);
1171 return -EIO;
1172 }
1173
1174 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1175 {
1176 struct sk_buff *skb = re->skb;
1177 int i;
1178
1179 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1180 PCI_DMA_FROMDEVICE);
1181
1182 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1183 pci_unmap_page(pdev, re->frag_addr[i],
1184 skb_shinfo(skb)->frags[i].size,
1185 PCI_DMA_FROMDEVICE);
1186 }
1187
1188 /* Tell chip where to start receive checksum.
1189 * Actually has two checksums, but set both same to avoid possible byte
1190 * order problems.
1191 */
1192 static void rx_set_checksum(struct sky2_port *sky2)
1193 {
1194 struct sky2_rx_le *le = sky2_next_rx(sky2);
1195
1196 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1197 le->ctrl = 0;
1198 le->opcode = OP_TCPSTART | HW_OWNER;
1199
1200 sky2_write32(sky2->hw,
1201 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1202 (sky2->netdev->features & NETIF_F_RXCSUM)
1203 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1204 }
1205
1206 /* Enable/disable receive hash calculation (RSS) */
1207 static void rx_set_rss(struct net_device *dev, u32 features)
1208 {
1209 struct sky2_port *sky2 = netdev_priv(dev);
1210 struct sky2_hw *hw = sky2->hw;
1211 int i, nkeys = 4;
1212
1213 /* Supports IPv6 and other modes */
1214 if (hw->flags & SKY2_HW_NEW_LE) {
1215 nkeys = 10;
1216 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1217 }
1218
1219 /* Program RSS initial values */
1220 if (features & NETIF_F_RXHASH) {
1221 u32 key[nkeys];
1222
1223 get_random_bytes(key, nkeys * sizeof(u32));
1224 for (i = 0; i < nkeys; i++)
1225 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1226 key[i]);
1227
1228 /* Need to turn on (undocumented) flag to make hashing work */
1229 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1230 RX_STFW_ENA);
1231
1232 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1233 BMU_ENA_RX_RSS_HASH);
1234 } else
1235 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1236 BMU_DIS_RX_RSS_HASH);
1237 }
1238
1239 /*
1240 * The RX Stop command will not work for Yukon-2 if the BMU does not
1241 * reach the end of packet and since we can't make sure that we have
1242 * incoming data, we must reset the BMU while it is not doing a DMA
1243 * transfer. Since it is possible that the RX path is still active,
1244 * the RX RAM buffer will be stopped first, so any possible incoming
1245 * data will not trigger a DMA. After the RAM buffer is stopped, the
1246 * BMU is polled until any DMA in progress is ended and only then it
1247 * will be reset.
1248 */
1249 static void sky2_rx_stop(struct sky2_port *sky2)
1250 {
1251 struct sky2_hw *hw = sky2->hw;
1252 unsigned rxq = rxqaddr[sky2->port];
1253 int i;
1254
1255 /* disable the RAM Buffer receive queue */
1256 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1257
1258 for (i = 0; i < 0xffff; i++)
1259 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1260 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1261 goto stopped;
1262
1263 netdev_warn(sky2->netdev, "receiver stop failed\n");
1264 stopped:
1265 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1266
1267 /* reset the Rx prefetch unit */
1268 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1269 mmiowb();
1270 }
1271
1272 /* Clean out receive buffer area, assumes receiver hardware stopped */
1273 static void sky2_rx_clean(struct sky2_port *sky2)
1274 {
1275 unsigned i;
1276
1277 memset(sky2->rx_le, 0, RX_LE_BYTES);
1278 for (i = 0; i < sky2->rx_pending; i++) {
1279 struct rx_ring_info *re = sky2->rx_ring + i;
1280
1281 if (re->skb) {
1282 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1283 kfree_skb(re->skb);
1284 re->skb = NULL;
1285 }
1286 }
1287 }
1288
1289 /* Basic MII support */
1290 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1291 {
1292 struct mii_ioctl_data *data = if_mii(ifr);
1293 struct sky2_port *sky2 = netdev_priv(dev);
1294 struct sky2_hw *hw = sky2->hw;
1295 int err = -EOPNOTSUPP;
1296
1297 if (!netif_running(dev))
1298 return -ENODEV; /* Phy still in reset */
1299
1300 switch (cmd) {
1301 case SIOCGMIIPHY:
1302 data->phy_id = PHY_ADDR_MARV;
1303
1304 /* fallthru */
1305 case SIOCGMIIREG: {
1306 u16 val = 0;
1307
1308 spin_lock_bh(&sky2->phy_lock);
1309 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1310 spin_unlock_bh(&sky2->phy_lock);
1311
1312 data->val_out = val;
1313 break;
1314 }
1315
1316 case SIOCSMIIREG:
1317 spin_lock_bh(&sky2->phy_lock);
1318 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1319 data->val_in);
1320 spin_unlock_bh(&sky2->phy_lock);
1321 break;
1322 }
1323 return err;
1324 }
1325
1326 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1327
1328 static void sky2_vlan_mode(struct net_device *dev, u32 features)
1329 {
1330 struct sky2_port *sky2 = netdev_priv(dev);
1331 struct sky2_hw *hw = sky2->hw;
1332 u16 port = sky2->port;
1333
1334 if (features & NETIF_F_HW_VLAN_RX)
1335 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1336 RX_VLAN_STRIP_ON);
1337 else
1338 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1339 RX_VLAN_STRIP_OFF);
1340
1341 if (features & NETIF_F_HW_VLAN_TX) {
1342 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1343 TX_VLAN_TAG_ON);
1344
1345 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1346 } else {
1347 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1348 TX_VLAN_TAG_OFF);
1349
1350 /* Can't do transmit offload of vlan without hw vlan */
1351 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1352 }
1353 }
1354
1355 /* Amount of required worst case padding in rx buffer */
1356 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1357 {
1358 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1359 }
1360
1361 /*
1362 * Allocate an skb for receiving. If the MTU is large enough
1363 * make the skb non-linear with a fragment list of pages.
1364 */
1365 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1366 {
1367 struct sk_buff *skb;
1368 int i;
1369
1370 skb = netdev_alloc_skb(sky2->netdev,
1371 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1372 if (!skb)
1373 goto nomem;
1374
1375 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1376 unsigned char *start;
1377 /*
1378 * Workaround for a bug in FIFO that cause hang
1379 * if the FIFO if the receive buffer is not 64 byte aligned.
1380 * The buffer returned from netdev_alloc_skb is
1381 * aligned except if slab debugging is enabled.
1382 */
1383 start = PTR_ALIGN(skb->data, 8);
1384 skb_reserve(skb, start - skb->data);
1385 } else
1386 skb_reserve(skb, NET_IP_ALIGN);
1387
1388 for (i = 0; i < sky2->rx_nfrags; i++) {
1389 struct page *page = alloc_page(GFP_ATOMIC);
1390
1391 if (!page)
1392 goto free_partial;
1393 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1394 }
1395
1396 return skb;
1397 free_partial:
1398 kfree_skb(skb);
1399 nomem:
1400 return NULL;
1401 }
1402
1403 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1404 {
1405 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1406 }
1407
1408 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1409 {
1410 struct sky2_hw *hw = sky2->hw;
1411 unsigned i;
1412
1413 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1414
1415 /* Fill Rx ring */
1416 for (i = 0; i < sky2->rx_pending; i++) {
1417 struct rx_ring_info *re = sky2->rx_ring + i;
1418
1419 re->skb = sky2_rx_alloc(sky2);
1420 if (!re->skb)
1421 return -ENOMEM;
1422
1423 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1424 dev_kfree_skb(re->skb);
1425 re->skb = NULL;
1426 return -ENOMEM;
1427 }
1428 }
1429 return 0;
1430 }
1431
1432 /*
1433 * Setup receiver buffer pool.
1434 * Normal case this ends up creating one list element for skb
1435 * in the receive ring. Worst case if using large MTU and each
1436 * allocation falls on a different 64 bit region, that results
1437 * in 6 list elements per ring entry.
1438 * One element is used for checksum enable/disable, and one
1439 * extra to avoid wrap.
1440 */
1441 static void sky2_rx_start(struct sky2_port *sky2)
1442 {
1443 struct sky2_hw *hw = sky2->hw;
1444 struct rx_ring_info *re;
1445 unsigned rxq = rxqaddr[sky2->port];
1446 unsigned i, thresh;
1447
1448 sky2->rx_put = sky2->rx_next = 0;
1449 sky2_qset(hw, rxq);
1450
1451 /* On PCI express lowering the watermark gives better performance */
1452 if (pci_is_pcie(hw->pdev))
1453 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1454
1455 /* These chips have no ram buffer?
1456 * MAC Rx RAM Read is controlled by hardware */
1457 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1458 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1459 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1460
1461 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1462
1463 if (!(hw->flags & SKY2_HW_NEW_LE))
1464 rx_set_checksum(sky2);
1465
1466 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1467 rx_set_rss(sky2->netdev, sky2->netdev->features);
1468
1469 /* submit Rx ring */
1470 for (i = 0; i < sky2->rx_pending; i++) {
1471 re = sky2->rx_ring + i;
1472 sky2_rx_submit(sky2, re);
1473 }
1474
1475 /*
1476 * The receiver hangs if it receives frames larger than the
1477 * packet buffer. As a workaround, truncate oversize frames, but
1478 * the register is limited to 9 bits, so if you do frames > 2052
1479 * you better get the MTU right!
1480 */
1481 thresh = sky2_get_rx_threshold(sky2);
1482 if (thresh > 0x1ff)
1483 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1484 else {
1485 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1486 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1487 }
1488
1489 /* Tell chip about available buffers */
1490 sky2_rx_update(sky2, rxq);
1491
1492 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1493 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1494 /*
1495 * Disable flushing of non ASF packets;
1496 * must be done after initializing the BMUs;
1497 * drivers without ASF support should do this too, otherwise
1498 * it may happen that they cannot run on ASF devices;
1499 * remember that the MAC FIFO isn't reset during initialization.
1500 */
1501 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1502 }
1503
1504 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1505 /* Enable RX Home Address & Routing Header checksum fix */
1506 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1507 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1508
1509 /* Enable TX Home Address & Routing Header checksum fix */
1510 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1511 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1512 }
1513 }
1514
1515 static int sky2_alloc_buffers(struct sky2_port *sky2)
1516 {
1517 struct sky2_hw *hw = sky2->hw;
1518
1519 /* must be power of 2 */
1520 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1521 sky2->tx_ring_size *
1522 sizeof(struct sky2_tx_le),
1523 &sky2->tx_le_map);
1524 if (!sky2->tx_le)
1525 goto nomem;
1526
1527 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1528 GFP_KERNEL);
1529 if (!sky2->tx_ring)
1530 goto nomem;
1531
1532 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1533 &sky2->rx_le_map);
1534 if (!sky2->rx_le)
1535 goto nomem;
1536 memset(sky2->rx_le, 0, RX_LE_BYTES);
1537
1538 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1539 GFP_KERNEL);
1540 if (!sky2->rx_ring)
1541 goto nomem;
1542
1543 return sky2_alloc_rx_skbs(sky2);
1544 nomem:
1545 return -ENOMEM;
1546 }
1547
1548 static void sky2_free_buffers(struct sky2_port *sky2)
1549 {
1550 struct sky2_hw *hw = sky2->hw;
1551
1552 sky2_rx_clean(sky2);
1553
1554 if (sky2->rx_le) {
1555 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1556 sky2->rx_le, sky2->rx_le_map);
1557 sky2->rx_le = NULL;
1558 }
1559 if (sky2->tx_le) {
1560 pci_free_consistent(hw->pdev,
1561 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1562 sky2->tx_le, sky2->tx_le_map);
1563 sky2->tx_le = NULL;
1564 }
1565 kfree(sky2->tx_ring);
1566 kfree(sky2->rx_ring);
1567
1568 sky2->tx_ring = NULL;
1569 sky2->rx_ring = NULL;
1570 }
1571
1572 static void sky2_hw_up(struct sky2_port *sky2)
1573 {
1574 struct sky2_hw *hw = sky2->hw;
1575 unsigned port = sky2->port;
1576 u32 ramsize;
1577 int cap;
1578 struct net_device *otherdev = hw->dev[sky2->port^1];
1579
1580 tx_init(sky2);
1581
1582 /*
1583 * On dual port PCI-X card, there is an problem where status
1584 * can be received out of order due to split transactions
1585 */
1586 if (otherdev && netif_running(otherdev) &&
1587 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1588 u16 cmd;
1589
1590 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1591 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1592 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1593 }
1594
1595 sky2_mac_init(hw, port);
1596
1597 /* Register is number of 4K blocks on internal RAM buffer. */
1598 ramsize = sky2_read8(hw, B2_E_0) * 4;
1599 if (ramsize > 0) {
1600 u32 rxspace;
1601
1602 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1603 if (ramsize < 16)
1604 rxspace = ramsize / 2;
1605 else
1606 rxspace = 8 + (2*(ramsize - 16))/3;
1607
1608 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1609 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1610
1611 /* Make sure SyncQ is disabled */
1612 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1613 RB_RST_SET);
1614 }
1615
1616 sky2_qset(hw, txqaddr[port]);
1617
1618 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1619 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1620 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1621
1622 /* Set almost empty threshold */
1623 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1624 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1625 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1626
1627 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1628 sky2->tx_ring_size - 1);
1629
1630 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1631 netdev_update_features(sky2->netdev);
1632
1633 sky2_rx_start(sky2);
1634 }
1635
1636 /* Bring up network interface. */
1637 static int sky2_up(struct net_device *dev)
1638 {
1639 struct sky2_port *sky2 = netdev_priv(dev);
1640 struct sky2_hw *hw = sky2->hw;
1641 unsigned port = sky2->port;
1642 u32 imask;
1643 int err;
1644
1645 netif_carrier_off(dev);
1646
1647 err = sky2_alloc_buffers(sky2);
1648 if (err)
1649 goto err_out;
1650
1651 sky2_hw_up(sky2);
1652
1653 /* Enable interrupts from phy/mac for port */
1654 imask = sky2_read32(hw, B0_IMSK);
1655 imask |= portirq_msk[port];
1656 sky2_write32(hw, B0_IMSK, imask);
1657 sky2_read32(hw, B0_IMSK);
1658
1659 netif_info(sky2, ifup, dev, "enabling interface\n");
1660
1661 return 0;
1662
1663 err_out:
1664 sky2_free_buffers(sky2);
1665 return err;
1666 }
1667
1668 /* Modular subtraction in ring */
1669 static inline int tx_inuse(const struct sky2_port *sky2)
1670 {
1671 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1672 }
1673
1674 /* Number of list elements available for next tx */
1675 static inline int tx_avail(const struct sky2_port *sky2)
1676 {
1677 return sky2->tx_pending - tx_inuse(sky2);
1678 }
1679
1680 /* Estimate of number of transmit list elements required */
1681 static unsigned tx_le_req(const struct sk_buff *skb)
1682 {
1683 unsigned count;
1684
1685 count = (skb_shinfo(skb)->nr_frags + 1)
1686 * (sizeof(dma_addr_t) / sizeof(u32));
1687
1688 if (skb_is_gso(skb))
1689 ++count;
1690 else if (sizeof(dma_addr_t) == sizeof(u32))
1691 ++count; /* possible vlan */
1692
1693 if (skb->ip_summed == CHECKSUM_PARTIAL)
1694 ++count;
1695
1696 return count;
1697 }
1698
1699 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1700 {
1701 if (re->flags & TX_MAP_SINGLE)
1702 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1703 dma_unmap_len(re, maplen),
1704 PCI_DMA_TODEVICE);
1705 else if (re->flags & TX_MAP_PAGE)
1706 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1707 dma_unmap_len(re, maplen),
1708 PCI_DMA_TODEVICE);
1709 re->flags = 0;
1710 }
1711
1712 /*
1713 * Put one packet in ring for transmit.
1714 * A single packet can generate multiple list elements, and
1715 * the number of ring elements will probably be less than the number
1716 * of list elements used.
1717 */
1718 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1719 struct net_device *dev)
1720 {
1721 struct sky2_port *sky2 = netdev_priv(dev);
1722 struct sky2_hw *hw = sky2->hw;
1723 struct sky2_tx_le *le = NULL;
1724 struct tx_ring_info *re;
1725 unsigned i, len;
1726 dma_addr_t mapping;
1727 u32 upper;
1728 u16 slot;
1729 u16 mss;
1730 u8 ctrl;
1731
1732 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1733 return NETDEV_TX_BUSY;
1734
1735 len = skb_headlen(skb);
1736 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1737
1738 if (pci_dma_mapping_error(hw->pdev, mapping))
1739 goto mapping_error;
1740
1741 slot = sky2->tx_prod;
1742 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1743 "tx queued, slot %u, len %d\n", slot, skb->len);
1744
1745 /* Send high bits if needed */
1746 upper = upper_32_bits(mapping);
1747 if (upper != sky2->tx_last_upper) {
1748 le = get_tx_le(sky2, &slot);
1749 le->addr = cpu_to_le32(upper);
1750 sky2->tx_last_upper = upper;
1751 le->opcode = OP_ADDR64 | HW_OWNER;
1752 }
1753
1754 /* Check for TCP Segmentation Offload */
1755 mss = skb_shinfo(skb)->gso_size;
1756 if (mss != 0) {
1757
1758 if (!(hw->flags & SKY2_HW_NEW_LE))
1759 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1760
1761 if (mss != sky2->tx_last_mss) {
1762 le = get_tx_le(sky2, &slot);
1763 le->addr = cpu_to_le32(mss);
1764
1765 if (hw->flags & SKY2_HW_NEW_LE)
1766 le->opcode = OP_MSS | HW_OWNER;
1767 else
1768 le->opcode = OP_LRGLEN | HW_OWNER;
1769 sky2->tx_last_mss = mss;
1770 }
1771 }
1772
1773 ctrl = 0;
1774
1775 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1776 if (vlan_tx_tag_present(skb)) {
1777 if (!le) {
1778 le = get_tx_le(sky2, &slot);
1779 le->addr = 0;
1780 le->opcode = OP_VLAN|HW_OWNER;
1781 } else
1782 le->opcode |= OP_VLAN;
1783 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1784 ctrl |= INS_VLAN;
1785 }
1786
1787 /* Handle TCP checksum offload */
1788 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1789 /* On Yukon EX (some versions) encoding change. */
1790 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1791 ctrl |= CALSUM; /* auto checksum */
1792 else {
1793 const unsigned offset = skb_transport_offset(skb);
1794 u32 tcpsum;
1795
1796 tcpsum = offset << 16; /* sum start */
1797 tcpsum |= offset + skb->csum_offset; /* sum write */
1798
1799 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1800 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1801 ctrl |= UDPTCP;
1802
1803 if (tcpsum != sky2->tx_tcpsum) {
1804 sky2->tx_tcpsum = tcpsum;
1805
1806 le = get_tx_le(sky2, &slot);
1807 le->addr = cpu_to_le32(tcpsum);
1808 le->length = 0; /* initial checksum value */
1809 le->ctrl = 1; /* one packet */
1810 le->opcode = OP_TCPLISW | HW_OWNER;
1811 }
1812 }
1813 }
1814
1815 re = sky2->tx_ring + slot;
1816 re->flags = TX_MAP_SINGLE;
1817 dma_unmap_addr_set(re, mapaddr, mapping);
1818 dma_unmap_len_set(re, maplen, len);
1819
1820 le = get_tx_le(sky2, &slot);
1821 le->addr = cpu_to_le32(lower_32_bits(mapping));
1822 le->length = cpu_to_le16(len);
1823 le->ctrl = ctrl;
1824 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1825
1826
1827 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1828 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1829
1830 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1831 frag->size, PCI_DMA_TODEVICE);
1832
1833 if (pci_dma_mapping_error(hw->pdev, mapping))
1834 goto mapping_unwind;
1835
1836 upper = upper_32_bits(mapping);
1837 if (upper != sky2->tx_last_upper) {
1838 le = get_tx_le(sky2, &slot);
1839 le->addr = cpu_to_le32(upper);
1840 sky2->tx_last_upper = upper;
1841 le->opcode = OP_ADDR64 | HW_OWNER;
1842 }
1843
1844 re = sky2->tx_ring + slot;
1845 re->flags = TX_MAP_PAGE;
1846 dma_unmap_addr_set(re, mapaddr, mapping);
1847 dma_unmap_len_set(re, maplen, frag->size);
1848
1849 le = get_tx_le(sky2, &slot);
1850 le->addr = cpu_to_le32(lower_32_bits(mapping));
1851 le->length = cpu_to_le16(frag->size);
1852 le->ctrl = ctrl;
1853 le->opcode = OP_BUFFER | HW_OWNER;
1854 }
1855
1856 re->skb = skb;
1857 le->ctrl |= EOP;
1858
1859 sky2->tx_prod = slot;
1860
1861 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1862 netif_stop_queue(dev);
1863
1864 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1865
1866 return NETDEV_TX_OK;
1867
1868 mapping_unwind:
1869 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1870 re = sky2->tx_ring + i;
1871
1872 sky2_tx_unmap(hw->pdev, re);
1873 }
1874
1875 mapping_error:
1876 if (net_ratelimit())
1877 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1878 dev_kfree_skb(skb);
1879 return NETDEV_TX_OK;
1880 }
1881
1882 /*
1883 * Free ring elements from starting at tx_cons until "done"
1884 *
1885 * NB:
1886 * 1. The hardware will tell us about partial completion of multi-part
1887 * buffers so make sure not to free skb to early.
1888 * 2. This may run in parallel start_xmit because the it only
1889 * looks at the tail of the queue of FIFO (tx_cons), not
1890 * the head (tx_prod)
1891 */
1892 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1893 {
1894 struct net_device *dev = sky2->netdev;
1895 unsigned idx;
1896
1897 BUG_ON(done >= sky2->tx_ring_size);
1898
1899 for (idx = sky2->tx_cons; idx != done;
1900 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1901 struct tx_ring_info *re = sky2->tx_ring + idx;
1902 struct sk_buff *skb = re->skb;
1903
1904 sky2_tx_unmap(sky2->hw->pdev, re);
1905
1906 if (skb) {
1907 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1908 "tx done %u\n", idx);
1909
1910 u64_stats_update_begin(&sky2->tx_stats.syncp);
1911 ++sky2->tx_stats.packets;
1912 sky2->tx_stats.bytes += skb->len;
1913 u64_stats_update_end(&sky2->tx_stats.syncp);
1914
1915 re->skb = NULL;
1916 dev_kfree_skb_any(skb);
1917
1918 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1919 }
1920 }
1921
1922 sky2->tx_cons = idx;
1923 smp_mb();
1924 }
1925
1926 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1927 {
1928 /* Disable Force Sync bit and Enable Alloc bit */
1929 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1930 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1931
1932 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1933 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1934 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1935
1936 /* Reset the PCI FIFO of the async Tx queue */
1937 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1938 BMU_RST_SET | BMU_FIFO_RST);
1939
1940 /* Reset the Tx prefetch units */
1941 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1942 PREF_UNIT_RST_SET);
1943
1944 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1945 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1946 }
1947
1948 static void sky2_hw_down(struct sky2_port *sky2)
1949 {
1950 struct sky2_hw *hw = sky2->hw;
1951 unsigned port = sky2->port;
1952 u16 ctrl;
1953
1954 /* Force flow control off */
1955 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1956
1957 /* Stop transmitter */
1958 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1959 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1960
1961 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1962 RB_RST_SET | RB_DIS_OP_MD);
1963
1964 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1965 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1966 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1967
1968 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1969
1970 /* Workaround shared GMAC reset */
1971 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1972 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1973 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1974
1975 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1976
1977 /* Force any delayed status interrrupt and NAPI */
1978 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1979 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1980 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1981 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1982
1983 sky2_rx_stop(sky2);
1984
1985 spin_lock_bh(&sky2->phy_lock);
1986 sky2_phy_power_down(hw, port);
1987 spin_unlock_bh(&sky2->phy_lock);
1988
1989 sky2_tx_reset(hw, port);
1990
1991 /* Free any pending frames stuck in HW queue */
1992 sky2_tx_complete(sky2, sky2->tx_prod);
1993 }
1994
1995 /* Network shutdown */
1996 static int sky2_down(struct net_device *dev)
1997 {
1998 struct sky2_port *sky2 = netdev_priv(dev);
1999 struct sky2_hw *hw = sky2->hw;
2000
2001 /* Never really got started! */
2002 if (!sky2->tx_le)
2003 return 0;
2004
2005 netif_info(sky2, ifdown, dev, "disabling interface\n");
2006
2007 /* Disable port IRQ */
2008 sky2_write32(hw, B0_IMSK,
2009 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2010 sky2_read32(hw, B0_IMSK);
2011
2012 synchronize_irq(hw->pdev->irq);
2013 napi_synchronize(&hw->napi);
2014
2015 sky2_hw_down(sky2);
2016
2017 sky2_free_buffers(sky2);
2018
2019 return 0;
2020 }
2021
2022 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2023 {
2024 if (hw->flags & SKY2_HW_FIBRE_PHY)
2025 return SPEED_1000;
2026
2027 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2028 if (aux & PHY_M_PS_SPEED_100)
2029 return SPEED_100;
2030 else
2031 return SPEED_10;
2032 }
2033
2034 switch (aux & PHY_M_PS_SPEED_MSK) {
2035 case PHY_M_PS_SPEED_1000:
2036 return SPEED_1000;
2037 case PHY_M_PS_SPEED_100:
2038 return SPEED_100;
2039 default:
2040 return SPEED_10;
2041 }
2042 }
2043
2044 static void sky2_link_up(struct sky2_port *sky2)
2045 {
2046 struct sky2_hw *hw = sky2->hw;
2047 unsigned port = sky2->port;
2048 static const char *fc_name[] = {
2049 [FC_NONE] = "none",
2050 [FC_TX] = "tx",
2051 [FC_RX] = "rx",
2052 [FC_BOTH] = "both",
2053 };
2054
2055 sky2_enable_rx_tx(sky2);
2056
2057 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2058
2059 netif_carrier_on(sky2->netdev);
2060
2061 mod_timer(&hw->watchdog_timer, jiffies + 1);
2062
2063 /* Turn on link LED */
2064 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2065 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2066
2067 netif_info(sky2, link, sky2->netdev,
2068 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2069 sky2->speed,
2070 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2071 fc_name[sky2->flow_status]);
2072 }
2073
2074 static void sky2_link_down(struct sky2_port *sky2)
2075 {
2076 struct sky2_hw *hw = sky2->hw;
2077 unsigned port = sky2->port;
2078 u16 reg;
2079
2080 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2081
2082 reg = gma_read16(hw, port, GM_GP_CTRL);
2083 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2084 gma_write16(hw, port, GM_GP_CTRL, reg);
2085
2086 netif_carrier_off(sky2->netdev);
2087
2088 /* Turn off link LED */
2089 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2090
2091 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2092
2093 sky2_phy_init(hw, port);
2094 }
2095
2096 static enum flow_control sky2_flow(int rx, int tx)
2097 {
2098 if (rx)
2099 return tx ? FC_BOTH : FC_RX;
2100 else
2101 return tx ? FC_TX : FC_NONE;
2102 }
2103
2104 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2105 {
2106 struct sky2_hw *hw = sky2->hw;
2107 unsigned port = sky2->port;
2108 u16 advert, lpa;
2109
2110 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2111 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2112 if (lpa & PHY_M_AN_RF) {
2113 netdev_err(sky2->netdev, "remote fault\n");
2114 return -1;
2115 }
2116
2117 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2118 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2119 return -1;
2120 }
2121
2122 sky2->speed = sky2_phy_speed(hw, aux);
2123 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2124
2125 /* Since the pause result bits seem to in different positions on
2126 * different chips. look at registers.
2127 */
2128 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2129 /* Shift for bits in fiber PHY */
2130 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2131 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2132
2133 if (advert & ADVERTISE_1000XPAUSE)
2134 advert |= ADVERTISE_PAUSE_CAP;
2135 if (advert & ADVERTISE_1000XPSE_ASYM)
2136 advert |= ADVERTISE_PAUSE_ASYM;
2137 if (lpa & LPA_1000XPAUSE)
2138 lpa |= LPA_PAUSE_CAP;
2139 if (lpa & LPA_1000XPAUSE_ASYM)
2140 lpa |= LPA_PAUSE_ASYM;
2141 }
2142
2143 sky2->flow_status = FC_NONE;
2144 if (advert & ADVERTISE_PAUSE_CAP) {
2145 if (lpa & LPA_PAUSE_CAP)
2146 sky2->flow_status = FC_BOTH;
2147 else if (advert & ADVERTISE_PAUSE_ASYM)
2148 sky2->flow_status = FC_RX;
2149 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2150 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2151 sky2->flow_status = FC_TX;
2152 }
2153
2154 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2155 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2156 sky2->flow_status = FC_NONE;
2157
2158 if (sky2->flow_status & FC_TX)
2159 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2160 else
2161 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2162
2163 return 0;
2164 }
2165
2166 /* Interrupt from PHY */
2167 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2168 {
2169 struct net_device *dev = hw->dev[port];
2170 struct sky2_port *sky2 = netdev_priv(dev);
2171 u16 istatus, phystat;
2172
2173 if (!netif_running(dev))
2174 return;
2175
2176 spin_lock(&sky2->phy_lock);
2177 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2178 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2179
2180 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2181 istatus, phystat);
2182
2183 if (istatus & PHY_M_IS_AN_COMPL) {
2184 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2185 !netif_carrier_ok(dev))
2186 sky2_link_up(sky2);
2187 goto out;
2188 }
2189
2190 if (istatus & PHY_M_IS_LSP_CHANGE)
2191 sky2->speed = sky2_phy_speed(hw, phystat);
2192
2193 if (istatus & PHY_M_IS_DUP_CHANGE)
2194 sky2->duplex =
2195 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2196
2197 if (istatus & PHY_M_IS_LST_CHANGE) {
2198 if (phystat & PHY_M_PS_LINK_UP)
2199 sky2_link_up(sky2);
2200 else
2201 sky2_link_down(sky2);
2202 }
2203 out:
2204 spin_unlock(&sky2->phy_lock);
2205 }
2206
2207 /* Special quick link interrupt (Yukon-2 Optima only) */
2208 static void sky2_qlink_intr(struct sky2_hw *hw)
2209 {
2210 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2211 u32 imask;
2212 u16 phy;
2213
2214 /* disable irq */
2215 imask = sky2_read32(hw, B0_IMSK);
2216 imask &= ~Y2_IS_PHY_QLNK;
2217 sky2_write32(hw, B0_IMSK, imask);
2218
2219 /* reset PHY Link Detect */
2220 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2221 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2222 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2223 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2224
2225 sky2_link_up(sky2);
2226 }
2227
2228 /* Transmit timeout is only called if we are running, carrier is up
2229 * and tx queue is full (stopped).
2230 */
2231 static void sky2_tx_timeout(struct net_device *dev)
2232 {
2233 struct sky2_port *sky2 = netdev_priv(dev);
2234 struct sky2_hw *hw = sky2->hw;
2235
2236 netif_err(sky2, timer, dev, "tx timeout\n");
2237
2238 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2239 sky2->tx_cons, sky2->tx_prod,
2240 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2241 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2242
2243 /* can't restart safely under softirq */
2244 schedule_work(&hw->restart_work);
2245 }
2246
2247 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2248 {
2249 struct sky2_port *sky2 = netdev_priv(dev);
2250 struct sky2_hw *hw = sky2->hw;
2251 unsigned port = sky2->port;
2252 int err;
2253 u16 ctl, mode;
2254 u32 imask;
2255
2256 /* MTU size outside the spec */
2257 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2258 return -EINVAL;
2259
2260 /* MTU > 1500 on yukon FE and FE+ not allowed */
2261 if (new_mtu > ETH_DATA_LEN &&
2262 (hw->chip_id == CHIP_ID_YUKON_FE ||
2263 hw->chip_id == CHIP_ID_YUKON_FE_P))
2264 return -EINVAL;
2265
2266 if (!netif_running(dev)) {
2267 dev->mtu = new_mtu;
2268 netdev_update_features(dev);
2269 return 0;
2270 }
2271
2272 imask = sky2_read32(hw, B0_IMSK);
2273 sky2_write32(hw, B0_IMSK, 0);
2274
2275 dev->trans_start = jiffies; /* prevent tx timeout */
2276 napi_disable(&hw->napi);
2277 netif_tx_disable(dev);
2278
2279 synchronize_irq(hw->pdev->irq);
2280
2281 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2282 sky2_set_tx_stfwd(hw, port);
2283
2284 ctl = gma_read16(hw, port, GM_GP_CTRL);
2285 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2286 sky2_rx_stop(sky2);
2287 sky2_rx_clean(sky2);
2288
2289 dev->mtu = new_mtu;
2290 netdev_update_features(dev);
2291
2292 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2293 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2294
2295 if (dev->mtu > ETH_DATA_LEN)
2296 mode |= GM_SMOD_JUMBO_ENA;
2297
2298 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2299
2300 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2301
2302 err = sky2_alloc_rx_skbs(sky2);
2303 if (!err)
2304 sky2_rx_start(sky2);
2305 else
2306 sky2_rx_clean(sky2);
2307 sky2_write32(hw, B0_IMSK, imask);
2308
2309 sky2_read32(hw, B0_Y2_SP_LISR);
2310 napi_enable(&hw->napi);
2311
2312 if (err)
2313 dev_close(dev);
2314 else {
2315 gma_write16(hw, port, GM_GP_CTRL, ctl);
2316
2317 netif_wake_queue(dev);
2318 }
2319
2320 return err;
2321 }
2322
2323 /* For small just reuse existing skb for next receive */
2324 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2325 const struct rx_ring_info *re,
2326 unsigned length)
2327 {
2328 struct sk_buff *skb;
2329
2330 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2331 if (likely(skb)) {
2332 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2333 length, PCI_DMA_FROMDEVICE);
2334 skb_copy_from_linear_data(re->skb, skb->data, length);
2335 skb->ip_summed = re->skb->ip_summed;
2336 skb->csum = re->skb->csum;
2337 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2338 length, PCI_DMA_FROMDEVICE);
2339 re->skb->ip_summed = CHECKSUM_NONE;
2340 skb_put(skb, length);
2341 }
2342 return skb;
2343 }
2344
2345 /* Adjust length of skb with fragments to match received data */
2346 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2347 unsigned int length)
2348 {
2349 int i, num_frags;
2350 unsigned int size;
2351
2352 /* put header into skb */
2353 size = min(length, hdr_space);
2354 skb->tail += size;
2355 skb->len += size;
2356 length -= size;
2357
2358 num_frags = skb_shinfo(skb)->nr_frags;
2359 for (i = 0; i < num_frags; i++) {
2360 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2361
2362 if (length == 0) {
2363 /* don't need this page */
2364 __free_page(frag->page);
2365 --skb_shinfo(skb)->nr_frags;
2366 } else {
2367 size = min(length, (unsigned) PAGE_SIZE);
2368
2369 frag->size = size;
2370 skb->data_len += size;
2371 skb->truesize += size;
2372 skb->len += size;
2373 length -= size;
2374 }
2375 }
2376 }
2377
2378 /* Normal packet - take skb from ring element and put in a new one */
2379 static struct sk_buff *receive_new(struct sky2_port *sky2,
2380 struct rx_ring_info *re,
2381 unsigned int length)
2382 {
2383 struct sk_buff *skb;
2384 struct rx_ring_info nre;
2385 unsigned hdr_space = sky2->rx_data_size;
2386
2387 nre.skb = sky2_rx_alloc(sky2);
2388 if (unlikely(!nre.skb))
2389 goto nobuf;
2390
2391 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2392 goto nomap;
2393
2394 skb = re->skb;
2395 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2396 prefetch(skb->data);
2397 *re = nre;
2398
2399 if (skb_shinfo(skb)->nr_frags)
2400 skb_put_frags(skb, hdr_space, length);
2401 else
2402 skb_put(skb, length);
2403 return skb;
2404
2405 nomap:
2406 dev_kfree_skb(nre.skb);
2407 nobuf:
2408 return NULL;
2409 }
2410
2411 /*
2412 * Receive one packet.
2413 * For larger packets, get new buffer.
2414 */
2415 static struct sk_buff *sky2_receive(struct net_device *dev,
2416 u16 length, u32 status)
2417 {
2418 struct sky2_port *sky2 = netdev_priv(dev);
2419 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2420 struct sk_buff *skb = NULL;
2421 u16 count = (status & GMR_FS_LEN) >> 16;
2422
2423 if (status & GMR_FS_VLAN)
2424 count -= VLAN_HLEN; /* Account for vlan tag */
2425
2426 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2427 "rx slot %u status 0x%x len %d\n",
2428 sky2->rx_next, status, length);
2429
2430 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2431 prefetch(sky2->rx_ring + sky2->rx_next);
2432
2433 /* This chip has hardware problems that generates bogus status.
2434 * So do only marginal checking and expect higher level protocols
2435 * to handle crap frames.
2436 */
2437 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2438 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2439 length != count)
2440 goto okay;
2441
2442 if (status & GMR_FS_ANY_ERR)
2443 goto error;
2444
2445 if (!(status & GMR_FS_RX_OK))
2446 goto resubmit;
2447
2448 /* if length reported by DMA does not match PHY, packet was truncated */
2449 if (length != count)
2450 goto error;
2451
2452 okay:
2453 if (length < copybreak)
2454 skb = receive_copy(sky2, re, length);
2455 else
2456 skb = receive_new(sky2, re, length);
2457
2458 dev->stats.rx_dropped += (skb == NULL);
2459
2460 resubmit:
2461 sky2_rx_submit(sky2, re);
2462
2463 return skb;
2464
2465 error:
2466 ++dev->stats.rx_errors;
2467
2468 if (net_ratelimit())
2469 netif_info(sky2, rx_err, dev,
2470 "rx error, status 0x%x length %d\n", status, length);
2471
2472 goto resubmit;
2473 }
2474
2475 /* Transmit complete */
2476 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2477 {
2478 struct sky2_port *sky2 = netdev_priv(dev);
2479
2480 if (netif_running(dev)) {
2481 sky2_tx_complete(sky2, last);
2482
2483 /* Wake unless it's detached, and called e.g. from sky2_down() */
2484 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2485 netif_wake_queue(dev);
2486 }
2487 }
2488
2489 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2490 u32 status, struct sk_buff *skb)
2491 {
2492 if (status & GMR_FS_VLAN)
2493 __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
2494
2495 if (skb->ip_summed == CHECKSUM_NONE)
2496 netif_receive_skb(skb);
2497 else
2498 napi_gro_receive(&sky2->hw->napi, skb);
2499 }
2500
2501 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2502 unsigned packets, unsigned bytes)
2503 {
2504 struct net_device *dev = hw->dev[port];
2505 struct sky2_port *sky2 = netdev_priv(dev);
2506
2507 if (packets == 0)
2508 return;
2509
2510 u64_stats_update_begin(&sky2->rx_stats.syncp);
2511 sky2->rx_stats.packets += packets;
2512 sky2->rx_stats.bytes += bytes;
2513 u64_stats_update_end(&sky2->rx_stats.syncp);
2514
2515 dev->last_rx = jiffies;
2516 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2517 }
2518
2519 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2520 {
2521 /* If this happens then driver assuming wrong format for chip type */
2522 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2523
2524 /* Both checksum counters are programmed to start at
2525 * the same offset, so unless there is a problem they
2526 * should match. This failure is an early indication that
2527 * hardware receive checksumming won't work.
2528 */
2529 if (likely((u16)(status >> 16) == (u16)status)) {
2530 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2531 skb->ip_summed = CHECKSUM_COMPLETE;
2532 skb->csum = le16_to_cpu(status);
2533 } else {
2534 dev_notice(&sky2->hw->pdev->dev,
2535 "%s: receive checksum problem (status = %#x)\n",
2536 sky2->netdev->name, status);
2537
2538 /* Disable checksum offload
2539 * It will be reenabled on next ndo_set_features, but if it's
2540 * really broken, will get disabled again
2541 */
2542 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2543 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2544 BMU_DIS_RX_CHKSUM);
2545 }
2546 }
2547
2548 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2549 {
2550 struct sk_buff *skb;
2551
2552 skb = sky2->rx_ring[sky2->rx_next].skb;
2553 skb->rxhash = le32_to_cpu(status);
2554 }
2555
2556 /* Process status response ring */
2557 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2558 {
2559 int work_done = 0;
2560 unsigned int total_bytes[2] = { 0 };
2561 unsigned int total_packets[2] = { 0 };
2562
2563 rmb();
2564 do {
2565 struct sky2_port *sky2;
2566 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2567 unsigned port;
2568 struct net_device *dev;
2569 struct sk_buff *skb;
2570 u32 status;
2571 u16 length;
2572 u8 opcode = le->opcode;
2573
2574 if (!(opcode & HW_OWNER))
2575 break;
2576
2577 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2578
2579 port = le->css & CSS_LINK_BIT;
2580 dev = hw->dev[port];
2581 sky2 = netdev_priv(dev);
2582 length = le16_to_cpu(le->length);
2583 status = le32_to_cpu(le->status);
2584
2585 le->opcode = 0;
2586 switch (opcode & ~HW_OWNER) {
2587 case OP_RXSTAT:
2588 total_packets[port]++;
2589 total_bytes[port] += length;
2590
2591 skb = sky2_receive(dev, length, status);
2592 if (!skb)
2593 break;
2594
2595 /* This chip reports checksum status differently */
2596 if (hw->flags & SKY2_HW_NEW_LE) {
2597 if ((dev->features & NETIF_F_RXCSUM) &&
2598 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2599 (le->css & CSS_TCPUDPCSOK))
2600 skb->ip_summed = CHECKSUM_UNNECESSARY;
2601 else
2602 skb->ip_summed = CHECKSUM_NONE;
2603 }
2604
2605 skb->protocol = eth_type_trans(skb, dev);
2606
2607 sky2_skb_rx(sky2, status, skb);
2608
2609 /* Stop after net poll weight */
2610 if (++work_done >= to_do)
2611 goto exit_loop;
2612 break;
2613
2614 case OP_RXVLAN:
2615 sky2->rx_tag = length;
2616 break;
2617
2618 case OP_RXCHKSVLAN:
2619 sky2->rx_tag = length;
2620 /* fall through */
2621 case OP_RXCHKS:
2622 if (likely(dev->features & NETIF_F_RXCSUM))
2623 sky2_rx_checksum(sky2, status);
2624 break;
2625
2626 case OP_RSS_HASH:
2627 sky2_rx_hash(sky2, status);
2628 break;
2629
2630 case OP_TXINDEXLE:
2631 /* TX index reports status for both ports */
2632 sky2_tx_done(hw->dev[0], status & 0xfff);
2633 if (hw->dev[1])
2634 sky2_tx_done(hw->dev[1],
2635 ((status >> 24) & 0xff)
2636 | (u16)(length & 0xf) << 8);
2637 break;
2638
2639 default:
2640 if (net_ratelimit())
2641 pr_warning("unknown status opcode 0x%x\n", opcode);
2642 }
2643 } while (hw->st_idx != idx);
2644
2645 /* Fully processed status ring so clear irq */
2646 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2647
2648 exit_loop:
2649 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2650 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2651
2652 return work_done;
2653 }
2654
2655 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2656 {
2657 struct net_device *dev = hw->dev[port];
2658
2659 if (net_ratelimit())
2660 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2661
2662 if (status & Y2_IS_PAR_RD1) {
2663 if (net_ratelimit())
2664 netdev_err(dev, "ram data read parity error\n");
2665 /* Clear IRQ */
2666 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2667 }
2668
2669 if (status & Y2_IS_PAR_WR1) {
2670 if (net_ratelimit())
2671 netdev_err(dev, "ram data write parity error\n");
2672
2673 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2674 }
2675
2676 if (status & Y2_IS_PAR_MAC1) {
2677 if (net_ratelimit())
2678 netdev_err(dev, "MAC parity error\n");
2679 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2680 }
2681
2682 if (status & Y2_IS_PAR_RX1) {
2683 if (net_ratelimit())
2684 netdev_err(dev, "RX parity error\n");
2685 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2686 }
2687
2688 if (status & Y2_IS_TCP_TXA1) {
2689 if (net_ratelimit())
2690 netdev_err(dev, "TCP segmentation error\n");
2691 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2692 }
2693 }
2694
2695 static void sky2_hw_intr(struct sky2_hw *hw)
2696 {
2697 struct pci_dev *pdev = hw->pdev;
2698 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2699 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2700
2701 status &= hwmsk;
2702
2703 if (status & Y2_IS_TIST_OV)
2704 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2705
2706 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2707 u16 pci_err;
2708
2709 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2710 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2711 if (net_ratelimit())
2712 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2713 pci_err);
2714
2715 sky2_pci_write16(hw, PCI_STATUS,
2716 pci_err | PCI_STATUS_ERROR_BITS);
2717 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2718 }
2719
2720 if (status & Y2_IS_PCI_EXP) {
2721 /* PCI-Express uncorrectable Error occurred */
2722 u32 err;
2723
2724 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2725 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2726 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2727 0xfffffffful);
2728 if (net_ratelimit())
2729 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2730
2731 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2732 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2733 }
2734
2735 if (status & Y2_HWE_L1_MASK)
2736 sky2_hw_error(hw, 0, status);
2737 status >>= 8;
2738 if (status & Y2_HWE_L1_MASK)
2739 sky2_hw_error(hw, 1, status);
2740 }
2741
2742 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2743 {
2744 struct net_device *dev = hw->dev[port];
2745 struct sky2_port *sky2 = netdev_priv(dev);
2746 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2747
2748 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2749
2750 if (status & GM_IS_RX_CO_OV)
2751 gma_read16(hw, port, GM_RX_IRQ_SRC);
2752
2753 if (status & GM_IS_TX_CO_OV)
2754 gma_read16(hw, port, GM_TX_IRQ_SRC);
2755
2756 if (status & GM_IS_RX_FF_OR) {
2757 ++dev->stats.rx_fifo_errors;
2758 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2759 }
2760
2761 if (status & GM_IS_TX_FF_UR) {
2762 ++dev->stats.tx_fifo_errors;
2763 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2764 }
2765 }
2766
2767 /* This should never happen it is a bug. */
2768 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2769 {
2770 struct net_device *dev = hw->dev[port];
2771 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2772
2773 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2774 dev->name, (unsigned) q, (unsigned) idx,
2775 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2776
2777 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2778 }
2779
2780 static int sky2_rx_hung(struct net_device *dev)
2781 {
2782 struct sky2_port *sky2 = netdev_priv(dev);
2783 struct sky2_hw *hw = sky2->hw;
2784 unsigned port = sky2->port;
2785 unsigned rxq = rxqaddr[port];
2786 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2787 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2788 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2789 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2790
2791 /* If idle and MAC or PCI is stuck */
2792 if (sky2->check.last == dev->last_rx &&
2793 ((mac_rp == sky2->check.mac_rp &&
2794 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2795 /* Check if the PCI RX hang */
2796 (fifo_rp == sky2->check.fifo_rp &&
2797 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2798 netdev_printk(KERN_DEBUG, dev,
2799 "hung mac %d:%d fifo %d (%d:%d)\n",
2800 mac_lev, mac_rp, fifo_lev,
2801 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2802 return 1;
2803 } else {
2804 sky2->check.last = dev->last_rx;
2805 sky2->check.mac_rp = mac_rp;
2806 sky2->check.mac_lev = mac_lev;
2807 sky2->check.fifo_rp = fifo_rp;
2808 sky2->check.fifo_lev = fifo_lev;
2809 return 0;
2810 }
2811 }
2812
2813 static void sky2_watchdog(unsigned long arg)
2814 {
2815 struct sky2_hw *hw = (struct sky2_hw *) arg;
2816
2817 /* Check for lost IRQ once a second */
2818 if (sky2_read32(hw, B0_ISRC)) {
2819 napi_schedule(&hw->napi);
2820 } else {
2821 int i, active = 0;
2822
2823 for (i = 0; i < hw->ports; i++) {
2824 struct net_device *dev = hw->dev[i];
2825 if (!netif_running(dev))
2826 continue;
2827 ++active;
2828
2829 /* For chips with Rx FIFO, check if stuck */
2830 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2831 sky2_rx_hung(dev)) {
2832 netdev_info(dev, "receiver hang detected\n");
2833 schedule_work(&hw->restart_work);
2834 return;
2835 }
2836 }
2837
2838 if (active == 0)
2839 return;
2840 }
2841
2842 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2843 }
2844
2845 /* Hardware/software error handling */
2846 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2847 {
2848 if (net_ratelimit())
2849 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2850
2851 if (status & Y2_IS_HW_ERR)
2852 sky2_hw_intr(hw);
2853
2854 if (status & Y2_IS_IRQ_MAC1)
2855 sky2_mac_intr(hw, 0);
2856
2857 if (status & Y2_IS_IRQ_MAC2)
2858 sky2_mac_intr(hw, 1);
2859
2860 if (status & Y2_IS_CHK_RX1)
2861 sky2_le_error(hw, 0, Q_R1);
2862
2863 if (status & Y2_IS_CHK_RX2)
2864 sky2_le_error(hw, 1, Q_R2);
2865
2866 if (status & Y2_IS_CHK_TXA1)
2867 sky2_le_error(hw, 0, Q_XA1);
2868
2869 if (status & Y2_IS_CHK_TXA2)
2870 sky2_le_error(hw, 1, Q_XA2);
2871 }
2872
2873 static int sky2_poll(struct napi_struct *napi, int work_limit)
2874 {
2875 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2876 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2877 int work_done = 0;
2878 u16 idx;
2879
2880 if (unlikely(status & Y2_IS_ERROR))
2881 sky2_err_intr(hw, status);
2882
2883 if (status & Y2_IS_IRQ_PHY1)
2884 sky2_phy_intr(hw, 0);
2885
2886 if (status & Y2_IS_IRQ_PHY2)
2887 sky2_phy_intr(hw, 1);
2888
2889 if (status & Y2_IS_PHY_QLNK)
2890 sky2_qlink_intr(hw);
2891
2892 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2893 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2894
2895 if (work_done >= work_limit)
2896 goto done;
2897 }
2898
2899 napi_complete(napi);
2900 sky2_read32(hw, B0_Y2_SP_LISR);
2901 done:
2902
2903 return work_done;
2904 }
2905
2906 static irqreturn_t sky2_intr(int irq, void *dev_id)
2907 {
2908 struct sky2_hw *hw = dev_id;
2909 u32 status;
2910
2911 /* Reading this mask interrupts as side effect */
2912 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2913 if (status == 0 || status == ~0)
2914 return IRQ_NONE;
2915
2916 prefetch(&hw->st_le[hw->st_idx]);
2917
2918 napi_schedule(&hw->napi);
2919
2920 return IRQ_HANDLED;
2921 }
2922
2923 #ifdef CONFIG_NET_POLL_CONTROLLER
2924 static void sky2_netpoll(struct net_device *dev)
2925 {
2926 struct sky2_port *sky2 = netdev_priv(dev);
2927
2928 napi_schedule(&sky2->hw->napi);
2929 }
2930 #endif
2931
2932 /* Chip internal frequency for clock calculations */
2933 static u32 sky2_mhz(const struct sky2_hw *hw)
2934 {
2935 switch (hw->chip_id) {
2936 case CHIP_ID_YUKON_EC:
2937 case CHIP_ID_YUKON_EC_U:
2938 case CHIP_ID_YUKON_EX:
2939 case CHIP_ID_YUKON_SUPR:
2940 case CHIP_ID_YUKON_UL_2:
2941 case CHIP_ID_YUKON_OPT:
2942 return 125;
2943
2944 case CHIP_ID_YUKON_FE:
2945 return 100;
2946
2947 case CHIP_ID_YUKON_FE_P:
2948 return 50;
2949
2950 case CHIP_ID_YUKON_XL:
2951 return 156;
2952
2953 default:
2954 BUG();
2955 }
2956 }
2957
2958 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2959 {
2960 return sky2_mhz(hw) * us;
2961 }
2962
2963 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2964 {
2965 return clk / sky2_mhz(hw);
2966 }
2967
2968
2969 static int __devinit sky2_init(struct sky2_hw *hw)
2970 {
2971 u8 t8;
2972
2973 /* Enable all clocks and check for bad PCI access */
2974 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2975
2976 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2977
2978 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2979 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2980
2981 switch (hw->chip_id) {
2982 case CHIP_ID_YUKON_XL:
2983 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2984 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
2985 hw->flags |= SKY2_HW_RSS_BROKEN;
2986 break;
2987
2988 case CHIP_ID_YUKON_EC_U:
2989 hw->flags = SKY2_HW_GIGABIT
2990 | SKY2_HW_NEWER_PHY
2991 | SKY2_HW_ADV_POWER_CTL;
2992 break;
2993
2994 case CHIP_ID_YUKON_EX:
2995 hw->flags = SKY2_HW_GIGABIT
2996 | SKY2_HW_NEWER_PHY
2997 | SKY2_HW_NEW_LE
2998 | SKY2_HW_ADV_POWER_CTL;
2999
3000 /* New transmit checksum */
3001 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3002 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3003 break;
3004
3005 case CHIP_ID_YUKON_EC:
3006 /* This rev is really old, and requires untested workarounds */
3007 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3008 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3009 return -EOPNOTSUPP;
3010 }
3011 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3012 break;
3013
3014 case CHIP_ID_YUKON_FE:
3015 hw->flags = SKY2_HW_RSS_BROKEN;
3016 break;
3017
3018 case CHIP_ID_YUKON_FE_P:
3019 hw->flags = SKY2_HW_NEWER_PHY
3020 | SKY2_HW_NEW_LE
3021 | SKY2_HW_AUTO_TX_SUM
3022 | SKY2_HW_ADV_POWER_CTL;
3023
3024 /* The workaround for status conflicts VLAN tag detection. */
3025 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3026 hw->flags |= SKY2_HW_VLAN_BROKEN;
3027 break;
3028
3029 case CHIP_ID_YUKON_SUPR:
3030 hw->flags = SKY2_HW_GIGABIT
3031 | SKY2_HW_NEWER_PHY
3032 | SKY2_HW_NEW_LE
3033 | SKY2_HW_AUTO_TX_SUM
3034 | SKY2_HW_ADV_POWER_CTL;
3035 break;
3036
3037 case CHIP_ID_YUKON_UL_2:
3038 hw->flags = SKY2_HW_GIGABIT
3039 | SKY2_HW_ADV_POWER_CTL;
3040 break;
3041
3042 case CHIP_ID_YUKON_OPT:
3043 hw->flags = SKY2_HW_GIGABIT
3044 | SKY2_HW_NEW_LE
3045 | SKY2_HW_ADV_POWER_CTL;
3046 break;
3047
3048 default:
3049 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3050 hw->chip_id);
3051 return -EOPNOTSUPP;
3052 }
3053
3054 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3055 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3056 hw->flags |= SKY2_HW_FIBRE_PHY;
3057
3058 hw->ports = 1;
3059 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3060 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3061 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3062 ++hw->ports;
3063 }
3064
3065 if (sky2_read8(hw, B2_E_0))
3066 hw->flags |= SKY2_HW_RAM_BUFFER;
3067
3068 return 0;
3069 }
3070
3071 static void sky2_reset(struct sky2_hw *hw)
3072 {
3073 struct pci_dev *pdev = hw->pdev;
3074 u16 status;
3075 int i;
3076 u32 hwe_mask = Y2_HWE_ALL_MASK;
3077
3078 /* disable ASF */
3079 if (hw->chip_id == CHIP_ID_YUKON_EX
3080 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3081 sky2_write32(hw, CPU_WDOG, 0);
3082 status = sky2_read16(hw, HCU_CCSR);
3083 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3084 HCU_CCSR_UC_STATE_MSK);
3085 /*
3086 * CPU clock divider shouldn't be used because
3087 * - ASF firmware may malfunction
3088 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3089 */
3090 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3091 sky2_write16(hw, HCU_CCSR, status);
3092 sky2_write32(hw, CPU_WDOG, 0);
3093 } else
3094 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3095 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3096
3097 /* do a SW reset */
3098 sky2_write8(hw, B0_CTST, CS_RST_SET);
3099 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3100
3101 /* allow writes to PCI config */
3102 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3103
3104 /* clear PCI errors, if any */
3105 status = sky2_pci_read16(hw, PCI_STATUS);
3106 status |= PCI_STATUS_ERROR_BITS;
3107 sky2_pci_write16(hw, PCI_STATUS, status);
3108
3109 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3110
3111 if (pci_is_pcie(pdev)) {
3112 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3113 0xfffffffful);
3114
3115 /* If error bit is stuck on ignore it */
3116 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3117 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3118 else
3119 hwe_mask |= Y2_IS_PCI_EXP;
3120 }
3121
3122 sky2_power_on(hw);
3123 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3124
3125 for (i = 0; i < hw->ports; i++) {
3126 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3127 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3128
3129 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3130 hw->chip_id == CHIP_ID_YUKON_SUPR)
3131 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3132 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3133 | GMC_BYP_RETR_ON);
3134
3135 }
3136
3137 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3138 /* enable MACSec clock gating */
3139 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3140 }
3141
3142 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3143 u16 reg;
3144 u32 msk;
3145
3146 if (hw->chip_rev == 0) {
3147 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3148 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3149
3150 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3151 reg = 10;
3152 } else {
3153 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3154 reg = 3;
3155 }
3156
3157 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3158
3159 /* reset PHY Link Detect */
3160 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3161 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3162 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3163 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3164
3165
3166 /* enable PHY Quick Link */
3167 msk = sky2_read32(hw, B0_IMSK);
3168 msk |= Y2_IS_PHY_QLNK;
3169 sky2_write32(hw, B0_IMSK, msk);
3170
3171 /* check if PSMv2 was running before */
3172 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3173 if (reg & PCI_EXP_LNKCTL_ASPMC)
3174 /* restore the PCIe Link Control register */
3175 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3176 reg);
3177
3178 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3179
3180 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3181 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3182 }
3183
3184 /* Clear I2C IRQ noise */
3185 sky2_write32(hw, B2_I2C_IRQ, 1);
3186
3187 /* turn off hardware timer (unused) */
3188 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3189 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3190
3191 /* Turn off descriptor polling */
3192 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3193
3194 /* Turn off receive timestamp */
3195 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3196 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3197
3198 /* enable the Tx Arbiters */
3199 for (i = 0; i < hw->ports; i++)
3200 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3201
3202 /* Initialize ram interface */
3203 for (i = 0; i < hw->ports; i++) {
3204 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3205
3206 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3207 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3208 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3209 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3210 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3211 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3212 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3213 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3214 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3215 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3216 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3217 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3218 }
3219
3220 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3221
3222 for (i = 0; i < hw->ports; i++)
3223 sky2_gmac_reset(hw, i);
3224
3225 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3226 hw->st_idx = 0;
3227
3228 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3229 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3230
3231 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3232 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3233
3234 /* Set the list last index */
3235 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3236
3237 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3238 sky2_write8(hw, STAT_FIFO_WM, 16);
3239
3240 /* set Status-FIFO ISR watermark */
3241 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3242 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3243 else
3244 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3245
3246 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3247 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3248 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3249
3250 /* enable status unit */
3251 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3252
3253 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3254 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3255 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3256 }
3257
3258 /* Take device down (offline).
3259 * Equivalent to doing dev_stop() but this does not
3260 * inform upper layers of the transition.
3261 */
3262 static void sky2_detach(struct net_device *dev)
3263 {
3264 if (netif_running(dev)) {
3265 netif_tx_lock(dev);
3266 netif_device_detach(dev); /* stop txq */
3267 netif_tx_unlock(dev);
3268 sky2_down(dev);
3269 }
3270 }
3271
3272 /* Bring device back after doing sky2_detach */
3273 static int sky2_reattach(struct net_device *dev)
3274 {
3275 int err = 0;
3276
3277 if (netif_running(dev)) {
3278 err = sky2_up(dev);
3279 if (err) {
3280 netdev_info(dev, "could not restart %d\n", err);
3281 dev_close(dev);
3282 } else {
3283 netif_device_attach(dev);
3284 sky2_set_multicast(dev);
3285 }
3286 }
3287
3288 return err;
3289 }
3290
3291 static void sky2_all_down(struct sky2_hw *hw)
3292 {
3293 int i;
3294
3295 sky2_read32(hw, B0_IMSK);
3296 sky2_write32(hw, B0_IMSK, 0);
3297 synchronize_irq(hw->pdev->irq);
3298 napi_disable(&hw->napi);
3299
3300 for (i = 0; i < hw->ports; i++) {
3301 struct net_device *dev = hw->dev[i];
3302 struct sky2_port *sky2 = netdev_priv(dev);
3303
3304 if (!netif_running(dev))
3305 continue;
3306
3307 netif_carrier_off(dev);
3308 netif_tx_disable(dev);
3309 sky2_hw_down(sky2);
3310 }
3311 }
3312
3313 static void sky2_all_up(struct sky2_hw *hw)
3314 {
3315 u32 imask = Y2_IS_BASE;
3316 int i;
3317
3318 for (i = 0; i < hw->ports; i++) {
3319 struct net_device *dev = hw->dev[i];
3320 struct sky2_port *sky2 = netdev_priv(dev);
3321
3322 if (!netif_running(dev))
3323 continue;
3324
3325 sky2_hw_up(sky2);
3326 sky2_set_multicast(dev);
3327 imask |= portirq_msk[i];
3328 netif_wake_queue(dev);
3329 }
3330
3331 sky2_write32(hw, B0_IMSK, imask);
3332 sky2_read32(hw, B0_IMSK);
3333
3334 sky2_read32(hw, B0_Y2_SP_LISR);
3335 napi_enable(&hw->napi);
3336 }
3337
3338 static void sky2_restart(struct work_struct *work)
3339 {
3340 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3341
3342 rtnl_lock();
3343
3344 sky2_all_down(hw);
3345 sky2_reset(hw);
3346 sky2_all_up(hw);
3347
3348 rtnl_unlock();
3349 }
3350
3351 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3352 {
3353 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3354 }
3355
3356 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3357 {
3358 const struct sky2_port *sky2 = netdev_priv(dev);
3359
3360 wol->supported = sky2_wol_supported(sky2->hw);
3361 wol->wolopts = sky2->wol;
3362 }
3363
3364 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3365 {
3366 struct sky2_port *sky2 = netdev_priv(dev);
3367 struct sky2_hw *hw = sky2->hw;
3368 bool enable_wakeup = false;
3369 int i;
3370
3371 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3372 !device_can_wakeup(&hw->pdev->dev))
3373 return -EOPNOTSUPP;
3374
3375 sky2->wol = wol->wolopts;
3376
3377 for (i = 0; i < hw->ports; i++) {
3378 struct net_device *dev = hw->dev[i];
3379 struct sky2_port *sky2 = netdev_priv(dev);
3380
3381 if (sky2->wol)
3382 enable_wakeup = true;
3383 }
3384 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3385
3386 return 0;
3387 }
3388
3389 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3390 {
3391 if (sky2_is_copper(hw)) {
3392 u32 modes = SUPPORTED_10baseT_Half
3393 | SUPPORTED_10baseT_Full
3394 | SUPPORTED_100baseT_Half
3395 | SUPPORTED_100baseT_Full;
3396
3397 if (hw->flags & SKY2_HW_GIGABIT)
3398 modes |= SUPPORTED_1000baseT_Half
3399 | SUPPORTED_1000baseT_Full;
3400 return modes;
3401 } else
3402 return SUPPORTED_1000baseT_Half
3403 | SUPPORTED_1000baseT_Full;
3404 }
3405
3406 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3407 {
3408 struct sky2_port *sky2 = netdev_priv(dev);
3409 struct sky2_hw *hw = sky2->hw;
3410
3411 ecmd->transceiver = XCVR_INTERNAL;
3412 ecmd->supported = sky2_supported_modes(hw);
3413 ecmd->phy_address = PHY_ADDR_MARV;
3414 if (sky2_is_copper(hw)) {
3415 ecmd->port = PORT_TP;
3416 ethtool_cmd_speed_set(ecmd, sky2->speed);
3417 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3418 } else {
3419 ethtool_cmd_speed_set(ecmd, SPEED_1000);
3420 ecmd->port = PORT_FIBRE;
3421 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3422 }
3423
3424 ecmd->advertising = sky2->advertising;
3425 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3426 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3427 ecmd->duplex = sky2->duplex;
3428 return 0;
3429 }
3430
3431 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3432 {
3433 struct sky2_port *sky2 = netdev_priv(dev);
3434 const struct sky2_hw *hw = sky2->hw;
3435 u32 supported = sky2_supported_modes(hw);
3436
3437 if (ecmd->autoneg == AUTONEG_ENABLE) {
3438 if (ecmd->advertising & ~supported)
3439 return -EINVAL;
3440
3441 if (sky2_is_copper(hw))
3442 sky2->advertising = ecmd->advertising |
3443 ADVERTISED_TP |
3444 ADVERTISED_Autoneg;
3445 else
3446 sky2->advertising = ecmd->advertising |
3447 ADVERTISED_FIBRE |
3448 ADVERTISED_Autoneg;
3449
3450 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3451 sky2->duplex = -1;
3452 sky2->speed = -1;
3453 } else {
3454 u32 setting;
3455 u32 speed = ethtool_cmd_speed(ecmd);
3456
3457 switch (speed) {
3458 case SPEED_1000:
3459 if (ecmd->duplex == DUPLEX_FULL)
3460 setting = SUPPORTED_1000baseT_Full;
3461 else if (ecmd->duplex == DUPLEX_HALF)
3462 setting = SUPPORTED_1000baseT_Half;
3463 else
3464 return -EINVAL;
3465 break;
3466 case SPEED_100:
3467 if (ecmd->duplex == DUPLEX_FULL)
3468 setting = SUPPORTED_100baseT_Full;
3469 else if (ecmd->duplex == DUPLEX_HALF)
3470 setting = SUPPORTED_100baseT_Half;
3471 else
3472 return -EINVAL;
3473 break;
3474
3475 case SPEED_10:
3476 if (ecmd->duplex == DUPLEX_FULL)
3477 setting = SUPPORTED_10baseT_Full;
3478 else if (ecmd->duplex == DUPLEX_HALF)
3479 setting = SUPPORTED_10baseT_Half;
3480 else
3481 return -EINVAL;
3482 break;
3483 default:
3484 return -EINVAL;
3485 }
3486
3487 if ((setting & supported) == 0)
3488 return -EINVAL;
3489
3490 sky2->speed = speed;
3491 sky2->duplex = ecmd->duplex;
3492 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3493 }
3494
3495 if (netif_running(dev)) {
3496 sky2_phy_reinit(sky2);
3497 sky2_set_multicast(dev);
3498 }
3499
3500 return 0;
3501 }
3502
3503 static void sky2_get_drvinfo(struct net_device *dev,
3504 struct ethtool_drvinfo *info)
3505 {
3506 struct sky2_port *sky2 = netdev_priv(dev);
3507
3508 strcpy(info->driver, DRV_NAME);
3509 strcpy(info->version, DRV_VERSION);
3510 strcpy(info->fw_version, "N/A");
3511 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3512 }
3513
3514 static const struct sky2_stat {
3515 char name[ETH_GSTRING_LEN];
3516 u16 offset;
3517 } sky2_stats[] = {
3518 { "tx_bytes", GM_TXO_OK_HI },
3519 { "rx_bytes", GM_RXO_OK_HI },
3520 { "tx_broadcast", GM_TXF_BC_OK },
3521 { "rx_broadcast", GM_RXF_BC_OK },
3522 { "tx_multicast", GM_TXF_MC_OK },
3523 { "rx_multicast", GM_RXF_MC_OK },
3524 { "tx_unicast", GM_TXF_UC_OK },
3525 { "rx_unicast", GM_RXF_UC_OK },
3526 { "tx_mac_pause", GM_TXF_MPAUSE },
3527 { "rx_mac_pause", GM_RXF_MPAUSE },
3528 { "collisions", GM_TXF_COL },
3529 { "late_collision",GM_TXF_LAT_COL },
3530 { "aborted", GM_TXF_ABO_COL },
3531 { "single_collisions", GM_TXF_SNG_COL },
3532 { "multi_collisions", GM_TXF_MUL_COL },
3533
3534 { "rx_short", GM_RXF_SHT },
3535 { "rx_runt", GM_RXE_FRAG },
3536 { "rx_64_byte_packets", GM_RXF_64B },
3537 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3538 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3539 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3540 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3541 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3542 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3543 { "rx_too_long", GM_RXF_LNG_ERR },
3544 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3545 { "rx_jabber", GM_RXF_JAB_PKT },
3546 { "rx_fcs_error", GM_RXF_FCS_ERR },
3547
3548 { "tx_64_byte_packets", GM_TXF_64B },
3549 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3550 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3551 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3552 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3553 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3554 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3555 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3556 };
3557
3558 static u32 sky2_get_msglevel(struct net_device *netdev)
3559 {
3560 struct sky2_port *sky2 = netdev_priv(netdev);
3561 return sky2->msg_enable;
3562 }
3563
3564 static int sky2_nway_reset(struct net_device *dev)
3565 {
3566 struct sky2_port *sky2 = netdev_priv(dev);
3567
3568 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3569 return -EINVAL;
3570
3571 sky2_phy_reinit(sky2);
3572 sky2_set_multicast(dev);
3573
3574 return 0;
3575 }
3576
3577 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3578 {
3579 struct sky2_hw *hw = sky2->hw;
3580 unsigned port = sky2->port;
3581 int i;
3582
3583 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3584 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3585
3586 for (i = 2; i < count; i++)
3587 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3588 }
3589
3590 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3591 {
3592 struct sky2_port *sky2 = netdev_priv(netdev);
3593 sky2->msg_enable = value;
3594 }
3595
3596 static int sky2_get_sset_count(struct net_device *dev, int sset)
3597 {
3598 switch (sset) {
3599 case ETH_SS_STATS:
3600 return ARRAY_SIZE(sky2_stats);
3601 default:
3602 return -EOPNOTSUPP;
3603 }
3604 }
3605
3606 static void sky2_get_ethtool_stats(struct net_device *dev,
3607 struct ethtool_stats *stats, u64 * data)
3608 {
3609 struct sky2_port *sky2 = netdev_priv(dev);
3610
3611 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3612 }
3613
3614 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3615 {
3616 int i;
3617
3618 switch (stringset) {
3619 case ETH_SS_STATS:
3620 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3621 memcpy(data + i * ETH_GSTRING_LEN,
3622 sky2_stats[i].name, ETH_GSTRING_LEN);
3623 break;
3624 }
3625 }
3626
3627 static int sky2_set_mac_address(struct net_device *dev, void *p)
3628 {
3629 struct sky2_port *sky2 = netdev_priv(dev);
3630 struct sky2_hw *hw = sky2->hw;
3631 unsigned port = sky2->port;
3632 const struct sockaddr *addr = p;
3633
3634 if (!is_valid_ether_addr(addr->sa_data))
3635 return -EADDRNOTAVAIL;
3636
3637 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3638 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3639 dev->dev_addr, ETH_ALEN);
3640 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3641 dev->dev_addr, ETH_ALEN);
3642
3643 /* virtual address for data */
3644 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3645
3646 /* physical address: used for pause frames */
3647 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3648
3649 return 0;
3650 }
3651
3652 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3653 {
3654 u32 bit;
3655
3656 bit = ether_crc(ETH_ALEN, addr) & 63;
3657 filter[bit >> 3] |= 1 << (bit & 7);
3658 }
3659
3660 static void sky2_set_multicast(struct net_device *dev)
3661 {
3662 struct sky2_port *sky2 = netdev_priv(dev);
3663 struct sky2_hw *hw = sky2->hw;
3664 unsigned port = sky2->port;
3665 struct netdev_hw_addr *ha;
3666 u16 reg;
3667 u8 filter[8];
3668 int rx_pause;
3669 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3670
3671 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3672 memset(filter, 0, sizeof(filter));
3673
3674 reg = gma_read16(hw, port, GM_RX_CTRL);
3675 reg |= GM_RXCR_UCF_ENA;
3676
3677 if (dev->flags & IFF_PROMISC) /* promiscuous */
3678 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3679 else if (dev->flags & IFF_ALLMULTI)
3680 memset(filter, 0xff, sizeof(filter));
3681 else if (netdev_mc_empty(dev) && !rx_pause)
3682 reg &= ~GM_RXCR_MCF_ENA;
3683 else {
3684 reg |= GM_RXCR_MCF_ENA;
3685
3686 if (rx_pause)
3687 sky2_add_filter(filter, pause_mc_addr);
3688
3689 netdev_for_each_mc_addr(ha, dev)
3690 sky2_add_filter(filter, ha->addr);
3691 }
3692
3693 gma_write16(hw, port, GM_MC_ADDR_H1,
3694 (u16) filter[0] | ((u16) filter[1] << 8));
3695 gma_write16(hw, port, GM_MC_ADDR_H2,
3696 (u16) filter[2] | ((u16) filter[3] << 8));
3697 gma_write16(hw, port, GM_MC_ADDR_H3,
3698 (u16) filter[4] | ((u16) filter[5] << 8));
3699 gma_write16(hw, port, GM_MC_ADDR_H4,
3700 (u16) filter[6] | ((u16) filter[7] << 8));
3701
3702 gma_write16(hw, port, GM_RX_CTRL, reg);
3703 }
3704
3705 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3706 struct rtnl_link_stats64 *stats)
3707 {
3708 struct sky2_port *sky2 = netdev_priv(dev);
3709 struct sky2_hw *hw = sky2->hw;
3710 unsigned port = sky2->port;
3711 unsigned int start;
3712 u64 _bytes, _packets;
3713
3714 do {
3715 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3716 _bytes = sky2->rx_stats.bytes;
3717 _packets = sky2->rx_stats.packets;
3718 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3719
3720 stats->rx_packets = _packets;
3721 stats->rx_bytes = _bytes;
3722
3723 do {
3724 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3725 _bytes = sky2->tx_stats.bytes;
3726 _packets = sky2->tx_stats.packets;
3727 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3728
3729 stats->tx_packets = _packets;
3730 stats->tx_bytes = _bytes;
3731
3732 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3733 + get_stats32(hw, port, GM_RXF_BC_OK);
3734
3735 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3736
3737 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3738 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3739 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3740 + get_stats32(hw, port, GM_RXE_FRAG);
3741 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3742
3743 stats->rx_dropped = dev->stats.rx_dropped;
3744 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3745 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3746
3747 return stats;
3748 }
3749
3750 /* Can have one global because blinking is controlled by
3751 * ethtool and that is always under RTNL mutex
3752 */
3753 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3754 {
3755 struct sky2_hw *hw = sky2->hw;
3756 unsigned port = sky2->port;
3757
3758 spin_lock_bh(&sky2->phy_lock);
3759 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3760 hw->chip_id == CHIP_ID_YUKON_EX ||
3761 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3762 u16 pg;
3763 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3764 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3765
3766 switch (mode) {
3767 case MO_LED_OFF:
3768 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3769 PHY_M_LEDC_LOS_CTRL(8) |
3770 PHY_M_LEDC_INIT_CTRL(8) |
3771 PHY_M_LEDC_STA1_CTRL(8) |
3772 PHY_M_LEDC_STA0_CTRL(8));
3773 break;
3774 case MO_LED_ON:
3775 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3776 PHY_M_LEDC_LOS_CTRL(9) |
3777 PHY_M_LEDC_INIT_CTRL(9) |
3778 PHY_M_LEDC_STA1_CTRL(9) |
3779 PHY_M_LEDC_STA0_CTRL(9));
3780 break;
3781 case MO_LED_BLINK:
3782 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3783 PHY_M_LEDC_LOS_CTRL(0xa) |
3784 PHY_M_LEDC_INIT_CTRL(0xa) |
3785 PHY_M_LEDC_STA1_CTRL(0xa) |
3786 PHY_M_LEDC_STA0_CTRL(0xa));
3787 break;
3788 case MO_LED_NORM:
3789 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3790 PHY_M_LEDC_LOS_CTRL(1) |
3791 PHY_M_LEDC_INIT_CTRL(8) |
3792 PHY_M_LEDC_STA1_CTRL(7) |
3793 PHY_M_LEDC_STA0_CTRL(7));
3794 }
3795
3796 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3797 } else
3798 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3799 PHY_M_LED_MO_DUP(mode) |
3800 PHY_M_LED_MO_10(mode) |
3801 PHY_M_LED_MO_100(mode) |
3802 PHY_M_LED_MO_1000(mode) |
3803 PHY_M_LED_MO_RX(mode) |
3804 PHY_M_LED_MO_TX(mode));
3805
3806 spin_unlock_bh(&sky2->phy_lock);
3807 }
3808
3809 /* blink LED's for finding board */
3810 static int sky2_set_phys_id(struct net_device *dev,
3811 enum ethtool_phys_id_state state)
3812 {
3813 struct sky2_port *sky2 = netdev_priv(dev);
3814
3815 switch (state) {
3816 case ETHTOOL_ID_ACTIVE:
3817 return 1; /* cycle on/off once per second */
3818 case ETHTOOL_ID_INACTIVE:
3819 sky2_led(sky2, MO_LED_NORM);
3820 break;
3821 case ETHTOOL_ID_ON:
3822 sky2_led(sky2, MO_LED_ON);
3823 break;
3824 case ETHTOOL_ID_OFF:
3825 sky2_led(sky2, MO_LED_OFF);
3826 break;
3827 }
3828
3829 return 0;
3830 }
3831
3832 static void sky2_get_pauseparam(struct net_device *dev,
3833 struct ethtool_pauseparam *ecmd)
3834 {
3835 struct sky2_port *sky2 = netdev_priv(dev);
3836
3837 switch (sky2->flow_mode) {
3838 case FC_NONE:
3839 ecmd->tx_pause = ecmd->rx_pause = 0;
3840 break;
3841 case FC_TX:
3842 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3843 break;
3844 case FC_RX:
3845 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3846 break;
3847 case FC_BOTH:
3848 ecmd->tx_pause = ecmd->rx_pause = 1;
3849 }
3850
3851 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3852 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3853 }
3854
3855 static int sky2_set_pauseparam(struct net_device *dev,
3856 struct ethtool_pauseparam *ecmd)
3857 {
3858 struct sky2_port *sky2 = netdev_priv(dev);
3859
3860 if (ecmd->autoneg == AUTONEG_ENABLE)
3861 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3862 else
3863 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3864
3865 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3866
3867 if (netif_running(dev))
3868 sky2_phy_reinit(sky2);
3869
3870 return 0;
3871 }
3872
3873 static int sky2_get_coalesce(struct net_device *dev,
3874 struct ethtool_coalesce *ecmd)
3875 {
3876 struct sky2_port *sky2 = netdev_priv(dev);
3877 struct sky2_hw *hw = sky2->hw;
3878
3879 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3880 ecmd->tx_coalesce_usecs = 0;
3881 else {
3882 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3883 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3884 }
3885 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3886
3887 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3888 ecmd->rx_coalesce_usecs = 0;
3889 else {
3890 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3891 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3892 }
3893 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3894
3895 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3896 ecmd->rx_coalesce_usecs_irq = 0;
3897 else {
3898 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3899 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3900 }
3901
3902 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3903
3904 return 0;
3905 }
3906
3907 /* Note: this affect both ports */
3908 static int sky2_set_coalesce(struct net_device *dev,
3909 struct ethtool_coalesce *ecmd)
3910 {
3911 struct sky2_port *sky2 = netdev_priv(dev);
3912 struct sky2_hw *hw = sky2->hw;
3913 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3914
3915 if (ecmd->tx_coalesce_usecs > tmax ||
3916 ecmd->rx_coalesce_usecs > tmax ||
3917 ecmd->rx_coalesce_usecs_irq > tmax)
3918 return -EINVAL;
3919
3920 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3921 return -EINVAL;
3922 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3923 return -EINVAL;
3924 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
3925 return -EINVAL;
3926
3927 if (ecmd->tx_coalesce_usecs == 0)
3928 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3929 else {
3930 sky2_write32(hw, STAT_TX_TIMER_INI,
3931 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3932 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3933 }
3934 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3935
3936 if (ecmd->rx_coalesce_usecs == 0)
3937 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3938 else {
3939 sky2_write32(hw, STAT_LEV_TIMER_INI,
3940 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3941 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3942 }
3943 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3944
3945 if (ecmd->rx_coalesce_usecs_irq == 0)
3946 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3947 else {
3948 sky2_write32(hw, STAT_ISR_TIMER_INI,
3949 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3950 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3951 }
3952 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3953 return 0;
3954 }
3955
3956 static void sky2_get_ringparam(struct net_device *dev,
3957 struct ethtool_ringparam *ering)
3958 {
3959 struct sky2_port *sky2 = netdev_priv(dev);
3960
3961 ering->rx_max_pending = RX_MAX_PENDING;
3962 ering->rx_mini_max_pending = 0;
3963 ering->rx_jumbo_max_pending = 0;
3964 ering->tx_max_pending = TX_MAX_PENDING;
3965
3966 ering->rx_pending = sky2->rx_pending;
3967 ering->rx_mini_pending = 0;
3968 ering->rx_jumbo_pending = 0;
3969 ering->tx_pending = sky2->tx_pending;
3970 }
3971
3972 static int sky2_set_ringparam(struct net_device *dev,
3973 struct ethtool_ringparam *ering)
3974 {
3975 struct sky2_port *sky2 = netdev_priv(dev);
3976
3977 if (ering->rx_pending > RX_MAX_PENDING ||
3978 ering->rx_pending < 8 ||
3979 ering->tx_pending < TX_MIN_PENDING ||
3980 ering->tx_pending > TX_MAX_PENDING)
3981 return -EINVAL;
3982
3983 sky2_detach(dev);
3984
3985 sky2->rx_pending = ering->rx_pending;
3986 sky2->tx_pending = ering->tx_pending;
3987 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3988
3989 return sky2_reattach(dev);
3990 }
3991
3992 static int sky2_get_regs_len(struct net_device *dev)
3993 {
3994 return 0x4000;
3995 }
3996
3997 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3998 {
3999 /* This complicated switch statement is to make sure and
4000 * only access regions that are unreserved.
4001 * Some blocks are only valid on dual port cards.
4002 */
4003 switch (b) {
4004 /* second port */
4005 case 5: /* Tx Arbiter 2 */
4006 case 9: /* RX2 */
4007 case 14 ... 15: /* TX2 */
4008 case 17: case 19: /* Ram Buffer 2 */
4009 case 22 ... 23: /* Tx Ram Buffer 2 */
4010 case 25: /* Rx MAC Fifo 1 */
4011 case 27: /* Tx MAC Fifo 2 */
4012 case 31: /* GPHY 2 */
4013 case 40 ... 47: /* Pattern Ram 2 */
4014 case 52: case 54: /* TCP Segmentation 2 */
4015 case 112 ... 116: /* GMAC 2 */
4016 return hw->ports > 1;
4017
4018 case 0: /* Control */
4019 case 2: /* Mac address */
4020 case 4: /* Tx Arbiter 1 */
4021 case 7: /* PCI express reg */
4022 case 8: /* RX1 */
4023 case 12 ... 13: /* TX1 */
4024 case 16: case 18:/* Rx Ram Buffer 1 */
4025 case 20 ... 21: /* Tx Ram Buffer 1 */
4026 case 24: /* Rx MAC Fifo 1 */
4027 case 26: /* Tx MAC Fifo 1 */
4028 case 28 ... 29: /* Descriptor and status unit */
4029 case 30: /* GPHY 1*/
4030 case 32 ... 39: /* Pattern Ram 1 */
4031 case 48: case 50: /* TCP Segmentation 1 */
4032 case 56 ... 60: /* PCI space */
4033 case 80 ... 84: /* GMAC 1 */
4034 return 1;
4035
4036 default:
4037 return 0;
4038 }
4039 }
4040
4041 /*
4042 * Returns copy of control register region
4043 * Note: ethtool_get_regs always provides full size (16k) buffer
4044 */
4045 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4046 void *p)
4047 {
4048 const struct sky2_port *sky2 = netdev_priv(dev);
4049 const void __iomem *io = sky2->hw->regs;
4050 unsigned int b;
4051
4052 regs->version = 1;
4053
4054 for (b = 0; b < 128; b++) {
4055 /* skip poisonous diagnostic ram region in block 3 */
4056 if (b == 3)
4057 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4058 else if (sky2_reg_access_ok(sky2->hw, b))
4059 memcpy_fromio(p, io, 128);
4060 else
4061 memset(p, 0, 128);
4062
4063 p += 128;
4064 io += 128;
4065 }
4066 }
4067
4068 static int sky2_get_eeprom_len(struct net_device *dev)
4069 {
4070 struct sky2_port *sky2 = netdev_priv(dev);
4071 struct sky2_hw *hw = sky2->hw;
4072 u16 reg2;
4073
4074 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4075 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4076 }
4077
4078 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4079 {
4080 unsigned long start = jiffies;
4081
4082 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4083 /* Can take up to 10.6 ms for write */
4084 if (time_after(jiffies, start + HZ/4)) {
4085 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4086 return -ETIMEDOUT;
4087 }
4088 mdelay(1);
4089 }
4090
4091 return 0;
4092 }
4093
4094 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4095 u16 offset, size_t length)
4096 {
4097 int rc = 0;
4098
4099 while (length > 0) {
4100 u32 val;
4101
4102 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4103 rc = sky2_vpd_wait(hw, cap, 0);
4104 if (rc)
4105 break;
4106
4107 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4108
4109 memcpy(data, &val, min(sizeof(val), length));
4110 offset += sizeof(u32);
4111 data += sizeof(u32);
4112 length -= sizeof(u32);
4113 }
4114
4115 return rc;
4116 }
4117
4118 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4119 u16 offset, unsigned int length)
4120 {
4121 unsigned int i;
4122 int rc = 0;
4123
4124 for (i = 0; i < length; i += sizeof(u32)) {
4125 u32 val = *(u32 *)(data + i);
4126
4127 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4128 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4129
4130 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4131 if (rc)
4132 break;
4133 }
4134 return rc;
4135 }
4136
4137 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4138 u8 *data)
4139 {
4140 struct sky2_port *sky2 = netdev_priv(dev);
4141 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4142
4143 if (!cap)
4144 return -EINVAL;
4145
4146 eeprom->magic = SKY2_EEPROM_MAGIC;
4147
4148 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4149 }
4150
4151 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4152 u8 *data)
4153 {
4154 struct sky2_port *sky2 = netdev_priv(dev);
4155 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4156
4157 if (!cap)
4158 return -EINVAL;
4159
4160 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4161 return -EINVAL;
4162
4163 /* Partial writes not supported */
4164 if ((eeprom->offset & 3) || (eeprom->len & 3))
4165 return -EINVAL;
4166
4167 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4168 }
4169
4170 static u32 sky2_fix_features(struct net_device *dev, u32 features)
4171 {
4172 const struct sky2_port *sky2 = netdev_priv(dev);
4173 const struct sky2_hw *hw = sky2->hw;
4174
4175 /* In order to do Jumbo packets on these chips, need to turn off the
4176 * transmit store/forward. Therefore checksum offload won't work.
4177 */
4178 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
4179 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
4180
4181 return features;
4182 }
4183
4184 static int sky2_set_features(struct net_device *dev, u32 features)
4185 {
4186 struct sky2_port *sky2 = netdev_priv(dev);
4187 u32 changed = dev->features ^ features;
4188
4189 if (changed & NETIF_F_RXCSUM) {
4190 u32 on = features & NETIF_F_RXCSUM;
4191 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4192 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4193 }
4194
4195 if (changed & NETIF_F_RXHASH)
4196 rx_set_rss(dev, features);
4197
4198 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4199 sky2_vlan_mode(dev, features);
4200
4201 return 0;
4202 }
4203
4204 static const struct ethtool_ops sky2_ethtool_ops = {
4205 .get_settings = sky2_get_settings,
4206 .set_settings = sky2_set_settings,
4207 .get_drvinfo = sky2_get_drvinfo,
4208 .get_wol = sky2_get_wol,
4209 .set_wol = sky2_set_wol,
4210 .get_msglevel = sky2_get_msglevel,
4211 .set_msglevel = sky2_set_msglevel,
4212 .nway_reset = sky2_nway_reset,
4213 .get_regs_len = sky2_get_regs_len,
4214 .get_regs = sky2_get_regs,
4215 .get_link = ethtool_op_get_link,
4216 .get_eeprom_len = sky2_get_eeprom_len,
4217 .get_eeprom = sky2_get_eeprom,
4218 .set_eeprom = sky2_set_eeprom,
4219 .get_strings = sky2_get_strings,
4220 .get_coalesce = sky2_get_coalesce,
4221 .set_coalesce = sky2_set_coalesce,
4222 .get_ringparam = sky2_get_ringparam,
4223 .set_ringparam = sky2_set_ringparam,
4224 .get_pauseparam = sky2_get_pauseparam,
4225 .set_pauseparam = sky2_set_pauseparam,
4226 .set_phys_id = sky2_set_phys_id,
4227 .get_sset_count = sky2_get_sset_count,
4228 .get_ethtool_stats = sky2_get_ethtool_stats,
4229 };
4230
4231 #ifdef CONFIG_SKY2_DEBUG
4232
4233 static struct dentry *sky2_debug;
4234
4235
4236 /*
4237 * Read and parse the first part of Vital Product Data
4238 */
4239 #define VPD_SIZE 128
4240 #define VPD_MAGIC 0x82
4241
4242 static const struct vpd_tag {
4243 char tag[2];
4244 char *label;
4245 } vpd_tags[] = {
4246 { "PN", "Part Number" },
4247 { "EC", "Engineering Level" },
4248 { "MN", "Manufacturer" },
4249 { "SN", "Serial Number" },
4250 { "YA", "Asset Tag" },
4251 { "VL", "First Error Log Message" },
4252 { "VF", "Second Error Log Message" },
4253 { "VB", "Boot Agent ROM Configuration" },
4254 { "VE", "EFI UNDI Configuration" },
4255 };
4256
4257 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4258 {
4259 size_t vpd_size;
4260 loff_t offs;
4261 u8 len;
4262 unsigned char *buf;
4263 u16 reg2;
4264
4265 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4266 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4267
4268 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4269 buf = kmalloc(vpd_size, GFP_KERNEL);
4270 if (!buf) {
4271 seq_puts(seq, "no memory!\n");
4272 return;
4273 }
4274
4275 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4276 seq_puts(seq, "VPD read failed\n");
4277 goto out;
4278 }
4279
4280 if (buf[0] != VPD_MAGIC) {
4281 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4282 goto out;
4283 }
4284 len = buf[1];
4285 if (len == 0 || len > vpd_size - 4) {
4286 seq_printf(seq, "Invalid id length: %d\n", len);
4287 goto out;
4288 }
4289
4290 seq_printf(seq, "%.*s\n", len, buf + 3);
4291 offs = len + 3;
4292
4293 while (offs < vpd_size - 4) {
4294 int i;
4295
4296 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4297 break;
4298 len = buf[offs + 2];
4299 if (offs + len + 3 >= vpd_size)
4300 break;
4301
4302 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4303 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4304 seq_printf(seq, " %s: %.*s\n",
4305 vpd_tags[i].label, len, buf + offs + 3);
4306 break;
4307 }
4308 }
4309 offs += len + 3;
4310 }
4311 out:
4312 kfree(buf);
4313 }
4314
4315 static int sky2_debug_show(struct seq_file *seq, void *v)
4316 {
4317 struct net_device *dev = seq->private;
4318 const struct sky2_port *sky2 = netdev_priv(dev);
4319 struct sky2_hw *hw = sky2->hw;
4320 unsigned port = sky2->port;
4321 unsigned idx, last;
4322 int sop;
4323
4324 sky2_show_vpd(seq, hw);
4325
4326 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4327 sky2_read32(hw, B0_ISRC),
4328 sky2_read32(hw, B0_IMSK),
4329 sky2_read32(hw, B0_Y2_SP_ICR));
4330
4331 if (!netif_running(dev)) {
4332 seq_printf(seq, "network not running\n");
4333 return 0;
4334 }
4335
4336 napi_disable(&hw->napi);
4337 last = sky2_read16(hw, STAT_PUT_IDX);
4338
4339 seq_printf(seq, "Status ring %u\n", hw->st_size);
4340 if (hw->st_idx == last)
4341 seq_puts(seq, "Status ring (empty)\n");
4342 else {
4343 seq_puts(seq, "Status ring\n");
4344 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4345 idx = RING_NEXT(idx, hw->st_size)) {
4346 const struct sky2_status_le *le = hw->st_le + idx;
4347 seq_printf(seq, "[%d] %#x %d %#x\n",
4348 idx, le->opcode, le->length, le->status);
4349 }
4350 seq_puts(seq, "\n");
4351 }
4352
4353 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4354 sky2->tx_cons, sky2->tx_prod,
4355 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4356 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4357
4358 /* Dump contents of tx ring */
4359 sop = 1;
4360 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4361 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4362 const struct sky2_tx_le *le = sky2->tx_le + idx;
4363 u32 a = le32_to_cpu(le->addr);
4364
4365 if (sop)
4366 seq_printf(seq, "%u:", idx);
4367 sop = 0;
4368
4369 switch (le->opcode & ~HW_OWNER) {
4370 case OP_ADDR64:
4371 seq_printf(seq, " %#x:", a);
4372 break;
4373 case OP_LRGLEN:
4374 seq_printf(seq, " mtu=%d", a);
4375 break;
4376 case OP_VLAN:
4377 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4378 break;
4379 case OP_TCPLISW:
4380 seq_printf(seq, " csum=%#x", a);
4381 break;
4382 case OP_LARGESEND:
4383 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4384 break;
4385 case OP_PACKET:
4386 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4387 break;
4388 case OP_BUFFER:
4389 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4390 break;
4391 default:
4392 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4393 a, le16_to_cpu(le->length));
4394 }
4395
4396 if (le->ctrl & EOP) {
4397 seq_putc(seq, '\n');
4398 sop = 1;
4399 }
4400 }
4401
4402 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4403 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4404 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4405 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4406
4407 sky2_read32(hw, B0_Y2_SP_LISR);
4408 napi_enable(&hw->napi);
4409 return 0;
4410 }
4411
4412 static int sky2_debug_open(struct inode *inode, struct file *file)
4413 {
4414 return single_open(file, sky2_debug_show, inode->i_private);
4415 }
4416
4417 static const struct file_operations sky2_debug_fops = {
4418 .owner = THIS_MODULE,
4419 .open = sky2_debug_open,
4420 .read = seq_read,
4421 .llseek = seq_lseek,
4422 .release = single_release,
4423 };
4424
4425 /*
4426 * Use network device events to create/remove/rename
4427 * debugfs file entries
4428 */
4429 static int sky2_device_event(struct notifier_block *unused,
4430 unsigned long event, void *ptr)
4431 {
4432 struct net_device *dev = ptr;
4433 struct sky2_port *sky2 = netdev_priv(dev);
4434
4435 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4436 return NOTIFY_DONE;
4437
4438 switch (event) {
4439 case NETDEV_CHANGENAME:
4440 if (sky2->debugfs) {
4441 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4442 sky2_debug, dev->name);
4443 }
4444 break;
4445
4446 case NETDEV_GOING_DOWN:
4447 if (sky2->debugfs) {
4448 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4449 debugfs_remove(sky2->debugfs);
4450 sky2->debugfs = NULL;
4451 }
4452 break;
4453
4454 case NETDEV_UP:
4455 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4456 sky2_debug, dev,
4457 &sky2_debug_fops);
4458 if (IS_ERR(sky2->debugfs))
4459 sky2->debugfs = NULL;
4460 }
4461
4462 return NOTIFY_DONE;
4463 }
4464
4465 static struct notifier_block sky2_notifier = {
4466 .notifier_call = sky2_device_event,
4467 };
4468
4469
4470 static __init void sky2_debug_init(void)
4471 {
4472 struct dentry *ent;
4473
4474 ent = debugfs_create_dir("sky2", NULL);
4475 if (!ent || IS_ERR(ent))
4476 return;
4477
4478 sky2_debug = ent;
4479 register_netdevice_notifier(&sky2_notifier);
4480 }
4481
4482 static __exit void sky2_debug_cleanup(void)
4483 {
4484 if (sky2_debug) {
4485 unregister_netdevice_notifier(&sky2_notifier);
4486 debugfs_remove(sky2_debug);
4487 sky2_debug = NULL;
4488 }
4489 }
4490
4491 #else
4492 #define sky2_debug_init()
4493 #define sky2_debug_cleanup()
4494 #endif
4495
4496 /* Two copies of network device operations to handle special case of
4497 not allowing netpoll on second port */
4498 static const struct net_device_ops sky2_netdev_ops[2] = {
4499 {
4500 .ndo_open = sky2_up,
4501 .ndo_stop = sky2_down,
4502 .ndo_start_xmit = sky2_xmit_frame,
4503 .ndo_do_ioctl = sky2_ioctl,
4504 .ndo_validate_addr = eth_validate_addr,
4505 .ndo_set_mac_address = sky2_set_mac_address,
4506 .ndo_set_multicast_list = sky2_set_multicast,
4507 .ndo_change_mtu = sky2_change_mtu,
4508 .ndo_fix_features = sky2_fix_features,
4509 .ndo_set_features = sky2_set_features,
4510 .ndo_tx_timeout = sky2_tx_timeout,
4511 .ndo_get_stats64 = sky2_get_stats,
4512 #ifdef CONFIG_NET_POLL_CONTROLLER
4513 .ndo_poll_controller = sky2_netpoll,
4514 #endif
4515 },
4516 {
4517 .ndo_open = sky2_up,
4518 .ndo_stop = sky2_down,
4519 .ndo_start_xmit = sky2_xmit_frame,
4520 .ndo_do_ioctl = sky2_ioctl,
4521 .ndo_validate_addr = eth_validate_addr,
4522 .ndo_set_mac_address = sky2_set_mac_address,
4523 .ndo_set_multicast_list = sky2_set_multicast,
4524 .ndo_change_mtu = sky2_change_mtu,
4525 .ndo_fix_features = sky2_fix_features,
4526 .ndo_set_features = sky2_set_features,
4527 .ndo_tx_timeout = sky2_tx_timeout,
4528 .ndo_get_stats64 = sky2_get_stats,
4529 },
4530 };
4531
4532 /* Initialize network device */
4533 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4534 unsigned port,
4535 int highmem, int wol)
4536 {
4537 struct sky2_port *sky2;
4538 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4539
4540 if (!dev) {
4541 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4542 return NULL;
4543 }
4544
4545 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4546 dev->irq = hw->pdev->irq;
4547 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4548 dev->watchdog_timeo = TX_WATCHDOG;
4549 dev->netdev_ops = &sky2_netdev_ops[port];
4550
4551 sky2 = netdev_priv(dev);
4552 sky2->netdev = dev;
4553 sky2->hw = hw;
4554 sky2->msg_enable = netif_msg_init(debug, default_msg);
4555
4556 /* Auto speed and flow control */
4557 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4558 if (hw->chip_id != CHIP_ID_YUKON_XL)
4559 dev->hw_features |= NETIF_F_RXCSUM;
4560
4561 sky2->flow_mode = FC_BOTH;
4562
4563 sky2->duplex = -1;
4564 sky2->speed = -1;
4565 sky2->advertising = sky2_supported_modes(hw);
4566 sky2->wol = wol;
4567
4568 spin_lock_init(&sky2->phy_lock);
4569
4570 sky2->tx_pending = TX_DEF_PENDING;
4571 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4572 sky2->rx_pending = RX_DEF_PENDING;
4573
4574 hw->dev[port] = dev;
4575
4576 sky2->port = port;
4577
4578 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4579
4580 if (highmem)
4581 dev->features |= NETIF_F_HIGHDMA;
4582
4583 /* Enable receive hashing unless hardware is known broken */
4584 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4585 dev->hw_features |= NETIF_F_RXHASH;
4586
4587 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4588 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4589 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4590 }
4591
4592 dev->features |= dev->hw_features;
4593
4594 /* read the mac address */
4595 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4596 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4597
4598 return dev;
4599 }
4600
4601 static void __devinit sky2_show_addr(struct net_device *dev)
4602 {
4603 const struct sky2_port *sky2 = netdev_priv(dev);
4604
4605 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4606 }
4607
4608 /* Handle software interrupt used during MSI test */
4609 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4610 {
4611 struct sky2_hw *hw = dev_id;
4612 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4613
4614 if (status == 0)
4615 return IRQ_NONE;
4616
4617 if (status & Y2_IS_IRQ_SW) {
4618 hw->flags |= SKY2_HW_USE_MSI;
4619 wake_up(&hw->msi_wait);
4620 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4621 }
4622 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4623
4624 return IRQ_HANDLED;
4625 }
4626
4627 /* Test interrupt path by forcing a a software IRQ */
4628 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4629 {
4630 struct pci_dev *pdev = hw->pdev;
4631 int err;
4632
4633 init_waitqueue_head(&hw->msi_wait);
4634
4635 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4636
4637 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4638 if (err) {
4639 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4640 return err;
4641 }
4642
4643 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4644 sky2_read8(hw, B0_CTST);
4645
4646 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4647
4648 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4649 /* MSI test failed, go back to INTx mode */
4650 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4651 "switching to INTx mode.\n");
4652
4653 err = -EOPNOTSUPP;
4654 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4655 }
4656
4657 sky2_write32(hw, B0_IMSK, 0);
4658 sky2_read32(hw, B0_IMSK);
4659
4660 free_irq(pdev->irq, hw);
4661
4662 return err;
4663 }
4664
4665 /* This driver supports yukon2 chipset only */
4666 static const char *sky2_name(u8 chipid, char *buf, int sz)
4667 {
4668 const char *name[] = {
4669 "XL", /* 0xb3 */
4670 "EC Ultra", /* 0xb4 */
4671 "Extreme", /* 0xb5 */
4672 "EC", /* 0xb6 */
4673 "FE", /* 0xb7 */
4674 "FE+", /* 0xb8 */
4675 "Supreme", /* 0xb9 */
4676 "UL 2", /* 0xba */
4677 "Unknown", /* 0xbb */
4678 "Optima", /* 0xbc */
4679 };
4680
4681 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4682 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4683 else
4684 snprintf(buf, sz, "(chip %#x)", chipid);
4685 return buf;
4686 }
4687
4688 static int __devinit sky2_probe(struct pci_dev *pdev,
4689 const struct pci_device_id *ent)
4690 {
4691 struct net_device *dev;
4692 struct sky2_hw *hw;
4693 int err, using_dac = 0, wol_default;
4694 u32 reg;
4695 char buf1[16];
4696
4697 err = pci_enable_device(pdev);
4698 if (err) {
4699 dev_err(&pdev->dev, "cannot enable PCI device\n");
4700 goto err_out;
4701 }
4702
4703 /* Get configuration information
4704 * Note: only regular PCI config access once to test for HW issues
4705 * other PCI access through shared memory for speed and to
4706 * avoid MMCONFIG problems.
4707 */
4708 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4709 if (err) {
4710 dev_err(&pdev->dev, "PCI read config failed\n");
4711 goto err_out;
4712 }
4713
4714 if (~reg == 0) {
4715 dev_err(&pdev->dev, "PCI configuration read error\n");
4716 goto err_out;
4717 }
4718
4719 err = pci_request_regions(pdev, DRV_NAME);
4720 if (err) {
4721 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4722 goto err_out_disable;
4723 }
4724
4725 pci_set_master(pdev);
4726
4727 if (sizeof(dma_addr_t) > sizeof(u32) &&
4728 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4729 using_dac = 1;
4730 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4731 if (err < 0) {
4732 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4733 "for consistent allocations\n");
4734 goto err_out_free_regions;
4735 }
4736 } else {
4737 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4738 if (err) {
4739 dev_err(&pdev->dev, "no usable DMA configuration\n");
4740 goto err_out_free_regions;
4741 }
4742 }
4743
4744
4745 #ifdef __BIG_ENDIAN
4746 /* The sk98lin vendor driver uses hardware byte swapping but
4747 * this driver uses software swapping.
4748 */
4749 reg &= ~PCI_REV_DESC;
4750 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4751 if (err) {
4752 dev_err(&pdev->dev, "PCI write config failed\n");
4753 goto err_out_free_regions;
4754 }
4755 #endif
4756
4757 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4758
4759 err = -ENOMEM;
4760
4761 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4762 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4763 if (!hw) {
4764 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4765 goto err_out_free_regions;
4766 }
4767
4768 hw->pdev = pdev;
4769 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4770
4771 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4772 if (!hw->regs) {
4773 dev_err(&pdev->dev, "cannot map device registers\n");
4774 goto err_out_free_hw;
4775 }
4776
4777 err = sky2_init(hw);
4778 if (err)
4779 goto err_out_iounmap;
4780
4781 /* ring for status responses */
4782 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4783 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4784 &hw->st_dma);
4785 if (!hw->st_le)
4786 goto err_out_reset;
4787
4788 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4789 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4790
4791 sky2_reset(hw);
4792
4793 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4794 if (!dev) {
4795 err = -ENOMEM;
4796 goto err_out_free_pci;
4797 }
4798
4799 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4800 err = sky2_test_msi(hw);
4801 if (err == -EOPNOTSUPP)
4802 pci_disable_msi(pdev);
4803 else if (err)
4804 goto err_out_free_netdev;
4805 }
4806
4807 err = register_netdev(dev);
4808 if (err) {
4809 dev_err(&pdev->dev, "cannot register net device\n");
4810 goto err_out_free_netdev;
4811 }
4812
4813 netif_carrier_off(dev);
4814
4815 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4816
4817 err = request_irq(pdev->irq, sky2_intr,
4818 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4819 hw->irq_name, hw);
4820 if (err) {
4821 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4822 goto err_out_unregister;
4823 }
4824 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4825 napi_enable(&hw->napi);
4826
4827 sky2_show_addr(dev);
4828
4829 if (hw->ports > 1) {
4830 struct net_device *dev1;
4831
4832 err = -ENOMEM;
4833 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4834 if (dev1 && (err = register_netdev(dev1)) == 0)
4835 sky2_show_addr(dev1);
4836 else {
4837 dev_warn(&pdev->dev,
4838 "register of second port failed (%d)\n", err);
4839 hw->dev[1] = NULL;
4840 hw->ports = 1;
4841 if (dev1)
4842 free_netdev(dev1);
4843 }
4844 }
4845
4846 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4847 INIT_WORK(&hw->restart_work, sky2_restart);
4848
4849 pci_set_drvdata(pdev, hw);
4850 pdev->d3_delay = 150;
4851
4852 return 0;
4853
4854 err_out_unregister:
4855 if (hw->flags & SKY2_HW_USE_MSI)
4856 pci_disable_msi(pdev);
4857 unregister_netdev(dev);
4858 err_out_free_netdev:
4859 free_netdev(dev);
4860 err_out_free_pci:
4861 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4862 hw->st_le, hw->st_dma);
4863 err_out_reset:
4864 sky2_write8(hw, B0_CTST, CS_RST_SET);
4865 err_out_iounmap:
4866 iounmap(hw->regs);
4867 err_out_free_hw:
4868 kfree(hw);
4869 err_out_free_regions:
4870 pci_release_regions(pdev);
4871 err_out_disable:
4872 pci_disable_device(pdev);
4873 err_out:
4874 pci_set_drvdata(pdev, NULL);
4875 return err;
4876 }
4877
4878 static void __devexit sky2_remove(struct pci_dev *pdev)
4879 {
4880 struct sky2_hw *hw = pci_get_drvdata(pdev);
4881 int i;
4882
4883 if (!hw)
4884 return;
4885
4886 del_timer_sync(&hw->watchdog_timer);
4887 cancel_work_sync(&hw->restart_work);
4888
4889 for (i = hw->ports-1; i >= 0; --i)
4890 unregister_netdev(hw->dev[i]);
4891
4892 sky2_write32(hw, B0_IMSK, 0);
4893
4894 sky2_power_aux(hw);
4895
4896 sky2_write8(hw, B0_CTST, CS_RST_SET);
4897 sky2_read8(hw, B0_CTST);
4898
4899 free_irq(pdev->irq, hw);
4900 if (hw->flags & SKY2_HW_USE_MSI)
4901 pci_disable_msi(pdev);
4902 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4903 hw->st_le, hw->st_dma);
4904 pci_release_regions(pdev);
4905 pci_disable_device(pdev);
4906
4907 for (i = hw->ports-1; i >= 0; --i)
4908 free_netdev(hw->dev[i]);
4909
4910 iounmap(hw->regs);
4911 kfree(hw);
4912
4913 pci_set_drvdata(pdev, NULL);
4914 }
4915
4916 static int sky2_suspend(struct device *dev)
4917 {
4918 struct pci_dev *pdev = to_pci_dev(dev);
4919 struct sky2_hw *hw = pci_get_drvdata(pdev);
4920 int i;
4921
4922 if (!hw)
4923 return 0;
4924
4925 del_timer_sync(&hw->watchdog_timer);
4926 cancel_work_sync(&hw->restart_work);
4927
4928 rtnl_lock();
4929
4930 sky2_all_down(hw);
4931 for (i = 0; i < hw->ports; i++) {
4932 struct net_device *dev = hw->dev[i];
4933 struct sky2_port *sky2 = netdev_priv(dev);
4934
4935 if (sky2->wol)
4936 sky2_wol_init(sky2);
4937 }
4938
4939 sky2_power_aux(hw);
4940 rtnl_unlock();
4941
4942 return 0;
4943 }
4944
4945 #ifdef CONFIG_PM_SLEEP
4946 static int sky2_resume(struct device *dev)
4947 {
4948 struct pci_dev *pdev = to_pci_dev(dev);
4949 struct sky2_hw *hw = pci_get_drvdata(pdev);
4950 int err;
4951
4952 if (!hw)
4953 return 0;
4954
4955 /* Re-enable all clocks */
4956 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4957 if (err) {
4958 dev_err(&pdev->dev, "PCI write config failed\n");
4959 goto out;
4960 }
4961
4962 rtnl_lock();
4963 sky2_reset(hw);
4964 sky2_all_up(hw);
4965 rtnl_unlock();
4966
4967 return 0;
4968 out:
4969
4970 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4971 pci_disable_device(pdev);
4972 return err;
4973 }
4974
4975 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
4976 #define SKY2_PM_OPS (&sky2_pm_ops)
4977
4978 #else
4979
4980 #define SKY2_PM_OPS NULL
4981 #endif
4982
4983 static void sky2_shutdown(struct pci_dev *pdev)
4984 {
4985 sky2_suspend(&pdev->dev);
4986 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4987 pci_set_power_state(pdev, PCI_D3hot);
4988 }
4989
4990 static struct pci_driver sky2_driver = {
4991 .name = DRV_NAME,
4992 .id_table = sky2_id_table,
4993 .probe = sky2_probe,
4994 .remove = __devexit_p(sky2_remove),
4995 .shutdown = sky2_shutdown,
4996 .driver.pm = SKY2_PM_OPS,
4997 };
4998
4999 static int __init sky2_init_module(void)
5000 {
5001 pr_info("driver version " DRV_VERSION "\n");
5002
5003 sky2_debug_init();
5004 return pci_register_driver(&sky2_driver);
5005 }
5006
5007 static void __exit sky2_cleanup_module(void)
5008 {
5009 pci_unregister_driver(&sky2_driver);
5010 sky2_debug_cleanup();
5011 }
5012
5013 module_init(sky2_init_module);
5014 module_exit(sky2_cleanup_module);
5015
5016 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5017 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5018 MODULE_LICENSE("GPL");
5019 MODULE_VERSION(DRV_VERSION);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree