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Staging: otus: use ARRAY_SIZE
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / otus / hal / hpmain.c
blob6d2d358d5ca9299324f21f377d66c0c15f530284
1 /*
2 * Copyright (c) 2007-2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 #include "../80211core/cprecomp.h"
17 #include "hpani.h"
18 #include "hpusb.h"
19 #include "otus.ini"
20
21 extern const u32_t zcFwImage[];
22 extern const u32_t zcFwImageSize;
23 extern const u32_t zcDKFwImage[];
24 extern const u32_t zcDKFwImageSize;
25 extern const u32_t zcFwImageSPI[];
26 extern const u32_t zcFwImageSPISize;
27
28 #ifdef ZM_OTUS_LINUX_PHASE_2
29 extern const u32_t zcFwBufImage[];
30 extern const u32_t zcFwBufImageSize;
31 extern const u32_t zcP2FwImage[];
32 extern const u32_t zcP2FwImageSize;
33 #endif
34 extern void zfInitCmdQueue(zdev_t* dev);
35 extern u16_t zfIssueCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen,
36 u16_t src, u8_t* buf);
37 extern void zfIdlRsp(zdev_t* dev, u32_t* rsp, u16_t rspLen);
38 extern u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val);
39 extern u16_t zfFlushDelayWrite(zdev_t* dev);
40 extern void zfUsbInit(zdev_t* dev);
41 extern u16_t zfFirmwareDownload(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset);
42 extern u16_t zfFirmwareDownloadNotJump(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset);
43 extern void zfUsbFree(zdev_t* dev);
44 extern u16_t zfCwmIsExtChanBusy(u32_t ctlBusy, u32_t extBusy);
45 extern void zfCoreCwmBusy(zdev_t* dev, u16_t busy);
46
47 /* Prototypes */
48 void zfInitRf(zdev_t* dev, u32_t frequency);
49 void zfInitPhy(zdev_t* dev, u32_t frequency, u8_t bw40);
50 void zfInitMac(zdev_t* dev);
51
52 void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset);
53 void zfInitPowerCal(zdev_t* dev);
54
55 #ifdef ZM_DRV_INIT_USB_MODE
56 void zfInitUsbMode(zdev_t* dev);
57 u16_t zfHpUsbReset(zdev_t* dev);
58 #endif
59
60 /* Bank 0 1 2 3 5 6 7 */
61 void zfSetRfRegs(zdev_t* dev, u32_t frequency);
62 /* Bank 4 */
63 void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40,
64 u8_t extOffset);
65 /* Get param for turnoffdyn */
66 void zfGetHwTurnOffdynParam(zdev_t* dev,
67 u32_t frequency, u8_t bw40, u8_t extOffset,
68 int* delta_slope_coeff_exp,
69 int* delta_slope_coeff_man,
70 int* delta_slope_coeff_exp_shgi,
71 int* delta_slope_coeff_man_shgi);
72
73 void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency);
74 u32_t zfHpEchoCommand(zdev_t* dev, u32_t value);
75
76
77
78 #define zm_hp_priv(x) (((struct zsHpPriv*)wd->hpPrivate)->x)
79 static struct zsHpPriv zgHpPriv;
80
81 #define ZM_FIRMWARE_WLAN_ADDR 0x200000
82 #define ZM_FIRMWARE_SPI_ADDR 0x114000
83 /* 0: real chip 1: FPGA test */
84 #define ZM_FPGA_PHY 0
85
86 #define reg_write(addr, val) zfDelayWriteInternalReg(dev, addr+0x1bc000, val)
87 #define zm_min(A, B) ((A>B)? B:A)
88
89
90 /******************** Intialization ********************/
91 u16_t zfHpInit(zdev_t* dev, u32_t frequency)
92 {
93 u16_t ret;
94 zmw_get_wlan_dev(dev);
95
96 /* Initializa HAL Plus private variables */
97 wd->hpPrivate = &zgHpPriv;
98
99 ((struct zsHpPriv*)wd->hpPrivate)->halCapability = ZM_HP_CAP_11N;
100
101 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = 0;
102 ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = 0;
103 ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = 0;
104
105 ((struct zsHpPriv*)wd->hpPrivate)->disableDfsCh = 0;
106
107 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0] = 1;
108 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[1] = 1;
109 ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0;
110 ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0;
111
112 ((struct zsHpPriv*)wd->hpPrivate)->slotType = 1;
113 ((struct zsHpPriv*)wd->hpPrivate)->aggPktNum = 0x10000a;
114
115 ((struct zsHpPriv*)wd->hpPrivate)->eepromImageIndex = 0;
116
117
118 ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq = 0;
119 #ifdef ZM_OTUS_RX_STREAM_MODE
120 ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL;
121 ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0;
122 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0;
123 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0;
124 ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0;
125 #endif
126
127 ((struct zsHpPriv*)wd->hpPrivate)->enableBBHeavyClip = 1;
128 ((struct zsHpPriv*)wd->hpPrivate)->hwBBHeavyClip = 1; // force enable 8107
129 ((struct zsHpPriv*)wd->hpPrivate)->doBBHeavyClip = 0;
130 ((struct zsHpPriv*)wd->hpPrivate)->setValueHeavyClip = 0;
131
132
133 /* Initialize driver core */
134 zfInitCmdQueue(dev);
135
136 /* Initialize USB */
137 zfUsbInit(dev);
138
139 #if ZM_SW_LOOP_BACK != 1
140
141 /* TODO : [Download FW] */
142 if (wd->modeMDKEnable)
143 {
144 /* download the MDK firmware */
145 ret = zfFirmwareDownload(dev, (u32_t*)zcDKFwImage,
146 (u32_t)zcDKFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
147 if (ret != ZM_SUCCESS)
148 {
149 /* TODO : exception handling */
150 //return 1;
151 }
152 }
153 else
154 {
155 #ifndef ZM_OTUS_LINUX_PHASE_2
156 /* download the normal firmware */
157 ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
158 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
159 if (ret != ZM_SUCCESS)
160 {
161 /* TODO : exception handling */
162 //return 1;
163 }
164 #else
165
166 // 1-PH fw: ReadMac() store some global variable
167 ret = zfFirmwareDownloadNotJump(dev, (u32_t*)zcFwBufImage,
168 (u32_t)zcFwBufImageSize, 0x102800);
169 if (ret != ZM_SUCCESS)
170 {
171 DbgPrint("Dl zcFwBufImage failed!");
172 }
173
174 zfwSleep(dev, 1000);
175
176 ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
177 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
178 if (ret != ZM_SUCCESS)
179 {
180 DbgPrint("Dl zcFwBufImage failed!");
181 }
182 #endif
183 }
184 #endif
185
186 #ifdef ZM_DRV_INIT_USB_MODE
187 /* Init USB Mode */
188 zfInitUsbMode(dev);
189
190 /* Do the USB Reset */
191 zfHpUsbReset(dev);
192 #endif
193
194 /* Register setting */
195 /* ZM_DRIVER_MODEL_TYPE_MDK
196 * 1=>for MDK, disable init RF, PHY, and MAC,
197 * 0=>normal init
198 */
199 //#if ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1))
200 #if ZM_SW_LOOP_BACK != 1
201 if(!wd->modeMDKEnable)
202 {
203 /* Init MAC */
204 zfInitMac(dev);
205
206 #if ZM_FW_LOOP_BACK != 1
207 /* Init PHY */
208 zfInitPhy(dev, frequency, 0);
209
210 /* Init RF */
211 zfInitRf(dev, frequency);
212
213 #if ZM_FPGA_PHY == 0
214 /* BringUp issue */
215 //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007);
216 //zfFlushDelayWrite(dev);
217 #endif
218
219 #endif /* end of ZM_FW_LOOP_BACK != 1 */
220 }
221 #endif /* end of ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1)) */
222
223 zfHpEchoCommand(dev, 0xAABBCCDD);
224
225 return 0;
226 }
227
228
229 u16_t zfHpReinit(zdev_t* dev, u32_t frequency)
230 {
231 u16_t ret;
232 zmw_get_wlan_dev(dev);
233
234 ((struct zsHpPriv*)wd->hpPrivate)->halReInit = 1;
235
236 ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0;
237 ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0;
238
239 #ifdef ZM_OTUS_RX_STREAM_MODE
240 if (((struct zsHpPriv*)wd->hpPrivate)->remainBuf != NULL)
241 {
242 zfwBufFree(dev, ((struct zsHpPriv*)wd->hpPrivate)->remainBuf, 0);
243 }
244 ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL;
245 ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0;
246 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0;
247 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0;
248 ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0;
249 #endif
250
251 zfInitCmdQueue(dev);
252 zfCoreReinit(dev);
253
254 #ifndef ZM_OTUS_LINUX_PHASE_2
255 /* Download firmware */
256 ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
257 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
258 if (ret != ZM_SUCCESS)
259 {
260 /* TODO : exception handling */
261 //return 1;
262 }
263 #else
264 ret = zfFirmwareDownload(dev, (u32_t*)zcP2FwImage,
265 (u32_t)zcP2FwImageSize, ZM_FIRMWARE_WLAN_ADDR);
266 if (ret != ZM_SUCCESS)
267 {
268 /* TODO : exception handling */
269 //return 1;
270 }
271 #endif
272
273 #ifdef ZM_DRV_INIT_USB_MODE
274 /* Init USB Mode */
275 zfInitUsbMode(dev);
276
277 /* Do the USB Reset */
278 zfHpUsbReset(dev);
279 #endif
280
281 /* Init MAC */
282 zfInitMac(dev);
283
284 /* Init PHY */
285 zfInitPhy(dev, frequency, 0);
286 /* Init RF */
287 zfInitRf(dev, frequency);
288
289 #if ZM_FPGA_PHY == 0
290 /* BringUp issue */
291 //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007);
292 //zfFlushDelayWrite(dev);
293 #endif
294
295 zfHpEchoCommand(dev, 0xAABBCCDD);
296
297 return 0;
298 }
299
300
301 u16_t zfHpRelease(zdev_t* dev)
302 {
303 /* Free USB resource */
304 zfUsbFree(dev);
305
306 return 0;
307 }
308
309 /* MDK mode setting for dontRetransmit */
310 void zfHpConfigFM(zdev_t* dev, u32_t RxMaxSize, u32_t DontRetransmit)
311 {
312 u32_t cmd[3];
313 u16_t ret;
314
315 cmd[0] = 8 | (ZM_CMD_CONFIG << 8);
316 cmd[1] = RxMaxSize; /* zgRxMaxSize */
317 cmd[2] = DontRetransmit; /* zgDontRetransmit */
318
319 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_INTERNAL_WRITE, 0);
320 }
321
322 const u8_t zcXpdToPd[16] =
323 {
324 /* 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF */
325 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2, 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
326 };
327
328 /******************** RF and PHY ********************/
329
330 void zfInitPhy(zdev_t* dev, u32_t frequency, u8_t bw40)
331 {
332 u16_t i, j, k;
333 u16_t entries;
334 u16_t modesIndex = 0;
335 u16_t freqIndex = 0;
336 u32_t tmp, tmp1;
337 struct zsHpPriv* hpPriv;
338
339 u32_t eepromBoardData[15][6] = {
340 /* Register A-20 A-20/40 G-20/40 G-20 G-Turbo */
341 {0x9964, 0, 0, 0, 0, 0},
342 {0x9960, 0, 0, 0, 0, 0},
343 {0xb960, 0, 0, 0, 0, 0},
344 {0x9844, 0, 0, 0, 0, 0},
345 {0x9850, 0, 0, 0, 0, 0},
346 {0x9834, 0, 0, 0, 0, 0},
347 {0x9828, 0, 0, 0, 0, 0},
348 {0xc864, 0, 0, 0, 0, 0},
349 {0x9848, 0, 0, 0, 0, 0},
350 {0xb848, 0, 0, 0, 0, 0},
351 {0xa20c, 0, 0, 0, 0, 0},
352 {0xc20c, 0, 0, 0, 0, 0},
353 {0x9920, 0, 0, 0, 0, 0},
354 {0xb920, 0, 0, 0, 0, 0},
355 {0xa258, 0, 0, 0, 0, 0},
356 };
357
358 zmw_get_wlan_dev(dev);
359 hpPriv=wd->hpPrivate;
360
361 /* #1 Save the initial value of the related RIFS register settings */
362 //((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy++;
363
364 /*
365 * Setup the indices for the next set of register array writes
366 * PHY mode is static20 / 2040
367 * Frequency is 2.4GHz (B) / 5GHz (A)
368 */
369 if ( frequency > ZM_CH_G_14 )
370 {
371 /* 5GHz */
372 freqIndex = 1;
373 if (bw40)
374 {
375 modesIndex = 2;
376 zm_debug_msg0("init ar5416Modes in 2: A-20/40");
377 }
378 else
379 {
380 modesIndex = 1;
381 zm_debug_msg0("init ar5416Modes in 1: A-20");
382 }
383 }
384 else
385 {
386 /* 2.4GHz */
387 freqIndex = 2;
388 if (bw40)
389 {
390 modesIndex = 3;
391 zm_debug_msg0("init ar5416Modes in 3: G-20/40");
392 }
393 else
394 {
395 modesIndex = 4;
396 zm_debug_msg0("init ar5416Modes in 4: G-20");
397 }
398 }
399
400
401 #if ZM_FPGA_PHY == 1
402 /* Starting External Hainan Register Initialization */
403 /* TODO: */
404
405 zfwSleep(dev, 10);
406 #endif
407
408 /*
409 *Set correct Baseband to analog shift setting to access analog chips.
410 */
411 //reg_write(PHY_BASE, 0x00000007);
412 // reg_write(0x9800, 0x00000007);
413
414 /*
415 * Write addac shifts
416 */
417 // do this in firmware
418
419
420
421 /* Zeroize board data */
422 for (j=0; j<15; j++)
423 {
424 for (k=1; k<=4; k++)
425 {
426 eepromBoardData[j][k] = 0;
427 }
428 }
429 /*
430 * Register setting by mode
431 */
432
433 entries = ARRAY_SIZE(ar5416Modes);
434 zm_msg1_scan(ZM_LV_2, "Modes register setting entries=", entries);
435 for (i=0; i<entries; i++)
436 {
437 #if 0
438 if ( ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit && (ar5416Modes[i][0] == 0xa27c) )
439 {
440 /* Force disable CR671 bit20 / 7823 */
441 /* The bug has to do with the polarity of the pdadc offset calibration. There */
442 /* is an initial calibration that is OK, and there is a continuous */
443 /* calibration that updates the pddac with the wrong polarity. Fortunately */
444 /* the second loop can be disabled with a bit called en_pd_dc_offset_thr. */
445
446 reg_write(ar5416Modes[i][0], (ar5416Modes[i][modesIndex]& 0xffefffff) );
447 ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit = 1;
448 }
449 else
450 {
451 #endif
452 /* FirstTime Init or not 0xa27c(CR671) */
453 reg_write(ar5416Modes[i][0], ar5416Modes[i][modesIndex]);
454 // }
455 /* Initialize board data */
456 for (j=0; j<15; j++)
457 {
458 if (ar5416Modes[i][0] == eepromBoardData[j][0])
459 {
460 for (k=1; k<=4; k++)
461 {
462 eepromBoardData[j][k] = ar5416Modes[i][k];
463 }
464 }
465 }
466 /* #1 Save the initial value of the related RIFS register settings */
467 //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 )
468 {
469 switch(ar5416Modes[i][0])
470 {
471 case 0x9850 :
472 ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize = ar5416Modes[i][modesIndex];
473 break;
474 case 0x985c :
475 ((struct zsHpPriv*)wd->hpPrivate)->initAGC = ar5416Modes[i][modesIndex];
476 break;
477 case 0x9860 :
478 ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl = ar5416Modes[i][modesIndex];
479 break;
480 case 0x9918 :
481 ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay = ar5416Modes[i][modesIndex];
482 break;
483 case 0x99ec :
484 ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams = ar5416Modes[i][modesIndex];
485 break;
486 case 0xa388 :
487 ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = ar5416Modes[i][modesIndex];
488 default :
489 break;
490 }
491 }
492 }
493 #if 0
494 zfFlushDelayWrite(dev);
495
496 /*
497 * Common Register setting
498 */
499 entries = ARRAY_SIZE(ar5416Common);
500 for (i=0; i<entries; i++)
501 {
502 reg_write(ar5416Common[i][0], ar5416Common[i][1]);
503 }
504 zfFlushDelayWrite(dev);
505
506 /*
507 * RF Gain setting by freqIndex
508 */
509 entries = ARRAY_SIZE(ar5416BB_RfGain);
510 for (i=0; i<entries; i++)
511 {
512 reg_write(ar5416BB_RfGain[i][0], ar5416BB_RfGain[i][freqIndex]);
513 }
514 zfFlushDelayWrite(dev);
515
516 /*
517 * Moved ar5416InitChainMask() here to ensure the swap bit is set before
518 * the pdadc table is written. Swap must occur before any radio dependent
519 * replicated register access. The pdadc curve addressing in particular
520 * depends on the consistent setting of the swap bit.
521 */
522 //ar5416InitChainMask(pDev);
523
524 /* Setup the transmit power values. */
525 // TODO
526 #endif
527
528 /* Update 5G board data */
529 //Ant control common
530 tmp = hpPriv->eepromImage[0x100+0x144*2/4];
531 eepromBoardData[0][1] = tmp;
532 eepromBoardData[0][2] = tmp;
533 //Ant control chain 0
534 tmp = hpPriv->eepromImage[0x100+0x140*2/4];
535 eepromBoardData[1][1] = tmp;
536 eepromBoardData[1][2] = tmp;
537 //Ant control chain 2
538 tmp = hpPriv->eepromImage[0x100+0x142*2/4];
539 eepromBoardData[2][1] = tmp;
540 eepromBoardData[2][2] = tmp;
541 //SwSettle
542 tmp = hpPriv->eepromImage[0x100+0x146*2/4];
543 tmp = (tmp >> 16) & 0x7f;
544 eepromBoardData[3][1] &= (~((u32_t)0x3f80));
545 eepromBoardData[3][1] |= (tmp << 7);
546 #if 0
547 //swSettleHt40
548 tmp = hpPriv->eepromImage[0x100+0x158*2/4];
549 tmp = (tmp) & 0x7f;
550 eepromBoardData[3][2] &= (~((u32_t)0x3f80));
551 eepromBoardData[3][2] |= (tmp << 7);
552 #endif
553 //adcDesired, pdaDesired
554 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
555 tmp = (tmp >> 24);
556 tmp1 = hpPriv->eepromImage[0x100+0x14a*2/4];
557 tmp1 = tmp1 & 0xff;
558 tmp = tmp + (tmp1<<8);
559 eepromBoardData[4][1] &= (~((u32_t)0xffff));
560 eepromBoardData[4][1] |= tmp;
561 eepromBoardData[4][2] &= (~((u32_t)0xffff));
562 eepromBoardData[4][2] |= tmp;
563 //TxEndToXpaOff, TxFrameToXpaOn
564 tmp = hpPriv->eepromImage[0x100+0x14a*2/4];
565 tmp = (tmp >> 24) & 0xff;
566 tmp1 = hpPriv->eepromImage[0x100+0x14c*2/4];
567 tmp1 = (tmp1 >> 8) & 0xff;
568 tmp = (tmp<<24) + (tmp<<16) + (tmp1<<8) + tmp1;
569 eepromBoardData[5][1] = tmp;
570 eepromBoardData[5][2] = tmp;
571 //TxEnaToRxOm
572 tmp = hpPriv->eepromImage[0x100+0x14c*2/4] & 0xff;
573 eepromBoardData[6][1] &= (~((u32_t)0xff0000));
574 eepromBoardData[6][1] |= (tmp<<16);
575 eepromBoardData[6][2] &= (~((u32_t)0xff0000));
576 eepromBoardData[6][2] |= (tmp<<16);
577 //Thresh62
578 tmp = hpPriv->eepromImage[0x100+0x14c*2/4];
579 tmp = (tmp >> 16) & 0x7f;
580 eepromBoardData[7][1] &= (~((u32_t)0x7f000));
581 eepromBoardData[7][1] |= (tmp<<12);
582 eepromBoardData[7][2] &= (~((u32_t)0x7f000));
583 eepromBoardData[7][2] |= (tmp<<12);
584 //TxRxAtten chain_0
585 tmp = hpPriv->eepromImage[0x100+0x146*2/4];
586 tmp = (tmp >> 24) & 0x3f;
587 eepromBoardData[8][1] &= (~((u32_t)0x3f000));
588 eepromBoardData[8][1] |= (tmp<<12);
589 eepromBoardData[8][2] &= (~((u32_t)0x3f000));
590 eepromBoardData[8][2] |= (tmp<<12);
591 //TxRxAtten chain_2
592 tmp = hpPriv->eepromImage[0x100+0x148*2/4] & 0x3f;
593 eepromBoardData[9][1] &= (~((u32_t)0x3f000));
594 eepromBoardData[9][1] |= (tmp<<12);
595 eepromBoardData[9][2] &= (~((u32_t)0x3f000));
596 eepromBoardData[9][2] |= (tmp<<12);
597 //TxRxMargin chain_0
598 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
599 tmp = (tmp >> 8) & 0x3f;
600 eepromBoardData[10][1] &= (~((u32_t)0xfc0000));
601 eepromBoardData[10][1] |= (tmp<<18);
602 eepromBoardData[10][2] &= (~((u32_t)0xfc0000));
603 eepromBoardData[10][2] |= (tmp<<18);
604 //TxRxMargin chain_2
605 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
606 tmp = (tmp >> 16) & 0x3f;
607 eepromBoardData[11][1] &= (~((u32_t)0xfc0000));
608 eepromBoardData[11][1] |= (tmp<<18);
609 eepromBoardData[11][2] &= (~((u32_t)0xfc0000));
610 eepromBoardData[11][2] |= (tmp<<18);
611 //iqCall chain_0, iqCallQ chain_0
612 tmp = hpPriv->eepromImage[0x100+0x14e*2/4];
613 tmp = (tmp >> 24) & 0x3f;
614 tmp1 = hpPriv->eepromImage[0x100+0x150*2/4];
615 tmp1 = (tmp1 >> 8) & 0x1f;
616 tmp = (tmp<<5) + tmp1;
617 eepromBoardData[12][1] &= (~((u32_t)0x7ff));
618 eepromBoardData[12][1] |= (tmp);
619 eepromBoardData[12][2] &= (~((u32_t)0x7ff));
620 eepromBoardData[12][2] |= (tmp);
621 //iqCall chain_2, iqCallQ chain_2
622 tmp = hpPriv->eepromImage[0x100+0x150*2/4];
623 tmp = tmp & 0x3f;
624 tmp1 = hpPriv->eepromImage[0x100+0x150*2/4];
625 tmp1 = (tmp1 >> 16) & 0x1f;
626 tmp = (tmp<<5) + tmp1;
627 eepromBoardData[13][1] &= (~((u32_t)0x7ff));
628 eepromBoardData[13][1] |= (tmp);
629 eepromBoardData[13][2] &= (~((u32_t)0x7ff));
630 eepromBoardData[13][2] |= (tmp);
631 //bsw_Margin chain_0
632 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
633 tmp = (tmp >> 16) & 0xf;
634 eepromBoardData[10][1] &= (~((u32_t)0x3c00));
635 eepromBoardData[10][1] |= (tmp << 10);
636 eepromBoardData[10][2] &= (~((u32_t)0x3c00));
637 eepromBoardData[10][2] |= (tmp << 10);
638 //xpd gain mask
639 tmp = hpPriv->eepromImage[0x100+0x14e*2/4];
640 tmp = (tmp >> 8) & 0xf;
641 eepromBoardData[14][1] &= (~((u32_t)0xf0000));
642 eepromBoardData[14][1] |= (zcXpdToPd[tmp] << 16);
643 eepromBoardData[14][2] &= (~((u32_t)0xf0000));
644 eepromBoardData[14][2] |= (zcXpdToPd[tmp] << 16);
645 #if 0
646 //bsw_Atten chain_0
647 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
648 tmp = (tmp) & 0x1f;
649 eepromBoardData[10][1] &= (~((u32_t)0x1f));
650 eepromBoardData[10][1] |= (tmp);
651 eepromBoardData[10][2] &= (~((u32_t)0x1f));
652 eepromBoardData[10][2] |= (tmp);
653 //bsw_Margin chain_2
654 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
655 tmp = (tmp >> 24) & 0xf;
656 eepromBoardData[11][1] &= (~((u32_t)0x3c00));
657 eepromBoardData[11][1] |= (tmp << 10);
658 eepromBoardData[11][2] &= (~((u32_t)0x3c00));
659 eepromBoardData[11][2] |= (tmp << 10);
660 //bsw_Atten chain_2
661 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
662 tmp = (tmp >> 8) & 0x1f;
663 eepromBoardData[11][1] &= (~((u32_t)0x1f));
664 eepromBoardData[11][1] |= (tmp);
665 eepromBoardData[11][2] &= (~((u32_t)0x1f));
666 eepromBoardData[11][2] |= (tmp);
667 #endif
668
669 /* Update 2.4G board data */
670 //Ant control common
671 tmp = hpPriv->eepromImage[0x100+0x170*2/4];
672 tmp = tmp >> 24;
673 tmp1 = hpPriv->eepromImage[0x100+0x172*2/4];
674 tmp = tmp + (tmp1 << 8);
675 eepromBoardData[0][3] = tmp;
676 eepromBoardData[0][4] = tmp;
677 //Ant control chain 0
678 tmp = hpPriv->eepromImage[0x100+0x16c*2/4];
679 tmp = tmp >> 24;
680 tmp1 = hpPriv->eepromImage[0x100+0x16e*2/4];
681 tmp = tmp + (tmp1 << 8);
682 eepromBoardData[1][3] = tmp;
683 eepromBoardData[1][4] = tmp;
684 //Ant control chain 2
685 tmp = hpPriv->eepromImage[0x100+0x16e*2/4];
686 tmp = tmp >> 24;
687 tmp1 = hpPriv->eepromImage[0x100+0x170*2/4];
688 tmp = tmp + (tmp1 << 8);
689 eepromBoardData[2][3] = tmp;
690 eepromBoardData[2][4] = tmp;
691 //SwSettle
692 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
693 tmp = (tmp >> 8) & 0x7f;
694 eepromBoardData[3][4] &= (~((u32_t)0x3f80));
695 eepromBoardData[3][4] |= (tmp << 7);
696 #if 0
697 //swSettleHt40
698 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
699 tmp = (tmp >> 24) & 0x7f;
700 eepromBoardData[3][3] &= (~((u32_t)0x3f80));
701 eepromBoardData[3][3] |= (tmp << 7);
702 #endif
703 //adcDesired, pdaDesired
704 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
705 tmp = (tmp >> 16) & 0xff;
706 tmp1 = hpPriv->eepromImage[0x100+0x176*2/4];
707 tmp1 = tmp1 >> 24;
708 tmp = tmp + (tmp1<<8);
709 eepromBoardData[4][3] &= (~((u32_t)0xffff));
710 eepromBoardData[4][3] |= tmp;
711 eepromBoardData[4][4] &= (~((u32_t)0xffff));
712 eepromBoardData[4][4] |= tmp;
713 //TxEndToXpaOff, TxFrameToXpaOn
714 tmp = hpPriv->eepromImage[0x100+0x178*2/4];
715 tmp = (tmp >> 16) & 0xff;
716 tmp1 = hpPriv->eepromImage[0x100+0x17a*2/4];
717 tmp1 = tmp1 & 0xff;
718 tmp = (tmp << 24) + (tmp << 16) + (tmp1 << 8) + tmp1;
719 eepromBoardData[5][3] = tmp;
720 eepromBoardData[5][4] = tmp;
721 //TxEnaToRxOm
722 tmp = hpPriv->eepromImage[0x100+0x178*2/4];
723 tmp = (tmp >> 24);
724 eepromBoardData[6][3] &= (~((u32_t)0xff0000));
725 eepromBoardData[6][3] |= (tmp<<16);
726 eepromBoardData[6][4] &= (~((u32_t)0xff0000));
727 eepromBoardData[6][4] |= (tmp<<16);
728 //Thresh62
729 tmp = hpPriv->eepromImage[0x100+0x17a*2/4];
730 tmp = (tmp >> 8) & 0x7f;
731 eepromBoardData[7][3] &= (~((u32_t)0x7f000));
732 eepromBoardData[7][3] |= (tmp<<12);
733 eepromBoardData[7][4] &= (~((u32_t)0x7f000));
734 eepromBoardData[7][4] |= (tmp<<12);
735 //TxRxAtten chain_0
736 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
737 tmp = (tmp >> 16) & 0x3f;
738 eepromBoardData[8][3] &= (~((u32_t)0x3f000));
739 eepromBoardData[8][3] |= (tmp<<12);
740 eepromBoardData[8][4] &= (~((u32_t)0x3f000));
741 eepromBoardData[8][4] |= (tmp<<12);
742 //TxRxAtten chain_2
743 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
744 tmp = (tmp >> 24) & 0x3f;
745 eepromBoardData[9][3] &= (~((u32_t)0x3f000));
746 eepromBoardData[9][3] |= (tmp<<12);
747 eepromBoardData[9][4] &= (~((u32_t)0x3f000));
748 eepromBoardData[9][4] |= (tmp<<12);
749 //TxRxMargin chain_0
750 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
751 tmp = (tmp) & 0x3f;
752 eepromBoardData[10][3] &= (~((u32_t)0xfc0000));
753 eepromBoardData[10][3] |= (tmp<<18);
754 eepromBoardData[10][4] &= (~((u32_t)0xfc0000));
755 eepromBoardData[10][4] |= (tmp<<18);
756 //TxRxMargin chain_2
757 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
758 tmp = (tmp >> 8) & 0x3f;
759 eepromBoardData[11][3] &= (~((u32_t)0xfc0000));
760 eepromBoardData[11][3] |= (tmp<<18);
761 eepromBoardData[11][4] &= (~((u32_t)0xfc0000));
762 eepromBoardData[11][4] |= (tmp<<18);
763 //iqCall chain_0, iqCallQ chain_0
764 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
765 tmp = (tmp >> 16) & 0x3f;
766 tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4];
767 tmp1 = (tmp1) & 0x1f;
768 tmp = (tmp<<5) + tmp1;
769 eepromBoardData[12][3] &= (~((u32_t)0x7ff));
770 eepromBoardData[12][3] |= (tmp);
771 eepromBoardData[12][4] &= (~((u32_t)0x7ff));
772 eepromBoardData[12][4] |= (tmp);
773 //iqCall chain_2, iqCallQ chain_2
774 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
775 tmp = (tmp>>24) & 0x3f;
776 tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4];
777 tmp1 = (tmp1 >> 8) & 0x1f;
778 tmp = (tmp<<5) + tmp1;
779 eepromBoardData[13][3] &= (~((u32_t)0x7ff));
780 eepromBoardData[13][3] |= (tmp);
781 eepromBoardData[13][4] &= (~((u32_t)0x7ff));
782 eepromBoardData[13][4] |= (tmp);
783 //xpd gain mask
784 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
785 tmp = tmp & 0xf;
786 DbgPrint("xpd=0x%x, pd=0x%x\n", tmp, zcXpdToPd[tmp]);
787 eepromBoardData[14][3] &= (~((u32_t)0xf0000));
788 eepromBoardData[14][3] |= (zcXpdToPd[tmp] << 16);
789 eepromBoardData[14][4] &= (~((u32_t)0xf0000));
790 eepromBoardData[14][4] |= (zcXpdToPd[tmp] << 16);
791 #if 0
792 //bsw_Margin chain_0
793 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
794 tmp = (tmp >> 8) & 0xf;
795 eepromBoardData[10][3] &= (~((u32_t)0x3c00));
796 eepromBoardData[10][3] |= (tmp << 10);
797 eepromBoardData[10][4] &= (~((u32_t)0x3c00));
798 eepromBoardData[10][4] |= (tmp << 10);
799 //bsw_Atten chain_0
800 tmp = hpPriv->eepromImage[0x100+0x182*2/4];
801 tmp = (tmp>>24) & 0x1f;
802 eepromBoardData[10][3] &= (~((u32_t)0x1f));
803 eepromBoardData[10][3] |= (tmp);
804 eepromBoardData[10][4] &= (~((u32_t)0x1f));
805 eepromBoardData[10][4] |= (tmp);
806 //bsw_Margin chain_2
807 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
808 tmp = (tmp >> 16) & 0xf;
809 eepromBoardData[11][3] &= (~((u32_t)0x3c00));
810 eepromBoardData[11][3] |= (tmp << 10);
811 eepromBoardData[11][4] &= (~((u32_t)0x3c00));
812 eepromBoardData[11][4] |= (tmp << 10);
813 //bsw_Atten chain_2
814 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
815 tmp = (tmp) & 0x1f;
816 eepromBoardData[11][3] &= (~((u32_t)0x1f));
817 eepromBoardData[11][3] |= (tmp);
818 eepromBoardData[11][4] &= (~((u32_t)0x1f));
819 eepromBoardData[11][4] |= (tmp);
820 #endif
821
822 #if 0
823 for (j=0; j<14; j++)
824 {
825 DbgPrint("%04x, %08x, %08x, %08x, %08x\n", eepromBoardData[j][0], eepromBoardData[j][1], eepromBoardData[j][2], eepromBoardData[j][3], eepromBoardData[j][4]);
826 }
827 #endif
828
829 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
830 {
831 /* Update board data to registers */
832 for (j=0; j<15; j++)
833 {
834 reg_write(eepromBoardData[j][0], eepromBoardData[j][modesIndex]);
835
836 /* #1 Save the initial value of the related RIFS register settings */
837 //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 )
838 {
839 switch(eepromBoardData[j][0])
840 {
841 case 0x9850 :
842 ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize = eepromBoardData[j][modesIndex];
843 break;
844 case 0x985c :
845 ((struct zsHpPriv*)wd->hpPrivate)->initAGC = eepromBoardData[j][modesIndex];
846 break;
847 case 0x9860 :
848 ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl = eepromBoardData[j][modesIndex];
849 break;
850 case 0x9918 :
851 ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay = eepromBoardData[j][modesIndex];
852 break;
853 case 0x99ec :
854 ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams = eepromBoardData[j][modesIndex];
855 break;
856 case 0xa388 :
857 ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = eepromBoardData[j][modesIndex];
858 default :
859 break;
860 }
861 }
862 }
863 } /* if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE */
864
865
866 /* Bringup issue : force tx gain */
867 //reg_write(0xa258, 0x0cc65381);
868 //reg_write(0xa274, 0x0a1a7c15);
869 zfInitPowerCal(dev);
870
871 if(frequency > ZM_CH_G_14)
872 {
873 zfDelayWriteInternalReg(dev, 0x1d4014, 0x5143);
874 }
875 else
876 {
877 zfDelayWriteInternalReg(dev, 0x1d4014, 0x5163);
878 }
879
880 zfFlushDelayWrite(dev);
881 }
882
883
884 void zfInitRf(zdev_t* dev, u32_t frequency)
885 {
886 u32_t cmd[8];
887 u16_t ret;
888 int delta_slope_coeff_exp;
889 int delta_slope_coeff_man;
890 int delta_slope_coeff_exp_shgi;
891 int delta_slope_coeff_man_shgi;
892
893 zmw_get_wlan_dev(dev);
894
895 zm_debug_msg1(" initRf frequency = ", frequency);
896
897 if (frequency == 0)
898 {
899 frequency = 2412;
900 }
901
902 /* Bank 0 1 2 3 5 6 7 */
903 zfSetRfRegs(dev, frequency);
904 /* Bank 4 */
905 zfSetBank4AndPowerTable(dev, frequency, 0, 0);
906
907 /* stroe frequency */
908 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency;
909
910 zfGetHwTurnOffdynParam(dev,
911 frequency, 0, 0,
912 &delta_slope_coeff_exp,
913 &delta_slope_coeff_man,
914 &delta_slope_coeff_exp_shgi,
915 &delta_slope_coeff_man_shgi);
916
917 /* related functions */
918 frequency = frequency*1000;
919 cmd[0] = 28 | (ZM_CMD_RF_INIT << 8);
920 cmd[1] = frequency;
921 cmd[2] = 0;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN;
922 cmd[3] = 1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE);
923 cmd[4] = delta_slope_coeff_exp;
924 cmd[5] = delta_slope_coeff_man;
925 cmd[6] = delta_slope_coeff_exp_shgi;
926 cmd[7] = delta_slope_coeff_man_shgi;
927
928 ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, 0);
929
930 // delay temporarily, wait for new PHY and RF
931 zfwSleep(dev, 1000);
932 }
933
934 int tn(int exp)
935 {
936 int i;
937 int tmp = 1;
938 for(i=0; i<exp; i++)
939 tmp = tmp*2;
940
941 return tmp;
942 }
943
944 /*int zfFloor(double indata)
945 {
946 if(indata<0)
947 return (int)indata-1;
948 else
949 return (int)indata;
950 }
951 */
952 u32_t reverse_bits(u32_t chan_sel)
953 {
954 /* reverse_bits */
955 u32_t chansel = 0;
956 u8_t i;
957
958 for (i=0; i<8; i++)
959 chansel |= ((chan_sel>>(7-i) & 0x1) << i);
960 return chansel;
961 }
962
963 /* Bank 0 1 2 3 5 6 7 */
964 void zfSetRfRegs(zdev_t* dev, u32_t frequency)
965 {
966 u16_t freqIndex = 0;
967 u16_t i;
968
969 //zmw_get_wlan_dev(dev);
970
971 if ( frequency > ZM_CH_G_14 )
972 {
973 /* 5G */
974 freqIndex = 1;
975 zm_msg0_scan(ZM_LV_2, "Set to 5GHz");
976
977 }
978 else
979 {
980 /* 2.4G */
981 freqIndex = 2;
982 zm_msg0_scan(ZM_LV_2, "Set to 2.4GHz");
983 }
984
985 #if 1
986 for (i=0; i<ARRAY_SIZE(otusBank); i++)
987 {
988 reg_write(otusBank[i][0], otusBank[i][freqIndex]);
989 }
990 #else
991 /* Bank0 */
992 for (i=0; i<ARRAY_SIZE(ar5416Bank0); i++)
993 {
994 reg_write(ar5416Bank0[i][0], ar5416Bank0[i][1]);
995 }
996 /* Bank1 */
997 for (i=0; i<ARRAY_SIZE(ar5416Bank1); i++)
998 {
999 reg_write(ar5416Bank1[i][0], ar5416Bank1[i][1]);
1000 }
1001 /* Bank2 */
1002 for (i=0; i<ARRAY_SIZE(ar5416Bank2); i++)
1003 {
1004 reg_write(ar5416Bank2[i][0], ar5416Bank2[i][1]);
1005 }
1006 /* Bank3 */
1007 for (i=0; i<ARRAY_SIZE(ar5416Bank3); i++)
1008 {
1009 reg_write(ar5416Bank3[i][0], ar5416Bank3[i][freqIndex]);
1010 }
1011 /* Bank5 */
1012 reg_write (0x98b0, 0x00000013);
1013 reg_write (0x98e4, 0x00000002);
1014 /* Bank6 */
1015 for (i=0; i<ARRAY_SIZE(ar5416Bank6); i++)
1016 {
1017 reg_write(ar5416Bank6[i][0], ar5416Bank6[i][freqIndex]);
1018 }
1019 /* Bank7 */
1020 for (i=0; i<ARRAY_SIZE(ar5416Bank7); i++)
1021 {
1022 reg_write(ar5416Bank7[i][0], ar5416Bank7[i][1]);
1023 }
1024 #endif
1025
1026 zfFlushDelayWrite(dev);
1027 }
1028
1029 /* Bank 4 */
1030 void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40,
1031 u8_t extOffset)
1032 {
1033 u32_t chup = 1;
1034 u32_t bmode_LF_synth_freq = 0;
1035 u32_t amode_refsel_1 = 0;
1036 u32_t amode_refsel_0 = 1;
1037 u32_t addr2 = 1;
1038 u32_t addr1 = 0;
1039 u32_t addr0 = 0;
1040
1041 u32_t d1;
1042 u32_t d0;
1043 u32_t tmp_0;
1044 u32_t tmp_1;
1045 u32_t data0;
1046 u32_t data1;
1047
1048 u8_t chansel;
1049 u8_t chan_sel;
1050 u32_t temp_chan_sel;
1051
1052 u16_t i;
1053
1054 zmw_get_wlan_dev(dev);
1055
1056
1057 /* if enable 802.11h, need to record curent channel index in channel array */
1058 if (wd->sta.DFSEnable)
1059 {
1060 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++)
1061 {
1062 if (wd->regulationTable.allowChannel[i].channel == frequency)
1063 break;
1064 }
1065 wd->regulationTable.CurChIndex = i;
1066 }
1067
1068 if (bw40 == 1)
1069 {
1070 if (extOffset == 1)
1071 {
1072 frequency += 10;
1073 }
1074 else
1075 {
1076 frequency -= 10;
1077 }
1078
1079 }
1080
1081
1082 if ( frequency > 3000 )
1083 {
1084 if ( frequency % 10 )
1085 {
1086 /* 5M */
1087 chan_sel = (u8_t)((frequency - 4800)/5);
1088 chan_sel = (u8_t)(chan_sel & 0xff);
1089 chansel = (u8_t)reverse_bits(chan_sel);
1090 }
1091 else
1092 {
1093 /* 10M : improve Tx EVM */
1094 chan_sel = (u8_t)((frequency - 4800)/10);
1095 chan_sel = (u8_t)(chan_sel & 0xff)<<1;
1096 chansel = (u8_t)reverse_bits(chan_sel);
1097
1098 amode_refsel_1 = 1;
1099 amode_refsel_0 = 0;
1100 }
1101 }
1102 else
1103 {
1104 //temp_chan_sel = (((frequency - 672)*2) - 3040)/10;
1105 if (frequency == 2484)
1106 {
1107 temp_chan_sel = 10 + (frequency - 2274)/5 ;
1108 bmode_LF_synth_freq = 1;
1109 }
1110 else
1111 {
1112 temp_chan_sel = 16 + (frequency - 2272)/5 ;
1113 bmode_LF_synth_freq = 0;
1114 }
1115 chan_sel = (u8_t)(temp_chan_sel << 2) & 0xff;
1116 chansel = (u8_t)reverse_bits(chan_sel);
1117 }
1118
1119 d1 = chansel; //# 8 bits of chan
1120 d0 = addr0<<7 | addr1<<6 | addr2<<5
1121 | amode_refsel_0<<3 | amode_refsel_1<<2
1122 | bmode_LF_synth_freq<<1 | chup;
1123
1124 tmp_0 = d0 & 0x1f; //# 5-1
1125 tmp_1 = d1 & 0x1f; //# 5-1
1126 data0 = tmp_1<<5 | tmp_0;
1127
1128 tmp_0 = d0>>5 & 0x7; //# 8-6
1129 tmp_1 = d1>>5 & 0x7; //# 8-6
1130 data1 = tmp_1<<5 | tmp_0;
1131
1132 /* Bank4 */
1133 reg_write (0x9800+(0x2c<<2), data0);
1134 reg_write (0x9800+(0x3a<<2), data1);
1135 //zm_debug_msg1("0x9800+(0x2c<<2 = ", data0);
1136 //zm_debug_msg1("0x9800+(0x3a<<2 = ", data1);
1137
1138
1139 zfFlushDelayWrite(dev);
1140
1141 zfwSleep(dev, 10);
1142
1143 return;
1144 }
1145
1146
1147 struct zsPhyFreqPara
1148 {
1149 u32_t coeff_exp;
1150 u32_t coeff_man;
1151 u32_t coeff_exp_shgi;
1152 u32_t coeff_man_shgi;
1153 };
1154
1155 struct zsPhyFreqTable
1156 {
1157 u32_t frequency;
1158 struct zsPhyFreqPara FpgaDynamicHT;
1159 struct zsPhyFreqPara FpgaStaticHT;
1160 struct zsPhyFreqPara ChipST20Mhz;
1161 struct zsPhyFreqPara Chip2040Mhz;
1162 struct zsPhyFreqPara Chip2040ExtAbove;
1163 };
1164
1165 const struct zsPhyFreqTable zgPhyFreqCoeff[] =
1166 {
1167 /*Index freq FPGA DYNAMIC_HT2040_EN FPGA STATIC_HT20 Real Chip static20MHz Real Chip 2040MHz Real Chip 2040Mhz */
1168 /* fclk = 10.8 21.6 40 ext below 40 ext above 40 */
1169 /* 0 */ {2412, {5, 23476, 5, 21128}, {4, 23476, 4, 21128}, {3, 21737, 3, 19563}, {3, 21827, 3, 19644}, {3, 21647, 3, 19482}},
1170 /* 1 */ {2417, {5, 23427, 5, 21084}, {4, 23427, 4, 21084}, {3, 21692, 3, 19523}, {3, 21782, 3, 19604}, {3, 21602, 3, 19442}},
1171 /* 2 */ {2422, {5, 23379, 5, 21041}, {4, 23379, 4, 21041}, {3, 21647, 3, 19482}, {3, 21737, 3, 19563}, {3, 21558, 3, 19402}},
1172 /* 3 */ {2427, {5, 23330, 5, 20997}, {4, 23330, 4, 20997}, {3, 21602, 3, 19442}, {3, 21692, 3, 19523}, {3, 21514, 3, 19362}},
1173 /* 4 */ {2432, {5, 23283, 5, 20954}, {4, 23283, 4, 20954}, {3, 21558, 3, 19402}, {3, 21647, 3, 19482}, {3, 21470, 3, 19323}},
1174 /* 5 */ {2437, {5, 23235, 5, 20911}, {4, 23235, 4, 20911}, {3, 21514, 3, 19362}, {3, 21602, 3, 19442}, {3, 21426, 3, 19283}},
1175 /* 6 */ {2442, {5, 23187, 5, 20868}, {4, 23187, 4, 20868}, {3, 21470, 3, 19323}, {3, 21558, 3, 19402}, {3, 21382, 3, 19244}},
1176 /* 7 */ {2447, {5, 23140, 5, 20826}, {4, 23140, 4, 20826}, {3, 21426, 3, 19283}, {3, 21514, 3, 19362}, {3, 21339, 3, 19205}},
1177 /* 8 */ {2452, {5, 23093, 5, 20783}, {4, 23093, 4, 20783}, {3, 21382, 3, 19244}, {3, 21470, 3, 19323}, {3, 21295, 3, 19166}},
1178 /* 9 */ {2457, {5, 23046, 5, 20741}, {4, 23046, 4, 20741}, {3, 21339, 3, 19205}, {3, 21426, 3, 19283}, {3, 21252, 3, 19127}},
1179 /* 10 */ {2462, {5, 22999, 5, 20699}, {4, 22999, 4, 20699}, {3, 21295, 3, 19166}, {3, 21382, 3, 19244}, {3, 21209, 3, 19088}},
1180 /* 11 */ {2467, {5, 22952, 5, 20657}, {4, 22952, 4, 20657}, {3, 21252, 3, 19127}, {3, 21339, 3, 19205}, {3, 21166, 3, 19050}},
1181 /* 12 */ {2472, {5, 22906, 5, 20615}, {4, 22906, 4, 20615}, {3, 21209, 3, 19088}, {3, 21295, 3, 19166}, {3, 21124, 3, 19011}},
1182 /* 13 */ {2484, {5, 22795, 5, 20516}, {4, 22795, 4, 20516}, {3, 21107, 3, 18996}, {3, 21192, 3, 19073}, {3, 21022, 3, 18920}},
1183 /* 14 */ {4920, {6, 23018, 6, 20716}, {5, 23018, 5, 20716}, {4, 21313, 4, 19181}, {4, 21356, 4, 19220}, {4, 21269, 4, 19142}},
1184 /* 15 */ {4940, {6, 22924, 6, 20632}, {5, 22924, 5, 20632}, {4, 21226, 4, 19104}, {4, 21269, 4, 19142}, {4, 21183, 4, 19065}},
1185 /* 16 */ {4960, {6, 22832, 6, 20549}, {5, 22832, 5, 20549}, {4, 21141, 4, 19027}, {4, 21183, 4, 19065}, {4, 21098, 4, 18988}},
1186 /* 17 */ {4980, {6, 22740, 6, 20466}, {5, 22740, 5, 20466}, {4, 21056, 4, 18950}, {4, 21098, 4, 18988}, {4, 21014, 4, 18912}},
1187 /* 18 */ {5040, {6, 22469, 6, 20223}, {5, 22469, 5, 20223}, {4, 20805, 4, 18725}, {4, 20846, 4, 18762}, {4, 20764, 4, 18687}},
1188 /* 19 */ {5060, {6, 22381, 6, 20143}, {5, 22381, 5, 20143}, {4, 20723, 4, 18651}, {4, 20764, 4, 18687}, {4, 20682, 4, 18614}},
1189 /* 20 */ {5080, {6, 22293, 6, 20063}, {5, 22293, 5, 20063}, {4, 20641, 4, 18577}, {4, 20682, 4, 18614}, {4, 20601, 4, 18541}},
1190 /* 21 */ {5180, {6, 21862, 6, 19676}, {5, 21862, 5, 19676}, {4, 20243, 4, 18219}, {4, 20282, 4, 18254}, {4, 20204, 4, 18183}},
1191 /* 22 */ {5200, {6, 21778, 6, 19600}, {5, 21778, 5, 19600}, {4, 20165, 4, 18148}, {4, 20204, 4, 18183}, {4, 20126, 4, 18114}},
1192 /* 23 */ {5220, {6, 21695, 6, 19525}, {5, 21695, 5, 19525}, {4, 20088, 4, 18079}, {4, 20126, 4, 18114}, {4, 20049, 4, 18044}},
1193 /* 24 */ {5240, {6, 21612, 6, 19451}, {5, 21612, 5, 19451}, {4, 20011, 4, 18010}, {4, 20049, 4, 18044}, {4, 19973, 4, 17976}},
1194 /* 25 */ {5260, {6, 21530, 6, 19377}, {5, 21530, 5, 19377}, {4, 19935, 4, 17941}, {4, 19973, 4, 17976}, {4, 19897, 4, 17907}},
1195 /* 26 */ {5280, {6, 21448, 6, 19303}, {5, 21448, 5, 19303}, {4, 19859, 4, 17873}, {4, 19897, 4, 17907}, {4, 19822, 4, 17840}},
1196 /* 27 */ {5300, {6, 21367, 6, 19230}, {5, 21367, 5, 19230}, {4, 19784, 4, 17806}, {4, 19822, 4, 17840}, {4, 19747, 4, 17772}},
1197 /* 28 */ {5320, {6, 21287, 6, 19158}, {5, 21287, 5, 19158}, {4, 19710, 4, 17739}, {4, 19747, 4, 17772}, {4, 19673, 4, 17706}},
1198 /* 29 */ {5500, {6, 20590, 6, 18531}, {5, 20590, 5, 18531}, {4, 19065, 4, 17159}, {4, 19100, 4, 17190}, {4, 19030, 4, 17127}},
1199 /* 30 */ {5520, {6, 20516, 6, 18464}, {5, 20516, 5, 18464}, {4, 18996, 4, 17096}, {4, 19030, 4, 17127}, {4, 18962, 4, 17065}},
1200 /* 31 */ {5540, {6, 20442, 6, 18397}, {5, 20442, 5, 18397}, {4, 18927, 4, 17035}, {4, 18962, 4, 17065}, {4, 18893, 4, 17004}},
1201 /* 32 */ {5560, {6, 20368, 6, 18331}, {5, 20368, 5, 18331}, {4, 18859, 4, 16973}, {4, 18893, 4, 17004}, {4, 18825, 4, 16943}},
1202 /* 33 */ {5580, {6, 20295, 6, 18266}, {5, 20295, 5, 18266}, {4, 18792, 4, 16913}, {4, 18825, 4, 16943}, {4, 18758, 4, 16882}},
1203 /* 34 */ {5600, {6, 20223, 6, 18200}, {5, 20223, 5, 18200}, {4, 18725, 4, 16852}, {4, 18758, 4, 16882}, {4, 18691, 4, 16822}},
1204 /* 35 */ {5620, {6, 20151, 6, 18136}, {5, 20151, 5, 18136}, {4, 18658, 4, 16792}, {4, 18691, 4, 16822}, {4, 18625, 4, 16762}},
1205 /* 36 */ {5640, {6, 20079, 6, 18071}, {5, 20079, 5, 18071}, {4, 18592, 4, 16733}, {4, 18625, 4, 16762}, {4, 18559, 4, 16703}},
1206 /* 37 */ {5660, {6, 20008, 6, 18007}, {5, 20008, 5, 18007}, {4, 18526, 4, 16673}, {4, 18559, 4, 16703}, {4, 18493, 4, 16644}},
1207 /* 38 */ {5680, {6, 19938, 6, 17944}, {5, 19938, 5, 17944}, {4, 18461, 4, 16615}, {4, 18493, 4, 16644}, {4, 18428, 4, 16586}},
1208 /* 39 */ {5700, {6, 19868, 6, 17881}, {5, 19868, 5, 17881}, {4, 18396, 4, 16556}, {4, 18428, 4, 16586}, {4, 18364, 4, 16527}},
1209 /* 40 */ {5745, {6, 19712, 6, 17741}, {5, 19712, 5, 17741}, {4, 18252, 4, 16427}, {4, 18284, 4, 16455}, {4, 18220, 4, 16398}},
1210 /* 41 */ {5765, {6, 19644, 6, 17679}, {5, 19644, 5, 17679}, {4, 18189, 5, 32740}, {4, 18220, 4, 16398}, {4, 18157, 5, 32683}},
1211 /* 42 */ {5785, {6, 19576, 6, 17618}, {5, 19576, 5, 17618}, {4, 18126, 5, 32626}, {4, 18157, 5, 32683}, {4, 18094, 5, 32570}},
1212 /* 43 */ {5805, {6, 19508, 6, 17558}, {5, 19508, 5, 17558}, {4, 18063, 5, 32514}, {4, 18094, 5, 32570}, {4, 18032, 5, 32458}},
1213 /* 44 */ {5825, {6, 19441, 6, 17497}, {5, 19441, 5, 17497}, {4, 18001, 5, 32402}, {4, 18032, 5, 32458}, {4, 17970, 5, 32347}},
1214 /* 45 */ {5170, {6, 21904, 6, 19714}, {5, 21904, 5, 19714}, {4, 20282, 4, 18254}, {4, 20321, 4, 18289}, {4, 20243, 4, 18219}},
1215 /* 46 */ {5190, {6, 21820, 6, 19638}, {5, 21820, 5, 19638}, {4, 20204, 4, 18183}, {4, 20243, 4, 18219}, {4, 20165, 4, 18148}},
1216 /* 47 */ {5210, {6, 21736, 6, 19563}, {5, 21736, 5, 19563}, {4, 20126, 4, 18114}, {4, 20165, 4, 18148}, {4, 20088, 4, 18079}},
1217 /* 48 */ {5230, {6, 21653, 6, 19488}, {5, 21653, 5, 19488}, {4, 20049, 4, 18044}, {4, 20088, 4, 18079}, {4, 20011, 4, 18010}}
1218 };
1219 /* to reduce search time, please modify this define if you add or delete channel in table */
1220 #define First5GChannelIndex 14
1221
1222 void zfGetHwTurnOffdynParam(zdev_t* dev,
1223 u32_t frequency, u8_t bw40, u8_t extOffset,
1224 int* delta_slope_coeff_exp,
1225 int* delta_slope_coeff_man,
1226 int* delta_slope_coeff_exp_shgi,
1227 int* delta_slope_coeff_man_shgi)
1228 {
1229 /* Get param for turnoffdyn */
1230 u16_t i, arraySize;
1231
1232 //zmw_get_wlan_dev(dev);
1233
1234 arraySize = sizeof(zgPhyFreqCoeff)/sizeof(struct zsPhyFreqTable);
1235 if (frequency < 3000)
1236 {
1237 /* 2.4GHz Channel */
1238 for (i = 0; i < First5GChannelIndex; i++)
1239 {
1240 if (frequency == zgPhyFreqCoeff[i].frequency)
1241 break;
1242 }
1243
1244 if (i < First5GChannelIndex)
1245 {
1246 }
1247 else
1248 {
1249 zm_msg1_scan(ZM_LV_0, "Unsupported 2.4G frequency = ", frequency);
1250 return;
1251 }
1252 }
1253 else
1254 {
1255 /* 5GHz Channel */
1256 for (i = First5GChannelIndex; i < arraySize; i++)
1257 {
1258 if (frequency == zgPhyFreqCoeff[i].frequency)
1259 break;
1260 }
1261
1262 if (i < arraySize)
1263 {
1264 }
1265 else
1266 {
1267 zm_msg1_scan(ZM_LV_0, "Unsupported 5G frequency = ", frequency);
1268 return;
1269 }
1270 }
1271
1272 /* FPGA DYNAMIC_HT2040_EN fclk = 10.8 */
1273 /* FPGA STATIC_HT20_ fclk = 21.6 */
1274 /* Real Chip fclk = 40 */
1275 #if ZM_FPGA_PHY == 1
1276 //fclk = 10.8;
1277 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp;
1278 *delta_slope_coeff_man = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man;
1279 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp_shgi;
1280 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man_shgi;
1281 #else
1282 //fclk = 40;
1283 if (bw40)
1284 {
1285 /* ht2040 */
1286 if (extOffset == 1) {
1287 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp;
1288 *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man;
1289 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp_shgi;
1290 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man_shgi;
1291 }
1292 else {
1293 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp;
1294 *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man;
1295 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp_shgi;
1296 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man_shgi;
1297 }
1298 }
1299 else
1300 {
1301 /* static 20 */
1302 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp;
1303 *delta_slope_coeff_man = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man;
1304 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp_shgi;
1305 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man_shgi;
1306 }
1307 #endif
1308 }
1309
1310 /* Main routin frequency setting function */
1311 /* If 2.4G/5G switch, PHY need resetting BB and RF for band switch */
1312 /* Do the setting switch in zfSendFrequencyCmd() */
1313 void zfHpSetFrequencyEx(zdev_t* dev, u32_t frequency, u8_t bw40,
1314 u8_t extOffset, u8_t initRF)
1315 {
1316 u32_t cmd[9];
1317 u16_t ret;
1318 u8_t old_band;
1319 u8_t new_band;
1320 u32_t checkLoopCount;
1321 u32_t tmpValue;
1322
1323 int delta_slope_coeff_exp;
1324 int delta_slope_coeff_man;
1325 int delta_slope_coeff_exp_shgi;
1326 int delta_slope_coeff_man_shgi;
1327 struct zsHpPriv* hpPriv;
1328
1329 zmw_get_wlan_dev(dev);
1330 hpPriv = wd->hpPrivate;
1331
1332 zm_msg1_scan(ZM_LV_1, "Frequency = ", frequency);
1333 zm_msg1_scan(ZM_LV_1, "bw40 = ", bw40);
1334 zm_msg1_scan(ZM_LV_1, "extOffset = ", extOffset);
1335
1336 if ( hpPriv->coldResetNeedFreq )
1337 {
1338 hpPriv->coldResetNeedFreq = 0;
1339 initRF = 2;
1340 zm_debug_msg0("zfHpSetFrequencyEx: Do ColdReset ");
1341 }
1342 if ( hpPriv->isSiteSurvey == 2 )
1343 {
1344 /* wait time for AGC and noise calibration : not in sitesurvey and connected */
1345 checkLoopCount = 2000; /* 2000*100 = 200ms */
1346 }
1347 else
1348 {
1349 /* wait time for AGC and noise calibration : in sitesurvey */
1350 checkLoopCount = 1000; /* 1000*100 = 100ms */
1351 }
1352
1353 hpPriv->latestFrequency = frequency;
1354 hpPriv->latestBw40 = bw40;
1355 hpPriv->latestExtOffset = extOffset;
1356
1357 if ((hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_GENERAL) ||
1358 (hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK))
1359 {
1360 if ( frequency <= ZM_CH_G_14 )
1361 {
1362 /* workaround for 11g Ad Hoc beacon distribution */
1363 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 0x7f0007);
1364 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, 0x1c04901c);
1365 }
1366 }
1367
1368 /* AHB, DAC, ADC clock selection by static20/ht2040 */
1369 zfSelAdcClk(dev, bw40, frequency);
1370
1371 /* clear bb_heavy_clip_enable */
1372 reg_write(0x99e0, 0x200);
1373 zfFlushDelayWrite(dev);
1374
1375 /* Set CTS/RTS rate */
1376 if ( frequency > ZM_CH_G_14 )
1377 {
1378 //zfHpSetRTSCTSRate(dev, 0x10b010b); /* OFDM 6M */
1379 new_band = 1;
1380 }
1381 else
1382 {
1383 //zfHpSetRTSCTSRate(dev, 0x30003); /* CCK 11M */
1384 new_band = 0;
1385 }
1386
1387 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency > ZM_CH_G_14)
1388 old_band = 1;
1389 else
1390 old_band = 0;
1391
1392 //Workaround for 2.4GHz only device
1393 if ((hpPriv->OpFlags & 0x1) == 0)
1394 {
1395 if ((((struct zsHpPriv*)wd->hpPrivate)->hwFrequency == ZM_CH_G_1) && (frequency == ZM_CH_G_2))
1396 {
1397 /* Force to do band switching */
1398 old_band = 1;
1399 }
1400 }
1401
1402 /* Notify channel switch to firmware */
1403 /* TX/RX must be stopped by now */
1404 cmd[0] = 0 | (ZM_CMD_FREQ_STRAT << 8);
1405 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, 0);
1406
1407 if ((initRF != 0) || (new_band != old_band)
1408 || (((struct zsHpPriv*)wd->hpPrivate)->hwBw40 != bw40))
1409 {
1410 /* band switch */
1411 zm_msg0_scan(ZM_LV_1, "=====band switch=====");
1412
1413 if (initRF == 2 )
1414 {
1415 //Cold reset BB/ADDA
1416 zfDelayWriteInternalReg(dev, 0x1d4004, 0x800);
1417 zfFlushDelayWrite(dev);
1418 zm_msg0_scan(ZM_LV_1, "Do cold reset BB/ADDA");
1419 }
1420 else
1421 {
1422 //Warm reset BB/ADDA
1423 zfDelayWriteInternalReg(dev, 0x1d4004, 0x400);
1424 zfFlushDelayWrite(dev);
1425 }
1426
1427 /* reset workaround state to default */
1428 hpPriv->rxStrongRSSI = 0;
1429 hpPriv->strongRSSI = 0;
1430
1431 zfDelayWriteInternalReg(dev, 0x1d4004, 0x0);
1432 zfFlushDelayWrite(dev);
1433
1434 zfInitPhy(dev, frequency, bw40);
1435
1436 // zfiCheckRifs(dev);
1437
1438 /* Bank 0 1 2 3 5 6 7 */
1439 zfSetRfRegs(dev, frequency);
1440 /* Bank 4 */
1441 zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset);
1442
1443 cmd[0] = 32 | (ZM_CMD_RF_INIT << 8);
1444 }
1445 else //((new_band == old_band) && !initRF)
1446 {
1447 /* same band */
1448
1449 /* Force disable CR671 bit20 / 7823 */
1450 /* The bug has to do with the polarity of the pdadc offset calibration. There */
1451 /* is an initial calibration that is OK, and there is a continuous */
1452 /* calibration that updates the pddac with the wrong polarity. Fortunately */
1453 /* the second loop can be disabled with a bit called en_pd_dc_offset_thr. */
1454 #if 0
1455 cmdB[0] = 8 | (ZM_CMD_BITAND << 8);;
1456 cmdB[1] = (0xa27c + 0x1bc000);
1457 cmdB[2] = 0xffefffff;
1458 ret = zfIssueCmd(dev, cmdB, 12, ZM_OID_INTERNAL_WRITE, 0);
1459 #endif
1460
1461 /* Bank 4 */
1462 zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset);
1463
1464
1465 cmd[0] = 32 | (ZM_CMD_FREQUENCY << 8);
1466 }
1467
1468 /* Compatibility for new layout UB83 */
1469 /* Setting code at CR1 here move from the func:zfHwHTEnable() in firmware */
1470 if (((struct zsHpPriv*)wd->hpPrivate)->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
1471 {
1472 /* UB83 : one stream */
1473 tmpValue = 0;
1474 }
1475 else
1476 {
1477 /* UB81, UB82 : two stream */
1478 tmpValue = 0x100;
1479 }
1480
1481 if (1) //if (((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE == 1)
1482 {
1483 if (bw40 == 1)
1484 {
1485 if (extOffset == 1) {
1486 reg_write(0x9804, tmpValue | 0x2d4); //3d4 for real
1487 }
1488 else {
1489 reg_write(0x9804, tmpValue | 0x2c4); //3c4 for real
1490 }
1491 //# Dyn HT2040.Refer to Reg 1.
1492 //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX
1493 //#[c]:allow short GI for HT40 packets; enable HT detection.
1494 //#[4]:enable 20/40 MHz channel detection.
1495 }
1496 else
1497 {
1498 reg_write(0x9804, tmpValue | 0x240);
1499 //# Static HT20
1500 //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX
1501 //#[4]:Otus don't allow short GI for HT20 packets yet; enable HT detection.
1502 //#[0]:disable 20/40 MHz channel detection.
1503 }
1504 }
1505 else
1506 {
1507 reg_write(0x9804, 0x0);
1508 //# Legacy;# Direct Mapping for each chain.
1509 //#Be modified by Oligo to add dynanic for legacy.
1510 if (bw40 == 1)
1511 {
1512 reg_write(0x9804, 0x4); //# Dyn Legacy .Refer to reg 1.
1513 }
1514 else
1515 {
1516 reg_write(0x9804, 0x0); //# Static Legacy
1517 }
1518 }
1519 zfFlushDelayWrite(dev);
1520 /* end of ub83 compatibility */
1521
1522 /* Set Power, TPC, Gain table... */
1523 zfSetPowerCalTable(dev, frequency, bw40, extOffset);
1524
1525
1526 /* store frequency */
1527 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency;
1528 ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = bw40;
1529 ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = extOffset;
1530
1531 zfGetHwTurnOffdynParam(dev,
1532 frequency, bw40, extOffset,
1533 &delta_slope_coeff_exp,
1534 &delta_slope_coeff_man,
1535 &delta_slope_coeff_exp_shgi,
1536 &delta_slope_coeff_man_shgi);
1537
1538 /* related functions */
1539 frequency = frequency*1000;
1540 /* len[36] : type[0x30] : seq[?] */
1541 // cmd[0] = 28 | (ZM_CMD_FREQUENCY << 8);
1542 cmd[1] = frequency;
1543 cmd[2] = bw40;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN;
1544 cmd[3] = (extOffset<<2)|0x1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE);
1545 cmd[4] = delta_slope_coeff_exp;
1546 cmd[5] = delta_slope_coeff_man;
1547 cmd[6] = delta_slope_coeff_exp_shgi;
1548 cmd[7] = delta_slope_coeff_man_shgi;
1549 cmd[8] = checkLoopCount;
1550
1551 ret = zfIssueCmd(dev, cmd, 36, ZM_CMD_SET_FREQUENCY, 0);
1552
1553 // delay temporarily, wait for new PHY and RF
1554 //zfwSleep(dev, 1000);
1555 }
1556
1557
1558 /******************** Key ********************/
1559
1560 u16_t zfHpResetKeyCache(zdev_t* dev)
1561 {
1562 u8_t i;
1563 u32_t key[4] = {0, 0, 0, 0};
1564 struct zsHpPriv* hpPriv;
1565
1566 zmw_get_wlan_dev(dev);
1567 hpPriv=wd->hpPrivate;
1568
1569 for(i=0;i<4;i++)
1570 {
1571 zfHpSetDefaultKey(dev, i, ZM_WEP64, key, NULL);
1572 }
1573 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, 0x00);
1574 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, 0x00);
1575 zfFlushDelayWrite(dev);
1576
1577 hpPriv->camRollCallTable = (u64_t) 0;
1578
1579 return 0;
1580 }
1581
1582
1583 /************************************************************************/
1584 /* */
1585 /* FUNCTION DESCRIPTION zfSetKey */
1586 /* Set key. */
1587 /* */
1588 /* INPUTS */
1589 /* dev : device pointer */
1590 /* */
1591 /* OUTPUTS */
1592 /* 0 : success */
1593 /* other : fail */
1594 /* */
1595 /* AUTHOR */
1596 /* Stephen Chen ZyDAS Technology Corporation 2006.1 */
1597 /* */
1598 /************************************************************************/
1599 /* ! please use zfCoreSetKey() in 80211Core for SetKey */
1600 u32_t zfHpSetKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t type,
1601 u16_t* mac, u32_t* key)
1602 {
1603 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1604 u16_t ret;
1605 u16_t i;
1606 struct zsHpPriv* hpPriv;
1607
1608 zmw_get_wlan_dev(dev);
1609 hpPriv=wd->hpPrivate;
1610
1611 #if 0 /* remove to zfCoreSetKey() */
1612 zmw_declare_for_critical_section();
1613
1614 zmw_enter_critical_section(dev);
1615 wd->sta.flagKeyChanging++;
1616 zm_debug_msg1(" zfHpSetKey++++ ", wd->sta.flagKeyChanging);
1617 zmw_leave_critical_section(dev);
1618 #endif
1619
1620 cmd[0] = 0x0000281C;
1621 cmd[1] = ((u32_t)keyId<<16) + (u32_t)user;
1622 cmd[2] = ((u32_t)mac[0]<<16) + (u32_t)type;
1623 cmd[3] = ((u32_t)mac[2]<<16) + ((u32_t)mac[1]);
1624
1625 for (i=0; i<4; i++)
1626 {
1627 cmd[4+i] = key[i];
1628 }
1629
1630 if (user < 64)
1631 {
1632 hpPriv->camRollCallTable |= ((u64_t) 1) << user;
1633 }
1634
1635 //ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, NULL);
1636 ret = zfIssueCmd(dev, cmd, 32, ZM_CMD_SET_KEY, NULL);
1637 return ret;
1638 }
1639
1640
1641 u32_t zfHpSetApPairwiseKey(zdev_t* dev, u16_t* staMacAddr, u8_t type,
1642 u32_t* key, u32_t* micKey, u16_t staAid)
1643 {
1644 if ((staAid!=0) && (staAid<64))
1645 {
1646 zfHpSetKey(dev, (staAid-1), 0, type, staMacAddr, key);
1647 if ((type == ZM_TKIP)
1648 #ifdef ZM_ENABLE_CENC
1649 || (type == ZM_CENC)
1650 #endif //ZM_ENABLE_CENC
1651 )
1652 zfHpSetKey(dev, (staAid-1), 1, type, staMacAddr, micKey);
1653 return 0;
1654 }
1655 return 1;
1656 }
1657
1658 u32_t zfHpSetApGroupKey(zdev_t* dev, u16_t* apMacAddr, u8_t type,
1659 u32_t* key, u32_t* micKey, u16_t vapId)
1660 {
1661 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 0, type, apMacAddr, key); // 6D18 modify from 0 to 1 ??
1662 if ((type == ZM_TKIP)
1663 #ifdef ZM_ENABLE_CENC
1664 || (type == ZM_CENC)
1665 #endif //ZM_ENABLE_CENC
1666 )
1667 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 1, type, apMacAddr, micKey);
1668 return 0;
1669 }
1670
1671 u32_t zfHpSetDefaultKey(zdev_t* dev, u8_t keyId, u8_t type, u32_t* key, u32_t* micKey)
1672 {
1673 u16_t macAddr[3] = {0, 0, 0};
1674
1675 #ifdef ZM_ENABLE_IBSS_WPA2PSK
1676 struct zsHpPriv* hpPriv;
1677
1678 zmw_get_wlan_dev(dev);
1679 hpPriv = wd->hpPrivate;
1680
1681 if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK )
1682 { /* If not wpa2psk , use traditional */
1683 /* Because the bug of chip , defaultkey should follow the key map rule in register 700 */
1684 if ( keyId == 0 )
1685 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1686 else
1687 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, key);
1688 }
1689 else
1690 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1691 #else
1692 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1693 #endif
1694 if ((type == ZM_TKIP)
1695
1696 #ifdef ZM_ENABLE_CENC
1697 || (type == ZM_CENC)
1698 #endif //ZM_ENABLE_CENC
1699 )
1700 {
1701 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, micKey);
1702 }
1703
1704 return 0;
1705 }
1706
1707 u32_t zfHpSetPerUserKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t* mac, u8_t type, u32_t* key, u32_t* micKey)
1708 {
1709 #ifdef ZM_ENABLE_IBSS_WPA2PSK
1710 struct zsHpPriv* hpPriv;
1711
1712 zmw_get_wlan_dev(dev);
1713 hpPriv = wd->hpPrivate;
1714
1715 if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK )
1716 { /* If not wpa2psk , use traditional */
1717 if(keyId)
1718 { /* Set Group Key */
1719 zfHpSetKey(dev, user, 1, type, (u16_t *)mac, key);
1720 }
1721 else if(keyId == 0)
1722 { /* Set Pairwise Key */
1723 zfHpSetKey(dev, user, 0, type, (u16_t *)mac, key);
1724 }
1725 }
1726 else
1727 {
1728 zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key);
1729 }
1730 #else
1731 zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key);
1732 #endif
1733
1734 if ((type == ZM_TKIP)
1735 #ifdef ZM_ENABLE_CENC
1736 || (type == ZM_CENC)
1737 #endif //ZM_ENABLE_CENC
1738 )
1739 {
1740 zfHpSetKey(dev, user, keyId + 1, type, (u16_t *)mac, micKey);
1741 }
1742 return 0;
1743 }
1744
1745 /************************************************************************/
1746 /* */
1747 /* FUNCTION DESCRIPTION zfHpRemoveKey */
1748 /* Remove key. */
1749 /* */
1750 /* INPUTS */
1751 /* dev : device pointer */
1752 /* */
1753 /* OUTPUTS */
1754 /* 0 : success */
1755 /* other : fail */
1756 /* */
1757 /* AUTHOR */
1758 /* Yuan-Gu Wei ZyDAS Technology Corporation 2006.6 */
1759 /* */
1760 /************************************************************************/
1761 u16_t zfHpRemoveKey(zdev_t* dev, u16_t user)
1762 {
1763 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1764 u16_t ret = 0;
1765
1766 cmd[0] = 0x00002904;
1767 cmd[1] = (u32_t)user;
1768
1769 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
1770 return ret;
1771 }
1772
1773
1774
1775 /******************** DMA ********************/
1776 u16_t zfHpStartRecv(zdev_t* dev)
1777 {
1778 zfDelayWriteInternalReg(dev, 0x1c3d30, 0x100);
1779 zfFlushDelayWrite(dev);
1780
1781 return 0;
1782 }
1783
1784 u16_t zfHpStopRecv(zdev_t* dev)
1785 {
1786 return 0;
1787 }
1788
1789
1790 /******************** MAC ********************/
1791 void zfInitMac(zdev_t* dev)
1792 {
1793 /* ACK extension register */
1794 // jhlee temp : change value 0x2c -> 0x40
1795 // honda resolve short preamble problem : 0x40 -> 0x75
1796 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_EXTENSION, 0x40); // 0x28 -> 0x2c 6522:yflee
1797
1798 /* TxQ0/1/2/3 Retry MAX=2 => transmit 3 times and degrade rate for retry */
1799 /* PB42 AP crash issue: */
1800 /* Workaround the crash issue by CTS/RTS, set retry max to zero for */
1801 /* workaround tx underrun which enable CTS/RTS */
1802 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RETRY_MAX, 0); // 0x11111 => 0
1803
1804 /* use hardware MIC check */
1805 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000);
1806
1807 /* Set Rx threshold to 1600 */
1808 #if ZM_LARGEPAYLOAD_TEST == 1
1809 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc4000);
1810 #else
1811 #ifndef ZM_DISABLE_AMSDU8K_SUPPORT
1812 /* The maximum A-MSDU length is 3839/7935 */
1813 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc1f80);
1814 #else
1815 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc0f80);
1816 #endif
1817 #endif
1818
1819 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A);
1820 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_PE_DELAY, 0x70);
1821 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
1822 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10);
1823
1824 /* CF-END mode */
1825 zfDelayWriteInternalReg(dev, 0x1c3b2c, 0x19000000);
1826
1827 //NAV protects ACK only (in TXOP)
1828 zfDelayWriteInternalReg(dev, 0x1c3b38, 0x201);
1829
1830
1831 /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
1832 /* OTUS set AM to 0x1 */
1833 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_HT1, 0x8000170);
1834
1835 /* TODO : wep backoff protection 0x63c */
1836 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BACKOFF_PROTECT, 0x105);
1837
1838 /* AGG test code*/
1839 /* Aggregation MAX number and timeout */
1840 zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x10000a);
1841 /* Filter any control frames, BAR is bit 24 */
1842 zfDelayWriteInternalReg(dev, 0x1c368c, 0x0500ffff);
1843 /* Enable deaggregator */
1844 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1845
1846 /* Basic rate */
1847 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, 0x150f);
1848 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MANDATORY_RATE, 0x150f);
1849 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, 0x10b01bb);
1850
1851 /* MIMO resposne control */
1852 zfDelayWriteInternalReg(dev, 0x1c3694, 0x4003C1E);/* bit 26~28 otus-AM */
1853
1854 /* Enable LED0 and LED1 */
1855 zfDelayWriteInternalReg(dev, 0x1d0100, 0x3);
1856 zfDelayWriteInternalReg(dev, 0x1d0104, 0x3);
1857
1858 /* switch MAC to OTUS interface */
1859 zfDelayWriteInternalReg(dev, 0x1c3600, 0x3);
1860
1861 /* RXMAC A-MPDU length threshold */
1862 zfDelayWriteInternalReg(dev, 0x1c3c50, 0xffff);
1863
1864 /* Phy register read timeout */
1865 zfDelayWriteInternalReg(dev, 0x1c3680, 0xf00008);
1866
1867 /* Disable Rx TimeOut : workaround for BB.
1868 * OTUS would interrupt the rx frame that sent by OWL TxUnderRun
1869 * because OTUS rx timeout behavior, then OTUS would not ack the BA for
1870 * this AMPDU from OWL.
1871 * Fix by Perry Hwang. 2007/05/10.
1872 * 0x1c362c : Rx timeout value : bit 27~16
1873 */
1874 zfDelayWriteInternalReg(dev, 0x1c362c, 0x0);
1875
1876 //Set USB Rx stream mode MAX packet number to 2
1877 // Max packet number = *0x1e1110 + 1
1878 zfDelayWriteInternalReg(dev, 0x1e1110, 0x4);
1879 //Set USB Rx stream mode timeout to 10us
1880 zfDelayWriteInternalReg(dev, 0x1e1114, 0x80);
1881
1882 //Set CPU clock frequency to 88/80MHz
1883 zfDelayWriteInternalReg(dev, 0x1D4008, 0x73);
1884
1885 //Set WLAN DMA interrupt mode : generate int per packet
1886 zfDelayWriteInternalReg(dev, 0x1c3d7c, 0x110011);
1887
1888 /* 7807 */
1889 /* enable func : Reset FIFO1 and FIFO2 when queue-gnt is low */
1890 /* 0x1c3bb0 Bit2 */
1891 /* Disable SwReset in firmware for TxHang, enable reset FIFO func. */
1892 zfDelayWriteInternalReg(dev, 0x1c3bb0, 0x4);
1893
1894 /* Disables the CF_END frame */
1895 zfDelayWriteInternalReg(dev, ZM_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141E0F48);
1896
1897 /* Disable the SW Decrypt*/
1898 zfDelayWriteInternalReg(dev, 0x1c3678, 0x70);
1899 zfFlushDelayWrite(dev);
1900 //---------------------
1901
1902 /* Set TxQs CWMIN, CWMAX, AIFS and TXO to WME STA default. */
1903 zfUpdateDefaultQosParameter(dev, 0);
1904
1905 //zfSelAdcClk(dev, 0);
1906
1907 return;
1908 }
1909
1910
1911 u16_t zfHpSetSnifferMode(zdev_t* dev, u16_t on)
1912 {
1913 if (on != 0)
1914 {
1915 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000001);
1916 }
1917 else
1918 {
1919 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000);
1920 }
1921 zfFlushDelayWrite(dev);
1922 return 0;
1923 }
1924
1925
1926 u16_t zfHpSetApStaMode(zdev_t* dev, u8_t mode)
1927 {
1928 struct zsHpPriv* hpPriv;
1929
1930 zmw_get_wlan_dev(dev);
1931 hpPriv = wd->hpPrivate;
1932 hpPriv->dot11Mode = mode;
1933
1934 switch(mode)
1935 {
1936 case ZM_HAL_80211_MODE_AP:
1937 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000a1);
1938 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1939 break;
1940
1941 case ZM_HAL_80211_MODE_STA:
1942 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000002);
1943 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1944 break;
1945
1946 case ZM_HAL_80211_MODE_IBSS_GENERAL:
1947 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000000);
1948 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1949 break;
1950
1951 case ZM_HAL_80211_MODE_IBSS_WPA2PSK:
1952 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000e0);
1953 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x41); // for multiple ( > 2 ) stations IBSS network
1954 break;
1955
1956 default:
1957 goto skip;
1958 }
1959
1960 zfFlushDelayWrite(dev);
1961
1962 skip:
1963 return 0;
1964 }
1965
1966
1967 u16_t zfHpSetBssid(zdev_t* dev, u8_t* bssidSrc)
1968 {
1969 u32_t address;
1970 u16_t *bssid = (u16_t *)bssidSrc;
1971
1972 address = bssid[0] + (((u32_t)bssid[1]) << 16);
1973 zfDelayWriteInternalReg(dev, 0x1c3618, address);
1974
1975 address = (u32_t)bssid[2];
1976 zfDelayWriteInternalReg(dev, 0x1c361C, address);
1977 zfFlushDelayWrite(dev);
1978 return 0;
1979 }
1980
1981
1982 /************************************************************************/
1983 /* */
1984 /* FUNCTION DESCRIPTION zfHpUpdateQosParameter */
1985 /* Update TxQs CWMIN, CWMAX, AIFS and TXOP. */
1986 /* */
1987 /* INPUTS */
1988 /* dev : device pointer */
1989 /* cwminTbl : CWMIN parameter for TxQs */
1990 /* cwmaxTbl : CWMAX parameter for TxQs */
1991 /* aifsTbl: AIFS parameter for TxQs */
1992 /* txopTbl : TXOP parameter for TxQs */
1993 /* */
1994 /* OUTPUTS */
1995 /* none */
1996 /* */
1997 /* AUTHOR */
1998 /* Stephen ZyDAS Technology Corporation 2006.6 */
1999 /* */
2000 /************************************************************************/
2001 u8_t zfHpUpdateQosParameter(zdev_t* dev, u16_t* cwminTbl, u16_t* cwmaxTbl,
2002 u16_t* aifsTbl, u16_t* txopTbl)
2003 {
2004 struct zsHpPriv* hpPriv;
2005
2006 zmw_get_wlan_dev(dev);
2007 hpPriv = wd->hpPrivate;
2008
2009 zm_msg0_mm(ZM_LV_0, "zfHalUpdateQosParameter()");
2010
2011 /* Note : Do not change cwmin for Q0 in Ad Hoc mode */
2012 /* otherwise driver will fail in Wifi beacon distribution */
2013 if (hpPriv->dot11Mode == ZM_HAL_80211_MODE_STA)
2014 {
2015 #if 0 //Restore CWmin to improve down link throughput
2016 //cheating in BE traffic
2017 if (wd->sta.EnableHT == 1)
2018 {
2019 //cheating in BE traffic
2020 cwminTbl[0] = 7;//15;
2021 }
2022 #endif
2023 cwmaxTbl[0] = 127;//1023;
2024 aifsTbl[0] = 2*9+10;//3 * 9 + 10;
2025 }
2026
2027 /* CWMIN and CWMAX */
2028 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, cwminTbl[0]
2029 + ((u32_t)cwmaxTbl[0]<<16));
2030 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_CW, cwminTbl[1]
2031 + ((u32_t)cwmaxTbl[1]<<16));
2032 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC2_CW, cwminTbl[2]
2033 + ((u32_t)cwmaxTbl[2]<<16));
2034 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_CW, cwminTbl[3]
2035 + ((u32_t)cwmaxTbl[3]<<16));
2036 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC4_CW, cwminTbl[4]
2037 + ((u32_t)cwmaxTbl[4]<<16));
2038
2039 /* AIFS */
2040 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, aifsTbl[0]
2041 +((u32_t)aifsTbl[0]<<12)+((u32_t)aifsTbl[0]<<24));
2042 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_AIFS, (aifsTbl[0]>>8)
2043 +((u32_t)aifsTbl[0]<<4)+((u32_t)aifsTbl[0]<<16));
2044
2045 /* TXOP */
2046 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, txopTbl[0]
2047 + ((u32_t)txopTbl[1]<<16));
2048 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_TXOP, txopTbl[2]
2049 + ((u32_t)txopTbl[3]<<16));
2050
2051 zfFlushDelayWrite(dev);
2052
2053 hpPriv->txop[0] = txopTbl[0];
2054 hpPriv->txop[1] = txopTbl[1];
2055 hpPriv->txop[2] = txopTbl[2];
2056 hpPriv->txop[3] = txopTbl[3];
2057 hpPriv->cwmin[0] = cwminTbl[0];
2058 hpPriv->cwmax[0] = cwmaxTbl[0];
2059 hpPriv->cwmin[1] = cwminTbl[1];
2060 hpPriv->cwmax[1] = cwmaxTbl[1];
2061
2062 return 0;
2063 }
2064
2065
2066 void zfHpSetAtimWindow(zdev_t* dev, u16_t atimWin)
2067 {
2068 zm_msg1_mm(ZM_LV_0, "Set ATIM window to ", atimWin);
2069 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ATIM_WINDOW, atimWin);
2070 zfFlushDelayWrite(dev);
2071 }
2072
2073
2074 void zfHpSetBasicRateSet(zdev_t* dev, u16_t bRateBasic, u16_t gRateBasic)
2075 {
2076 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, bRateBasic
2077 | ((u16_t)gRateBasic<<8));
2078 zfFlushDelayWrite(dev);
2079 }
2080
2081
2082 /* HT40 send by OFDM 6M */
2083 /* otherwise use reg 0x638 */
2084 void zfHpSetRTSCTSRate(zdev_t* dev, u32_t rate)
2085 {
2086 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, rate);
2087 zfFlushDelayWrite(dev);
2088 }
2089
2090 void zfHpSetMacAddress(zdev_t* dev, u16_t* macAddr, u16_t macAddrId)
2091 {
2092 if (macAddrId == 0)
2093 {
2094 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_L,
2095 (((u32_t)macAddr[1])<<16) | macAddr[0]);
2096 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_H, macAddr[2]);
2097 }
2098 else if (macAddrId <= 7)
2099 {
2100 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8),
2101 macAddr[0] + ((u32_t)macAddr[1]<<16));
2102 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8)+4,
2103 macAddr[2]);
2104 }
2105 zfFlushDelayWrite(dev);
2106 }
2107
2108 void zfHpSetMulticastList(zdev_t* dev, u8_t size, u8_t* pList, u8_t bAllMulticast)
2109 {
2110 struct zsMulticastAddr* pMacList = (struct zsMulticastAddr*) pList;
2111 u8_t i;
2112 u32_t value;
2113 u32_t swRegMulHashValueH, swRegMulHashValueL;
2114
2115 swRegMulHashValueH = 0x80000000;
2116 swRegMulHashValueL = 0;
2117
2118 if ( bAllMulticast )
2119 {
2120 swRegMulHashValueH = swRegMulHashValueL = ~0;
2121 }
2122 else
2123 {
2124 for(i=0; i<size; i++)
2125 {
2126 value = pMacList[i].addr[5] >> 2;
2127
2128 if ( value < 32 )
2129 {
2130 swRegMulHashValueL |= (1 << value);
2131 }
2132 else
2133 {
2134 swRegMulHashValueH |= (1 << (value-32));
2135 }
2136 }
2137 }
2138
2139 zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_L,
2140 swRegMulHashValueL);
2141 zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_H,
2142 swRegMulHashValueH);
2143 zfFlushDelayWrite(dev);
2144 return;
2145 }
2146
2147 /******************** Beacon ********************/
2148 void zfHpEnableBeacon(zdev_t* dev, u16_t mode, u16_t bcnInterval, u16_t dtim, u8_t enableAtim)
2149 {
2150 u32_t value;
2151
2152 zmw_get_wlan_dev(dev);
2153
2154 /* Beacon Ready */
2155 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_CTRL, 0);
2156 /* Beacon DMA buffer address */
2157 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS);
2158
2159 value = bcnInterval;
2160
2161 value |= (((u32_t) dtim) << 16);
2162
2163 if (mode == ZM_MODE_AP)
2164 {
2165
2166 value |= 0x1000000;
2167 }
2168 else if (mode == ZM_MODE_IBSS)
2169 {
2170 value |= 0x2000000;
2171
2172 if ( enableAtim )
2173 {
2174 value |= 0x4000000;
2175 }
2176 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 1;
2177 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnInterval = value;
2178 }
2179 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16);
2180
2181 /* Beacon period and beacon enable */
2182 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, value);
2183 zfFlushDelayWrite(dev);
2184 }
2185
2186 void zfHpDisableBeacon(zdev_t* dev)
2187 {
2188 zmw_get_wlan_dev(dev);
2189
2190 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 0;
2191
2192 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0);
2193 zfFlushDelayWrite(dev);
2194 }
2195
2196 void zfHpLedCtrl(zdev_t* dev, u16_t ledId, u8_t mode)
2197 {
2198 u16_t state;
2199 zmw_get_wlan_dev(dev);
2200
2201 //zm_debug_msg1("LED ID=", ledId);
2202 //zm_debug_msg1("LED mode=", mode);
2203 if (ledId < 2)
2204 {
2205 if (((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] != mode)
2206 {
2207 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] = mode;
2208
2209 state = ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0]
2210 | (((struct zsHpPriv*)wd->hpPrivate)->ledMode[1]<<1);
2211 zfDelayWriteInternalReg(dev, 0x1d0104, state);
2212 zfFlushDelayWrite(dev);
2213 //zm_debug_msg0("Update LED");
2214 }
2215 }
2216 }
2217
2218 /************************************************************************/
2219 /* */
2220 /* FUNCTION DESCRIPTION zfHpResetTxRx */
2221 /* Reset Tx and Rx Desc. */
2222 /* */
2223 /* INPUTS */
2224 /* dev : device pointer */
2225 /* */
2226 /* OUTPUTS */
2227 /* 0 : success */
2228 /* other : fail */
2229 /* */
2230 /* AUTHOR */
2231 /* Chao-Wen Yang ZyDAS Technology Corporation 2007.3 */
2232 /* */
2233 /************************************************************************/
2234 u16_t zfHpUsbReset(zdev_t* dev)
2235 {
2236 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
2237 u16_t ret = 0;
2238
2239 //zm_debug_msg0("CWY - Reset Tx and Rx");
2240
2241 cmd[0] = 0 | (ZM_CMD_RESET << 8);
2242
2243 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_INTERNAL_WRITE, NULL);
2244 return ret;
2245 }
2246
2247 u16_t zfHpDKReset(zdev_t* dev, u8_t flag)
2248 {
2249 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
2250 u16_t ret = 0;
2251
2252 //zm_debug_msg0("CWY - Reset Tx and Rx");
2253
2254 cmd[0] = 4 | (ZM_CMD_DKRESET << 8);
2255 cmd[1] = flag;
2256
2257 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
2258 return ret;
2259 }
2260
2261 u32_t zfHpCwmUpdate(zdev_t* dev)
2262 {
2263 //u32_t cmd[3];
2264 //u16_t ret;
2265 //
2266 //cmd[0] = 0x00000008;
2267 //cmd[1] = 0x1c36e8;
2268 //cmd[2] = 0x1c36ec;
2269 //
2270 //ret = zfIssueCmd(dev, cmd, 12, ZM_CWM_READ, 0);
2271 //return ret;
2272
2273 struct zsHpPriv* hpPriv;
2274
2275 zmw_get_wlan_dev(dev);
2276 hpPriv=wd->hpPrivate;
2277
2278 zfCoreCwmBusy(dev, zfCwmIsExtChanBusy(hpPriv->ctlBusy, hpPriv->extBusy));
2279
2280 hpPriv->ctlBusy = 0;
2281 hpPriv->extBusy = 0;
2282
2283 return 0;
2284 }
2285
2286 u32_t zfHpAniUpdate(zdev_t* dev)
2287 {
2288 u32_t cmd[5];
2289 u16_t ret;
2290
2291 cmd[0] = 0x00000010;
2292 cmd[1] = 0x1c36e8;
2293 cmd[2] = 0x1c36ec;
2294 cmd[3] = 0x1c3cb4;
2295 cmd[4] = 0x1c3cb8;
2296
2297 ret = zfIssueCmd(dev, cmd, 20, ZM_ANI_READ, 0);
2298 return ret;
2299 }
2300
2301 /*
2302 * Update Beacon RSSI in ANI
2303 */
2304 u32_t zfHpAniUpdateRssi(zdev_t* dev, u8_t rssi)
2305 {
2306 struct zsHpPriv* hpPriv;
2307
2308 zmw_get_wlan_dev(dev);
2309 hpPriv=wd->hpPrivate;
2310
2311 hpPriv->stats.ast_nodestats.ns_avgbrssi = rssi;
2312
2313 return 0;
2314 }
2315
2316 #define ZM_SEEPROM_MAC_ADDRESS_OFFSET (0x1400 + (0x106<<1))
2317 #define ZM_SEEPROM_REGDOMAIN_OFFSET (0x1400 + (0x104<<1))
2318 #define ZM_SEEPROM_VERISON_OFFSET (0x1400 + (0x102<<1))
2319 #define ZM_SEEPROM_HARDWARE_TYPE_OFFSET (0x1374)
2320 #define ZM_SEEPROM_HW_HEAVY_CLIP (0x161c)
2321
2322 u32_t zfHpGetMacAddress(zdev_t* dev)
2323 {
2324 u32_t cmd[7];
2325 u16_t ret;
2326
2327 cmd[0] = 0x00000000 | 24;
2328 cmd[1] = ZM_SEEPROM_MAC_ADDRESS_OFFSET;
2329 cmd[2] = ZM_SEEPROM_MAC_ADDRESS_OFFSET+4;
2330 cmd[3] = ZM_SEEPROM_REGDOMAIN_OFFSET;
2331 cmd[4] = ZM_SEEPROM_VERISON_OFFSET;
2332 cmd[5] = ZM_SEEPROM_HARDWARE_TYPE_OFFSET;
2333 cmd[6] = ZM_SEEPROM_HW_HEAVY_CLIP;
2334
2335 ret = zfIssueCmd(dev, cmd, 28, ZM_MAC_READ, 0);
2336 return ret;
2337 }
2338
2339 u32_t zfHpGetTransmitPower(zdev_t* dev)
2340 {
2341 struct zsHpPriv* hpPriv;
2342 u16_t tpc = 0;
2343
2344 zmw_get_wlan_dev(dev);
2345 hpPriv = wd->hpPrivate;
2346
2347 if (hpPriv->hwFrequency < 3000) {
2348 tpc = hpPriv->tPow2x2g[0] & 0x3f;
2349 wd->maxTxPower2 &= 0x3f;
2350 tpc = (tpc > wd->maxTxPower2)? wd->maxTxPower2 : tpc;
2351 } else {
2352 tpc = hpPriv->tPow2x5g[0] & 0x3f;
2353 wd->maxTxPower5 &= 0x3f;
2354 tpc = (tpc > wd->maxTxPower5)? wd->maxTxPower5 : tpc;
2355 }
2356
2357 return tpc;
2358 }
2359
2360 u8_t zfHpGetMinTxPower(zdev_t* dev)
2361 {
2362 struct zsHpPriv* hpPriv;
2363 u8_t tpc = 0;
2364
2365 zmw_get_wlan_dev(dev);
2366 hpPriv = wd->hpPrivate;
2367
2368 if (hpPriv->hwFrequency < 3000)
2369 {
2370 if(wd->BandWidth40)
2371 {
2372 //40M
2373 tpc = (hpPriv->tPow2x2gHt40[7]&0x3f);
2374 }
2375 else
2376 {
2377 //20M
2378 tpc = (hpPriv->tPow2x2gHt20[7]&0x3f);
2379 }
2380 }
2381 else
2382 {
2383 if(wd->BandWidth40)
2384 {
2385 //40M
2386 tpc = (hpPriv->tPow2x5gHt40[7]&0x3f);
2387 }
2388 else
2389 {
2390 //20M
2391 tpc = (hpPriv->tPow2x5gHt20[7]&0x3f);
2392 }
2393 }
2394
2395 return tpc;
2396 }
2397
2398 u8_t zfHpGetMaxTxPower(zdev_t* dev)
2399 {
2400 struct zsHpPriv* hpPriv;
2401 u8_t tpc = 0;
2402
2403 zmw_get_wlan_dev(dev);
2404 hpPriv = wd->hpPrivate;
2405
2406 if (hpPriv->hwFrequency < 3000)
2407 {
2408 tpc = (hpPriv->tPow2xCck[0]&0x3f);
2409 }
2410 else
2411 {
2412 tpc =(hpPriv->tPow2x5g[0]&0x3f);
2413 }
2414
2415 return tpc;
2416 }
2417
2418 u32_t zfHpLoadEEPROMFromFW(zdev_t* dev)
2419 {
2420 u32_t cmd[16];
2421 u32_t ret=0, i, j;
2422 zmw_get_wlan_dev(dev);
2423
2424 i = ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq;
2425
2426 cmd[0] = ZM_HAL_MAX_EEPROM_PRQ*4;
2427
2428 for (j=0; j<ZM_HAL_MAX_EEPROM_PRQ; j++)
2429 {
2430 cmd[j+1] = 0x1000 + (((i*ZM_HAL_MAX_EEPROM_PRQ) + j)*4);
2431 }
2432
2433 ret = zfIssueCmd(dev, cmd, (ZM_HAL_MAX_EEPROM_PRQ+1)*4, ZM_EEPROM_READ, 0);
2434
2435 return ret;
2436 }
2437
2438 void zfHpHeartBeat(zdev_t* dev)
2439 {
2440 struct zsHpPriv* hpPriv;
2441 u8_t polluted = 0;
2442 u8_t ackTpc;
2443
2444 zmw_get_wlan_dev(dev);
2445 hpPriv=wd->hpPrivate;
2446
2447 /* Workaround : Make OTUS fire more beacon in ad hoc mode in 2.4GHz */
2448 if (hpPriv->ibssBcnEnabled != 0)
2449 {
2450 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2451 {
2452 if ((wd->tick % 10) == 0)
2453 {
2454 if ((wd->tick % 40) == 0)
2455 {
2456 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval-1);
2457 polluted = 1;
2458 }
2459 else
2460 {
2461 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval);
2462 polluted = 1;
2463 }
2464 }
2465 }
2466 }
2467
2468 if ((wd->tick & 0x3f) == 0x25)
2469 {
2470 /* Workaround for beacon stuck after SW reset */
2471 if (hpPriv->ibssBcnEnabled != 0)
2472 {
2473 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS);
2474 polluted = 1;
2475 }
2476
2477 //DbgPrint("hpPriv->aggMaxDurationBE=%d", hpPriv->aggMaxDurationBE);
2478 //DbgPrint("wd->sta.avgSizeOfReceivePackets=%d", wd->sta.avgSizeOfReceivePackets);
2479 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2480 && (zfStaIsConnected(dev))
2481 && (wd->sta.EnableHT == 1) //11n mode
2482 && (wd->BandWidth40 == 1) //40MHz mode
2483 && (wd->sta.enableDrvBA ==0) //Marvel AP
2484 && (hpPriv->aggMaxDurationBE > 2000) //BE TXOP > 2ms
2485 && (wd->sta.avgSizeOfReceivePackets > 1420))
2486 {
2487 zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x8000a);
2488 polluted = 1;
2489 }
2490 else
2491 {
2492 zfDelayWriteInternalReg(dev, 0x1c3b9c, hpPriv->aggPktNum);
2493 polluted = 1;
2494 }
2495
2496 if (wd->dynamicSIFSEnable == 0)
2497 {
2498 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2499 && (zfStaIsConnected(dev))
2500 && (wd->sta.EnableHT == 1) //11n mode
2501 && (wd->BandWidth40 == 0) //20MHz mode
2502 && (wd->sta.enableDrvBA ==0)) //Marvel AP
2503 {
2504 zfDelayWriteInternalReg(dev, 0x1c3698, 0x5144000);
2505 polluted = 1;
2506 }
2507 else
2508 {
2509 zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000);
2510 polluted = 1;
2511 }
2512 }
2513 else
2514 {
2515 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2516 && (zfStaIsConnected(dev))
2517 && (wd->sta.EnableHT == 1) //11n mode
2518 && (wd->sta.athOwlAp == 1)) //Atheros AP
2519 {
2520 if (hpPriv->retransmissionEvent)
2521 {
2522 switch(hpPriv->latestSIFS)
2523 {
2524 case 0:
2525 hpPriv->latestSIFS = 1;
2526 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0x8144000);
2527 break;
2528 case 1:
2529 hpPriv->latestSIFS = 2;
2530 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2531 break;
2532 case 2:
2533 hpPriv->latestSIFS = 3;
2534 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xc144000);
2535 break;
2536 case 3:
2537 hpPriv->latestSIFS = 0;
2538 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2539 break;
2540 default:
2541 hpPriv->latestSIFS = 0;
2542 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2543 break;
2544 }
2545 polluted = 1;
2546 zm_debug_msg1("##### Correct Tx retransmission issue #####, ", hpPriv->latestSIFS);
2547 hpPriv->retransmissionEvent = 0;
2548 }
2549 }
2550 else
2551 {
2552 hpPriv->latestSIFS = 0;
2553 hpPriv->retransmissionEvent = 0;
2554 zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000);
2555 polluted = 1;
2556 }
2557 }
2558
2559 if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE))
2560 {
2561 #define ZM_SIGNAL_THRESHOLD 66
2562 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2563 && (zfStaIsConnected(dev))
2564 && (wd->SignalStrength > ZM_SIGNAL_THRESHOLD))
2565 {
2566 /* remove state handle, always rewrite register setting */
2567 //if (hpPriv->strongRSSI == 0)
2568 {
2569 hpPriv->strongRSSI = 1;
2570 /* Strong RSSI, set ACK to one Tx stream and lower Tx power 7dbm */
2571 if (hpPriv->currentAckRtsTpc > (14+10))
2572 {
2573 ackTpc = hpPriv->currentAckRtsTpc - 14;
2574 }
2575 else
2576 {
2577 ackTpc = 10;
2578 }
2579 zfDelayWriteInternalReg(dev, 0x1c3694, ((ackTpc) << 20) | (0x1<<26));
2580 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((ackTpc) << 5 ) | (0x1<<11) |
2581 ((ackTpc) << 21) | (0x1<<27) );
2582 polluted = 1;
2583 }
2584 }
2585 else
2586 {
2587 /* remove state handle, always rewrite register setting */
2588 //if (hpPriv->strongRSSI == 1)
2589 {
2590 hpPriv->strongRSSI = 0;
2591 if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
2592 {
2593 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x1<<26));
2594 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x1<<11) |
2595 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x1<<27) );
2596 }
2597 else
2598 {
2599 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26));
2600 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) |
2601 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27) );
2602 }
2603 polluted = 1;
2604 }
2605 }
2606 #undef ZM_SIGNAL_THRESHOLD
2607 }
2608
2609 if ((hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM) == 0)
2610 {
2611 if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE))
2612 {
2613 #define ZM_RX_SIGNAL_THRESHOLD_H 71
2614 #define ZM_RX_SIGNAL_THRESHOLD_L 66
2615 u8_t rxSignalThresholdH = ZM_RX_SIGNAL_THRESHOLD_H;
2616 u8_t rxSignalThresholdL = ZM_RX_SIGNAL_THRESHOLD_L;
2617 #undef ZM_RX_SIGNAL_THRESHOLD_H
2618 #undef ZM_RX_SIGNAL_THRESHOLD_L
2619
2620 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2621 && (zfStaIsConnected(dev))
2622 && (wd->SignalStrength > rxSignalThresholdH)
2623 )//&& (hpPriv->rxStrongRSSI == 0))
2624 {
2625 hpPriv->rxStrongRSSI = 1;
2626 //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1220);
2627 //zfDelayWriteInternalReg(dev, 0x1c5960, 0x900);
2628 //zfDelayWriteInternalReg(dev, 0x1c6960, 0x900);
2629 //zfDelayWriteInternalReg(dev, 0x1c7960, 0x900);
2630 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
2631 {
2632 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2633 {
2634 zfDelayWriteInternalReg(dev, 0x1c8960, 0x900);
2635 }
2636 else
2637 {
2638 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
2639 }
2640 }
2641 else
2642 {
2643 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
2644 }
2645 polluted = 1;
2646 }
2647 else if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2648 && (zfStaIsConnected(dev))
2649 && (wd->SignalStrength > rxSignalThresholdL)
2650 )//&& (hpPriv->rxStrongRSSI == 1))
2651 {
2652 //Do nothing to prevent frequently Rx switching
2653 }
2654 else
2655 {
2656 /* remove state handle, always rewrite register setting */
2657 //if (hpPriv->rxStrongRSSI == 1)
2658 {
2659 hpPriv->rxStrongRSSI = 0;
2660 //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1120);
2661 //zfDelayWriteInternalReg(dev, 0x1c5960, 0x9b40);
2662 //zfDelayWriteInternalReg(dev, 0x1c6960, 0x9b40);
2663 //zfDelayWriteInternalReg(dev, 0x1c7960, 0x9b40);
2664 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
2665 {
2666 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2667 {
2668 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
2669 }
2670 else
2671 {
2672 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
2673 }
2674 }
2675 else
2676 {
2677 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40);
2678 }
2679 polluted = 1;
2680 }
2681 }
2682
2683 }
2684 }
2685
2686 if (hpPriv->usbAcSendBytes[3] > (hpPriv->usbAcSendBytes[0]*2))
2687 {
2688 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[3]);
2689 polluted = 1;
2690 }
2691 else if (hpPriv->usbAcSendBytes[2] > (hpPriv->usbAcSendBytes[0]*2))
2692 {
2693 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[2]);
2694 polluted = 1;
2695 }
2696 else if (hpPriv->usbAcSendBytes[1] > (hpPriv->usbAcSendBytes[0]*2))
2697 {
2698 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[1]+((u32_t)hpPriv->cwmax[1]<<16));
2699 polluted = 1;
2700 }
2701 else
2702 {
2703 if (hpPriv->slotType == 1)
2704 {
2705 if ((wd->sta.enableDrvBA ==0) //Marvel AP
2706 && (hpPriv->aggMaxDurationBE > 2000)) //BE TXOP > 2ms
2707 {
2708 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, (hpPriv->cwmin[0]/2)+((u32_t)hpPriv->cwmax[0]<<16));
2709 }
2710 else
2711 {
2712 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16));
2713 }
2714 polluted = 1;
2715 }
2716 else
2717 {
2718 /* Compensation for 20us slot time */
2719 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 58+((u32_t)hpPriv->cwmax[0]<<16));
2720 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16));
2721 polluted = 1;
2722 }
2723
2724 if ((wd->sta.SWEncryptEnable & (ZM_SW_TKIP_ENCRY_EN|ZM_SW_WEP_ENCRY_EN)) == 0)
2725 {
2726 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[0]);
2727 polluted = 1;
2728 }
2729 else
2730 {
2731 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, 0x30);
2732 polluted = 1;
2733 }
2734
2735 }
2736 hpPriv->usbAcSendBytes[3] = 0;
2737 hpPriv->usbAcSendBytes[2] = 0;
2738 hpPriv->usbAcSendBytes[1] = 0;
2739 hpPriv->usbAcSendBytes[0] = 0;
2740 }
2741
2742 if (polluted == 1)
2743 {
2744 zfFlushDelayWrite(dev);
2745 }
2746
2747 return;
2748 }
2749
2750 /*
2751 * 0x1d4008 : AHB, DAC, ADC clock selection
2752 * bit1~0 AHB_CLK : AHB clock selection,
2753 * 00 : OSC 40MHz;
2754 * 01 : 20MHz in A mode, 22MHz in G mode;
2755 * 10 : 40MHz in A mode, 44MHz in G mode;
2756 * 11 : 80MHz in A mode, 88MHz in G mode.
2757 * bit3~2 CLK_SEL : Select the clock source of clk160 in ADDAC.
2758 * 00 : PLL divider's output;
2759 * 01 : PLL divider's output divided by 2;
2760 * 10 : PLL divider's output divided by 4;
2761 * 11 : REFCLK from XTALOSCPAD.
2762 */
2763 void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency)
2764 {
2765 if(bw40 == 1)
2766 {
2767 //zfDelayWriteInternalReg(dev, 0x1D4008, 0x73);
2768 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A);
2769 zfFlushDelayWrite(dev);
2770 }
2771 else
2772 {
2773 //zfDelayWriteInternalReg(dev, 0x1D4008, 0x70);
2774 if ( frequency <= ZM_CH_G_14 )
2775 {
2776 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x105);
2777 }
2778 else
2779 {
2780 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x104);
2781 }
2782 zfFlushDelayWrite(dev);
2783 }
2784 }
2785
2786 u32_t zfHpEchoCommand(zdev_t* dev, u32_t value)
2787 {
2788 u32_t cmd[2];
2789 u16_t ret;
2790
2791 cmd[0] = 0x00008004;
2792 cmd[1] = value;
2793
2794 ret = zfIssueCmd(dev, cmd, 8, ZM_CMD_ECHO, NULL);
2795 return ret;
2796 }
2797
2798 #ifdef ZM_DRV_INIT_USB_MODE
2799
2800 #define ZM_USB_US_STREAM_MODE 0x00000000
2801 #define ZM_USB_US_PACKET_MODE 0x00000008
2802 #define ZM_USB_DS_ENABLE 0x00000001
2803 #define ZM_USB_US_ENABLE 0x00000002
2804
2805 #define ZM_USB_RX_STREAM_4K 0x00000000
2806 #define ZM_USB_RX_STREAM_8K 0x00000010
2807 #define ZM_USB_RX_STREAM_16K 0x00000020
2808 #define ZM_USB_RX_STREAM_32K 0x00000030
2809
2810 #define ZM_USB_TX_STREAM_MODE 0x00000040
2811
2812 #define ZM_USB_MODE_CTRL_REG 0x001E1108
2813
2814 void zfInitUsbMode(zdev_t* dev)
2815 {
2816 u32_t mode;
2817 zmw_get_wlan_dev(dev);
2818
2819 /* TODO: Set USB mode by reading registery */
2820 mode = ZM_USB_DS_ENABLE | ZM_USB_US_ENABLE | ZM_USB_US_PACKET_MODE;
2821
2822 zfDelayWriteInternalReg(dev, ZM_USB_MODE_CTRL_REG, mode);
2823 zfFlushDelayWrite(dev);
2824 }
2825 #endif
2826
2827 void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage);
2828 void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40);
2829 void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40);
2830
2831
2832 s32_t zfInterpolateFunc(s32_t x, s32_t x1, s32_t y1, s32_t x2, s32_t y2)
2833 {
2834 s32_t y;
2835
2836 if (y2 == y1)
2837 {
2838 y = y1;
2839 }
2840 else if (x == x1)
2841 {
2842 y = y1;
2843 }
2844 else if (x == x2)
2845 {
2846 y = y2;
2847 }
2848 else if (x2 != x1)
2849 {
2850 y = y1 + (((y2-y1) * (x-x1))/(x2-x1));
2851 }
2852 else
2853 {
2854 y = y1;
2855 }
2856
2857 return y;
2858 }
2859
2860 //#define ZM_ENABLE_TPC_WINDOWS_DEBUG
2861 //#define ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
2862
2863 /* the tx power offset workaround for ART vs NDIS/MDK */
2864 #define HALTX_POWER_OFFSET 0
2865
2866 u8_t zfInterpolateFuncX(u8_t x, u8_t x1, u8_t y1, u8_t x2, u8_t y2)
2867 {
2868 s32_t y;
2869 s32_t inc;
2870
2871 #define ZM_MULTIPLIER 8
2872 y = zfInterpolateFunc((s32_t)x<<ZM_MULTIPLIER,
2873 (s32_t)x1<<ZM_MULTIPLIER,
2874 (s32_t)y1<<ZM_MULTIPLIER,
2875 (s32_t)x2<<ZM_MULTIPLIER,
2876 (s32_t)y2<<ZM_MULTIPLIER);
2877
2878 inc = (y & (1<<(ZM_MULTIPLIER-1))) >> (ZM_MULTIPLIER-1);
2879 y = (y >> ZM_MULTIPLIER) + inc;
2880 #undef ZM_MULTIPLIER
2881
2882 return (u8_t)y;
2883 }
2884
2885 u8_t zfGetInterpolatedValue(u8_t x, u8_t* x_array, u8_t* y_array)
2886 {
2887 s32_t y;
2888 u16_t xIndex;
2889
2890 if (x <= x_array[1])
2891 {
2892 xIndex = 0;
2893 }
2894 else if (x <= x_array[2])
2895 {
2896 xIndex = 1;
2897 }
2898 else if (x <= x_array[3])
2899 {
2900 xIndex = 2;
2901 }
2902 else //(x > x_array[3])
2903 {
2904 xIndex = 3;
2905 }
2906
2907 y = zfInterpolateFuncX(x,
2908 x_array[xIndex],
2909 y_array[xIndex],
2910 x_array[xIndex+1],
2911 y_array[xIndex+1]);
2912
2913 return (u8_t)y;
2914 }
2915
2916 u8_t zfFindFreqIndex(u8_t f, u8_t* fArray, u8_t fArraySize)
2917 {
2918 u8_t i;
2919 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
2920 DbgPrint("f=%d ", f);
2921 for (i=0; i<fArraySize; i++)
2922 {
2923 DbgPrint("%d ", fArray[i]);
2924 }
2925 DbgPrint("\n");
2926 #endif
2927 i=fArraySize-2;
2928 while(1)
2929 {
2930 if (f >= fArray[i])
2931 {
2932 return i;
2933 }
2934 if (i!=0)
2935 {
2936 i--;
2937 }
2938 else
2939 {
2940 return 0;
2941 }
2942 }
2943 }
2944
2945
2946
2947
2948 void zfInitPowerCal(zdev_t* dev)
2949 {
2950 //Program PHY Tx power relatives registers
2951 #define zm_write_phy_reg(cr, val) reg_write((cr*4)+0x9800, val)
2952
2953 zm_write_phy_reg(79, 0x7f);
2954 zm_write_phy_reg(77, 0x3f3f3f3f);
2955 zm_write_phy_reg(78, 0x3f3f3f3f);
2956 zm_write_phy_reg(653, 0x3f3f3f3f);
2957 zm_write_phy_reg(654, 0x3f3f3f3f);
2958 zm_write_phy_reg(739, 0x3f3f3f3f);
2959 zm_write_phy_reg(740, 0x3f3f3f3f);
2960 zm_write_phy_reg(755, 0x3f3f3f3f);
2961 zm_write_phy_reg(756, 0x3f3f3f3f);
2962 zm_write_phy_reg(757, 0x3f3f3f3f);
2963
2964 #undef zm_write_phy_reg
2965 }
2966
2967
2968
2969 void zfPrintTp(u8_t* pwr0, u8_t* vpd0, u8_t* pwr1, u8_t* vpd1)
2970 {
2971 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
2972 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
2973 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
2974 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
2975 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
2976 #endif
2977 }
2978
2979
2980 /*
2981 * To find CTL index(0~23)
2982 * return 24(AR5416_NUM_CTLS)=>no desired index found
2983 */
2984 u8_t zfFindCtlEdgesIndex(zdev_t* dev, u8_t desired_CtlIndex)
2985 {
2986 u8_t i;
2987 struct zsHpPriv* hpPriv;
2988 struct ar5416Eeprom* eepromImage;
2989
2990 zmw_get_wlan_dev(dev);
2991
2992 hpPriv = wd->hpPrivate;
2993
2994 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
2995
2996 //for (i = 0; (i < AR5416_NUM_CTLS) && eepromImage->ctlIndex[i]; i++)
2997 for (i = 0; i < AR5416_NUM_CTLS; i++)
2998 {
2999 if(desired_CtlIndex == eepromImage->ctlIndex[i])
3000 break;
3001 }
3002 return i;
3003 }
3004
3005 /**************************************************************************
3006 * fbin2freq
3007 *
3008 * Get channel value from binary representation held in eeprom
3009 * RETURNS: the frequency in MHz
3010 */
3011 u32_t
3012 fbin2freq(u8_t fbin, u8_t is2GHz)
3013 {
3014 /*
3015 * Reserved value 0xFF provides an empty definition both as
3016 * an fbin and as a frequency - do not convert
3017 */
3018 if (fbin == AR5416_BCHAN_UNUSED) {
3019 return fbin;
3020 }
3021
3022 return (u32_t)((is2GHz==1) ? (2300 + fbin) : (4800 + 5 * fbin));
3023 }
3024
3025
3026 u8_t zfGetMaxEdgePower(zdev_t* dev, CAL_CTL_EDGES *pCtlEdges, u32_t freq)
3027 {
3028 u8_t i;
3029 u8_t maxEdgePower;
3030 u8_t is2GHz;
3031 struct zsHpPriv* hpPriv;
3032 struct ar5416Eeprom* eepromImage;
3033
3034 zmw_get_wlan_dev(dev);
3035
3036 hpPriv = wd->hpPrivate;
3037
3038 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
3039
3040 if(freq > ZM_CH_G_14)
3041 is2GHz = 0;
3042 else
3043 is2GHz = 1;
3044
3045 maxEdgePower = AR5416_MAX_RATE_POWER;
3046
3047 /* Get the edge power */
3048 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++)
3049 {
3050 /*
3051 * If there's an exact channel match or an inband flag set
3052 * on the lower channel use the given rdEdgePower
3053 */
3054 if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz))
3055 {
3056 maxEdgePower = pCtlEdges[i].tPower;
3057 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3058 zm_dbg(("zfGetMaxEdgePower index i = %d \n", i));
3059 #endif
3060 break;
3061 }
3062 else if ((i > 0) && (freq < fbin2freq(pCtlEdges[i].bChannel, is2GHz)))
3063 {
3064 if (fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) < freq && pCtlEdges[i - 1].flag)
3065 {
3066 maxEdgePower = pCtlEdges[i - 1].tPower;
3067 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3068 zm_dbg(("zfGetMaxEdgePower index i-1 = %d \n", i-1));
3069 #endif
3070 }
3071 /* Leave loop - no more affecting edges possible in this monotonic increasing list */
3072 break;
3073 }
3074
3075 }
3076
3077 if( i == AR5416_NUM_BAND_EDGES )
3078 {
3079 if (freq > fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) && pCtlEdges[i - 1].flag)
3080 {
3081 maxEdgePower = pCtlEdges[i - 1].tPower;
3082 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3083 zm_dbg(("zfGetMaxEdgePower index=>i-1 = %d \n", i-1));
3084 #endif
3085 }
3086 }
3087
3088 zm_assert(maxEdgePower > 0);
3089
3090 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3091 if ( maxEdgePower == AR5416_MAX_RATE_POWER )
3092 {
3093 zm_dbg(("zfGetMaxEdgePower = %d !!!\n", AR5416_MAX_RATE_POWER));
3094 }
3095 #endif
3096 return maxEdgePower;
3097 }
3098
3099 u32_t zfAdjustHT40FreqOffset(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset)
3100 {
3101 u32_t newFreq = frequency;
3102
3103 if (bw40 == 1)
3104 {
3105 if (extOffset == 1)
3106 {
3107 newFreq += 10;
3108 }
3109 else
3110 {
3111 newFreq -= 10;
3112 }
3113 }
3114 return newFreq;
3115 }
3116
3117 u32_t zfHpCheckDoHeavyClip(zdev_t* dev, u32_t freq, CAL_CTL_EDGES *pCtlEdges, u8_t bw40)
3118 {
3119 u32_t ret = 0;
3120 u8_t i;
3121 u8_t is2GHz;
3122 struct zsHpPriv* hpPriv;
3123
3124 zmw_get_wlan_dev(dev);
3125
3126 hpPriv = wd->hpPrivate;
3127
3128 if(freq > ZM_CH_G_14)
3129 is2GHz = 0;
3130 else
3131 is2GHz = 1;
3132
3133 /* HT40 force enable heavy clip */
3134 if (bw40)
3135 {
3136 ret |= 0xf0;
3137 }
3138 #if 1
3139 /* HT20 : frequency bandedge */
3140 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++)
3141 {
3142 if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz))
3143 {
3144 if (pCtlEdges[i].flag == 0)
3145 {
3146 ret |= 0xf;
3147 }
3148 break;
3149 }
3150 }
3151 #endif
3152
3153 return ret;
3154 }
3155
3156
3157 void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset)
3158 {
3159 struct ar5416Eeprom* eepromImage;
3160 u8_t pwr0[5];
3161 u8_t pwr1[5];
3162 u8_t vpd0[5];
3163 u8_t vpd1[5];
3164 u8_t vpd_chain1[128];
3165 u8_t vpd_chain3[128];
3166 u16_t boundary1 = 18; //CR 667
3167 u16_t powerTxMax = 63; //CR 79
3168 u8_t i;
3169 struct zsHpPriv* hpPriv;
3170 u8_t fbin;
3171 u8_t index, max2gIndex, max5gIndex;
3172 u8_t chain0pwrPdg0[5];
3173 u8_t chain0vpdPdg0[5];
3174 u8_t chain0pwrPdg1[5];
3175 u8_t chain0vpdPdg1[5];
3176 u8_t chain2pwrPdg0[5];
3177 u8_t chain2vpdPdg0[5];
3178 u8_t chain2pwrPdg1[5];
3179 u8_t chain2vpdPdg1[5];
3180 u8_t fbinArray[8];
3181
3182 /* 4 CTL */
3183 u8_t ctl_i;
3184 u8_t desired_CtlIndex;
3185
3186 u8_t ctlEdgesMaxPowerCCK = AR5416_MAX_RATE_POWER;
3187 u8_t ctlEdgesMaxPower2G = AR5416_MAX_RATE_POWER;
3188 u8_t ctlEdgesMaxPower2GHT20 = AR5416_MAX_RATE_POWER;
3189 u8_t ctlEdgesMaxPower2GHT40 = AR5416_MAX_RATE_POWER;
3190 u8_t ctlEdgesMaxPower5G = AR5416_MAX_RATE_POWER;
3191 u8_t ctlEdgesMaxPower5GHT20 = AR5416_MAX_RATE_POWER;
3192 u8_t ctlEdgesMaxPower5GHT40 = AR5416_MAX_RATE_POWER;
3193
3194 u8_t ctlOffset;
3195
3196 zmw_get_wlan_dev(dev);
3197
3198 hpPriv = wd->hpPrivate;
3199
3200 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
3201
3202 // Check the total bytes of the EEPROM structure to see the dongle have been calibrated or not.
3203 if (eepromImage->baseEepHeader.length == 0xffff)
3204 {
3205 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3206 zm_dbg(("Warning! This dongle not been calibrated\n"));
3207 #endif
3208 return;
3209 }
3210
3211 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3212 DbgPrint("-----zfSetPowerCalTable : frequency=%d-----\n", frequency);
3213 #endif
3214 /* TODO : 1. boundary1 and powerTxMax should be refered to CR667 and CR79 */
3215 /* in otus.ini file */
3216
3217 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3218 /* 2. Interpolate pwr and vpd test points from frequency */
3219 DbgPrint("calFreqPier5G : %d, %d, %d, %d ,%d, %d, %d, %d\n",
3220 eepromImage->calFreqPier5G[0]*5+4800,
3221 eepromImage->calFreqPier5G[1]*5+4800,
3222 eepromImage->calFreqPier5G[2]*5+4800,
3223 eepromImage->calFreqPier5G[3]*5+4800,
3224 eepromImage->calFreqPier5G[4]*5+4800,
3225 eepromImage->calFreqPier5G[5]*5+4800,
3226 eepromImage->calFreqPier5G[6]*5+4800,
3227 eepromImage->calFreqPier5G[7]*5+4800
3228 );
3229 DbgPrint("calFreqPier2G : %d, %d, %d, %d\n",
3230 eepromImage->calFreqPier2G[0]+2300,
3231 eepromImage->calFreqPier2G[1]+2300,
3232 eepromImage->calFreqPier2G[2]+2300,
3233 eepromImage->calFreqPier2G[3]+2300
3234 );
3235 #endif
3236 if (frequency < 3000)
3237 {
3238 for (i=0; i<4; i++)
3239 {
3240 if (eepromImage->calFreqPier2G[i] == 0xff)
3241 {
3242 break;
3243 }
3244 }
3245 max2gIndex = i;
3246 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3247 DbgPrint("max2gIndex : %d\n", max2gIndex);
3248 #endif
3249 fbin = (u8_t)(frequency - 2300);
3250 index = zfFindFreqIndex(fbin, eepromImage->calFreqPier2G, max2gIndex);
3251 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3252 DbgPrint("2G index : %d\n", index);
3253 DbgPrint("chain 0 index\n");
3254 #endif
3255 zfPrintTp(&eepromImage->calPierData2G[0][index].pwrPdg[0][0],
3256 &eepromImage->calPierData2G[0][index].vpdPdg[0][0],
3257 &eepromImage->calPierData2G[0][index].pwrPdg[1][0],
3258 &eepromImage->calPierData2G[0][index].vpdPdg[1][0]
3259 );
3260 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3261 DbgPrint("chain 0 index+1\n");
3262 #endif
3263 zfPrintTp(&eepromImage->calPierData2G[0][index+1].pwrPdg[0][0],
3264 &eepromImage->calPierData2G[0][index+1].vpdPdg[0][0],
3265 &eepromImage->calPierData2G[0][index+1].pwrPdg[1][0],
3266 &eepromImage->calPierData2G[0][index+1].vpdPdg[1][0]
3267 );
3268
3269 for (i=0; i<5; i++)
3270 {
3271 chain0pwrPdg0[i] = zfInterpolateFuncX(fbin,
3272 eepromImage->calFreqPier2G[index],
3273 eepromImage->calPierData2G[0][index].pwrPdg[0][i],
3274 eepromImage->calFreqPier2G[index+1],
3275 eepromImage->calPierData2G[0][index+1].pwrPdg[0][i]
3276 );
3277 chain0vpdPdg0[i] = zfInterpolateFuncX(fbin,
3278 eepromImage->calFreqPier2G[index],
3279 eepromImage->calPierData2G[0][index].vpdPdg[0][i],
3280 eepromImage->calFreqPier2G[index+1],
3281 eepromImage->calPierData2G[0][index+1].vpdPdg[0][i]
3282 );
3283 chain0pwrPdg1[i] = zfInterpolateFuncX(fbin,
3284 eepromImage->calFreqPier2G[index],
3285 eepromImage->calPierData2G[0][index].pwrPdg[1][i],
3286 eepromImage->calFreqPier2G[index+1],
3287 eepromImage->calPierData2G[0][index+1].pwrPdg[1][i]
3288 );
3289 chain0vpdPdg1[i] = zfInterpolateFuncX(fbin,
3290 eepromImage->calFreqPier2G[index],
3291 eepromImage->calPierData2G[0][index].vpdPdg[1][i],
3292 eepromImage->calFreqPier2G[index+1],
3293 eepromImage->calPierData2G[0][index+1].vpdPdg[1][i]
3294 );
3295
3296 chain2pwrPdg0[i] = zfInterpolateFuncX(fbin,
3297 eepromImage->calFreqPier2G[index],
3298 eepromImage->calPierData2G[1][index].pwrPdg[0][i],
3299 eepromImage->calFreqPier2G[index+1],
3300 eepromImage->calPierData2G[1][index+1].pwrPdg[0][i]
3301 );
3302 chain2vpdPdg0[i] = zfInterpolateFuncX(fbin,
3303 eepromImage->calFreqPier2G[index],
3304 eepromImage->calPierData2G[1][index].vpdPdg[0][i],
3305 eepromImage->calFreqPier2G[index+1],
3306 eepromImage->calPierData2G[1][index+1].vpdPdg[0][i]
3307 );
3308 chain2pwrPdg1[i] = zfInterpolateFuncX(fbin,
3309 eepromImage->calFreqPier2G[index],
3310 eepromImage->calPierData2G[1][index].pwrPdg[1][i],
3311 eepromImage->calFreqPier2G[index+1],
3312 eepromImage->calPierData2G[1][index+1].pwrPdg[1][i]
3313 );
3314 chain2vpdPdg1[i] = zfInterpolateFuncX(fbin,
3315 eepromImage->calFreqPier2G[index],
3316 eepromImage->calPierData2G[1][index].vpdPdg[1][i],
3317 eepromImage->calFreqPier2G[index+1],
3318 eepromImage->calPierData2G[1][index+1].vpdPdg[1][i]
3319 );
3320 }
3321 }
3322 else
3323 {
3324 for (i=0; i<8; i++)
3325 {
3326 if (eepromImage->calFreqPier5G[i] == 0xff)
3327 {
3328 break;
3329 }
3330 }
3331 max5gIndex = i;
3332 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3333 DbgPrint("max5gIndex : %d\n", max5gIndex);
3334 #endif
3335 fbin = (u8_t)((frequency - 4800)/5);
3336 index = zfFindFreqIndex(fbin, eepromImage->calFreqPier5G, max5gIndex);
3337 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3338 DbgPrint("5G index : %d\n", index);
3339 #endif
3340
3341 for (i=0; i<5; i++)
3342 {
3343 chain0pwrPdg0[i] = zfInterpolateFuncX(fbin,
3344 eepromImage->calFreqPier5G[index],
3345 eepromImage->calPierData5G[0][index].pwrPdg[0][i],
3346 eepromImage->calFreqPier5G[index+1],
3347 eepromImage->calPierData5G[0][index+1].pwrPdg[0][i]
3348 );
3349 chain0vpdPdg0[i] = zfInterpolateFuncX(fbin,
3350 eepromImage->calFreqPier5G[index],
3351 eepromImage->calPierData5G[0][index].vpdPdg[0][i],
3352 eepromImage->calFreqPier5G[index+1],
3353 eepromImage->calPierData5G[0][index+1].vpdPdg[0][i]
3354 );
3355 chain0pwrPdg1[i] = zfInterpolateFuncX(fbin,
3356 eepromImage->calFreqPier5G[index],
3357 eepromImage->calPierData5G[0][index].pwrPdg[1][i],
3358 eepromImage->calFreqPier5G[index+1],
3359 eepromImage->calPierData5G[0][index+1].pwrPdg[1][i]
3360 );
3361 chain0vpdPdg1[i] = zfInterpolateFuncX(fbin,
3362 eepromImage->calFreqPier5G[index],
3363 eepromImage->calPierData5G[0][index].vpdPdg[1][i],
3364 eepromImage->calFreqPier5G[index+1],
3365 eepromImage->calPierData5G[0][index+1].vpdPdg[1][i]
3366 );
3367
3368 chain2pwrPdg0[i] = zfInterpolateFuncX(fbin,
3369 eepromImage->calFreqPier5G[index],
3370 eepromImage->calPierData5G[1][index].pwrPdg[0][i],
3371 eepromImage->calFreqPier5G[index+1],
3372 eepromImage->calPierData5G[1][index+1].pwrPdg[0][i]
3373 );
3374 chain2vpdPdg0[i] = zfInterpolateFuncX(fbin,
3375 eepromImage->calFreqPier5G[index],
3376 eepromImage->calPierData5G[1][index].vpdPdg[0][i],
3377 eepromImage->calFreqPier5G[index+1],
3378 eepromImage->calPierData5G[1][index+1].vpdPdg[0][i]
3379 );
3380 chain2pwrPdg1[i] = zfInterpolateFuncX(fbin,
3381 eepromImage->calFreqPier5G[index],
3382 eepromImage->calPierData5G[1][index].pwrPdg[1][i],
3383 eepromImage->calFreqPier5G[index+1],
3384 eepromImage->calPierData5G[1][index+1].pwrPdg[1][i]
3385 );
3386 chain2vpdPdg1[i] = zfInterpolateFuncX(fbin,
3387 eepromImage->calFreqPier5G[index],
3388 eepromImage->calPierData5G[1][index].vpdPdg[1][i],
3389 eepromImage->calFreqPier5G[index+1],
3390 eepromImage->calPierData5G[1][index+1].vpdPdg[1][i]
3391 );
3392 }
3393
3394 }
3395
3396
3397 /* Chain 1 */
3398 /* Get pwr and vpd test points from frequency */
3399 for (i=0; i<5; i++)
3400 {
3401 pwr0[i] = chain0pwrPdg0[i]>>1;
3402 vpd0[i] = chain0vpdPdg0[i];
3403 pwr1[i] = chain0pwrPdg1[i]>>1;
3404 vpd1[i] = chain0vpdPdg1[i];
3405 }
3406 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3407 DbgPrint("Test Points\n");
3408 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
3409 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
3410 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
3411 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
3412 #endif
3413 /* Generate the vpd arrays */
3414 for (i=0; i<boundary1+1+6; i++)
3415 {
3416 vpd_chain1[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]);
3417 }
3418 for (; i<powerTxMax+1+6+6; i++)
3419 {
3420 vpd_chain1[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]);
3421 }
3422 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3423 DbgPrint("vpd_chain1\n");
3424 for (i=0; i<powerTxMax+1+6+6; i+=10)
3425 {
3426 DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n",
3427 vpd_chain1[i+0], vpd_chain1[i+1], vpd_chain1[i+2], vpd_chain1[i+3], vpd_chain1[i+4],
3428 vpd_chain1[i+5], vpd_chain1[i+6], vpd_chain1[i+7], vpd_chain1[i+8], vpd_chain1[i+9]);
3429 }
3430 #endif
3431 /* Write PHY regs 672-703 */
3432 for (i=0; i<128; i+=4)
3433 {
3434 u32_t val;
3435
3436 val = ((u32_t)vpd_chain1[i+3]<<24) |
3437 ((u32_t)vpd_chain1[i+2]<<16) |
3438 ((u32_t)vpd_chain1[i+1]<<8) |
3439 ((u32_t)vpd_chain1[i]);
3440
3441 #ifndef ZM_OTUS_LINUX_PHASE_2
3442 reg_write(regAddr + i, val); /* CR672 */
3443 #endif
3444 }
3445
3446 /* Chain 2 */
3447 /* Get pwr and vpd test points from frequency */
3448 for (i=0; i<5; i++)
3449 {
3450 pwr0[i] = chain2pwrPdg0[i]>>1;
3451 vpd0[i] = chain2vpdPdg0[i];
3452 pwr1[i] = chain2pwrPdg1[i]>>1;
3453 vpd1[i] = chain2vpdPdg1[i];
3454 }
3455 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3456 DbgPrint("Test Points\n");
3457 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
3458 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
3459 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
3460 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
3461 #endif
3462 /* Generate the vpd arrays */
3463 for (i=0; i<boundary1+1+6; i++)
3464 {
3465 vpd_chain3[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]);
3466 }
3467 for (; i<powerTxMax+1+6+6; i++)
3468 {
3469 vpd_chain3[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]);
3470 }
3471 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3472 DbgPrint("vpd_chain3\n");
3473 for (i=0; i<powerTxMax+1+6+6; i+=10)
3474 {
3475 DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n",
3476 vpd_chain3[i+0], vpd_chain3[i+1], vpd_chain3[i+2], vpd_chain3[i+3], vpd_chain3[i+4],
3477 vpd_chain3[i+5], vpd_chain3[i+6], vpd_chain3[i+7], vpd_chain3[i+8], vpd_chain3[i+9]);
3478 }
3479 #endif
3480
3481 /* Write PHY regs 672-703 + 0x1000 */
3482 for (i=0; i<128; i+=4)
3483 {
3484 u32_t val;
3485
3486 val = ((u32_t)vpd_chain3[i+3]<<24) |
3487 ((u32_t)vpd_chain3[i+2]<<16) |
3488 ((u32_t)vpd_chain3[i+1]<<8) |
3489 ((u32_t)vpd_chain3[i]);
3490
3491 #ifndef ZM_OTUS_LINUX_PHASE_2
3492 reg_write(regAddr + i, val); /* CR672 */
3493 #endif
3494 }
3495
3496 zfFlushDelayWrite(dev);
3497
3498 /* 3. Generate target power table */
3499 if (frequency < 3000)
3500 {
3501 for (i=0; i<3; i++)
3502 {
3503 if (eepromImage->calTargetPowerCck[i].bChannel != 0xff)
3504 {
3505 fbinArray[i] = eepromImage->calTargetPowerCck[i].bChannel;
3506 }
3507 else
3508 {
3509 break;
3510 }
3511
3512 }
3513 index = zfFindFreqIndex(fbin, fbinArray, i);
3514 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3515 DbgPrint("CCK index=%d\n", index);
3516 #endif
3517 for (i=0; i<4; i++)
3518 {
3519 hpPriv->tPow2xCck[i] = zfInterpolateFuncX(fbin,
3520 eepromImage->calTargetPowerCck[index].bChannel,
3521 eepromImage->calTargetPowerCck[index].tPow2x[i],
3522 eepromImage->calTargetPowerCck[index+1].bChannel,
3523 eepromImage->calTargetPowerCck[index+1].tPow2x[i]
3524 );
3525 }
3526
3527 for (i=0; i<4; i++)
3528 {
3529 if (eepromImage->calTargetPower2G[i].bChannel != 0xff)
3530 {
3531 fbinArray[i] = eepromImage->calTargetPower2G[i].bChannel;
3532 }
3533 else
3534 {
3535 break;
3536 }
3537
3538 }
3539 index = zfFindFreqIndex(fbin, fbinArray, i);
3540 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3541 DbgPrint("2G index=%d\n", index);
3542 #endif
3543 for (i=0; i<4; i++)
3544 {
3545 hpPriv->tPow2x2g[i] = zfInterpolateFuncX(fbin,
3546 eepromImage->calTargetPower2G[index].bChannel,
3547 eepromImage->calTargetPower2G[index].tPow2x[i],
3548 eepromImage->calTargetPower2G[index+1].bChannel,
3549 eepromImage->calTargetPower2G[index+1].tPow2x[i]
3550 );
3551 }
3552
3553 for (i=0; i<4; i++)
3554 {
3555 if (eepromImage->calTargetPower2GHT20[i].bChannel != 0xff)
3556 {
3557 fbinArray[i] = eepromImage->calTargetPower2GHT20[i].bChannel;
3558 }
3559 else
3560 {
3561 break;
3562 }
3563
3564 }
3565 index = zfFindFreqIndex(fbin, fbinArray, i);
3566 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3567 DbgPrint("2G HT20 index=%d\n", index);
3568 #endif
3569 for (i=0; i<8; i++)
3570 {
3571 hpPriv->tPow2x2gHt20[i] = zfInterpolateFuncX(fbin,
3572 eepromImage->calTargetPower2GHT20[index].bChannel,
3573 eepromImage->calTargetPower2GHT20[index].tPow2x[i],
3574 eepromImage->calTargetPower2GHT20[index+1].bChannel,
3575 eepromImage->calTargetPower2GHT20[index+1].tPow2x[i]
3576 );
3577 }
3578
3579 for (i=0; i<4; i++)
3580 {
3581 if (eepromImage->calTargetPower2GHT40[i].bChannel != 0xff)
3582 {
3583 fbinArray[i] = eepromImage->calTargetPower2GHT40[i].bChannel;
3584 }
3585 else
3586 {
3587 break;
3588 }
3589
3590 }
3591 index = zfFindFreqIndex( (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i);
3592 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3593 DbgPrint("2G HT40 index=%d\n", index);
3594 #endif
3595 for (i=0; i<8; i++)
3596 {
3597 hpPriv->tPow2x2gHt40[i] = zfInterpolateFuncX(
3598 (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset),
3599 eepromImage->calTargetPower2GHT40[index].bChannel,
3600 eepromImage->calTargetPower2GHT40[index].tPow2x[i],
3601 eepromImage->calTargetPower2GHT40[index+1].bChannel,
3602 eepromImage->calTargetPower2GHT40[index+1].tPow2x[i]
3603 );
3604 }
3605
3606 zfPrintTargetPower2G(hpPriv->tPow2xCck,
3607 hpPriv->tPow2x2g,
3608 hpPriv->tPow2x2gHt20,
3609 hpPriv->tPow2x2gHt40);
3610 }
3611 else
3612 {
3613 /* 5G */
3614 for (i=0; i<8; i++)
3615 {
3616 if (eepromImage->calTargetPower5G[i].bChannel != 0xff)
3617 {
3618 fbinArray[i] = eepromImage->calTargetPower5G[i].bChannel;
3619 }
3620 else
3621 {
3622 break;
3623 }
3624
3625 }
3626 index = zfFindFreqIndex(fbin, fbinArray, i);
3627 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3628 DbgPrint("5G index=%d\n", index);
3629 #endif
3630 for (i=0; i<4; i++)
3631 {
3632 hpPriv->tPow2x5g[i] = zfInterpolateFuncX(fbin,
3633 eepromImage->calTargetPower5G[index].bChannel,
3634 eepromImage->calTargetPower5G[index].tPow2x[i],
3635 eepromImage->calTargetPower5G[index+1].bChannel,
3636 eepromImage->calTargetPower5G[index+1].tPow2x[i]
3637 );
3638 }
3639
3640 for (i=0; i<8; i++)
3641 {
3642 if (eepromImage->calTargetPower5GHT20[i].bChannel != 0xff)
3643 {
3644 fbinArray[i] = eepromImage->calTargetPower5GHT20[i].bChannel;
3645 }
3646 else
3647 {
3648 break;
3649 }
3650
3651 }
3652 index = zfFindFreqIndex(fbin, fbinArray, i);
3653 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3654 DbgPrint("5G HT20 index=%d\n", index);
3655 #endif
3656 for (i=0; i<8; i++)
3657 {
3658 hpPriv->tPow2x5gHt20[i] = zfInterpolateFuncX(fbin,
3659 eepromImage->calTargetPower5GHT20[index].bChannel,
3660 eepromImage->calTargetPower5GHT20[index].tPow2x[i],
3661 eepromImage->calTargetPower5GHT20[index+1].bChannel,
3662 eepromImage->calTargetPower5GHT20[index+1].tPow2x[i]
3663 );
3664 }
3665
3666 for (i=0; i<8; i++)
3667 {
3668 if (eepromImage->calTargetPower5GHT40[i].bChannel != 0xff)
3669 {
3670 fbinArray[i] = eepromImage->calTargetPower5GHT40[i].bChannel;
3671 }
3672 else
3673 {
3674 break;
3675 }
3676
3677 }
3678 index = zfFindFreqIndex((u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i);
3679 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3680 DbgPrint("5G HT40 index=%d\n", index);
3681 #endif
3682 for (i=0; i<8; i++)
3683 {
3684 hpPriv->tPow2x5gHt40[i] = zfInterpolateFuncX(
3685 (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset),
3686 eepromImage->calTargetPower5GHT40[index].bChannel,
3687 eepromImage->calTargetPower5GHT40[index].tPow2x[i],
3688 eepromImage->calTargetPower5GHT40[index+1].bChannel,
3689 eepromImage->calTargetPower5GHT40[index+1].tPow2x[i]
3690 );
3691 }
3692
3693 zfPrintTargetPower5G(
3694 hpPriv->tPow2x5g,
3695 hpPriv->tPow2x5gHt20,
3696 hpPriv->tPow2x5gHt40);
3697 }
3698
3699
3700
3701 /* 4. CTL */
3702 /*
3703 * 4.1 Get the bandedges tx power by frequency
3704 * 2.4G we get ctlEdgesMaxPowerCCK
3705 * ctlEdgesMaxPower2G
3706 * ctlEdgesMaxPower2GHT20
3707 * ctlEdgesMaxPower2GHT40
3708 * 5G we get ctlEdgesMaxPower5G
3709 * ctlEdgesMaxPower5GHT20
3710 * ctlEdgesMaxPower5GHT40
3711 * 4.2 Update (3.) target power table by 4.1
3712 * 4.3 Tx power offset for ART - NDIS/MDK
3713 * 4.4 Write MAC reg 0x694 for ACK's TPC
3714 *
3715 */
3716
3717 //zfDumpEepBandEdges(eepromImage);
3718
3719 /* get the cfg from Eeprom: regionCode => RegulatoryDomain : 0x10-FFC 0x30-eu 0x40-jap */
3720 desired_CtlIndex = zfHpGetRegulatoryDomain(dev);
3721 if ((desired_CtlIndex == 0x30) || (desired_CtlIndex == 0x40) || (desired_CtlIndex == 0x0))
3722 {
3723 /* skip CTL and heavy clip */
3724 hpPriv->enableBBHeavyClip = 0;
3725 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3726 zm_dbg(("RegulatoryDomain = 0, skip CTL and heavy clip\n"));
3727 #endif
3728 }
3729 else
3730 {
3731 hpPriv->enableBBHeavyClip = 1;
3732
3733 if (desired_CtlIndex == 0xff)
3734 {
3735 /* desired index not found */
3736 desired_CtlIndex = 0x10;
3737 }
3738
3739 /* first part : 2.4G */
3740 if (frequency <= ZM_CH_G_14)
3741 {
3742 /* 2.4G - CTL_11B */
3743 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11B);
3744 if(ctl_i<AR5416_NUM_CTLS)
3745 {
3746 ctlEdgesMaxPowerCCK = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3747 }
3748 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3749 zm_dbg(("CTL_11B ctl_i = %d\n", ctl_i));
3750 #endif
3751
3752 /* 2.4G - CTL_11G */
3753 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G);
3754 if(ctl_i<AR5416_NUM_CTLS)
3755 {
3756 ctlEdgesMaxPower2G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3757 }
3758 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3759 zm_dbg(("CTL_11G ctl_i = %d\n", ctl_i));
3760 #endif
3761
3762 /* 2.4G - CTL_2GHT20 */
3763 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT20);
3764 if(ctl_i<AR5416_NUM_CTLS)
3765 {
3766 ctlEdgesMaxPower2GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3767 }
3768 else
3769 {
3770 /* workaround for no data in Eeprom, replace by normal 2G */
3771 ctlEdgesMaxPower2GHT20 = ctlEdgesMaxPower2G;
3772 }
3773 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3774 zm_dbg(("CTL_2GHT20 ctl_i = %d\n", ctl_i));
3775 #endif
3776
3777 /* 2.4G - CTL_2GHT40 */
3778 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT40);
3779 if(ctl_i<AR5416_NUM_CTLS)
3780 {
3781 ctlEdgesMaxPower2GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1],
3782 zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset));
3783 }
3784 else
3785 {
3786 /* workaround for no data in Eeprom, replace by normal 2G */
3787 ctlEdgesMaxPower2GHT40 = ctlEdgesMaxPower2G;
3788 }
3789 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3790 zm_dbg(("CTL_2GHT40 ctl_i = %d\n", ctl_i));
3791 #endif
3792
3793
3794 /* 7a17 : */
3795 /* Max power (dBm) for channel range when using DFS define by madwifi*/
3796 for (i=0; i<wd->regulationTable.allowChannelCnt; i++)
3797 {
3798 if (wd->regulationTable.allowChannel[i].channel == frequency)
3799 {
3800 if (zfHpIsDfsChannel(dev, (u16_t)frequency))
3801 {
3802 zm_debug_msg1("frequency use DFS -- ", frequency);
3803 ctlEdgesMaxPowerCCK = zm_min(ctlEdgesMaxPowerCCK, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3804 ctlEdgesMaxPower2G = zm_min(ctlEdgesMaxPower2G, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3805 ctlEdgesMaxPower2GHT20 = zm_min(ctlEdgesMaxPower2GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3806 ctlEdgesMaxPower2GHT40 = zm_min(ctlEdgesMaxPower2GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3807 }
3808 break;
3809 }
3810 }
3811
3812 /* Apply ctl mode to correct target power set */
3813 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3814 zm_debug_msg1("ctlEdgesMaxPowerCCK = ", ctlEdgesMaxPowerCCK);
3815 zm_debug_msg1("ctlEdgesMaxPower2G = ", ctlEdgesMaxPower2G);
3816 zm_debug_msg1("ctlEdgesMaxPower2GHT20 = ", ctlEdgesMaxPower2GHT20);
3817 zm_debug_msg1("ctlEdgesMaxPower2GHT40 = ", ctlEdgesMaxPower2GHT40);
3818 #endif
3819 for (i=0; i<4; i++)
3820 {
3821 hpPriv->tPow2xCck[i] = zm_min(hpPriv->tPow2xCck[i], ctlEdgesMaxPowerCCK) + HALTX_POWER_OFFSET;
3822 }
3823 hpPriv->tPow2x2g24HeavyClipOffset = 0;
3824 if (hpPriv->enableBBHeavyClip)
3825 {
3826 ctlOffset = 2;
3827 }
3828 else
3829 {
3830 ctlOffset = 0;
3831 }
3832 for (i=0; i<4; i++)
3833 {
3834 if (((frequency == 2412) || (frequency == 2462)))
3835 {
3836 if (i != 0)
3837 {
3838 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G-ctlOffset) + HALTX_POWER_OFFSET;
3839 }
3840 else
3841 {
3842 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET;
3843 if (hpPriv->tPow2x2g[i] > (ctlEdgesMaxPower2G-ctlOffset))
3844 {
3845 hpPriv->tPow2x2g24HeavyClipOffset = hpPriv->tPow2x2g[i] - (ctlEdgesMaxPower2G-ctlOffset);
3846 }
3847 }
3848 }
3849 else
3850 {
3851 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET;
3852 }
3853 }
3854 for (i=0; i<8; i++)
3855 {
3856 if (((frequency == 2412) || (frequency == 2462)) && (i>=3))
3857 {
3858 hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20-ctlOffset) + HALTX_POWER_OFFSET;
3859 }
3860 else
3861 {
3862 hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20) + HALTX_POWER_OFFSET;
3863 }
3864 }
3865 for (i=0; i<8; i++)
3866 {
3867 if ((frequency == 2412) && (i>=3))
3868 {
3869 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-ctlOffset) + HALTX_POWER_OFFSET;
3870 }
3871 else if ((frequency == 2462) && (i>=3))
3872 {
3873 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-(ctlOffset*2)) + HALTX_POWER_OFFSET;
3874 }
3875 else
3876 {
3877 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40) + HALTX_POWER_OFFSET;
3878 }
3879 }
3880 }
3881 else
3882 {
3883 /* 5G - CTL_11A */
3884 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A);
3885 if(ctl_i<AR5416_NUM_CTLS)
3886 {
3887 ctlEdgesMaxPower5G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3888 }
3889 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3890 zm_dbg(("CTL_11A ctl_i = %d\n", ctl_i));
3891 #endif
3892
3893 /* 5G - CTL_5GHT20 */
3894 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT20);
3895 if(ctl_i<AR5416_NUM_CTLS)
3896 {
3897 ctlEdgesMaxPower5GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3898 }
3899 else
3900 {
3901 /* workaround for no data in Eeprom, replace by normal 5G */
3902 ctlEdgesMaxPower5GHT20 = ctlEdgesMaxPower5G;
3903 }
3904 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3905 zm_dbg(("CTL_5GHT20 ctl_i = %d\n", ctl_i));
3906 #endif
3907
3908 /* 5G - CTL_5GHT40 */
3909 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT40);
3910 if(ctl_i<AR5416_NUM_CTLS)
3911 {
3912 ctlEdgesMaxPower5GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1],
3913 zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset));
3914 }
3915 else
3916 {
3917 /* workaround for no data in Eeprom, replace by normal 5G */
3918 ctlEdgesMaxPower5GHT40 = ctlEdgesMaxPower5G;
3919 }
3920 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3921 zm_dbg(("CTL_5GHT40 ctl_i = %d\n", ctl_i));
3922 #endif
3923
3924 /* 7a17 : */
3925 /* Max power (dBm) for channel range when using DFS define by madwifi*/
3926 for (i=0; i<wd->regulationTable.allowChannelCnt; i++)
3927 {
3928 if (wd->regulationTable.allowChannel[i].channel == frequency)
3929 {
3930 if (zfHpIsDfsChannel(dev, (u16_t)frequency))
3931 {
3932 zm_debug_msg1("frequency use DFS -- ", frequency);
3933 ctlEdgesMaxPower5G = zm_min(ctlEdgesMaxPower5G, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3934 ctlEdgesMaxPower5GHT20 = zm_min(ctlEdgesMaxPower5GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3935 ctlEdgesMaxPower5GHT40 = zm_min(ctlEdgesMaxPower5GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3936 }
3937 break;
3938 }
3939 }
3940
3941
3942 /* Apply ctl mode to correct target power set */
3943 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3944 zm_debug_msg1("ctlEdgesMaxPower5G = ", ctlEdgesMaxPower5G);
3945 zm_debug_msg1("ctlEdgesMaxPower5GHT20 = ", ctlEdgesMaxPower5GHT20);
3946 zm_debug_msg1("ctlEdgesMaxPower5GHT40 = ", ctlEdgesMaxPower5GHT40);
3947 #endif
3948 for (i=0; i<4; i++)
3949 {
3950 hpPriv->tPow2x5g[i] = zm_min(hpPriv->tPow2x5g[i], ctlEdgesMaxPower5G) + HALTX_POWER_OFFSET;
3951 }
3952 for (i=0; i<8; i++)
3953 {
3954 hpPriv->tPow2x5gHt20[i] = zm_min(hpPriv->tPow2x5gHt20[i], ctlEdgesMaxPower5GHT20) + HALTX_POWER_OFFSET;
3955 }
3956 for (i=0; i<8; i++)
3957 {
3958 hpPriv->tPow2x5gHt40[i] = zm_min(hpPriv->tPow2x5gHt40[i], ctlEdgesMaxPower5GHT40) + HALTX_POWER_OFFSET;
3959 }
3960
3961 }/* end of bandedges of 5G */
3962 }/* end of if ((desired_CtlIndex = zfHpGetRegulatoryDomain(dev)) == 0) */
3963
3964 /* workaround */
3965 /* 5. BB heavy clip */
3966 /* only 2.4G do heavy clip */
3967 if (hpPriv->enableBBHeavyClip && hpPriv->hwBBHeavyClip && (frequency <= ZM_CH_G_14))
3968 {
3969 if (frequency <= ZM_CH_G_14)
3970 {
3971 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G);
3972 }
3973 else
3974 {
3975 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A);
3976 }
3977
3978 hpPriv->setValueHeavyClip = zfHpCheckDoHeavyClip(dev, frequency, eepromImage->ctlData[ctl_i].ctlEdges[1], bw40);
3979
3980 if (hpPriv->setValueHeavyClip)
3981 {
3982 hpPriv->doBBHeavyClip = 1;
3983 }
3984 else
3985 {
3986 hpPriv->doBBHeavyClip = 0;
3987 }
3988 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3989 zm_dbg(("zfHpCheckDoHeavyClip ret = %02x, doBBHeavyClip = %d\n",
3990 hpPriv->setValueHeavyClip, hpPriv->doBBHeavyClip));
3991 #endif
3992
3993 if (hpPriv->doBBHeavyClip)
3994 {
3995 if (hpPriv->setValueHeavyClip & 0xf0)
3996 {
3997 hpPriv->tPow2x2gHt40[0] -= 1;
3998 hpPriv->tPow2x2gHt40[1] -= 1;
3999 hpPriv->tPow2x2gHt40[2] -= 1;
4000 }
4001
4002 if (hpPriv->setValueHeavyClip & 0xf)
4003 {
4004 hpPriv->tPow2x2gHt20[0] += 1;
4005 hpPriv->tPow2x2gHt20[1] += 1;
4006 hpPriv->tPow2x2gHt20[2] += 1;
4007 }
4008 }
4009 }
4010 else
4011 {
4012 hpPriv->doBBHeavyClip = 0;
4013 hpPriv->setValueHeavyClip = 0;
4014 }
4015
4016 /* Final : write MAC register for some ctrl frame Tx power */
4017 /* first part : 2.4G */
4018 if (frequency <= ZM_CH_G_14)
4019 {
4020 /* Write MAC reg 0x694 for ACK's TPC */
4021 /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */
4022 /* Always use two stream for low legacy rate */
4023 #if 0
4024 //if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
4025 //{
4026 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x1<<26));
4027 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x1<<11) |
4028 ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x1<<27) );
4029 //}
4030 #endif
4031 #if 1
4032 //else
4033 {
4034 #ifndef ZM_OTUS_LINUX_PHASE_2
4035 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x5<<26));
4036 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x5<<11) |
4037 ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x5<<27) );
4038 #endif
4039 hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0];
4040 }
4041 #endif
4042 zfFlushDelayWrite(dev);
4043
4044 zfPrintTargetPower2G(hpPriv->tPow2xCck,
4045 hpPriv->tPow2x2g,
4046 hpPriv->tPow2x2gHt20,
4047 hpPriv->tPow2x2gHt40);
4048 }
4049 else
4050 {
4051 /* Write MAC reg 0x694 for ACK's TPC */
4052 /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */
4053 /* Always use two stream for low legacy rate */
4054 if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
4055 {
4056 #ifndef ZM_OTUS_LINUX_PHASE_2
4057 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x1<<26));
4058 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x1<<11) |
4059 ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x1<<27) );
4060 #endif
4061 }
4062 else
4063 {
4064 #ifndef ZM_OTUS_LINUX_PHASE_2
4065 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x5<<26));
4066 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x5<<11) |
4067 ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x5<<27) );
4068 #endif
4069 hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0];
4070 }
4071
4072
4073 zfFlushDelayWrite(dev);
4074
4075 zfPrintTargetPower5G(
4076 hpPriv->tPow2x5g,
4077 hpPriv->tPow2x5gHt20,
4078 hpPriv->tPow2x5gHt40);
4079 }/* end of bandedges of 5G */
4080
4081 }
4082
4083 void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage)
4084 {
4085 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4086 u8_t i, j, k;
4087
4088 #if 0
4089 zm_dbg(("\n === BandEdges index dump ==== \n"));
4090
4091 for (i = 0; i < AR5416_NUM_CTLS; i++)
4092 {
4093 zm_dbg(("%02x ", eepromImage->ctlIndex[i]));
4094 }
4095
4096 zm_dbg(("\n === BandEdges data dump ==== \n"));
4097
4098 for (i = 0; i < AR5416_NUM_CTLS; i++)
4099 {
4100 for (j = 0; j < 2; j++)
4101 {
4102 for(k = 0; k < AR5416_NUM_BAND_EDGES; k++)
4103 {
4104 u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j][k]);
4105 zm_dbg(("(%02x %02x)", pdata[0], pdata[1]));
4106 }
4107 zm_dbg(("\n"));
4108 }
4109 }
4110 #else
4111 zm_dbg(("\n === BandEdges index dump ==== \n"));
4112 for (i = 0; i < 24; i+=8)
4113 {
4114 zm_dbg(("%02x %02x %02x %02x %02x %02x %02x %02x",
4115 eepromImage->ctlIndex[i+0], eepromImage->ctlIndex[i+1], eepromImage->ctlIndex[i+2], eepromImage->ctlIndex[i+3],
4116 eepromImage->ctlIndex[i+4], eepromImage->ctlIndex[i+5], eepromImage->ctlIndex[i+6], eepromImage->ctlIndex[i+7]
4117 ));
4118 }
4119
4120 zm_dbg(("\n === BandEdges data dump ==== \n"));
4121
4122 for (i = 0; i < AR5416_NUM_CTLS; i++)
4123 {
4124 for (j = 0; j < 2; j++)
4125 {
4126 u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j]);
4127 zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n",
4128 pdata[0], pdata[1], pdata[2], pdata[3],
4129 pdata[4], pdata[5], pdata[6], pdata[7]
4130 ));
4131 zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n",
4132 pdata[8], pdata[9], pdata[10], pdata[11],
4133 pdata[12], pdata[13], pdata[14], pdata[15]
4134 ));
4135 }
4136 }
4137 #endif
4138 #endif
4139 }
4140
4141 void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40)
4142 {
4143 //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
4144 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4145 DbgPrint("targetPwr CCK : %d, %d, %d, %d\n",
4146 tPow2xCck[0],
4147 tPow2xCck[1],
4148 tPow2xCck[2],
4149 tPow2xCck[3]
4150 );
4151 DbgPrint("targetPwr 2G : %d, %d, %d, %d\n",
4152 tPow2x2g[0],
4153 tPow2x2g[1],
4154 tPow2x2g[2],
4155 tPow2x2g[3]
4156 );
4157 DbgPrint("targetPwr 2GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4158 tPow2x2gHt20[0],
4159 tPow2x2gHt20[1],
4160 tPow2x2gHt20[2],
4161 tPow2x2gHt20[3],
4162 tPow2x2gHt20[4],
4163 tPow2x2gHt20[5],
4164 tPow2x2gHt20[6],
4165 tPow2x2gHt20[7]
4166 );
4167 DbgPrint("targetPwr 2GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4168 tPow2x2gHt40[0],
4169 tPow2x2gHt40[1],
4170 tPow2x2gHt40[2],
4171 tPow2x2gHt40[3],
4172 tPow2x2gHt40[4],
4173 tPow2x2gHt40[5],
4174 tPow2x2gHt40[6],
4175 tPow2x2gHt40[7]
4176 );
4177 #endif
4178 return;
4179 }
4180
4181 void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40)
4182 {
4183 //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
4184 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4185 DbgPrint("targetPwr 5G : %d, %d, %d, %d\n",
4186 tPow2x5g[0],
4187 tPow2x5g[1],
4188 tPow2x5g[2],
4189 tPow2x5g[3]
4190 );
4191 DbgPrint("targetPwr 5GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4192 tPow2x5gHt20[0],
4193 tPow2x5gHt20[1],
4194 tPow2x5gHt20[2],
4195 tPow2x5gHt20[3],
4196 tPow2x5gHt20[4],
4197 tPow2x5gHt20[5],
4198 tPow2x5gHt20[6],
4199 tPow2x5gHt20[7]
4200 );
4201 DbgPrint("targetPwr 5GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4202 tPow2x5gHt40[0],
4203 tPow2x5gHt40[1],
4204 tPow2x5gHt40[2],
4205 tPow2x5gHt40[3],
4206 tPow2x5gHt40[4],
4207 tPow2x5gHt40[5],
4208 tPow2x5gHt40[6],
4209 tPow2x5gHt40[7]
4210 );
4211 #endif
4212 return;
4213 }
4214
4215 void zfHpPowerSaveSetMode(zdev_t* dev, u8_t staMode, u8_t psMode, u16_t bcnInterval)
4216 {
4217 if ( staMode == 0 )
4218 {
4219 if ( psMode == 0 )
4220 {
4221 // Turn off pre-TBTT interrupt
4222 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, 0);
4223 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0);
4224 zfFlushDelayWrite(dev);
4225 }
4226 else
4227 {
4228 // Turn on pre-TBTT interrupt
4229 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16);
4230 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, bcnInterval);
4231 zfFlushDelayWrite(dev);
4232 }
4233 }
4234 }
4235
4236 void zfHpPowerSaveSetState(zdev_t* dev, u8_t psState)
4237 {
4238 struct zsHpPriv* hpPriv;
4239
4240 zmw_get_wlan_dev(dev);
4241 hpPriv = wd->hpPrivate;
4242
4243 //DbgPrint("INTO zfHpPowerSaveSetState");
4244
4245 if ( psState == 0 ) //power up
4246 {
4247 //DbgPrint("zfHpPowerSaveSetState Wake up from PS\n");
4248 reg_write(0x982C, 0x0000a000); //wake up ADDAC
4249 reg_write(0x9808, 0x0); //enable all agc gain and offset updates to a2
4250 //# bank 3
4251 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14)
4252 {
4253 /* 11g */
4254 //reg_write (0x98f0, 0x01c00018);
4255 reg_write (0x98f0, 0x01c20098);//syn_on+RX_ON
4256 }
4257 else
4258 {
4259 /* 11a */
4260 //reg_write (0x98f0, 0x01400018);
4261 reg_write (0x98f0, 0x01420098);//syn_on+RX_ON
4262 }
4263
4264 ////#bank 5
4265 //reg_write(0x98b0, 0x00000013);
4266 //reg_write(0x98e4, 0x00000002);
4267
4268
4269 zfFlushDelayWrite(dev);
4270 }
4271 else //power down
4272 {
4273 //DbgPrint("zfHpPowerSaveSetState Go to PS\n");
4274 //reg_write(0x982C, 0xa000a000);
4275 reg_write(0x9808, 0x8000000); //disable all agc gain and offset updates to a2
4276 reg_write(0x982C, 0xa000a000); //power down ADDAC
4277 //# bank 3
4278 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14)
4279 {
4280 /* 11g */
4281 reg_write (0x98f0, 0x00c00018);//syn_off+RX_off
4282 }
4283 else
4284 {
4285 /* 11a */
4286 reg_write (0x98f0, 0x00400018);//syn_off+RX_off
4287 }
4288
4289 ////#bank 5
4290 //reg_write(0x98b0, 0x000e0013);
4291 //reg_write(0x98e4, 0x00018002);
4292
4293
4294 zfFlushDelayWrite(dev);
4295 }
4296 }
4297
4298 void zfHpSetAggPktNum(zdev_t* dev, u32_t num)
4299 {
4300 struct zsHpPriv* hpPriv;
4301
4302 zmw_get_wlan_dev(dev);
4303 hpPriv = wd->hpPrivate;
4304
4305 num = (num << 16) | (0xa);
4306
4307 hpPriv->aggPktNum = num;
4308
4309 //aggregation number will be update in HAL heart beat
4310 //zfDelayWriteInternalReg(dev, 0x1c3b9c, num);
4311 //zfFlushDelayWrite(dev);
4312 }
4313
4314 void zfHpSetMPDUDensity(zdev_t* dev, u8_t density)
4315 {
4316 u32_t value;
4317
4318 if (density > ZM_MPDU_DENSITY_8US)
4319 {
4320 return;
4321 }
4322
4323 /* Default value in this register */
4324 value = 0x140A00 | density;
4325
4326 zfDelayWriteInternalReg(dev, 0x1c3ba0, value);
4327 zfFlushDelayWrite(dev);
4328 return;
4329 }
4330
4331 void zfHpSetSlotTime(zdev_t* dev, u8_t type)
4332 {
4333 struct zsHpPriv* hpPriv;
4334
4335 zmw_get_wlan_dev(dev);
4336 hpPriv = wd->hpPrivate;
4337
4338 if (type == 0)
4339 {
4340 //normal slot = 20us
4341 hpPriv->slotType = 0;
4342 }
4343 else //if (type == 1)
4344 {
4345 //short slot = 9us
4346 hpPriv->slotType = 1;
4347 }
4348
4349 return;
4350 }
4351
4352 void zfHpSetSlotTimeRegister(zdev_t* dev, u8_t type)
4353 {
4354 if(type == 0)
4355 {
4356 //normal slot = 20us
4357 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 20<<10);
4358 }
4359 else
4360 {
4361 //short slot = 9us
4362 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10);
4363 }
4364 }
4365
4366 void zfHpSetRifs(zdev_t* dev, u8_t ht_enable, u8_t ht2040, u8_t g_mode)
4367 {
4368 zfDelayWriteInternalReg(dev, 0x1c6388, 0x0c000000);
4369
4370 zfDelayWriteInternalReg(dev, 0x1c59ec, 0x0cc80caa);
4371
4372 if (ht_enable)
4373 {
4374 if (ht2040)
4375 {
4376 zfDelayWriteInternalReg(dev, 0x1c5918, 40);
4377 }
4378 else
4379 {
4380 zfDelayWriteInternalReg(dev, 0x1c5918, 20);
4381 }
4382 }
4383
4384 if (g_mode)
4385 {
4386 zfDelayWriteInternalReg(dev, 0x1c5850, 0xec08b4e2);
4387 zfDelayWriteInternalReg(dev, 0x1c585c, 0x313a5d5e);
4388 }
4389 else
4390 {
4391 zfDelayWriteInternalReg(dev, 0x1c5850, 0xede8b4e0);
4392 zfDelayWriteInternalReg(dev, 0x1c585c, 0x3139605e);
4393 }
4394
4395 zfFlushDelayWrite(dev);
4396 return;
4397 }
4398
4399 void zfHpBeginSiteSurvey(zdev_t* dev, u8_t status)
4400 {
4401 struct zsHpPriv* hpPriv;
4402
4403 zmw_get_wlan_dev(dev);
4404 hpPriv=wd->hpPrivate;
4405
4406 if ( status == 1 )
4407 { // Connected
4408 hpPriv->isSiteSurvey = 1;
4409 }
4410 else
4411 { // Not connected
4412 hpPriv->isSiteSurvey = 0;
4413 }
4414
4415 /* reset workaround state to default */
4416 // if (hpPriv->rxStrongRSSI == 1)
4417 {
4418 hpPriv->rxStrongRSSI = 0;
4419 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
4420 {
4421 if (hpPriv->hwFrequency <= ZM_CH_G_14)
4422 {
4423 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
4424 }
4425 else
4426 {
4427 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
4428 }
4429 }
4430 else
4431 {
4432 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40);
4433 }
4434 zfFlushDelayWrite(dev);
4435 }
4436 // if (hpPriv->strongRSSI == 1)
4437 {
4438 hpPriv->strongRSSI = 0;
4439 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26));
4440 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) |
4441 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27) );
4442 zfFlushDelayWrite(dev);
4443 }
4444 }
4445
4446 void zfHpFinishSiteSurvey(zdev_t* dev, u8_t status)
4447 {
4448 struct zsHpPriv* hpPriv;
4449
4450 zmw_get_wlan_dev(dev);
4451 hpPriv=wd->hpPrivate;
4452
4453 zmw_declare_for_critical_section();
4454
4455 zmw_enter_critical_section(dev);
4456 if ( status == 1 )
4457 {
4458 hpPriv->isSiteSurvey = 2;
4459 }
4460 else
4461 {
4462 hpPriv->isSiteSurvey = 0;
4463 }
4464 zmw_leave_critical_section(dev);
4465 }
4466
4467 u16_t zfFwRetry(zdev_t* dev, u8_t enable)
4468 {
4469 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
4470 u16_t ret = 0;
4471
4472 cmd[0] = 4 | (0x92 << 8);
4473 cmd[1] = (enable == 1) ? 0x01 : 0x00;
4474
4475 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
4476 return ret;
4477 }
4478
4479 u16_t zfHpEnableHwRetry(zdev_t* dev)
4480 {
4481 u16_t ret;
4482
4483 ret = zfFwRetry(dev, 0);
4484
4485 zfDelayWriteInternalReg(dev, 0x1c3b28, 0x33333);
4486 zfFlushDelayWrite(dev);
4487
4488 return ret;
4489 }
4490
4491 u16_t zfHpDisableHwRetry(zdev_t* dev)
4492 {
4493 u16_t ret;
4494
4495 ret = zfFwRetry(dev, 1);
4496
4497 zfDelayWriteInternalReg(dev, 0x1c3b28, 0x00000);
4498 zfFlushDelayWrite(dev);
4499
4500 return ret;
4501 }
4502
4503 /* Download SPI Fw */
4504 #define ZM_FIRMWARE_WLAN 0
4505 #define ZM_FIRMWARE_SPI_FLASH 1
4506
4507
4508 u16_t zfHpFirmwareDownload(zdev_t* dev, u8_t fwType)
4509 {
4510 u16_t ret = ZM_SUCCESS;
4511
4512 if (fwType == ZM_FIRMWARE_WLAN)
4513 {
4514 ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
4515 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
4516 }
4517 else if (fwType == ZM_FIRMWARE_SPI_FLASH)
4518 {
4519 ret = zfFirmwareDownload(dev, (u32_t*)zcFwImageSPI,
4520 (u32_t)zcFwImageSPISize, ZM_FIRMWARE_SPI_ADDR);
4521 }
4522 else
4523 {
4524 zm_debug_msg1("Unknown firmware type = ", fwType);
4525 ret = ZM_ERR_FIRMWARE_WRONG_TYPE;
4526 }
4527
4528 return ret;
4529 }
4530
4531 /* Enable software decryption */
4532 void zfHpSWDecrypt(zdev_t* dev, u8_t enable)
4533 {
4534 u32_t value = 0x70;
4535
4536 /* Bit 4 for enable software decryption */
4537 if (enable == 1)
4538 {
4539 value = 0x78;
4540 }
4541
4542 zfDelayWriteInternalReg(dev, 0x1c3678, value);
4543 zfFlushDelayWrite(dev);
4544 }
4545
4546 /* Enable software encryption */
4547 void zfHpSWEncrypt(zdev_t* dev, u8_t enable)
4548 {
4549 /* Because encryption by software or hardware is judged by driver in Otus,
4550 we don't need to do anything in the HAL layer.
4551 */
4552 }
4553
4554 u32_t zfHpCapability(zdev_t* dev)
4555 {
4556 struct zsHpPriv* hpPriv;
4557
4558 zmw_get_wlan_dev(dev);
4559 hpPriv=wd->hpPrivate;
4560
4561 return hpPriv->halCapability;
4562 }
4563
4564 void zfHpSetRollCallTable(zdev_t* dev)
4565 {
4566 struct zsHpPriv* hpPriv;
4567
4568 zmw_get_wlan_dev(dev);
4569 hpPriv=wd->hpPrivate;
4570
4571 if (hpPriv->camRollCallTable != (u64_t) 0)
4572 {
4573 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, (u32_t)(hpPriv->camRollCallTable & 0xffffffff));
4574 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, (u32_t)((hpPriv->camRollCallTable >> 32) & 0xffffffff));
4575 zfFlushDelayWrite(dev);
4576 }
4577 }
4578
4579 void zfHpSetTTSIFSTime(zdev_t* dev, u8_t sifs_time)
4580 {
4581 u32_t reg_value = 0;
4582
4583 sifs_time &= 0x3f;
4584 reg_value = 0x14400b | (((u32_t)sifs_time)<<24);
4585
4586 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, reg_value);
4587 zfFlushDelayWrite(dev);
4588 }
4589
4590 /* #3 Enable RIFS function if the RIFS pattern matched ! */
4591 void zfHpEnableRifs(zdev_t* dev, u8_t mode24g, u8_t modeHt, u8_t modeHt2040)
4592 {
4593
4594 /* # Enable Reset TDOMAIN
4595 * $rddata = &$phyreg_read(0x9800+(738<<2));
4596 * $wrdata = $rddata | (0x1 << 26) | (0x1 << 27);
4597 * &$phyreg_write(0x9800+(738<<2), $wrdata);
4598 */
4599 reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26) | (0x1 << 27));
4600 //reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26));
4601
4602 /* # reg 123: heavy clip factor, xr / RIFS search parameters */
4603 reg_write (0x99ec, 0x0cc80caa);
4604
4605 /* # Reduce Search Start Delay for RIFS */
4606 if (modeHt == 1) /* ($HT_ENABLE == 1) */
4607 {
4608 if (modeHt2040 == 0x1) /* ($DYNAMIC_HT2040_EN == 0x1) */
4609 {
4610 reg_write(0x9800+(70<<2), 40);/*40*/
4611 }
4612 else
4613 {
4614 reg_write(0x9800+(70<<2), 20);
4615 if(mode24g == 0x0)
4616 {
4617 /* $rddata = &$phyreg_read(0x9800+(24<<2));#0x9860;0x1c5860
4618 *$wrdata = ($rddata & 0xffffffc7) | (0x4 << 3);
4619 * &$phyreg_write(0x9800+(24<<2), $wrdata);
4620 */
4621 reg_write(0x9800+(24<<2), (0x0004dd10 & 0xffffffc7) | (0x4 << 3));
4622 }
4623 }
4624 }
4625
4626 if (mode24g == 0x1)
4627 {
4628 reg_write(0x9850, 0xece8b4e4);/*org*/
4629 //reg_write(0x9850, 0xece8b4e2);
4630 reg_write(0x985c, 0x313a5d5e);
4631 }
4632 else
4633 {
4634 reg_write(0x9850, 0xede8b4e4);
4635 reg_write(0x985c, 0x3139605e);
4636 }
4637
4638 zfFlushDelayWrite(dev);
4639
4640 return;
4641 }
4642
4643 /* #4 Disable RIFS function if the RIFS timer is timeout ! */
4644 void zfHpDisableRifs(zdev_t* dev)
4645 {
4646 zmw_get_wlan_dev(dev);
4647
4648 /* Disable RIFS function is to store these HW register initial value while the device plug-in and
4649 re-write to these register if the RIFS function is disabled */
4650
4651 // reg : 9850
4652 reg_write(0x9850, ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize);
4653
4654 // reg : 985c
4655 reg_write(0x985c, ((struct zsHpPriv*)wd->hpPrivate)->initAGC);
4656
4657 // reg : 9860
4658 reg_write(0x9800+(24<<2), ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl);
4659
4660 // reg : 9918
4661 reg_write(0x9800+(70<<2), ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay);
4662
4663 // reg : 991c
4664 reg_write (0x99ec, ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams);
4665
4666 // reg : a388
4667 reg_write (0x9800+(738<<2), ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl);
4668
4669 zfFlushDelayWrite(dev);
4670
4671 return;
4672 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree