3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
15 * This file contains the low-level support and setup for the
16 * PowerPC-64 platform, including trap and interrupt dispatch.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
24 #include <linux/threads.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/iseries/lpar_map.h>
35 #include <asm/thread_info.h>
36 #include <asm/firmware.h>
37 #include <asm/page_64.h>
38 #include <asm/exception.h>
40 #define DO_SOFT_DISABLE
43 * We layout physical memory as follows:
44 * 0x0000 - 0x00ff : Secondary processor spin code
45 * 0x0100 - 0x2fff : pSeries Interrupt prologs
46 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
47 * 0x6000 - 0x6fff : Initial (CPU0) segment table
48 * 0x7000 - 0x7fff : FWNMI data area
49 * 0x8000 - : Early init and support code
57 * SPRG0 reserved for hypervisor
58 * SPRG1 temp - used to save gpr
59 * SPRG2 temp - used to save gpr
60 * SPRG3 virt addr of paca
64 * Entering into this code we make the following assumptions:
66 * 1. The MMU is off & open firmware is running in real mode.
67 * 2. The kernel is entered at __start
70 * 1. The MMU is on (as it always is for iSeries)
71 * 2. The kernel is entered at system_reset_iSeries
78 /* NOP this out unconditionally */
80 b .__start_initialization_multiplatform
83 /* Catch branch to 0 in real mode */
86 /* Secondary processors spin on this value until it goes to 1. */
87 .globl __secondary_hold_spinloop
88 __secondary_hold_spinloop:
91 /* Secondary processors write this value with their cpu # */
92 /* after they enter the spin loop immediately below. */
93 .globl __secondary_hold_acknowledge
94 __secondary_hold_acknowledge:
97 #ifdef CONFIG_PPC_ISERIES
99 * At offset 0x20, there is a pointer to iSeries LPAR data.
100 * This is required by the hypervisor
103 .llong hvReleaseData-KERNELBASE
104 #endif /* CONFIG_PPC_ISERIES */
108 * The following code is used to hold secondary processors
109 * in a spin loop after they have entered the kernel, but
110 * before the bulk of the kernel has been relocated. This code
111 * is relocated to physical address 0x60 before prom_init is run.
112 * All of it must fit below the first exception vector at 0x100.
114 _GLOBAL(__secondary_hold)
117 mtmsrd r24 /* RI on */
119 /* Grab our physical cpu number */
122 /* Tell the master cpu we're here */
123 /* Relocation is off & we are located at an address less */
124 /* than 0x100, so only need to grab low order offset. */
125 std r24,__secondary_hold_acknowledge@l(0)
128 /* All secondary cpus wait here until told to start. */
129 100: ld r4,__secondary_hold_spinloop@l(0)
133 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
134 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
142 /* This value is used to mark exception frames on the stack. */
145 .tc ID_72656773_68657265[TC],0x7265677368657265
149 * This is the start of the interrupt handlers for pSeries
150 * This code runs with relocation off.
153 .globl __start_interrupts
156 STD_EXCEPTION_PSERIES(0x100, system_reset)
159 _machine_check_pSeries:
161 mtspr SPRN_SPRG1,r13 /* save r13 */
162 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
165 .globl data_access_pSeries
174 rlwimi r13,r12,16,0x20
177 beq do_stab_bolted_pSeries
180 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
181 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
184 .globl data_access_slb_pSeries
185 data_access_slb_pSeries:
188 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
189 std r3,PACA_EXSLB+EX_R3(r13)
191 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
194 /* Keep that around for when we re-implement dynamic VSIDs */
196 bge slb_miss_user_pseries
197 #endif /* __DISABLED__ */
198 std r10,PACA_EXSLB+EX_R10(r13)
199 std r11,PACA_EXSLB+EX_R11(r13)
200 std r12,PACA_EXSLB+EX_R12(r13)
202 std r10,PACA_EXSLB+EX_R13(r13)
203 mfspr r12,SPRN_SRR1 /* and SRR1 */
204 b .slb_miss_realmode /* Rel. branch works in real mode */
206 STD_EXCEPTION_PSERIES(0x400, instruction_access)
209 .globl instruction_access_slb_pSeries
210 instruction_access_slb_pSeries:
213 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
214 std r3,PACA_EXSLB+EX_R3(r13)
215 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
216 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
219 /* Keep that around for when we re-implement dynamic VSIDs */
221 bge slb_miss_user_pseries
222 #endif /* __DISABLED__ */
223 std r10,PACA_EXSLB+EX_R10(r13)
224 std r11,PACA_EXSLB+EX_R11(r13)
225 std r12,PACA_EXSLB+EX_R12(r13)
227 std r10,PACA_EXSLB+EX_R13(r13)
228 mfspr r12,SPRN_SRR1 /* and SRR1 */
229 b .slb_miss_realmode /* Rel. branch works in real mode */
231 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
232 STD_EXCEPTION_PSERIES(0x600, alignment)
233 STD_EXCEPTION_PSERIES(0x700, program_check)
234 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
235 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
236 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
237 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
240 .globl system_call_pSeries
248 oris r12,r12,system_call_common@h
249 ori r12,r12,system_call_common@l
251 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
255 b . /* prevent speculative execution */
257 STD_EXCEPTION_PSERIES(0xd00, single_step)
258 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
260 /* We need to deal with the Altivec unavailable exception
261 * here which is at 0xf20, thus in the middle of the
262 * prolog code of the PerformanceMonitor one. A little
263 * trickery is thus necessary
266 b performance_monitor_pSeries
268 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
270 #ifdef CONFIG_CBE_RAS
271 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
272 #endif /* CONFIG_CBE_RAS */
273 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
274 #ifdef CONFIG_CBE_RAS
275 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
276 #endif /* CONFIG_CBE_RAS */
277 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
278 #ifdef CONFIG_CBE_RAS
279 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
280 #endif /* CONFIG_CBE_RAS */
284 /*** pSeries interrupt support ***/
286 /* moved from 0xf00 */
287 STD_EXCEPTION_PSERIES(., performance_monitor)
290 * An interrupt came in while soft-disabled; clear EE in SRR1,
291 * clear paca->hard_enabled and return.
294 stb r10,PACAHARDIRQEN(r13)
296 ld r9,PACA_EXGEN+EX_R9(r13)
298 rldicl r10,r10,48,1 /* clear MSR_EE */
301 ld r10,PACA_EXGEN+EX_R10(r13)
307 do_stab_bolted_pSeries:
310 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
313 * We have some room here we use that to put
314 * the peries slb miss user trampoline code so it's reasonably
315 * away from slb_miss_user_common to avoid problems with rfid
317 * This is used for when the SLB miss handler has to go virtual,
318 * which doesn't happen for now anymore but will once we re-implement
319 * dynamic VSIDs for shared page tables
322 slb_miss_user_pseries:
323 std r10,PACA_EXGEN+EX_R10(r13)
324 std r11,PACA_EXGEN+EX_R11(r13)
325 std r12,PACA_EXGEN+EX_R12(r13)
327 ld r11,PACA_EXSLB+EX_R9(r13)
328 ld r12,PACA_EXSLB+EX_R3(r13)
329 std r10,PACA_EXGEN+EX_R13(r13)
330 std r11,PACA_EXGEN+EX_R9(r13)
331 std r12,PACA_EXGEN+EX_R3(r13)
334 mfspr r11,SRR0 /* save SRR0 */
335 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
336 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
338 mfspr r12,SRR1 /* and SRR1 */
341 b . /* prevent spec. execution */
342 #endif /* __DISABLED__ */
345 * Vectors for the FWNMI option. Share common code.
347 .globl system_reset_fwnmi
351 mtspr SPRN_SPRG1,r13 /* save r13 */
352 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common)
354 .globl machine_check_fwnmi
358 mtspr SPRN_SPRG1,r13 /* save r13 */
359 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common)
361 /*** Common interrupt handlers ***/
363 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
366 * Machine check is different because we use a different
367 * save area: PACA_EXMC instead of PACA_EXGEN.
370 .globl machine_check_common
371 machine_check_common:
372 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
376 addi r3,r1,STACK_FRAME_OVERHEAD
377 bl .machine_check_exception
380 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
381 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
382 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
383 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
384 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
385 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
386 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
387 #ifdef CONFIG_ALTIVEC
388 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
390 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
392 #ifdef CONFIG_CBE_RAS
393 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
394 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
395 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
396 #endif /* CONFIG_CBE_RAS */
399 * Here we have detected that the kernel stack pointer is bad.
400 * R9 contains the saved CR, r13 points to the paca,
401 * r10 contains the (bad) kernel stack pointer,
402 * r11 and r12 contain the saved SRR0 and SRR1.
403 * We switch to using an emergency stack, save the registers there,
404 * and call kernel_bad_stack(), which panics.
407 ld r1,PACAEMERGSP(r13)
408 subi r1,r1,64+INT_FRAME_SIZE
429 lhz r12,PACA_TRAP_SAVE(r13)
431 addi r11,r1,INT_FRAME_SIZE
436 1: addi r3,r1,STACK_FRAME_OVERHEAD
441 * Return from an exception with minimal checks.
442 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
443 * If interrupts have been enabled, or anything has been
444 * done that might have changed the scheduling status of
445 * any task or sent any task a signal, you should use
446 * ret_from_except or ret_from_except_lite instead of this.
448 fast_exc_return_irq: /* restores irq state too */
451 stb r3,PACASOFTIRQEN(r13) /* restore paca->soft_enabled */
452 rldicl r4,r12,49,63 /* get MSR_EE to LSB */
453 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */
456 .globl fast_exception_return
457 fast_exception_return:
460 andi. r3,r12,MSR_RI /* check if RI is set */
463 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
466 ACCOUNT_CPU_USER_EXIT(r3, r4)
482 rldicl r10,r10,48,1 /* clear EE */
483 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */
491 b . /* prevent speculative execution */
495 1: addi r3,r1,STACK_FRAME_OVERHEAD
496 bl .unrecoverable_exception
500 * Here r13 points to the paca, r9 contains the saved CR,
501 * SRR0 and SRR1 are saved in r11 and r12,
502 * r9 - r13 are saved in paca->exgen.
505 .globl data_access_common
508 std r10,PACA_EXGEN+EX_DAR(r13)
510 stw r10,PACA_EXGEN+EX_DSISR(r13)
511 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
512 ld r3,PACA_EXGEN+EX_DAR(r13)
513 lwz r4,PACA_EXGEN+EX_DSISR(r13)
515 b .do_hash_page /* Try to handle as hpte fault */
518 .globl instruction_access_common
519 instruction_access_common:
520 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
524 b .do_hash_page /* Try to handle as hpte fault */
527 * Here is the common SLB miss user that is used when going to virtual
528 * mode for SLB misses, that is currently not used
532 .globl slb_miss_user_common
533 slb_miss_user_common:
535 std r3,PACA_EXGEN+EX_DAR(r13)
536 stw r9,PACA_EXGEN+EX_CCR(r13)
537 std r10,PACA_EXGEN+EX_LR(r13)
538 std r11,PACA_EXGEN+EX_SRR0(r13)
539 bl .slb_allocate_user
541 ld r10,PACA_EXGEN+EX_LR(r13)
542 ld r3,PACA_EXGEN+EX_R3(r13)
543 lwz r9,PACA_EXGEN+EX_CCR(r13)
544 ld r11,PACA_EXGEN+EX_SRR0(r13)
548 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
549 beq- unrecov_user_slb
557 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
563 ld r9,PACA_EXGEN+EX_R9(r13)
564 ld r10,PACA_EXGEN+EX_R10(r13)
565 ld r11,PACA_EXGEN+EX_R11(r13)
566 ld r12,PACA_EXGEN+EX_R12(r13)
567 ld r13,PACA_EXGEN+EX_R13(r13)
572 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
573 ld r4,PACA_EXGEN+EX_DAR(r13)
580 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
583 1: addi r3,r1,STACK_FRAME_OVERHEAD
584 bl .unrecoverable_exception
587 #endif /* __DISABLED__ */
591 * r13 points to the PACA, r9 contains the saved CR,
592 * r12 contain the saved SRR1, SRR0 is still ready for return
593 * r3 has the faulting address
594 * r9 - r13 are saved in paca->exslb.
595 * r3 is saved in paca->slb_r3
596 * We assume we aren't going to take any exceptions during this procedure.
598 _GLOBAL(slb_miss_realmode)
601 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
602 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
604 bl .slb_allocate_realmode
606 /* All done -- return from exception. */
608 ld r10,PACA_EXSLB+EX_LR(r13)
609 ld r3,PACA_EXSLB+EX_R3(r13)
610 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
611 #ifdef CONFIG_PPC_ISERIES
613 ld r11,PACALPPACAPTR(r13)
614 ld r11,LPPACASRR0(r11) /* get SRR0 value */
615 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
616 #endif /* CONFIG_PPC_ISERIES */
620 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
626 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
629 #ifdef CONFIG_PPC_ISERIES
633 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
634 #endif /* CONFIG_PPC_ISERIES */
635 ld r9,PACA_EXSLB+EX_R9(r13)
636 ld r10,PACA_EXSLB+EX_R10(r13)
637 ld r11,PACA_EXSLB+EX_R11(r13)
638 ld r12,PACA_EXSLB+EX_R12(r13)
639 ld r13,PACA_EXSLB+EX_R13(r13)
641 b . /* prevent speculative execution */
644 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
647 1: addi r3,r1,STACK_FRAME_OVERHEAD
648 bl .unrecoverable_exception
652 .globl hardware_interrupt_common
653 .globl hardware_interrupt_entry
654 hardware_interrupt_common:
655 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
657 hardware_interrupt_entry:
660 bl .ppc64_runlatch_on
661 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
662 addi r3,r1,STACK_FRAME_OVERHEAD
664 b .ret_from_except_lite
666 #ifdef CONFIG_PPC_970_NAP
669 std r9,TI_LOCAL_FLAGS(r11)
670 ld r10,_LINK(r1) /* make idle task do the */
671 std r10,_NIP(r1) /* equivalent of a blr */
676 .globl alignment_common
679 std r10,PACA_EXGEN+EX_DAR(r13)
681 stw r10,PACA_EXGEN+EX_DSISR(r13)
682 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
683 ld r3,PACA_EXGEN+EX_DAR(r13)
684 lwz r4,PACA_EXGEN+EX_DSISR(r13)
688 addi r3,r1,STACK_FRAME_OVERHEAD
690 bl .alignment_exception
694 .globl program_check_common
695 program_check_common:
696 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
698 addi r3,r1,STACK_FRAME_OVERHEAD
700 bl .program_check_exception
704 .globl fp_unavailable_common
705 fp_unavailable_common:
706 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
707 bne 1f /* if from user, just load it up */
709 addi r3,r1,STACK_FRAME_OVERHEAD
711 bl .kernel_fp_unavailable_exception
716 .globl altivec_unavailable_common
717 altivec_unavailable_common:
718 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
719 #ifdef CONFIG_ALTIVEC
721 bne .load_up_altivec /* if from user, just load it up */
722 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
725 addi r3,r1,STACK_FRAME_OVERHEAD
727 bl .altivec_unavailable_exception
730 #ifdef CONFIG_ALTIVEC
732 * load_up_altivec(unused, unused, tsk)
733 * Disable VMX for the task which had it previously,
734 * and save its vector registers in its thread_struct.
735 * Enables the VMX for use in the kernel on return.
736 * On SMP we know the VMX is free, since we give it up every
737 * switch (ie, no lazy save of the vector registers).
738 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
740 _STATIC(load_up_altivec)
741 mfmsr r5 /* grab the current MSR */
743 mtmsrd r5 /* enable use of VMX now */
747 * For SMP, we don't do lazy VMX switching because it just gets too
748 * horrendously complex, especially when a task switches from one CPU
749 * to another. Instead we call giveup_altvec in switch_to.
750 * VRSAVE isn't dealt with here, that is done in the normal context
751 * switch code. Note that we could rely on vrsave value to eventually
752 * avoid saving all of the VREGs here...
755 ld r3,last_task_used_altivec@got(r2)
759 /* Save VMX state to last_task_used_altivec's THREAD struct */
765 /* Disable VMX for last_task_used_altivec */
767 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
770 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
772 #endif /* CONFIG_SMP */
773 /* Hack: if we get an altivec unavailable trap with VRSAVE
774 * set to all zeros, we assume this is a broken application
775 * that fails to set it properly, and thus we switch it to
784 /* enable use of VMX after return */
785 ld r4,PACACURRENT(r13)
786 addi r5,r4,THREAD /* Get THREAD */
787 oris r12,r12,MSR_VEC@h
791 stw r4,THREAD_USED_VR(r5)
796 /* Update last_task_used_math to 'current' */
797 subi r4,r5,THREAD /* Back to 'current' */
799 #endif /* CONFIG_SMP */
800 /* restore registers and return */
801 b fast_exception_return
802 #endif /* CONFIG_ALTIVEC */
808 _GLOBAL(do_hash_page)
812 andis. r0,r4,0xa450 /* weird error? */
813 bne- handle_page_fault /* if not, try to insert a HPTE */
815 andis. r0,r4,0x0020 /* Is it a segment table fault? */
816 bne- do_ste_alloc /* If so handle it */
817 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
820 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
821 * accessing a userspace segment (even from the kernel). We assume
822 * kernel addresses always have the high bit set.
824 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
825 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
826 orc r0,r12,r0 /* MSR_PR | ~high_bit */
827 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
828 ori r4,r4,1 /* add _PAGE_PRESENT */
829 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
832 * On iSeries, we soft-disable interrupts here, then
833 * hard-enable interrupts so that the hash_page code can spin on
834 * the hash_table_lock without problems on a shared processor.
839 * r3 contains the faulting address
840 * r4 contains the required access permissions
841 * r5 contains the trap number
843 * at return r3 = 0 for success
845 bl .hash_page /* build HPTE if possible */
846 cmpdi r3,0 /* see if hash_page succeeded */
848 #ifdef DO_SOFT_DISABLE
851 * If we had interrupts soft-enabled at the point where the
852 * DSI/ISI occurred, and an interrupt came in during hash_page,
854 * We jump to ret_from_except_lite rather than fast_exception_return
855 * because ret_from_except_lite will check for and handle pending
856 * interrupts if necessary.
859 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
863 * Here we have interrupts hard-disabled, so it is sufficient
864 * to restore paca->{soft,hard}_enable and get out.
866 beq fast_exc_return_irq /* Return from exception on success */
867 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
869 /* For a hash failure, we don't bother re-enabling interrupts */
873 * hash_page couldn't handle it, set soft interrupt enable back
874 * to what it was before the trap. Note that .local_irq_restore
875 * handles any interrupts pending at this point.
878 bl .local_irq_restore
881 /* Here we have a page fault that hash_page can't handle. */
886 addi r3,r1,STACK_FRAME_OVERHEAD
892 addi r3,r1,STACK_FRAME_OVERHEAD
897 13: b .ret_from_except_lite
899 /* We have a page fault that hash_page could handle but HV refused
903 addi r3,r1,STACK_FRAME_OVERHEAD
908 /* here we have a segment miss */
910 bl .ste_allocate /* try to insert stab entry */
912 bne- handle_page_fault
913 b fast_exception_return
916 * r13 points to the PACA, r9 contains the saved CR,
917 * r11 and r12 contain the saved SRR0 and SRR1.
918 * r9 - r13 are saved in paca->exslb.
919 * We assume we aren't going to take any exceptions during this procedure.
920 * We assume (DAR >> 60) == 0xc.
923 _GLOBAL(do_stab_bolted)
924 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
925 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
927 /* Hash to the primary group */
928 ld r10,PACASTABVIRT(r13)
931 rldimi r10,r11,7,52 /* r10 = first ste of the group */
934 /* This is a kernel address, so protovsid = ESID */
935 ASM_VSID_SCRAMBLE(r11, r9)
936 rldic r9,r11,12,16 /* r9 = vsid << 12 */
938 /* Search the primary group for a free entry */
939 1: ld r11,0(r10) /* Test valid bit of the current ste */
946 /* Stick for only searching the primary group for now. */
947 /* At least for now, we use a very simple random castout scheme */
948 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
950 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
953 /* r10 currently points to an ste one past the group of interest */
954 /* make it point to the randomly selected entry */
956 or r10,r10,r11 /* r10 is the entry to invalidate */
958 isync /* mark the entry invalid */
960 rldicl r11,r11,56,1 /* clear the valid bit */
965 clrrdi r11,r11,28 /* Get the esid part of the ste */
968 2: std r9,8(r10) /* Store the vsid part of the ste */
971 mfspr r11,SPRN_DAR /* Get the new esid */
972 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
973 ori r11,r11,0x90 /* Turn on valid and kp */
974 std r11,0(r10) /* Put new entry back into the stab */
978 /* All done -- return from exception. */
979 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
980 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
985 mtcrf 0x80,r9 /* restore CR */
993 ld r9,PACA_EXSLB+EX_R9(r13)
994 ld r10,PACA_EXSLB+EX_R10(r13)
995 ld r11,PACA_EXSLB+EX_R11(r13)
996 ld r12,PACA_EXSLB+EX_R12(r13)
997 ld r13,PACA_EXSLB+EX_R13(r13)
999 b . /* prevent speculative execution */
1002 * Space for CPU0's segment table.
1004 * On iSeries, the hypervisor must fill in at least one entry before
1005 * we get control (with relocate on). The address is given to the hv
1006 * as a page number (see xLparMap below), so this must be at a
1007 * fixed address (the linker can't compute (u64)&initial_stab >>
1010 . = STAB0_OFFSET /* 0x6000 */
1016 * Data area reserved for FWNMI option.
1017 * This address (0x7000) is fixed by the RPA.
1020 .globl fwnmi_data_area
1023 /* iSeries does not use the FWNMI stuff, so it is safe to put
1024 * this here, even if we later allow kernels that will boot on
1025 * both pSeries and iSeries */
1026 #ifdef CONFIG_PPC_ISERIES
1030 .quad HvEsidsToMap /* xNumberEsids */
1031 .quad HvRangesToMap /* xNumberRanges */
1032 .quad STAB0_PAGE /* xSegmentTableOffs */
1033 .zero 40 /* xRsvd */
1034 /* xEsids (HvEsidsToMap entries of 2 quads) */
1035 .quad PAGE_OFFSET_ESID /* xKernelEsid */
1036 .quad PAGE_OFFSET_VSID /* xKernelVsid */
1037 .quad VMALLOC_START_ESID /* xKernelEsid */
1038 .quad VMALLOC_START_VSID /* xKernelVsid */
1039 /* xRanges (HvRangesToMap entries of 3 quads) */
1040 .quad HvPagesToMap /* xPages */
1041 .quad 0 /* xOffset */
1042 .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */
1044 #endif /* CONFIG_PPC_ISERIES */
1049 * On pSeries and most other platforms, secondary processors spin
1050 * in the following code.
1051 * At entry, r3 = this processor's number (physical cpu id)
1053 _GLOBAL(generic_secondary_smp_init)
1056 /* turn on 64-bit mode */
1059 /* Set up a paca value for this processor. Since we have the
1060 * physical cpu id in r24, we need to search the pacas to find
1061 * which logical id maps to our physical one.
1063 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1064 li r5,0 /* logical cpu id */
1065 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1066 cmpw r6,r24 /* Compare to our id */
1068 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1073 mr r3,r24 /* not found, copy phys to r3 */
1074 b .kexec_wait /* next kernel might do better */
1076 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1077 /* From now on, r24 is expected to be logical cpuid */
1080 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1085 b 3b /* Never go on non-SMP */
1088 beq 3b /* Loop until told to go */
1090 /* See if we need to call a cpu state restore handler */
1091 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1093 ld r23,CPU_SPEC_RESTORE(r23)
1100 4: /* Create a temp kernel stack for use before relocation is on. */
1101 ld r1,PACAEMERGSP(r13)
1102 subi r1,r1,STACK_FRAME_OVERHEAD
1109 andi. r0,r3,MSR_IR|MSR_DR
1116 b . /* prevent speculative execution */
1120 * Here is our main kernel entry point. We support currently 2 kind of entries
1121 * depending on the value of r5.
1123 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1126 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1127 * DT block, r4 is a physical pointer to the kernel itself
1130 _GLOBAL(__start_initialization_multiplatform)
1132 * Are we booted from a PROM Of-type client-interface ?
1136 b .__boot_from_prom /* yes -> prom */
1138 /* Save parameters */
1142 /* Make sure we are running in 64 bits mode */
1145 /* Setup some critical 970 SPRs before switching MMU off */
1148 cmpwi r0,0x39 /* 970 */
1150 cmpwi r0,0x3c /* 970FX */
1152 cmpwi r0,0x44 /* 970MP */
1154 cmpwi r0,0x45 /* 970GX */
1156 1: bl .__cpu_preinit_ppc970
1159 /* Switch off MMU if not already */
1160 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1163 b .__after_prom_start
1165 _INIT_STATIC(__boot_from_prom)
1166 /* Save parameters */
1174 * Align the stack to 16-byte boundary
1175 * Depending on the size and layout of the ELF sections in the initial
1176 * boot binary, the stack pointer will be unalignet on PowerMac
1180 /* Make sure we are running in 64 bits mode */
1183 /* put a relocation offset into r3 */
1186 LOAD_REG_IMMEDIATE(r2,__toc_start)
1190 /* Relocate the TOC from a virt addr to a real addr */
1193 /* Restore parameters */
1200 /* Do all of the interaction with OF client interface */
1202 /* We never return */
1205 _STATIC(__after_prom_start)
1208 * We need to run with __start at physical address PHYSICAL_START.
1209 * This will leave some code in the first 256B of
1210 * real memory, which are reserved for software use.
1211 * The remainder of the first page is loaded with the fixed
1212 * interrupt vectors. The next two pages are filled with
1213 * unknown exception placeholders.
1215 * Note: This process overwrites the OF exception vectors.
1216 * r26 == relocation offset
1221 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1223 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1225 // XXX FIXME: Use phys returned by OF (r30)
1226 add r4,r27,r26 /* source addr */
1227 /* current address of _start */
1228 /* i.e. where we are running */
1229 /* the source addr */
1231 cmpdi r4,0 /* In some cases the loader may */
1233 b .start_here_multiplatform /* have already put us at zero */
1234 /* so we can skip the copy. */
1235 1: LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1238 li r6,0x100 /* Start offset, the first 0x100 */
1239 /* bytes were copied earlier. */
1241 bl .copy_and_flush /* copy the first n bytes */
1242 /* this includes the code being */
1243 /* executed here. */
1245 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1246 mtctr r0 /* that we just made/relocated */
1249 4: LOAD_REG_IMMEDIATE(r5,klimit)
1251 ld r5,0(r5) /* get the value of klimit */
1253 bl .copy_and_flush /* copy the rest */
1254 b .start_here_multiplatform
1257 * Copy routine used to copy the kernel to start at physical address 0
1258 * and flush and invalidate the caches as needed.
1259 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1260 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1262 * Note: this routine *only* clobbers r0, r6 and lr
1264 _GLOBAL(copy_and_flush)
1267 4: li r0,8 /* Use the smallest common */
1268 /* denominator cache line */
1269 /* size. This results in */
1270 /* extra cache line flushes */
1271 /* but operation is correct. */
1272 /* Can't get cache line size */
1273 /* from NACA as it is being */
1276 mtctr r0 /* put # words/line in ctr */
1277 3: addi r6,r6,8 /* copy a cache line */
1281 dcbst r6,r3 /* write it to memory */
1283 icbi r6,r3 /* flush the icache line */
1295 #ifdef CONFIG_PPC_PMAC
1297 * On PowerMac, secondary processors starts from the reset vector, which
1298 * is temporarily turned into a call to one of the functions below.
1303 .globl __secondary_start_pmac_0
1304 __secondary_start_pmac_0:
1305 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1315 _GLOBAL(pmac_secondary_start)
1316 /* turn on 64-bit mode */
1319 /* Copy some CPU settings from CPU 0 */
1320 bl .__restore_cpu_ppc970
1322 /* pSeries do that early though I don't think we really need it */
1325 mtmsrd r3 /* RI on */
1327 /* Set up a paca value for this processor. */
1328 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1329 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1330 add r13,r13,r4 /* for this processor. */
1331 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1333 /* Create a temp kernel stack for use before relocation is on. */
1334 ld r1,PACAEMERGSP(r13)
1335 subi r1,r1,STACK_FRAME_OVERHEAD
1339 #endif /* CONFIG_PPC_PMAC */
1342 * This function is called after the master CPU has released the
1343 * secondary processors. The execution environment is relocation off.
1344 * The paca for this processor has the following fields initialized at
1346 * 1. Processor number
1347 * 2. Segment table pointer (virtual address)
1348 * On entry the following are set:
1349 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1350 * r24 = cpu# (in Linux terms)
1351 * r13 = paca virtual address
1352 * SPRG3 = paca virtual address
1354 .globl __secondary_start
1356 /* Set thread priority to MEDIUM */
1362 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1363 bl .early_setup_secondary
1365 /* Initialize the kernel stack. Just a repeat for iSeries. */
1366 LOAD_REG_ADDR(r3, current_set)
1367 sldi r28,r24,3 /* get current_set[cpu#] */
1369 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1370 std r1,PACAKSAVE(r13)
1372 /* Clear backchain so we get nice backtraces */
1376 /* enable MMU and jump to start_secondary */
1377 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1378 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1379 #ifdef CONFIG_PPC_ISERIES
1380 BEGIN_FW_FTR_SECTION
1382 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1384 BEGIN_FW_FTR_SECTION
1385 stb r7,PACASOFTIRQEN(r13)
1386 stb r7,PACAHARDIRQEN(r13)
1387 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1392 b . /* prevent speculative execution */
1395 * Running with relocation on at this point. All we want to do is
1396 * zero the stack back-chain pointer before going into C code.
1398 _GLOBAL(start_secondary_prolog)
1400 std r3,0(r1) /* Zero the stack frame pointer */
1406 * This subroutine clobbers r11 and r12
1408 _GLOBAL(enable_64b_mode)
1409 mfmsr r11 /* grab the current MSR */
1411 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1414 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1421 * This is where the main kernel code starts.
1423 _INIT_STATIC(start_here_multiplatform)
1424 /* get a new offset, now that the kernel has moved. */
1428 /* Clear out the BSS. It may have been done in prom_init,
1429 * already but that's irrelevant since prom_init will soon
1430 * be detached from the kernel completely. Besides, we need
1431 * to clear it now for kexec-style entry.
1433 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1434 LOAD_REG_IMMEDIATE(r8,__bss_start)
1435 sub r11,r11,r8 /* bss size */
1436 addi r11,r11,7 /* round up to an even double word */
1437 rldicl. r11,r11,61,3 /* shift right by 3 */
1441 mtctr r11 /* zero this many doublewords */
1448 mtmsrd r6 /* RI on */
1450 /* The following gets the stack and TOC set up with the regs */
1451 /* pointing to the real addr of the kernel stack. This is */
1452 /* all done to support the C function call below which sets */
1453 /* up the htab. This is done because we have relocated the */
1454 /* kernel but are still running in real mode. */
1456 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1459 /* set up a stack pointer (physical address) */
1460 addi r1,r3,THREAD_SIZE
1462 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1464 /* set up the TOC (physical address) */
1465 LOAD_REG_IMMEDIATE(r2,__toc_start)
1470 /* Do very early kernel initializations, including initial hash table,
1471 * stab and slb setup before we turn on relocation. */
1473 /* Restore parameters passed from prom_init/kexec */
1477 LOAD_REG_IMMEDIATE(r3, .start_here_common)
1478 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1482 b . /* prevent speculative execution */
1484 /* This is where all platforms converge execution */
1485 _INIT_GLOBAL(start_here_common)
1486 /* relocation is on at this point */
1488 /* The following code sets up the SP and TOC now that we are */
1489 /* running with translation enabled. */
1491 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1493 /* set up the stack */
1494 addi r1,r3,THREAD_SIZE
1496 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1498 /* ptr to current */
1499 LOAD_REG_IMMEDIATE(r4, init_task)
1500 std r4,PACACURRENT(r13)
1504 std r1,PACAKSAVE(r13)
1508 /* Load up the kernel context */
1511 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
1512 #ifdef CONFIG_PPC_ISERIES
1513 BEGIN_FW_FTR_SECTION
1515 ori r5,r5,MSR_EE /* Hard Enabled */
1517 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1519 BEGIN_FW_FTR_SECTION
1520 stb r5,PACAHARDIRQEN(r13)
1521 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1529 * We put a few things here that have to be page-aligned.
1530 * This stuff goes at the beginning of the bss, which is page-aligned.
1536 .globl empty_zero_page
1540 .globl swapper_pg_dir