| blob | c86c626cf156431210fe70cacb50771cc7f2eaf8 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 *
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
24 #include <asm/reg.h>
25 #include <asm/page.h>
26 #include <asm/mmu.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/cache.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
34 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
35 #define LOAD_BAT(n, reg, RA, RB) \
36 /* see the comment for clear_bats() -- Cort */ \
37 li RA,0; \
38 mtspr SPRN_IBAT##n##U,RA; \
39 mtspr SPRN_DBAT##n##U,RA; \
40 lwz RA,(n*16)+0(reg); \
41 lwz RB,(n*16)+4(reg); \
42 mtspr SPRN_IBAT##n##U,RA; \
43 mtspr SPRN_IBAT##n##L,RB; \
44 beq 1f; \
45 lwz RA,(n*16)+8(reg); \
46 lwz RB,(n*16)+12(reg); \
47 mtspr SPRN_DBAT##n##U,RA; \
48 mtspr SPRN_DBAT##n##L,RB; \
49 1:
51 .section .text.head, "ax"
52 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
53 .stabs "head_32.S",N_SO,0,0,0f
54 0:
55 _ENTRY(_stext);
57 /*
58 * _start is defined this way because the XCOFF loader in the OpenFirmware
59 * on the powermac expects the entry point to be a procedure descriptor.
60 */
61 _ENTRY(_start);
62 /*
63 * These are here for legacy reasons, the kernel used to
64 * need to look like a coff function entry for the pmac
65 * but we're always started by some kind of bootloader now.
66 * -- Cort
67 */
68 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
69 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
70 nop
72 /* PMAC
73 * Enter here with the kernel text, data and bss loaded starting at
74 * 0, running with virtual == physical mapping.
75 * r5 points to the prom entry point (the client interface handler
76 * address). Address translation is turned on, with the prom
77 * managing the hash table. Interrupts are disabled. The stack
78 * pointer (r1) points to just below the end of the half-meg region
79 * from 0x380000 - 0x400000, which is mapped in already.
80 *
81 * If we are booted from MacOS via BootX, we enter with the kernel
82 * image loaded somewhere, and the following values in registers:
83 * r3: 'BooX' (0x426f6f58)
84 * r4: virtual address of boot_infos_t
85 * r5: 0
86 *
87 * PREP
88 * This is jumped to on prep systems right after the kernel is relocated
89 * to its proper place in memory by the boot loader. The expected layout
90 * of the regs is:
91 * r3: ptr to residual data
92 * r4: initrd_start or if no initrd then 0
93 * r5: initrd_end - unused if r4 is 0
94 * r6: Start of command line string
95 * r7: End of command line string
96 *
97 * This just gets a minimal mmu environment setup so we can call
98 * start_here() to do the real work.
99 * -- Cort
100 */
102 .globl __start
103 __start:
104 /*
105 * We have to do any OF calls before we map ourselves to KERNELBASE,
106 * because OF may have I/O devices mapped into that area
107 * (particularly on CHRP).
108 */
109 #ifdef CONFIG_PPC_MULTIPLATFORM
110 cmpwi 0,r5,0
111 beq 1f
112 bl prom_init
113 trap
114 #endif
116 /*
117 * Check for BootX signature when supporting PowerMac and branch to
118 * appropriate trampoline if it's present
119 */
120 #ifdef CONFIG_PPC_PMAC
121 1: lis r31,0x426f
122 ori r31,r31,0x6f58
123 cmpw 0,r3,r31
124 bne 1f
125 bl bootx_init
126 trap
127 #endif /* CONFIG_PPC_PMAC */
129 1: mr r31,r3 /* save parameters */
130 mr r30,r4
131 li r24,0 /* cpu # */
133 /*
134 * early_init() does the early machine identification and does
135 * the necessary low-level setup and clears the BSS
136 * -- Cort <cort@fsmlabs.com>
137 */
138 bl early_init
140 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
141 * the physical address we are running at, returned by early_init()
142 */
143 bl mmu_off
144 __after_mmu_off:
145 bl clear_bats
146 bl flush_tlbs
148 bl initial_bats
149 #if defined(CONFIG_BOOTX_TEXT)
150 bl setup_disp_bat
151 #endif
153 /*
154 * Call setup_cpu for CPU 0 and initialize 6xx Idle
155 */
156 bl reloc_offset
157 li r24,0 /* cpu# */
158 bl call_setup_cpu /* Call setup_cpu for this CPU */
159 #ifdef CONFIG_6xx
160 bl reloc_offset
161 bl init_idle_6xx
162 #endif /* CONFIG_6xx */
165 /*
166 * We need to run with _start at physical address 0.
167 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
168 * the exception vectors at 0 (and therefore this copy
169 * overwrites OF's exception vectors with our own).
170 * The MMU is off at this point.
171 */
172 bl reloc_offset
173 mr r26,r3
174 addis r4,r3,KERNELBASE@h /* current address of _start */
175 cmpwi 0,r4,0 /* are we already running at 0? */
176 bne relocate_kernel
177 /*
178 * we now have the 1st 16M of ram mapped with the bats.
179 * prep needs the mmu to be turned on here, but pmac already has it on.
180 * this shouldn't bother the pmac since it just gets turned on again
181 * as we jump to our code at KERNELBASE. -- Cort
182 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
183 * off, and in other cases, we now turn it off before changing BATs above.
184 */
185 turn_on_mmu:
186 mfmsr r0
187 ori r0,r0,MSR_DR|MSR_IR
188 mtspr SPRN_SRR1,r0
189 lis r0,start_here@h
190 ori r0,r0,start_here@l
191 mtspr SPRN_SRR0,r0
192 SYNC
193 RFI /* enables MMU */
195 /*
196 * We need __secondary_hold as a place to hold the other cpus on
197 * an SMP machine, even when we are running a UP kernel.
198 */
199 . = 0xc0 /* for prep bootloader */
200 li r3,1 /* MTX only has 1 cpu */
201 .globl __secondary_hold
202 __secondary_hold:
203 /* tell the master we're here */
204 stw r3,__secondary_hold_acknowledge@l(0)
205 #ifdef CONFIG_SMP
206 100: lwz r4,0(0)
207 /* wait until we're told to start */
208 cmpw 0,r4,r3
209 bne 100b
210 /* our cpu # was at addr 0 - go */
211 mr r24,r3 /* cpu # */
212 b __secondary_start
213 #else
214 b .
215 #endif /* CONFIG_SMP */
217 .globl __secondary_hold_spinloop
218 __secondary_hold_spinloop:
219 .long 0
220 .globl __secondary_hold_acknowledge
221 __secondary_hold_acknowledge:
222 .long -1
224 /*
225 * Exception entry code. This code runs with address translation
226 * turned off, i.e. using physical addresses.
227 * We assume sprg3 has the physical address of the current
228 * task's thread_struct.
229 */
230 #define EXCEPTION_PROLOG \
231 mtspr SPRN_SPRG0,r10; \
232 mtspr SPRN_SPRG1,r11; \
233 mfcr r10; \
234 EXCEPTION_PROLOG_1; \
235 EXCEPTION_PROLOG_2
237 #define EXCEPTION_PROLOG_1 \
238 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
239 andi. r11,r11,MSR_PR; \
240 tophys(r11,r1); /* use tophys(r1) if kernel */ \
241 beq 1f; \
242 mfspr r11,SPRN_SPRG3; \
243 lwz r11,THREAD_INFO-THREAD(r11); \
244 addi r11,r11,THREAD_SIZE; \
245 tophys(r11,r11); \
246 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
249 #define EXCEPTION_PROLOG_2 \
250 CLR_TOP32(r11); \
251 stw r10,_CCR(r11); /* save registers */ \
252 stw r12,GPR12(r11); \
253 stw r9,GPR9(r11); \
254 mfspr r10,SPRN_SPRG0; \
255 stw r10,GPR10(r11); \
256 mfspr r12,SPRN_SPRG1; \
257 stw r12,GPR11(r11); \
258 mflr r10; \
259 stw r10,_LINK(r11); \
260 mfspr r12,SPRN_SRR0; \
261 mfspr r9,SPRN_SRR1; \
262 stw r1,GPR1(r11); \
263 stw r1,0(r11); \
264 tovirt(r1,r11); /* set new kernel sp */ \
265 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
266 MTMSRD(r10); /* (except for mach check in rtas) */ \
267 stw r0,GPR0(r11); \
268 lis r10,0x7265; /* put exception frame marker */ \
269 addi r10,r10,0x6773; \
270 stw r10,8(r11); \
271 SAVE_4GPRS(3, r11); \
272 SAVE_2GPRS(7, r11)
274 /*
275 * Note: code which follows this uses cr0.eq (set if from kernel),
276 * r11, r12 (SRR0), and r9 (SRR1).
277 *
278 * Note2: once we have set r1 we are in a position to take exceptions
279 * again, and we could thus set MSR:RI at that point.
280 */
282 /*
283 * Exception vectors.
284 */
285 #define EXCEPTION(n, label, hdlr, xfer) \
286 . = n; \
287 label: \
288 EXCEPTION_PROLOG; \
289 addi r3,r1,STACK_FRAME_OVERHEAD; \
290 xfer(n, hdlr)
292 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
293 li r10,trap; \
294 stw r10,_TRAP(r11); \
295 li r10,MSR_KERNEL; \
296 copyee(r10, r9); \
297 bl tfer; \
298 i##n: \
299 .long hdlr; \
300 .long ret
302 #define COPY_EE(d, s) rlwimi d,s,0,16,16
303 #define NOCOPY(d, s)
305 #define EXC_XFER_STD(n, hdlr) \
306 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
307 ret_from_except_full)
309 #define EXC_XFER_LITE(n, hdlr) \
310 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
311 ret_from_except)
313 #define EXC_XFER_EE(n, hdlr) \
314 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
315 ret_from_except_full)
317 #define EXC_XFER_EE_LITE(n, hdlr) \
318 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
319 ret_from_except)
321 /* System reset */
322 /* core99 pmac starts the seconary here by changing the vector, and
323 putting it back to what it was (unknown_exception) when done. */
324 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
326 /* Machine check */
327 /*
328 * On CHRP, this is complicated by the fact that we could get a
329 * machine check inside RTAS, and we have no guarantee that certain
330 * critical registers will have the values we expect. The set of
331 * registers that might have bad values includes all the GPRs
332 * and all the BATs. We indicate that we are in RTAS by putting
333 * a non-zero value, the address of the exception frame to use,
334 * in SPRG2. The machine check handler checks SPRG2 and uses its
335 * value if it is non-zero. If we ever needed to free up SPRG2,
336 * we could use a field in the thread_info or thread_struct instead.
337 * (Other exception handlers assume that r1 is a valid kernel stack
338 * pointer when we take an exception from supervisor mode.)
339 * -- paulus.
340 */
341 . = 0x200
342 mtspr SPRN_SPRG0,r10
343 mtspr SPRN_SPRG1,r11
344 mfcr r10
345 #ifdef CONFIG_PPC_CHRP
346 mfspr r11,SPRN_SPRG2
347 cmpwi 0,r11,0
348 bne 7f
349 #endif /* CONFIG_PPC_CHRP */
350 EXCEPTION_PROLOG_1
351 7: EXCEPTION_PROLOG_2
352 addi r3,r1,STACK_FRAME_OVERHEAD
353 #ifdef CONFIG_PPC_CHRP
354 mfspr r4,SPRN_SPRG2
355 cmpwi cr1,r4,0
356 bne cr1,1f
357 #endif
358 EXC_XFER_STD(0x200, machine_check_exception)
359 #ifdef CONFIG_PPC_CHRP
360 1: b machine_check_in_rtas
361 #endif
363 /* Data access exception. */
364 . = 0x300
365 DataAccess:
366 EXCEPTION_PROLOG
367 mfspr r10,SPRN_DSISR
368 andis. r0,r10,0xa470 /* weird error? */
369 bne 1f /* if not, try to put a PTE */
370 mfspr r4,SPRN_DAR /* into the hash table */
371 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
372 bl hash_page
373 1: stw r10,_DSISR(r11)
374 mr r5,r10
375 mfspr r4,SPRN_DAR
376 EXC_XFER_EE_LITE(0x300, handle_page_fault)
379 /* Instruction access exception. */
380 . = 0x400
381 InstructionAccess:
382 EXCEPTION_PROLOG
383 andis. r0,r9,0x4000 /* no pte found? */
384 beq 1f /* if so, try to put a PTE */
385 li r3,0 /* into the hash table */
386 mr r4,r12 /* SRR0 is fault address */
387 bl hash_page
388 1: mr r4,r12
389 mr r5,r9
390 EXC_XFER_EE_LITE(0x400, handle_page_fault)
392 /* External interrupt */
393 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
395 /* Alignment exception */
396 . = 0x600
397 Alignment:
398 EXCEPTION_PROLOG
399 mfspr r4,SPRN_DAR
400 stw r4,_DAR(r11)
401 mfspr r5,SPRN_DSISR
402 stw r5,_DSISR(r11)
403 addi r3,r1,STACK_FRAME_OVERHEAD
404 EXC_XFER_EE(0x600, alignment_exception)
406 /* Program check exception */
407 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
409 /* Floating-point unavailable */
410 . = 0x800
411 FPUnavailable:
412 BEGIN_FTR_SECTION
413 /*
414 * Certain Freescale cores don't have a FPU and treat fp instructions
415 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
416 */
417 b ProgramCheck
418 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
419 EXCEPTION_PROLOG
420 bne load_up_fpu /* if from user, just load it up */
421 addi r3,r1,STACK_FRAME_OVERHEAD
422 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
424 /* Decrementer */
425 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
427 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
428 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
430 /* System call */
431 . = 0xc00
432 SystemCall:
433 EXCEPTION_PROLOG
434 EXC_XFER_EE_LITE(0xc00, DoSyscall)
436 /* Single step - not used on 601 */
437 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
438 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
440 /*
441 * The Altivec unavailable trap is at 0x0f20. Foo.
442 * We effectively remap it to 0x3000.
443 * We include an altivec unavailable exception vector even if
444 * not configured for Altivec, so that you can't panic a
445 * non-altivec kernel running on a machine with altivec just
446 * by executing an altivec instruction.
447 */
448 . = 0xf00
449 b PerformanceMonitor
451 . = 0xf20
452 b AltiVecUnavailable
454 /*
455 * Handle TLB miss for instruction on 603/603e.
456 * Note: we get an alternate set of r0 - r3 to use automatically.
457 */
458 . = 0x1000
459 InstructionTLBMiss:
460 /*
461 * r0: stored ctr
462 * r1: linux style pte ( later becomes ppc hardware pte )
463 * r2: ptr to linux-style pte
464 * r3: scratch
465 */
466 mfctr r0
467 /* Get PTE (linux-style) and check access */
468 mfspr r3,SPRN_IMISS
469 lis r1,KERNELBASE@h /* check if kernel address */
470 cmplw 0,r3,r1
471 mfspr r2,SPRN_SPRG3
472 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
473 lwz r2,PGDIR(r2)
474 blt+ 112f
475 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
476 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
477 lis r2,swapper_pg_dir@ha /* if kernel address, use */
478 addi r2,r2,swapper_pg_dir@l /* kernel page table */
479 112: tophys(r2,r2)
480 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
481 lwz r2,0(r2) /* get pmd entry */
482 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
483 beq- InstructionAddressInvalid /* return if no mapping */
484 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
485 lwz r3,0(r2) /* get linux-style pte */
486 andc. r1,r1,r3 /* check access & ~permission */
487 bne- InstructionAddressInvalid /* return if access not permitted */
488 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
489 /*
490 * NOTE! We are assuming this is not an SMP system, otherwise
491 * we would need to update the pte atomically with lwarx/stwcx.
492 */
493 stw r3,0(r2) /* update PTE (accessed bit) */
494 /* Convert linux-style PTE to low word of PPC-style PTE */
495 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
496 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
497 and r1,r1,r2 /* writable if _RW and _DIRTY */
498 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
499 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
500 ori r1,r1,0xe14 /* clear out reserved bits and M */
501 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
502 mtspr SPRN_RPA,r1
503 mfspr r3,SPRN_IMISS
504 tlbli r3
505 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
506 mtcrf 0x80,r3
507 rfi
508 InstructionAddressInvalid:
509 mfspr r3,SPRN_SRR1
510 rlwinm r1,r3,9,6,6 /* Get load/store bit */
512 addis r1,r1,0x2000
513 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
514 mtctr r0 /* Restore CTR */
515 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
516 or r2,r2,r1
517 mtspr SPRN_SRR1,r2
518 mfspr r1,SPRN_IMISS /* Get failing address */
519 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
520 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
521 xor r1,r1,r2
522 mtspr SPRN_DAR,r1 /* Set fault address */
523 mfmsr r0 /* Restore "normal" registers */
524 xoris r0,r0,MSR_TGPR>>16
525 mtcrf 0x80,r3 /* Restore CR0 */
526 mtmsr r0
527 b InstructionAccess
529 /*
530 * Handle TLB miss for DATA Load operation on 603/603e
531 */
532 . = 0x1100
533 DataLoadTLBMiss:
534 /*
535 * r0: stored ctr
536 * r1: linux style pte ( later becomes ppc hardware pte )
537 * r2: ptr to linux-style pte
538 * r3: scratch
539 */
540 mfctr r0
541 /* Get PTE (linux-style) and check access */
542 mfspr r3,SPRN_DMISS
543 lis r1,KERNELBASE@h /* check if kernel address */
544 cmplw 0,r3,r1
545 mfspr r2,SPRN_SPRG3
546 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
547 lwz r2,PGDIR(r2)
548 blt+ 112f
549 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
550 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
551 lis r2,swapper_pg_dir@ha /* if kernel address, use */
552 addi r2,r2,swapper_pg_dir@l /* kernel page table */
553 112: tophys(r2,r2)
554 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
555 lwz r2,0(r2) /* get pmd entry */
556 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
557 beq- DataAddressInvalid /* return if no mapping */
558 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
559 lwz r3,0(r2) /* get linux-style pte */
560 andc. r1,r1,r3 /* check access & ~permission */
561 bne- DataAddressInvalid /* return if access not permitted */
562 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
563 /*
564 * NOTE! We are assuming this is not an SMP system, otherwise
565 * we would need to update the pte atomically with lwarx/stwcx.
566 */
567 stw r3,0(r2) /* update PTE (accessed bit) */
568 /* Convert linux-style PTE to low word of PPC-style PTE */
569 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
570 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
571 and r1,r1,r2 /* writable if _RW and _DIRTY */
572 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
573 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
574 ori r1,r1,0xe14 /* clear out reserved bits and M */
575 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
576 mtspr SPRN_RPA,r1
577 mfspr r3,SPRN_DMISS
578 tlbld r3
579 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
580 mtcrf 0x80,r3
581 rfi
582 DataAddressInvalid:
583 mfspr r3,SPRN_SRR1
584 rlwinm r1,r3,9,6,6 /* Get load/store bit */
585 addis r1,r1,0x2000
586 mtspr SPRN_DSISR,r1
587 mtctr r0 /* Restore CTR */
588 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
589 mtspr SPRN_SRR1,r2
590 mfspr r1,SPRN_DMISS /* Get failing address */
591 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
592 beq 20f /* Jump if big endian */
593 xori r1,r1,3
594 20: mtspr SPRN_DAR,r1 /* Set fault address */
595 mfmsr r0 /* Restore "normal" registers */
596 xoris r0,r0,MSR_TGPR>>16
597 mtcrf 0x80,r3 /* Restore CR0 */
598 mtmsr r0
599 b DataAccess
601 /*
602 * Handle TLB miss for DATA Store on 603/603e
603 */
604 . = 0x1200
605 DataStoreTLBMiss:
606 /*
607 * r0: stored ctr
608 * r1: linux style pte ( later becomes ppc hardware pte )
609 * r2: ptr to linux-style pte
610 * r3: scratch
611 */
612 mfctr r0
613 /* Get PTE (linux-style) and check access */
614 mfspr r3,SPRN_DMISS
615 lis r1,KERNELBASE@h /* check if kernel address */
616 cmplw 0,r3,r1
617 mfspr r2,SPRN_SPRG3
618 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
619 lwz r2,PGDIR(r2)
620 blt+ 112f
621 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
622 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
623 lis r2,swapper_pg_dir@ha /* if kernel address, use */
624 addi r2,r2,swapper_pg_dir@l /* kernel page table */
625 112: tophys(r2,r2)
626 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
627 lwz r2,0(r2) /* get pmd entry */
628 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
629 beq- DataAddressInvalid /* return if no mapping */
630 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
631 lwz r3,0(r2) /* get linux-style pte */
632 andc. r1,r1,r3 /* check access & ~permission */
633 bne- DataAddressInvalid /* return if access not permitted */
634 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
635 /*
636 * NOTE! We are assuming this is not an SMP system, otherwise
637 * we would need to update the pte atomically with lwarx/stwcx.
638 */
639 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
640 /* Convert linux-style PTE to low word of PPC-style PTE */
641 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
642 li r1,0xe15 /* clear out reserved bits and M */
643 andc r1,r3,r1 /* PP = user? 2: 0 */
644 mtspr SPRN_RPA,r1
645 mfspr r3,SPRN_DMISS
646 tlbld r3
647 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
648 mtcrf 0x80,r3
649 rfi
651 #ifndef CONFIG_ALTIVEC
652 #define altivec_assist_exception unknown_exception
653 #endif
655 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
656 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
657 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
658 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
659 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
660 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
661 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
662 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
663 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
664 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
665 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
666 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
667 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
668 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
669 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
670 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
671 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
672 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
673 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
674 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
675 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
676 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
677 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
678 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
679 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
680 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
681 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
682 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
683 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
685 .globl mol_trampoline
686 .set mol_trampoline, i0x2f00
688 . = 0x3000
690 AltiVecUnavailable:
691 EXCEPTION_PROLOG
692 #ifdef CONFIG_ALTIVEC
693 bne load_up_altivec /* if from user, just load it up */
694 #endif /* CONFIG_ALTIVEC */
695 addi r3,r1,STACK_FRAME_OVERHEAD
696 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
698 PerformanceMonitor:
699 EXCEPTION_PROLOG
700 addi r3,r1,STACK_FRAME_OVERHEAD
701 EXC_XFER_STD(0xf00, performance_monitor_exception)
703 #ifdef CONFIG_ALTIVEC
704 /* Note that the AltiVec support is closely modeled after the FP
705 * support. Changes to one are likely to be applicable to the
706 * other! */
707 load_up_altivec:
708 /*
709 * Disable AltiVec for the task which had AltiVec previously,
710 * and save its AltiVec registers in its thread_struct.
711 * Enables AltiVec for use in the kernel on return.
712 * On SMP we know the AltiVec units are free, since we give it up every
713 * switch. -- Kumar
714 */
715 mfmsr r5
716 oris r5,r5,MSR_VEC@h
717 MTMSRD(r5) /* enable use of AltiVec now */
718 isync
719 /*
720 * For SMP, we don't do lazy AltiVec switching because it just gets too
721 * horrendously complex, especially when a task switches from one CPU
722 * to another. Instead we call giveup_altivec in switch_to.
723 */
724 #ifndef CONFIG_SMP
725 tophys(r6,0)
726 addis r3,r6,last_task_used_altivec@ha
727 lwz r4,last_task_used_altivec@l(r3)
728 cmpwi 0,r4,0
729 beq 1f
730 add r4,r4,r6
731 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
732 SAVE_32VRS(0,r10,r4)
733 mfvscr vr0
734 li r10,THREAD_VSCR
735 stvx vr0,r10,r4
736 lwz r5,PT_REGS(r4)
737 add r5,r5,r6
738 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
739 lis r10,MSR_VEC@h
740 andc r4,r4,r10 /* disable altivec for previous task */
741 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
742 1:
743 #endif /* CONFIG_SMP */
744 /* enable use of AltiVec after return */
745 oris r9,r9,MSR_VEC@h
746 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
747 li r4,1
748 li r10,THREAD_VSCR
749 stw r4,THREAD_USED_VR(r5)
750 lvx vr0,r10,r5
751 mtvscr vr0
752 REST_32VRS(0,r10,r5)
753 #ifndef CONFIG_SMP
754 subi r4,r5,THREAD
755 sub r4,r4,r6
756 stw r4,last_task_used_altivec@l(r3)
757 #endif /* CONFIG_SMP */
758 /* restore registers and return */
759 /* we haven't used ctr or xer or lr */
760 b fast_exception_return
762 /*
763 * AltiVec unavailable trap from kernel - print a message, but let
764 * the task use AltiVec in the kernel until it returns to user mode.
765 */
766 KernelAltiVec:
767 lwz r3,_MSR(r1)
768 oris r3,r3,MSR_VEC@h
769 stw r3,_MSR(r1) /* enable use of AltiVec after return */
770 lis r3,87f@h
771 ori r3,r3,87f@l
772 mr r4,r2 /* current */
773 lwz r5,_NIP(r1)
774 bl printk
775 b ret_from_except
776 87: .string "AltiVec used in kernel (task=%p, pc=%x) \n"
777 .align 4,0
779 /*
780 * giveup_altivec(tsk)
781 * Disable AltiVec for the task given as the argument,
782 * and save the AltiVec registers in its thread_struct.
783 * Enables AltiVec for use in the kernel on return.
784 */
786 .globl giveup_altivec
787 giveup_altivec:
788 mfmsr r5
789 oris r5,r5,MSR_VEC@h
790 SYNC
791 MTMSRD(r5) /* enable use of AltiVec now */
792 isync
793 cmpwi 0,r3,0
794 beqlr- /* if no previous owner, done */
795 addi r3,r3,THREAD /* want THREAD of task */
796 lwz r5,PT_REGS(r3)
797 cmpwi 0,r5,0
798 SAVE_32VRS(0, r4, r3)
799 mfvscr vr0
800 li r4,THREAD_VSCR
801 stvx vr0,r4,r3
802 beq 1f
803 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
804 lis r3,MSR_VEC@h
805 andc r4,r4,r3 /* disable AltiVec for previous task */
806 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
807 1:
808 #ifndef CONFIG_SMP
809 li r5,0
810 lis r4,last_task_used_altivec@ha
811 stw r5,last_task_used_altivec@l(r4)
812 #endif /* CONFIG_SMP */
813 blr
814 #endif /* CONFIG_ALTIVEC */
816 /*
817 * This code is jumped to from the startup code to copy
818 * the kernel image to physical address 0.
819 */
820 relocate_kernel:
821 addis r9,r26,klimit@ha /* fetch klimit */
822 lwz r25,klimit@l(r9)
823 addis r25,r25,-KERNELBASE@h
824 li r3,0 /* Destination base address */
825 li r6,0 /* Destination offset */
826 li r5,0x4000 /* # bytes of memory to copy */
827 bl copy_and_flush /* copy the first 0x4000 bytes */
828 addi r0,r3,4f@l /* jump to the address of 4f */
829 mtctr r0 /* in copy and do the rest. */
830 bctr /* jump to the copy */
831 4: mr r5,r25
832 bl copy_and_flush /* copy the rest */
833 b turn_on_mmu
835 /*
836 * Copy routine used to copy the kernel to start at physical address 0
837 * and flush and invalidate the caches as needed.
838 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
839 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
840 */
841 _ENTRY(copy_and_flush)
842 addi r5,r5,-4
843 addi r6,r6,-4
844 4: li r0,L1_CACHE_BYTES/4
845 mtctr r0
846 3: addi r6,r6,4 /* copy a cache line */
847 lwzx r0,r6,r4
848 stwx r0,r6,r3
849 bdnz 3b
850 dcbst r6,r3 /* write it to memory */
851 sync
852 icbi r6,r3 /* flush the icache line */
853 cmplw 0,r6,r5
854 blt 4b
855 sync /* additional sync needed on g4 */
856 isync
857 addi r5,r5,4
858 addi r6,r6,4
859 blr
861 #ifdef CONFIG_SMP
862 #ifdef CONFIG_GEMINI
863 .globl __secondary_start_gemini
864 __secondary_start_gemini:
865 mfspr r4,SPRN_HID0
866 ori r4,r4,HID0_ICFI
867 li r3,0
868 ori r3,r3,HID0_ICE
869 andc r4,r4,r3
870 mtspr SPRN_HID0,r4
871 sync
872 b __secondary_start
873 #endif /* CONFIG_GEMINI */
875 .globl __secondary_start_mpc86xx
876 __secondary_start_mpc86xx:
877 mfspr r3, SPRN_PIR
878 stw r3, __secondary_hold_acknowledge@l(0)
879 mr r24, r3 /* cpu # */
880 b __secondary_start
882 .globl __secondary_start_pmac_0
883 __secondary_start_pmac_0:
884 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
885 li r24,0
886 b 1f
887 li r24,1
888 b 1f
889 li r24,2
890 b 1f
891 li r24,3
892 1:
893 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
894 set to map the 0xf0000000 - 0xffffffff region */
895 mfmsr r0
896 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
897 SYNC
898 mtmsr r0
899 isync
901 .globl __secondary_start
902 __secondary_start:
903 /* Copy some CPU settings from CPU 0 */
904 bl __restore_cpu_setup
906 lis r3,-KERNELBASE@h
907 mr r4,r24
908 bl call_setup_cpu /* Call setup_cpu for this CPU */
909 #ifdef CONFIG_6xx
910 lis r3,-KERNELBASE@h
911 bl init_idle_6xx
912 #endif /* CONFIG_6xx */
914 /* get current_thread_info and current */
915 lis r1,secondary_ti@ha
916 tophys(r1,r1)
917 lwz r1,secondary_ti@l(r1)
918 tophys(r2,r1)
919 lwz r2,TI_TASK(r2)
921 /* stack */
922 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
923 li r0,0
924 tophys(r3,r1)
925 stw r0,0(r3)
927 /* load up the MMU */
928 bl load_up_mmu
930 /* ptr to phys current thread */
931 tophys(r4,r2)
932 addi r4,r4,THREAD /* phys address of our thread_struct */
933 CLR_TOP32(r4)
934 mtspr SPRN_SPRG3,r4
935 li r3,0
936 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
938 /* enable MMU and jump to start_secondary */
939 li r4,MSR_KERNEL
940 FIX_SRR1(r4,r5)
941 lis r3,start_secondary@h
942 ori r3,r3,start_secondary@l
943 mtspr SPRN_SRR0,r3
944 mtspr SPRN_SRR1,r4
945 SYNC
946 RFI
947 #endif /* CONFIG_SMP */
949 /*
950 * Those generic dummy functions are kept for CPUs not
951 * included in CONFIG_6xx
952 */
953 #if !defined(CONFIG_6xx)
954 _ENTRY(__save_cpu_setup)
955 blr
956 _ENTRY(__restore_cpu_setup)
957 blr
958 #endif /* !defined(CONFIG_6xx) */
961 /*
962 * Load stuff into the MMU. Intended to be called with
963 * IR=0 and DR=0.
964 */
965 load_up_mmu:
966 sync /* Force all PTE updates to finish */
967 isync
968 tlbia /* Clear all TLB entries */
969 sync /* wait for tlbia/tlbie to finish */
970 TLBSYNC /* ... on all CPUs */
971 /* Load the SDR1 register (hash table base & size) */
972 lis r6,_SDR1@ha
973 tophys(r6,r6)
974 lwz r6,_SDR1@l(r6)
975 mtspr SPRN_SDR1,r6
976 li r0,16 /* load up segment register values */
977 mtctr r0 /* for context 0 */
978 lis r3,0x2000 /* Ku = 1, VSID = 0 */
979 li r4,0
980 3: mtsrin r3,r4
981 addi r3,r3,0x111 /* increment VSID */
982 addis r4,r4,0x1000 /* address of next segment */
983 bdnz 3b
985 /* Load the BAT registers with the values set up by MMU_init.
986 MMU_init takes care of whether we're on a 601 or not. */
987 mfpvr r3
988 srwi r3,r3,16
989 cmpwi r3,1
990 lis r3,BATS@ha
991 addi r3,r3,BATS@l
992 tophys(r3,r3)
993 LOAD_BAT(0,r3,r4,r5)
994 LOAD_BAT(1,r3,r4,r5)
995 LOAD_BAT(2,r3,r4,r5)
996 LOAD_BAT(3,r3,r4,r5)
997 BEGIN_FTR_SECTION
998 LOAD_BAT(4,r3,r4,r5)
999 LOAD_BAT(5,r3,r4,r5)
1000 LOAD_BAT(6,r3,r4,r5)
1001 LOAD_BAT(7,r3,r4,r5)
1002 END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
1003 blr
1005 /*
1006 * This is where the main kernel code starts.
1007 */
1008 start_here:
1009 /* ptr to current */
1010 lis r2,init_task@h
1011 ori r2,r2,init_task@l
1012 /* Set up for using our exception vectors */
1013 /* ptr to phys current thread */
1014 tophys(r4,r2)
1015 addi r4,r4,THREAD /* init task's THREAD */
1016 CLR_TOP32(r4)
1017 mtspr SPRN_SPRG3,r4
1018 li r3,0
1019 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1021 /* stack */
1022 lis r1,init_thread_union@ha
1023 addi r1,r1,init_thread_union@l
1024 li r0,0
1025 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1026 /*
1027 * Do early platform-specific initialization,
1028 * and set up the MMU.
1029 */
1030 mr r3,r31
1031 mr r4,r30
1032 bl machine_init
1033 bl __save_cpu_setup
1034 bl MMU_init
1036 /*
1037 * Go back to running unmapped so we can load up new values
1038 * for SDR1 (hash table pointer) and the segment registers
1039 * and change to using our exception vectors.
1040 */
1041 lis r4,2f@h
1042 ori r4,r4,2f@l
1043 tophys(r4,r4)
1044 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1045 FIX_SRR1(r3,r5)
1046 mtspr SPRN_SRR0,r4
1047 mtspr SPRN_SRR1,r3
1048 SYNC
1049 RFI
1050 /* Load up the kernel context */
1051 2: bl load_up_mmu
1053 #ifdef CONFIG_BDI_SWITCH
1054 /* Add helper information for the Abatron bdiGDB debugger.
1055 * We do this here because we know the mmu is disabled, and
1056 * will be enabled for real in just a few instructions.
1057 */
1058 lis r5, abatron_pteptrs@h
1059 ori r5, r5, abatron_pteptrs@l
1060 stw r5, 0xf0(r0) /* This much match your Abatron config */
1061 lis r6, swapper_pg_dir@h
1062 ori r6, r6, swapper_pg_dir@l
1063 tophys(r5, r5)
1064 stw r6, 0(r5)
1065 #endif /* CONFIG_BDI_SWITCH */
1067 /* Now turn on the MMU for real! */
1068 li r4,MSR_KERNEL
1069 FIX_SRR1(r4,r5)
1070 lis r3,start_kernel@h
1071 ori r3,r3,start_kernel@l
1072 mtspr SPRN_SRR0,r3
1073 mtspr SPRN_SRR1,r4
1074 SYNC
1075 RFI
1077 /*
1078 * Set up the segment registers for a new context.
1079 */
1080 _ENTRY(set_context)
1081 mulli r3,r3,897 /* multiply context by skew factor */
1082 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1083 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1084 li r0,NUM_USER_SEGMENTS
1085 mtctr r0
1087 #ifdef CONFIG_BDI_SWITCH
1088 /* Context switch the PTE pointer for the Abatron BDI2000.
1089 * The PGDIR is passed as second argument.
1090 */
1091 lis r5, KERNELBASE@h
1092 lwz r5, 0xf0(r5)
1093 stw r4, 0x4(r5)
1094 #endif
1095 li r4,0
1096 isync
1097 3:
1098 mtsrin r3,r4
1099 addi r3,r3,0x111 /* next VSID */
1100 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1101 addis r4,r4,0x1000 /* address of next segment */
1102 bdnz 3b
1103 sync
1104 isync
1105 blr
1107 /*
1108 * An undocumented "feature" of 604e requires that the v bit
1109 * be cleared before changing BAT values.
1110 *
1111 * Also, newer IBM firmware does not clear bat3 and 4 so
1112 * this makes sure it's done.
1113 * -- Cort
1114 */
1115 clear_bats:
1116 li r10,0
1117 mfspr r9,SPRN_PVR
1118 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1119 cmpwi r9, 1
1120 beq 1f
1122 mtspr SPRN_DBAT0U,r10
1123 mtspr SPRN_DBAT0L,r10
1124 mtspr SPRN_DBAT1U,r10
1125 mtspr SPRN_DBAT1L,r10
1126 mtspr SPRN_DBAT2U,r10
1127 mtspr SPRN_DBAT2L,r10
1128 mtspr SPRN_DBAT3U,r10
1129 mtspr SPRN_DBAT3L,r10
1130 1:
1131 mtspr SPRN_IBAT0U,r10
1132 mtspr SPRN_IBAT0L,r10
1133 mtspr SPRN_IBAT1U,r10
1134 mtspr SPRN_IBAT1L,r10
1135 mtspr SPRN_IBAT2U,r10
1136 mtspr SPRN_IBAT2L,r10
1137 mtspr SPRN_IBAT3U,r10
1138 mtspr SPRN_IBAT3L,r10
1139 BEGIN_FTR_SECTION
1140 /* Here's a tweak: at this point, CPU setup have
1141 * not been called yet, so HIGH_BAT_EN may not be
1142 * set in HID0 for the 745x processors. However, it
1143 * seems that doesn't affect our ability to actually
1144 * write to these SPRs.
1145 */
1146 mtspr SPRN_DBAT4U,r10
1147 mtspr SPRN_DBAT4L,r10
1148 mtspr SPRN_DBAT5U,r10
1149 mtspr SPRN_DBAT5L,r10
1150 mtspr SPRN_DBAT6U,r10
1151 mtspr SPRN_DBAT6L,r10
1152 mtspr SPRN_DBAT7U,r10
1153 mtspr SPRN_DBAT7L,r10
1154 mtspr SPRN_IBAT4U,r10
1155 mtspr SPRN_IBAT4L,r10
1156 mtspr SPRN_IBAT5U,r10
1157 mtspr SPRN_IBAT5L,r10
1158 mtspr SPRN_IBAT6U,r10
1159 mtspr SPRN_IBAT6L,r10
1160 mtspr SPRN_IBAT7U,r10
1161 mtspr SPRN_IBAT7L,r10
1162 END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
1163 blr
1165 flush_tlbs:
1166 lis r10, 0x40
1167 1: addic. r10, r10, -0x1000
1168 tlbie r10
1169 blt 1b
1170 sync
1171 blr
1173 mmu_off:
1174 addi r4, r3, __after_mmu_off - _start
1175 mfmsr r3
1176 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1177 beqlr
1178 andc r3,r3,r0
1179 mtspr SPRN_SRR0,r4
1180 mtspr SPRN_SRR1,r3
1181 sync
1182 RFI
1184 /*
1185 * Use the first pair of BAT registers to map the 1st 16MB
1186 * of RAM to KERNELBASE. From this point on we can't safely
1187 * call OF any more.
1188 */
1189 initial_bats:
1190 lis r11,KERNELBASE@h
1191 mfspr r9,SPRN_PVR
1192 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1193 cmpwi 0,r9,1
1194 bne 4f
1195 ori r11,r11,4 /* set up BAT registers for 601 */
1196 li r8,0x7f /* valid, block length = 8MB */
1197 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1198 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1199 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1200 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1201 mtspr SPRN_IBAT1U,r9
1202 mtspr SPRN_IBAT1L,r10
1203 isync
1204 blr
1206 4: tophys(r8,r11)
1207 #ifdef CONFIG_SMP
1208 ori r8,r8,0x12 /* R/W access, M=1 */
1209 #else
1210 ori r8,r8,2 /* R/W access */
1211 #endif /* CONFIG_SMP */
1212 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1214 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1215 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1216 mtspr SPRN_IBAT0L,r8
1217 mtspr SPRN_IBAT0U,r11
1218 isync
1219 blr
1222 #ifdef CONFIG_BOOTX_TEXT
1223 setup_disp_bat:
1224 /*
1225 * setup the display bat prepared for us in prom.c
1226 */
1227 mflr r8
1228 bl reloc_offset
1229 mtlr r8
1230 addis r8,r3,disp_BAT@ha
1231 addi r8,r8,disp_BAT@l
1232 cmpwi cr0,r8,0
1233 beqlr
1234 lwz r11,0(r8)
1235 lwz r8,4(r8)
1236 mfspr r9,SPRN_PVR
1237 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1238 cmpwi 0,r9,1
1239 beq 1f
1240 mtspr SPRN_DBAT3L,r8
1241 mtspr SPRN_DBAT3U,r11
1242 blr
1243 1: mtspr SPRN_IBAT3L,r8
1244 mtspr SPRN_IBAT3U,r11
1245 blr
1246 #endif /* CONFIG_BOOTX_TEXT */
1248 #ifdef CONFIG_8260
1249 /* Jump into the system reset for the rom.
1250 * We first disable the MMU, and then jump to the ROM reset address.
1251 *
1252 * r3 is the board info structure, r4 is the location for starting.
1253 * I use this for building a small kernel that can load other kernels,
1254 * rather than trying to write or rely on a rom monitor that can tftp load.
1255 */
1256 .globl m8260_gorom
1257 m8260_gorom:
1258 mfmsr r0
1259 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1260 sync
1261 mtmsr r0
1262 sync
1263 mfspr r11, SPRN_HID0
1264 lis r10, 0
1265 ori r10,r10,HID0_ICE|HID0_DCE
1266 andc r11, r11, r10
1267 mtspr SPRN_HID0, r11
1268 isync
1269 li r5, MSR_ME|MSR_RI
1270 lis r6,2f@h
1271 addis r6,r6,-KERNELBASE@h
1272 ori r6,r6,2f@l
1273 mtspr SPRN_SRR0,r6
1274 mtspr SPRN_SRR1,r5
1275 isync
1276 sync
1277 rfi
1278 2:
1279 mtlr r4
1280 blr
1281 #endif
1284 /*
1285 * We put a few things here that have to be page-aligned.
1286 * This stuff goes at the beginning of the data segment,
1287 * which is page-aligned.
1288 */
1289 .data
1290 .globl sdata
1291 sdata:
1292 .globl empty_zero_page
1293 empty_zero_page:
1294 .space 4096
1296 .globl swapper_pg_dir
1297 swapper_pg_dir:
1298 .space 4096
1300 .globl intercept_table
1301 intercept_table:
1302 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1303 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1304 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1305 .long 0, 0, 0, 0, 0, 0, 0, 0
1306 .long 0, 0, 0, 0, 0, 0, 0, 0
1307 .long 0, 0, 0, 0, 0, 0, 0, 0
1309 /* Room for two PTE pointers, usually the kernel and current user pointers
1310 * to their respective root page table.
1311 */
1312 abatron_pteptrs:
1313 .space 8