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thinkpad-acpi: fix default brightness_mode for R50e/R51
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / pci / ens1370.c
blob1b50ed52fcd339857639f3d8dceedaa663503936
1 /*
2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
4 * Thomas Sailer <sailer@ife.ee.ethz.ch>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22 /* Power-Management-Code ( CONFIG_PM )
23 * for ens1371 only ( FIXME )
24 * derived from cs4281.c, atiixp.c and via82xx.c
25 * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm
26 * by Kurt J. Bosch
27 */
28
29 #include <asm/io.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/slab.h>
35 #include <linux/gameport.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38
39 #include <sound/core.h>
40 #include <sound/control.h>
41 #include <sound/pcm.h>
42 #include <sound/rawmidi.h>
43 #ifdef CHIP1371
44 #include <sound/ac97_codec.h>
45 #else
46 #include <sound/ak4531_codec.h>
47 #endif
48 #include <sound/initval.h>
49 #include <sound/asoundef.h>
50
51 #ifndef CHIP1371
52 #undef CHIP1370
53 #define CHIP1370
54 #endif
55
56 #ifdef CHIP1370
57 #define DRIVER_NAME "ENS1370"
58 #else
59 #define DRIVER_NAME "ENS1371"
60 #endif
61
62
63 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
64 MODULE_LICENSE("GPL");
65 #ifdef CHIP1370
66 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
67 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
68 "{Creative Labs,SB PCI64/128 (ES1370)}}");
69 #endif
70 #ifdef CHIP1371
71 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
72 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
73 "{Ensoniq,AudioPCI ES1373},"
74 "{Creative Labs,Ectiva EV1938},"
75 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
76 "{Creative Labs,Vibra PCI128},"
77 "{Ectiva,EV1938}}");
78 #endif
79
80 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
81 #define SUPPORT_JOYSTICK
82 #endif
83
84 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
85 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
86 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
87 #ifdef SUPPORT_JOYSTICK
88 #ifdef CHIP1371
89 static int joystick_port[SNDRV_CARDS];
90 #else
91 static int joystick[SNDRV_CARDS];
92 #endif
93 #endif
94 #ifdef CHIP1371
95 static int spdif[SNDRV_CARDS];
96 static int lineio[SNDRV_CARDS];
97 #endif
98
99 module_param_array(index, int, NULL, 0444);
100 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
101 module_param_array(id, charp, NULL, 0444);
102 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
103 module_param_array(enable, bool, NULL, 0444);
104 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
105 #ifdef SUPPORT_JOYSTICK
106 #ifdef CHIP1371
107 module_param_array(joystick_port, int, NULL, 0444);
108 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
109 #else
110 module_param_array(joystick, bool, NULL, 0444);
111 MODULE_PARM_DESC(joystick, "Enable joystick.");
112 #endif
113 #endif /* SUPPORT_JOYSTICK */
114 #ifdef CHIP1371
115 module_param_array(spdif, int, NULL, 0444);
116 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
117 module_param_array(lineio, int, NULL, 0444);
118 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
119 #endif
120
121 /* ES1371 chip ID */
122 /* This is a little confusing because all ES1371 compatible chips have the
123 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
124 This is only significant if you want to enable features on the later parts.
125 Yes, I know it's stupid and why didn't we use the sub IDs?
126 */
127 #define ES1371REV_ES1373_A 0x04
128 #define ES1371REV_ES1373_B 0x06
129 #define ES1371REV_CT5880_A 0x07
130 #define CT5880REV_CT5880_C 0x02
131 #define CT5880REV_CT5880_D 0x03 /* ??? -jk */
132 #define CT5880REV_CT5880_E 0x04 /* mw */
133 #define ES1371REV_ES1371_B 0x09
134 #define EV1938REV_EV1938_A 0x00
135 #define ES1371REV_ES1373_8 0x08
136
137 /*
138 * Direct registers
139 */
140
141 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
142
143 #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
144 #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
145 #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
146 #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
147 #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
148 #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
149 #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
150 #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
151 #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
152 #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
153 #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
154 #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
155 #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
156 #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
157 #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
158 #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
159 #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
160 #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
161 #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
162 #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
163 #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
164 #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
165 #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
166 #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
167 #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
168 #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
169 #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
170 #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
171 #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
172 #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
173 #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
174 #define ES_1371_PDLEVM (0x03<<8) /* mask for above */
175 #define ES_BREQ (1<<7) /* memory bus request enable */
176 #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
177 #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
178 #define ES_ADC_EN (1<<4) /* ADC capture channel enable */
179 #define ES_UART_EN (1<<3) /* UART enable */
180 #define ES_JYSTK_EN (1<<2) /* Joystick module enable */
181 #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
182 #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
183 #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
184 #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
185 #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
186 #define ES_INTR (1<<31) /* Interrupt is pending */
187 #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
188 #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
189 #define ES_1373_REAR_BIT26 (1<<26)
190 #define ES_1373_REAR_BIT24 (1<<24)
191 #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
192 #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
193 #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
194 #define ES_1371_TEST (1<<16) /* test ASIC */
195 #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
196 #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
197 #define ES_1370_CBUSY (1<<9) /* CODEC is busy */
198 #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
199 #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
200 #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
201 #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
202 #define ES_1371_MPWR (1<<5) /* power level interrupt pending */
203 #define ES_MCCB (1<<4) /* CCB interrupt pending */
204 #define ES_UART (1<<3) /* UART interrupt pending */
205 #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
206 #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
207 #define ES_ADC (1<<0) /* ADC channel interrupt pending */
208 #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
209 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
210 #define ES_RXINT (1<<7) /* RX interrupt occurred */
211 #define ES_TXINT (1<<2) /* TX interrupt occurred */
212 #define ES_TXRDY (1<<1) /* transmitter ready */
213 #define ES_RXRDY (1<<0) /* receiver ready */
214 #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
215 #define ES_RXINTEN (1<<7) /* RX interrupt enable */
216 #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
217 #define ES_TXINTENM (0x03<<5) /* mask for above */
218 #define ES_TXINTENI(i) (((i)>>5)&0x03)
219 #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
220 #define ES_CNTRLM (0x03<<0) /* mask for above */
221 #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
222 #define ES_TEST_MODE (1<<0) /* test mode enabled */
223 #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
224 #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
225 #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
226 #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
227 #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
228 #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
229 #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
230 #define ES_1371_CODEC_RDY (1<<31) /* codec ready */
231 #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
232 #define EV_1938_CODEC_MAGIC (1<<26)
233 #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
234 #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
235 #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
236 #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
237
238 #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
239 #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
240 #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
241 #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
242 #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
243 #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
244 #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
245 #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
246 #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
247 #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
248 #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
249 #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
250 #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
251
252 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
253 #define ES_1371_JFAST (1<<31) /* fast joystick timing */
254 #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
255 #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
256 #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
257 #define ES_1371_VMPUM (0x03<<27) /* mask for above */
258 #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
259 #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
260 #define ES_1371_VCDCM (0x03<<25) /* mask for above */
261 #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
262 #define ES_1371_FIRQ (1<<24) /* force an interrupt */
263 #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
264 #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
265 #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
266 #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
267 #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
268 #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
269 #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
270 #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
271 #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
272 #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
273 #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
274 #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
275
276 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
277
278 #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
279 #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
280 #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
281 #define ES_P2_END_INCM (0x07<<19) /* mask for above */
282 #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
283 #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
284 #define ES_P2_ST_INCM (0x07<<16) /* mask for above */
285 #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
286 #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
287 #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
288 #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
289 #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
290 #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
291 #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
292 #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
293 #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
294 #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
295 #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
296 #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
297 #define ES_R1_MODEM (0x03<<4) /* mask for above */
298 #define ES_R1_MODEI(i) (((i)>>4)&0x03)
299 #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
300 #define ES_P2_MODEM (0x03<<2) /* mask for above */
301 #define ES_P2_MODEI(i) (((i)>>2)&0x03)
302 #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
303 #define ES_P1_MODEM (0x03<<0) /* mask for above */
304 #define ES_P1_MODEI(i) (((i)>>0)&0x03)
305
306 #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
307 #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
308 #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
309 #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
310 #define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
311 #define ES_REG_COUNTM (0xffff<<0)
312 #define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
313
314 #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
315 #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
316 #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
317 #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
318 #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
319 #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
320 #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
321 #define ES_REG_FCURR_COUNTM (0xffff<<16)
322 #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
323 #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
324 #define ES_REG_FSIZEM (0xffff<<0)
325 #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
326 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
327 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
328
329 #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
330 #define ES_REG_UF_VALID (1<<8)
331 #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
332 #define ES_REG_UF_BYTEM (0xff<<0)
333 #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
334
335
336 /*
337 * Pages
338 */
339
340 #define ES_PAGE_DAC 0x0c
341 #define ES_PAGE_ADC 0x0d
342 #define ES_PAGE_UART 0x0e
343 #define ES_PAGE_UART1 0x0f
344
345 /*
346 * Sample rate converter addresses
347 */
348
349 #define ES_SMPREG_DAC1 0x70
350 #define ES_SMPREG_DAC2 0x74
351 #define ES_SMPREG_ADC 0x78
352 #define ES_SMPREG_VOL_ADC 0x6c
353 #define ES_SMPREG_VOL_DAC1 0x7c
354 #define ES_SMPREG_VOL_DAC2 0x7e
355 #define ES_SMPREG_TRUNC_N 0x00
356 #define ES_SMPREG_INT_REGS 0x01
357 #define ES_SMPREG_ACCUM_FRAC 0x02
358 #define ES_SMPREG_VFREQ_FRAC 0x03
359
360 /*
361 * Some contants
362 */
363
364 #define ES_1370_SRCLOCK 1411200
365 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
366
367 /*
368 * Open modes
369 */
370
371 #define ES_MODE_PLAY1 0x0001
372 #define ES_MODE_PLAY2 0x0002
373 #define ES_MODE_CAPTURE 0x0004
374
375 #define ES_MODE_OUTPUT 0x0001 /* for MIDI */
376 #define ES_MODE_INPUT 0x0002 /* for MIDI */
377
378 /*
379
380 */
381
382 struct ensoniq {
383 spinlock_t reg_lock;
384 struct mutex src_mutex;
385
386 int irq;
387
388 unsigned long playback1size;
389 unsigned long playback2size;
390 unsigned long capture3size;
391
392 unsigned long port;
393 unsigned int mode;
394 unsigned int uartm; /* UART mode */
395
396 unsigned int ctrl; /* control register */
397 unsigned int sctrl; /* serial control register */
398 unsigned int cssr; /* control status register */
399 unsigned int uartc; /* uart control register */
400 unsigned int rev; /* chip revision */
401
402 union {
403 #ifdef CHIP1371
404 struct {
405 struct snd_ac97 *ac97;
406 } es1371;
407 #else
408 struct {
409 int pclkdiv_lock;
410 struct snd_ak4531 *ak4531;
411 } es1370;
412 #endif
413 } u;
414
415 struct pci_dev *pci;
416 struct snd_card *card;
417 struct snd_pcm *pcm1; /* DAC1/ADC PCM */
418 struct snd_pcm *pcm2; /* DAC2 PCM */
419 struct snd_pcm_substream *playback1_substream;
420 struct snd_pcm_substream *playback2_substream;
421 struct snd_pcm_substream *capture_substream;
422 unsigned int p1_dma_size;
423 unsigned int p2_dma_size;
424 unsigned int c_dma_size;
425 unsigned int p1_period_size;
426 unsigned int p2_period_size;
427 unsigned int c_period_size;
428 struct snd_rawmidi *rmidi;
429 struct snd_rawmidi_substream *midi_input;
430 struct snd_rawmidi_substream *midi_output;
431
432 unsigned int spdif;
433 unsigned int spdif_default;
434 unsigned int spdif_stream;
435
436 #ifdef CHIP1370
437 struct snd_dma_buffer dma_bug;
438 #endif
439
440 #ifdef SUPPORT_JOYSTICK
441 struct gameport *gameport;
442 #endif
443 };
444
445 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
446
447 static struct pci_device_id snd_audiopci_ids[] = {
448 #ifdef CHIP1370
449 { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1370 */
450 #endif
451 #ifdef CHIP1371
452 { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1371 */
453 { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1373 - CT5880 */
454 { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Ectiva EV1938 */
455 #endif
456 { 0, }
457 };
458
459 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
460
461 /*
462 * constants
463 */
464
465 #define POLL_COUNT 0xa000
466
467 #ifdef CHIP1370
468 static unsigned int snd_es1370_fixed_rates[] =
469 {5512, 11025, 22050, 44100};
470 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
471 .count = 4,
472 .list = snd_es1370_fixed_rates,
473 .mask = 0,
474 };
475 static struct snd_ratnum es1370_clock = {
476 .num = ES_1370_SRCLOCK,
477 .den_min = 29,
478 .den_max = 353,
479 .den_step = 1,
480 };
481 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
482 .nrats = 1,
483 .rats = &es1370_clock,
484 };
485 #else
486 static struct snd_ratden es1371_dac_clock = {
487 .num_min = 3000 * (1 << 15),
488 .num_max = 48000 * (1 << 15),
489 .num_step = 3000,
490 .den = 1 << 15,
491 };
492 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
493 .nrats = 1,
494 .rats = &es1371_dac_clock,
495 };
496 static struct snd_ratnum es1371_adc_clock = {
497 .num = 48000 << 15,
498 .den_min = 32768,
499 .den_max = 393216,
500 .den_step = 1,
501 };
502 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
503 .nrats = 1,
504 .rats = &es1371_adc_clock,
505 };
506 #endif
507 static const unsigned int snd_ensoniq_sample_shift[] =
508 {0, 1, 1, 2};
509
510 /*
511 * common I/O routines
512 */
513
514 #ifdef CHIP1371
515
516 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
517 {
518 unsigned int t, r = 0;
519
520 for (t = 0; t < POLL_COUNT; t++) {
521 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
522 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
523 return r;
524 cond_resched();
525 }
526 snd_printk(KERN_ERR "wait src ready timeout 0x%lx [0x%x]\n",
527 ES_REG(ensoniq, 1371_SMPRATE), r);
528 return 0;
529 }
530
531 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
532 {
533 unsigned int temp, i, orig, r;
534
535 /* wait for ready */
536 temp = orig = snd_es1371_wait_src_ready(ensoniq);
537
538 /* expose the SRC state bits */
539 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
540 ES_1371_DIS_P2 | ES_1371_DIS_R1);
541 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
542 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
543
544 /* now, wait for busy and the correct time to read */
545 temp = snd_es1371_wait_src_ready(ensoniq);
546
547 if ((temp & 0x00870000) != 0x00010000) {
548 /* wait for the right state */
549 for (i = 0; i < POLL_COUNT; i++) {
550 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
551 if ((temp & 0x00870000) == 0x00010000)
552 break;
553 }
554 }
555
556 /* hide the state bits */
557 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
558 ES_1371_DIS_P2 | ES_1371_DIS_R1);
559 r |= ES_1371_SRC_RAM_ADDRO(reg);
560 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
561
562 return temp;
563 }
564
565 static void snd_es1371_src_write(struct ensoniq * ensoniq,
566 unsigned short reg, unsigned short data)
567 {
568 unsigned int r;
569
570 r = snd_es1371_wait_src_ready(ensoniq) &
571 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
572 ES_1371_DIS_P2 | ES_1371_DIS_R1);
573 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
574 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
575 }
576
577 #endif /* CHIP1371 */
578
579 #ifdef CHIP1370
580
581 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
582 unsigned short reg, unsigned short val)
583 {
584 struct ensoniq *ensoniq = ak4531->private_data;
585 unsigned long end_time = jiffies + HZ / 10;
586
587 #if 0
588 printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
589 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
590 #endif
591 do {
592 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
593 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
594 return;
595 }
596 schedule_timeout_uninterruptible(1);
597 } while (time_after(end_time, jiffies));
598 snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
599 inl(ES_REG(ensoniq, STATUS)));
600 }
601
602 #endif /* CHIP1370 */
603
604 #ifdef CHIP1371
605
606 static inline bool is_ev1938(struct ensoniq *ensoniq)
607 {
608 return ensoniq->pci->device == 0x8938;
609 }
610
611 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
612 unsigned short reg, unsigned short val)
613 {
614 struct ensoniq *ensoniq = ac97->private_data;
615 unsigned int t, x, flag;
616
617 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
618 mutex_lock(&ensoniq->src_mutex);
619 for (t = 0; t < POLL_COUNT; t++) {
620 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
621 /* save the current state for latter */
622 x = snd_es1371_wait_src_ready(ensoniq);
623 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
624 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
625 ES_REG(ensoniq, 1371_SMPRATE));
626 /* wait for not busy (state 0) first to avoid
627 transition states */
628 for (t = 0; t < POLL_COUNT; t++) {
629 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
630 0x00000000)
631 break;
632 }
633 /* wait for a SAFE time to write addr/data and then do it, dammit */
634 for (t = 0; t < POLL_COUNT; t++) {
635 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
636 0x00010000)
637 break;
638 }
639 outl(ES_1371_CODEC_WRITE(reg, val) | flag,
640 ES_REG(ensoniq, 1371_CODEC));
641 /* restore SRC reg */
642 snd_es1371_wait_src_ready(ensoniq);
643 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
644 mutex_unlock(&ensoniq->src_mutex);
645 return;
646 }
647 }
648 mutex_unlock(&ensoniq->src_mutex);
649 snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
650 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
651 }
652
653 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
654 unsigned short reg)
655 {
656 struct ensoniq *ensoniq = ac97->private_data;
657 unsigned int t, x, flag, fail = 0;
658
659 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
660 __again:
661 mutex_lock(&ensoniq->src_mutex);
662 for (t = 0; t < POLL_COUNT; t++) {
663 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
664 /* save the current state for latter */
665 x = snd_es1371_wait_src_ready(ensoniq);
666 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
667 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
668 ES_REG(ensoniq, 1371_SMPRATE));
669 /* wait for not busy (state 0) first to avoid
670 transition states */
671 for (t = 0; t < POLL_COUNT; t++) {
672 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
673 0x00000000)
674 break;
675 }
676 /* wait for a SAFE time to write addr/data and then do it, dammit */
677 for (t = 0; t < POLL_COUNT; t++) {
678 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
679 0x00010000)
680 break;
681 }
682 outl(ES_1371_CODEC_READS(reg) | flag,
683 ES_REG(ensoniq, 1371_CODEC));
684 /* restore SRC reg */
685 snd_es1371_wait_src_ready(ensoniq);
686 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
687 /* wait for WIP again */
688 for (t = 0; t < POLL_COUNT; t++) {
689 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
690 break;
691 }
692 /* now wait for the stinkin' data (RDY) */
693 for (t = 0; t < POLL_COUNT; t++) {
694 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
695 if (is_ev1938(ensoniq)) {
696 for (t = 0; t < 100; t++)
697 inl(ES_REG(ensoniq, CONTROL));
698 x = inl(ES_REG(ensoniq, 1371_CODEC));
699 }
700 mutex_unlock(&ensoniq->src_mutex);
701 return ES_1371_CODEC_READ(x);
702 }
703 }
704 mutex_unlock(&ensoniq->src_mutex);
705 if (++fail > 10) {
706 snd_printk(KERN_ERR "codec read timeout (final) "
707 "at 0x%lx, reg = 0x%x [0x%x]\n",
708 ES_REG(ensoniq, 1371_CODEC), reg,
709 inl(ES_REG(ensoniq, 1371_CODEC)));
710 return 0;
711 }
712 goto __again;
713 }
714 }
715 mutex_unlock(&ensoniq->src_mutex);
716 snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
717 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
718 return 0;
719 }
720
721 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
722 {
723 msleep(750);
724 snd_es1371_codec_read(ac97, AC97_RESET);
725 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
726 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
727 msleep(50);
728 }
729
730 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
731 {
732 unsigned int n, truncm, freq, result;
733
734 mutex_lock(&ensoniq->src_mutex);
735 n = rate / 3000;
736 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
737 n--;
738 truncm = (21 * n - 1) | 1;
739 freq = ((48000UL << 15) / rate) * n;
740 result = (48000UL << 15) / (freq / n);
741 if (rate >= 24000) {
742 if (truncm > 239)
743 truncm = 239;
744 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
745 (((239 - truncm) >> 1) << 9) | (n << 4));
746 } else {
747 if (truncm > 119)
748 truncm = 119;
749 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
750 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
751 }
752 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
753 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
754 ES_SMPREG_INT_REGS) & 0x00ff) |
755 ((freq >> 5) & 0xfc00));
756 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
757 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
758 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
759 mutex_unlock(&ensoniq->src_mutex);
760 }
761
762 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
763 {
764 unsigned int freq, r;
765
766 mutex_lock(&ensoniq->src_mutex);
767 freq = ((rate << 15) + 1500) / 3000;
768 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
769 ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
770 ES_1371_DIS_P1;
771 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
772 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
773 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
774 ES_SMPREG_INT_REGS) & 0x00ff) |
775 ((freq >> 5) & 0xfc00));
776 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
777 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
778 ES_1371_DIS_P2 | ES_1371_DIS_R1));
779 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
780 mutex_unlock(&ensoniq->src_mutex);
781 }
782
783 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
784 {
785 unsigned int freq, r;
786
787 mutex_lock(&ensoniq->src_mutex);
788 freq = ((rate << 15) + 1500) / 3000;
789 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
790 ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
791 ES_1371_DIS_P2;
792 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
793 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
794 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
795 ES_SMPREG_INT_REGS) & 0x00ff) |
796 ((freq >> 5) & 0xfc00));
797 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
798 freq & 0x7fff);
799 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
800 ES_1371_DIS_P1 | ES_1371_DIS_R1));
801 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
802 mutex_unlock(&ensoniq->src_mutex);
803 }
804
805 #endif /* CHIP1371 */
806
807 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
808 {
809 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
810 switch (cmd) {
811 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
812 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
813 {
814 unsigned int what = 0;
815 struct snd_pcm_substream *s;
816 snd_pcm_group_for_each_entry(s, substream) {
817 if (s == ensoniq->playback1_substream) {
818 what |= ES_P1_PAUSE;
819 snd_pcm_trigger_done(s, substream);
820 } else if (s == ensoniq->playback2_substream) {
821 what |= ES_P2_PAUSE;
822 snd_pcm_trigger_done(s, substream);
823 } else if (s == ensoniq->capture_substream)
824 return -EINVAL;
825 }
826 spin_lock(&ensoniq->reg_lock);
827 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
828 ensoniq->sctrl |= what;
829 else
830 ensoniq->sctrl &= ~what;
831 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
832 spin_unlock(&ensoniq->reg_lock);
833 break;
834 }
835 case SNDRV_PCM_TRIGGER_START:
836 case SNDRV_PCM_TRIGGER_STOP:
837 {
838 unsigned int what = 0;
839 struct snd_pcm_substream *s;
840 snd_pcm_group_for_each_entry(s, substream) {
841 if (s == ensoniq->playback1_substream) {
842 what |= ES_DAC1_EN;
843 snd_pcm_trigger_done(s, substream);
844 } else if (s == ensoniq->playback2_substream) {
845 what |= ES_DAC2_EN;
846 snd_pcm_trigger_done(s, substream);
847 } else if (s == ensoniq->capture_substream) {
848 what |= ES_ADC_EN;
849 snd_pcm_trigger_done(s, substream);
850 }
851 }
852 spin_lock(&ensoniq->reg_lock);
853 if (cmd == SNDRV_PCM_TRIGGER_START)
854 ensoniq->ctrl |= what;
855 else
856 ensoniq->ctrl &= ~what;
857 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
858 spin_unlock(&ensoniq->reg_lock);
859 break;
860 }
861 default:
862 return -EINVAL;
863 }
864 return 0;
865 }
866
867 /*
868 * PCM part
869 */
870
871 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
872 struct snd_pcm_hw_params *hw_params)
873 {
874 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
875 }
876
877 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
878 {
879 return snd_pcm_lib_free_pages(substream);
880 }
881
882 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
883 {
884 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
885 struct snd_pcm_runtime *runtime = substream->runtime;
886 unsigned int mode = 0;
887
888 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
889 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
890 if (snd_pcm_format_width(runtime->format) == 16)
891 mode |= 0x02;
892 if (runtime->channels > 1)
893 mode |= 0x01;
894 spin_lock_irq(&ensoniq->reg_lock);
895 ensoniq->ctrl &= ~ES_DAC1_EN;
896 #ifdef CHIP1371
897 /* 48k doesn't need SRC (it breaks AC3-passthru) */
898 if (runtime->rate == 48000)
899 ensoniq->ctrl |= ES_1373_BYPASS_P1;
900 else
901 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
902 #endif
903 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
904 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
905 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
906 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
907 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
908 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
909 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
910 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
911 ES_REG(ensoniq, DAC1_COUNT));
912 #ifdef CHIP1370
913 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
914 switch (runtime->rate) {
915 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
916 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
917 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
918 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
919 default: snd_BUG();
920 }
921 #endif
922 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
923 spin_unlock_irq(&ensoniq->reg_lock);
924 #ifndef CHIP1370
925 snd_es1371_dac1_rate(ensoniq, runtime->rate);
926 #endif
927 return 0;
928 }
929
930 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
931 {
932 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
933 struct snd_pcm_runtime *runtime = substream->runtime;
934 unsigned int mode = 0;
935
936 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
937 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
938 if (snd_pcm_format_width(runtime->format) == 16)
939 mode |= 0x02;
940 if (runtime->channels > 1)
941 mode |= 0x01;
942 spin_lock_irq(&ensoniq->reg_lock);
943 ensoniq->ctrl &= ~ES_DAC2_EN;
944 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
945 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
946 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
947 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
948 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
949 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
950 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
951 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
952 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
953 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
954 ES_REG(ensoniq, DAC2_COUNT));
955 #ifdef CHIP1370
956 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
957 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
958 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
959 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
960 }
961 #endif
962 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
963 spin_unlock_irq(&ensoniq->reg_lock);
964 #ifndef CHIP1370
965 snd_es1371_dac2_rate(ensoniq, runtime->rate);
966 #endif
967 return 0;
968 }
969
970 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
971 {
972 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
973 struct snd_pcm_runtime *runtime = substream->runtime;
974 unsigned int mode = 0;
975
976 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
977 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
978 if (snd_pcm_format_width(runtime->format) == 16)
979 mode |= 0x02;
980 if (runtime->channels > 1)
981 mode |= 0x01;
982 spin_lock_irq(&ensoniq->reg_lock);
983 ensoniq->ctrl &= ~ES_ADC_EN;
984 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
985 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
986 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
987 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
988 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
989 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
990 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
991 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
992 ES_REG(ensoniq, ADC_COUNT));
993 #ifdef CHIP1370
994 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
995 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
996 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
997 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
998 }
999 #endif
1000 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1001 spin_unlock_irq(&ensoniq->reg_lock);
1002 #ifndef CHIP1370
1003 snd_es1371_adc_rate(ensoniq, runtime->rate);
1004 #endif
1005 return 0;
1006 }
1007
1008 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
1009 {
1010 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1011 size_t ptr;
1012
1013 spin_lock(&ensoniq->reg_lock);
1014 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1015 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1016 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1017 ptr = bytes_to_frames(substream->runtime, ptr);
1018 } else {
1019 ptr = 0;
1020 }
1021 spin_unlock(&ensoniq->reg_lock);
1022 return ptr;
1023 }
1024
1025 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1026 {
1027 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1028 size_t ptr;
1029
1030 spin_lock(&ensoniq->reg_lock);
1031 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1032 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1033 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1034 ptr = bytes_to_frames(substream->runtime, ptr);
1035 } else {
1036 ptr = 0;
1037 }
1038 spin_unlock(&ensoniq->reg_lock);
1039 return ptr;
1040 }
1041
1042 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1043 {
1044 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1045 size_t ptr;
1046
1047 spin_lock(&ensoniq->reg_lock);
1048 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1049 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1050 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1051 ptr = bytes_to_frames(substream->runtime, ptr);
1052 } else {
1053 ptr = 0;
1054 }
1055 spin_unlock(&ensoniq->reg_lock);
1056 return ptr;
1057 }
1058
1059 static struct snd_pcm_hardware snd_ensoniq_playback1 =
1060 {
1061 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1062 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1063 SNDRV_PCM_INFO_MMAP_VALID |
1064 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1065 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1066 .rates =
1067 #ifndef CHIP1370
1068 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1069 #else
1070 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1071 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1072 SNDRV_PCM_RATE_44100),
1073 #endif
1074 .rate_min = 4000,
1075 .rate_max = 48000,
1076 .channels_min = 1,
1077 .channels_max = 2,
1078 .buffer_bytes_max = (128*1024),
1079 .period_bytes_min = 64,
1080 .period_bytes_max = (128*1024),
1081 .periods_min = 1,
1082 .periods_max = 1024,
1083 .fifo_size = 0,
1084 };
1085
1086 static struct snd_pcm_hardware snd_ensoniq_playback2 =
1087 {
1088 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1089 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1090 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1091 SNDRV_PCM_INFO_SYNC_START),
1092 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1093 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1094 .rate_min = 4000,
1095 .rate_max = 48000,
1096 .channels_min = 1,
1097 .channels_max = 2,
1098 .buffer_bytes_max = (128*1024),
1099 .period_bytes_min = 64,
1100 .period_bytes_max = (128*1024),
1101 .periods_min = 1,
1102 .periods_max = 1024,
1103 .fifo_size = 0,
1104 };
1105
1106 static struct snd_pcm_hardware snd_ensoniq_capture =
1107 {
1108 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1109 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1110 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1111 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1112 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1113 .rate_min = 4000,
1114 .rate_max = 48000,
1115 .channels_min = 1,
1116 .channels_max = 2,
1117 .buffer_bytes_max = (128*1024),
1118 .period_bytes_min = 64,
1119 .period_bytes_max = (128*1024),
1120 .periods_min = 1,
1121 .periods_max = 1024,
1122 .fifo_size = 0,
1123 };
1124
1125 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1126 {
1127 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1128 struct snd_pcm_runtime *runtime = substream->runtime;
1129
1130 ensoniq->mode |= ES_MODE_PLAY1;
1131 ensoniq->playback1_substream = substream;
1132 runtime->hw = snd_ensoniq_playback1;
1133 snd_pcm_set_sync(substream);
1134 spin_lock_irq(&ensoniq->reg_lock);
1135 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1136 ensoniq->spdif_stream = ensoniq->spdif_default;
1137 spin_unlock_irq(&ensoniq->reg_lock);
1138 #ifdef CHIP1370
1139 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1140 &snd_es1370_hw_constraints_rates);
1141 #else
1142 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1143 &snd_es1371_hw_constraints_dac_clock);
1144 #endif
1145 return 0;
1146 }
1147
1148 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1149 {
1150 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1151 struct snd_pcm_runtime *runtime = substream->runtime;
1152
1153 ensoniq->mode |= ES_MODE_PLAY2;
1154 ensoniq->playback2_substream = substream;
1155 runtime->hw = snd_ensoniq_playback2;
1156 snd_pcm_set_sync(substream);
1157 spin_lock_irq(&ensoniq->reg_lock);
1158 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1159 ensoniq->spdif_stream = ensoniq->spdif_default;
1160 spin_unlock_irq(&ensoniq->reg_lock);
1161 #ifdef CHIP1370
1162 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1163 &snd_es1370_hw_constraints_clock);
1164 #else
1165 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1166 &snd_es1371_hw_constraints_dac_clock);
1167 #endif
1168 return 0;
1169 }
1170
1171 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1172 {
1173 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1174 struct snd_pcm_runtime *runtime = substream->runtime;
1175
1176 ensoniq->mode |= ES_MODE_CAPTURE;
1177 ensoniq->capture_substream = substream;
1178 runtime->hw = snd_ensoniq_capture;
1179 snd_pcm_set_sync(substream);
1180 #ifdef CHIP1370
1181 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1182 &snd_es1370_hw_constraints_clock);
1183 #else
1184 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1185 &snd_es1371_hw_constraints_adc_clock);
1186 #endif
1187 return 0;
1188 }
1189
1190 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1191 {
1192 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1193
1194 ensoniq->playback1_substream = NULL;
1195 ensoniq->mode &= ~ES_MODE_PLAY1;
1196 return 0;
1197 }
1198
1199 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1200 {
1201 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1202
1203 ensoniq->playback2_substream = NULL;
1204 spin_lock_irq(&ensoniq->reg_lock);
1205 #ifdef CHIP1370
1206 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1207 #endif
1208 ensoniq->mode &= ~ES_MODE_PLAY2;
1209 spin_unlock_irq(&ensoniq->reg_lock);
1210 return 0;
1211 }
1212
1213 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1214 {
1215 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1216
1217 ensoniq->capture_substream = NULL;
1218 spin_lock_irq(&ensoniq->reg_lock);
1219 #ifdef CHIP1370
1220 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1221 #endif
1222 ensoniq->mode &= ~ES_MODE_CAPTURE;
1223 spin_unlock_irq(&ensoniq->reg_lock);
1224 return 0;
1225 }
1226
1227 static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1228 .open = snd_ensoniq_playback1_open,
1229 .close = snd_ensoniq_playback1_close,
1230 .ioctl = snd_pcm_lib_ioctl,
1231 .hw_params = snd_ensoniq_hw_params,
1232 .hw_free = snd_ensoniq_hw_free,
1233 .prepare = snd_ensoniq_playback1_prepare,
1234 .trigger = snd_ensoniq_trigger,
1235 .pointer = snd_ensoniq_playback1_pointer,
1236 };
1237
1238 static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1239 .open = snd_ensoniq_playback2_open,
1240 .close = snd_ensoniq_playback2_close,
1241 .ioctl = snd_pcm_lib_ioctl,
1242 .hw_params = snd_ensoniq_hw_params,
1243 .hw_free = snd_ensoniq_hw_free,
1244 .prepare = snd_ensoniq_playback2_prepare,
1245 .trigger = snd_ensoniq_trigger,
1246 .pointer = snd_ensoniq_playback2_pointer,
1247 };
1248
1249 static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1250 .open = snd_ensoniq_capture_open,
1251 .close = snd_ensoniq_capture_close,
1252 .ioctl = snd_pcm_lib_ioctl,
1253 .hw_params = snd_ensoniq_hw_params,
1254 .hw_free = snd_ensoniq_hw_free,
1255 .prepare = snd_ensoniq_capture_prepare,
1256 .trigger = snd_ensoniq_trigger,
1257 .pointer = snd_ensoniq_capture_pointer,
1258 };
1259
1260 static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1261 struct snd_pcm ** rpcm)
1262 {
1263 struct snd_pcm *pcm;
1264 int err;
1265
1266 if (rpcm)
1267 *rpcm = NULL;
1268 #ifdef CHIP1370
1269 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1270 #else
1271 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1272 #endif
1273 if (err < 0)
1274 return err;
1275
1276 #ifdef CHIP1370
1277 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1278 #else
1279 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1280 #endif
1281 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1282
1283 pcm->private_data = ensoniq;
1284 pcm->info_flags = 0;
1285 #ifdef CHIP1370
1286 strcpy(pcm->name, "ES1370 DAC2/ADC");
1287 #else
1288 strcpy(pcm->name, "ES1371 DAC2/ADC");
1289 #endif
1290 ensoniq->pcm1 = pcm;
1291
1292 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1293 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1294
1295 if (rpcm)
1296 *rpcm = pcm;
1297 return 0;
1298 }
1299
1300 static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1301 struct snd_pcm ** rpcm)
1302 {
1303 struct snd_pcm *pcm;
1304 int err;
1305
1306 if (rpcm)
1307 *rpcm = NULL;
1308 #ifdef CHIP1370
1309 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1310 #else
1311 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1312 #endif
1313 if (err < 0)
1314 return err;
1315
1316 #ifdef CHIP1370
1317 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1318 #else
1319 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1320 #endif
1321 pcm->private_data = ensoniq;
1322 pcm->info_flags = 0;
1323 #ifdef CHIP1370
1324 strcpy(pcm->name, "ES1370 DAC1");
1325 #else
1326 strcpy(pcm->name, "ES1371 DAC1");
1327 #endif
1328 ensoniq->pcm2 = pcm;
1329
1330 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1331 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1332
1333 if (rpcm)
1334 *rpcm = pcm;
1335 return 0;
1336 }
1337
1338 /*
1339 * Mixer section
1340 */
1341
1342 /*
1343 * ENS1371 mixer (including SPDIF interface)
1344 */
1345 #ifdef CHIP1371
1346 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1347 struct snd_ctl_elem_info *uinfo)
1348 {
1349 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1350 uinfo->count = 1;
1351 return 0;
1352 }
1353
1354 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1355 struct snd_ctl_elem_value *ucontrol)
1356 {
1357 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1358 spin_lock_irq(&ensoniq->reg_lock);
1359 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1360 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1361 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1362 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1363 spin_unlock_irq(&ensoniq->reg_lock);
1364 return 0;
1365 }
1366
1367 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1368 struct snd_ctl_elem_value *ucontrol)
1369 {
1370 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1371 unsigned int val;
1372 int change;
1373
1374 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1375 ((u32)ucontrol->value.iec958.status[1] << 8) |
1376 ((u32)ucontrol->value.iec958.status[2] << 16) |
1377 ((u32)ucontrol->value.iec958.status[3] << 24);
1378 spin_lock_irq(&ensoniq->reg_lock);
1379 change = ensoniq->spdif_default != val;
1380 ensoniq->spdif_default = val;
1381 if (change && ensoniq->playback1_substream == NULL &&
1382 ensoniq->playback2_substream == NULL)
1383 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1384 spin_unlock_irq(&ensoniq->reg_lock);
1385 return change;
1386 }
1387
1388 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1389 struct snd_ctl_elem_value *ucontrol)
1390 {
1391 ucontrol->value.iec958.status[0] = 0xff;
1392 ucontrol->value.iec958.status[1] = 0xff;
1393 ucontrol->value.iec958.status[2] = 0xff;
1394 ucontrol->value.iec958.status[3] = 0xff;
1395 return 0;
1396 }
1397
1398 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1399 struct snd_ctl_elem_value *ucontrol)
1400 {
1401 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1402 spin_lock_irq(&ensoniq->reg_lock);
1403 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1404 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1405 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1406 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1407 spin_unlock_irq(&ensoniq->reg_lock);
1408 return 0;
1409 }
1410
1411 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1412 struct snd_ctl_elem_value *ucontrol)
1413 {
1414 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1415 unsigned int val;
1416 int change;
1417
1418 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1419 ((u32)ucontrol->value.iec958.status[1] << 8) |
1420 ((u32)ucontrol->value.iec958.status[2] << 16) |
1421 ((u32)ucontrol->value.iec958.status[3] << 24);
1422 spin_lock_irq(&ensoniq->reg_lock);
1423 change = ensoniq->spdif_stream != val;
1424 ensoniq->spdif_stream = val;
1425 if (change && (ensoniq->playback1_substream != NULL ||
1426 ensoniq->playback2_substream != NULL))
1427 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1428 spin_unlock_irq(&ensoniq->reg_lock);
1429 return change;
1430 }
1431
1432 #define ES1371_SPDIF(xname) \
1433 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1434 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1435
1436 #define snd_es1371_spdif_info snd_ctl_boolean_mono_info
1437
1438 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1439 struct snd_ctl_elem_value *ucontrol)
1440 {
1441 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1442
1443 spin_lock_irq(&ensoniq->reg_lock);
1444 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1445 spin_unlock_irq(&ensoniq->reg_lock);
1446 return 0;
1447 }
1448
1449 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1450 struct snd_ctl_elem_value *ucontrol)
1451 {
1452 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1453 unsigned int nval1, nval2;
1454 int change;
1455
1456 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1457 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1458 spin_lock_irq(&ensoniq->reg_lock);
1459 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1460 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1461 ensoniq->ctrl |= nval1;
1462 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1463 ensoniq->cssr |= nval2;
1464 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1465 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1466 spin_unlock_irq(&ensoniq->reg_lock);
1467 return change;
1468 }
1469
1470
1471 /* spdif controls */
1472 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
1473 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1474 {
1475 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1476 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1477 .info = snd_ens1373_spdif_info,
1478 .get = snd_ens1373_spdif_default_get,
1479 .put = snd_ens1373_spdif_default_put,
1480 },
1481 {
1482 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1483 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1484 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1485 .info = snd_ens1373_spdif_info,
1486 .get = snd_ens1373_spdif_mask_get
1487 },
1488 {
1489 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1490 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1491 .info = snd_ens1373_spdif_info,
1492 .get = snd_ens1373_spdif_stream_get,
1493 .put = snd_ens1373_spdif_stream_put
1494 },
1495 };
1496
1497
1498 #define snd_es1373_rear_info snd_ctl_boolean_mono_info
1499
1500 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1501 struct snd_ctl_elem_value *ucontrol)
1502 {
1503 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1504 int val = 0;
1505
1506 spin_lock_irq(&ensoniq->reg_lock);
1507 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1508 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1509 val = 1;
1510 ucontrol->value.integer.value[0] = val;
1511 spin_unlock_irq(&ensoniq->reg_lock);
1512 return 0;
1513 }
1514
1515 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1516 struct snd_ctl_elem_value *ucontrol)
1517 {
1518 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1519 unsigned int nval1;
1520 int change;
1521
1522 nval1 = ucontrol->value.integer.value[0] ?
1523 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1524 spin_lock_irq(&ensoniq->reg_lock);
1525 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1526 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1527 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1528 ensoniq->cssr |= nval1;
1529 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1530 spin_unlock_irq(&ensoniq->reg_lock);
1531 return change;
1532 }
1533
1534 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1535 {
1536 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1537 .name = "AC97 2ch->4ch Copy Switch",
1538 .info = snd_es1373_rear_info,
1539 .get = snd_es1373_rear_get,
1540 .put = snd_es1373_rear_put,
1541 };
1542
1543 #define snd_es1373_line_info snd_ctl_boolean_mono_info
1544
1545 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1546 struct snd_ctl_elem_value *ucontrol)
1547 {
1548 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1549 int val = 0;
1550
1551 spin_lock_irq(&ensoniq->reg_lock);
1552 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1553 val = 1;
1554 ucontrol->value.integer.value[0] = val;
1555 spin_unlock_irq(&ensoniq->reg_lock);
1556 return 0;
1557 }
1558
1559 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1560 struct snd_ctl_elem_value *ucontrol)
1561 {
1562 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1563 int changed;
1564 unsigned int ctrl;
1565
1566 spin_lock_irq(&ensoniq->reg_lock);
1567 ctrl = ensoniq->ctrl;
1568 if (ucontrol->value.integer.value[0])
1569 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1570 else
1571 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1572 changed = (ctrl != ensoniq->ctrl);
1573 if (changed)
1574 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1575 spin_unlock_irq(&ensoniq->reg_lock);
1576 return changed;
1577 }
1578
1579 static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1580 {
1581 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1582 .name = "Line In->Rear Out Switch",
1583 .info = snd_es1373_line_info,
1584 .get = snd_es1373_line_get,
1585 .put = snd_es1373_line_put,
1586 };
1587
1588 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1589 {
1590 struct ensoniq *ensoniq = ac97->private_data;
1591 ensoniq->u.es1371.ac97 = NULL;
1592 }
1593
1594 struct es1371_quirk {
1595 unsigned short vid; /* vendor ID */
1596 unsigned short did; /* device ID */
1597 unsigned char rev; /* revision */
1598 };
1599
1600 static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1601 struct es1371_quirk *list)
1602 {
1603 while (list->vid != (unsigned short)PCI_ANY_ID) {
1604 if (ensoniq->pci->vendor == list->vid &&
1605 ensoniq->pci->device == list->did &&
1606 ensoniq->rev == list->rev)
1607 return 1;
1608 list++;
1609 }
1610 return 0;
1611 }
1612
1613 static struct es1371_quirk es1371_spdif_present[] __devinitdata = {
1614 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1615 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1616 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1617 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1618 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1619 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1620 };
1621
1622 static struct snd_pci_quirk ens1373_line_quirk[] __devinitdata = {
1623 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1624 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1625 { } /* end */
1626 };
1627
1628 static int __devinit snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1629 int has_spdif, int has_line)
1630 {
1631 struct snd_card *card = ensoniq->card;
1632 struct snd_ac97_bus *pbus;
1633 struct snd_ac97_template ac97;
1634 int err;
1635 static struct snd_ac97_bus_ops ops = {
1636 .write = snd_es1371_codec_write,
1637 .read = snd_es1371_codec_read,
1638 .wait = snd_es1371_codec_wait,
1639 };
1640
1641 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1642 return err;
1643
1644 memset(&ac97, 0, sizeof(ac97));
1645 ac97.private_data = ensoniq;
1646 ac97.private_free = snd_ensoniq_mixer_free_ac97;
1647 ac97.pci = ensoniq->pci;
1648 ac97.scaps = AC97_SCAP_AUDIO;
1649 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1650 return err;
1651 if (has_spdif > 0 ||
1652 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1653 struct snd_kcontrol *kctl;
1654 int i, is_spdif = 0;
1655
1656 ensoniq->spdif_default = ensoniq->spdif_stream =
1657 SNDRV_PCM_DEFAULT_CON_SPDIF;
1658 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1659
1660 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1661 is_spdif++;
1662
1663 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1664 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1665 if (!kctl)
1666 return -ENOMEM;
1667 kctl->id.index = is_spdif;
1668 err = snd_ctl_add(card, kctl);
1669 if (err < 0)
1670 return err;
1671 }
1672 }
1673 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1674 /* mirror rear to front speakers */
1675 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1676 ensoniq->cssr |= ES_1373_REAR_BIT26;
1677 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1678 if (err < 0)
1679 return err;
1680 }
1681 if (has_line > 0 ||
1682 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1683 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1684 ensoniq));
1685 if (err < 0)
1686 return err;
1687 }
1688
1689 return 0;
1690 }
1691
1692 #endif /* CHIP1371 */
1693
1694 /* generic control callbacks for ens1370 */
1695 #ifdef CHIP1370
1696 #define ENSONIQ_CONTROL(xname, mask) \
1697 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1698 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1699 .private_value = mask }
1700
1701 #define snd_ensoniq_control_info snd_ctl_boolean_mono_info
1702
1703 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1704 struct snd_ctl_elem_value *ucontrol)
1705 {
1706 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1707 int mask = kcontrol->private_value;
1708
1709 spin_lock_irq(&ensoniq->reg_lock);
1710 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1711 spin_unlock_irq(&ensoniq->reg_lock);
1712 return 0;
1713 }
1714
1715 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1716 struct snd_ctl_elem_value *ucontrol)
1717 {
1718 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1719 int mask = kcontrol->private_value;
1720 unsigned int nval;
1721 int change;
1722
1723 nval = ucontrol->value.integer.value[0] ? mask : 0;
1724 spin_lock_irq(&ensoniq->reg_lock);
1725 change = (ensoniq->ctrl & mask) != nval;
1726 ensoniq->ctrl &= ~mask;
1727 ensoniq->ctrl |= nval;
1728 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1729 spin_unlock_irq(&ensoniq->reg_lock);
1730 return change;
1731 }
1732
1733 /*
1734 * ENS1370 mixer
1735 */
1736
1737 static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1738 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1739 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1740 };
1741
1742 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1743
1744 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1745 {
1746 struct ensoniq *ensoniq = ak4531->private_data;
1747 ensoniq->u.es1370.ak4531 = NULL;
1748 }
1749
1750 static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1751 {
1752 struct snd_card *card = ensoniq->card;
1753 struct snd_ak4531 ak4531;
1754 unsigned int idx;
1755 int err;
1756
1757 /* try reset AK4531 */
1758 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1759 inw(ES_REG(ensoniq, 1370_CODEC));
1760 udelay(100);
1761 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1762 inw(ES_REG(ensoniq, 1370_CODEC));
1763 udelay(100);
1764
1765 memset(&ak4531, 0, sizeof(ak4531));
1766 ak4531.write = snd_es1370_codec_write;
1767 ak4531.private_data = ensoniq;
1768 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1769 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1770 return err;
1771 for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1772 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1773 if (err < 0)
1774 return err;
1775 }
1776 return 0;
1777 }
1778
1779 #endif /* CHIP1370 */
1780
1781 #ifdef SUPPORT_JOYSTICK
1782
1783 #ifdef CHIP1371
1784 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1785 {
1786 switch (joystick_port[dev]) {
1787 case 0: /* disabled */
1788 case 1: /* auto-detect */
1789 case 0x200:
1790 case 0x208:
1791 case 0x210:
1792 case 0x218:
1793 return joystick_port[dev];
1794
1795 default:
1796 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1797 return 0;
1798 }
1799 }
1800 #else
1801 static inline int snd_ensoniq_get_joystick_port(int dev)
1802 {
1803 return joystick[dev] ? 0x200 : 0;
1804 }
1805 #endif
1806
1807 static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1808 {
1809 struct gameport *gp;
1810 int io_port;
1811
1812 io_port = snd_ensoniq_get_joystick_port(dev);
1813
1814 switch (io_port) {
1815 case 0:
1816 return -ENOSYS;
1817
1818 case 1: /* auto_detect */
1819 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1820 if (request_region(io_port, 8, "ens137x: gameport"))
1821 break;
1822 if (io_port > 0x218) {
1823 printk(KERN_WARNING "ens137x: no gameport ports available\n");
1824 return -EBUSY;
1825 }
1826 break;
1827
1828 default:
1829 if (!request_region(io_port, 8, "ens137x: gameport")) {
1830 printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1831 io_port);
1832 return -EBUSY;
1833 }
1834 break;
1835 }
1836
1837 ensoniq->gameport = gp = gameport_allocate_port();
1838 if (!gp) {
1839 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1840 release_region(io_port, 8);
1841 return -ENOMEM;
1842 }
1843
1844 gameport_set_name(gp, "ES137x");
1845 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1846 gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1847 gp->io = io_port;
1848
1849 ensoniq->ctrl |= ES_JYSTK_EN;
1850 #ifdef CHIP1371
1851 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1852 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1853 #endif
1854 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1855
1856 gameport_register_port(ensoniq->gameport);
1857
1858 return 0;
1859 }
1860
1861 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1862 {
1863 if (ensoniq->gameport) {
1864 int port = ensoniq->gameport->io;
1865
1866 gameport_unregister_port(ensoniq->gameport);
1867 ensoniq->gameport = NULL;
1868 ensoniq->ctrl &= ~ES_JYSTK_EN;
1869 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1870 release_region(port, 8);
1871 }
1872 }
1873 #else
1874 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1875 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1876 #endif /* SUPPORT_JOYSTICK */
1877
1878 /*
1879
1880 */
1881
1882 static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1883 struct snd_info_buffer *buffer)
1884 {
1885 struct ensoniq *ensoniq = entry->private_data;
1886
1887 #ifdef CHIP1370
1888 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1889 #else
1890 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1891 #endif
1892 snd_iprintf(buffer, "Joystick enable : %s\n",
1893 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1894 #ifdef CHIP1370
1895 snd_iprintf(buffer, "MIC +5V bias : %s\n",
1896 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1897 snd_iprintf(buffer, "Line In to AOUT : %s\n",
1898 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1899 #else
1900 snd_iprintf(buffer, "Joystick port : 0x%x\n",
1901 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1902 #endif
1903 }
1904
1905 static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1906 {
1907 struct snd_info_entry *entry;
1908
1909 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1910 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read);
1911 }
1912
1913 /*
1914
1915 */
1916
1917 static int snd_ensoniq_free(struct ensoniq *ensoniq)
1918 {
1919 snd_ensoniq_free_gameport(ensoniq);
1920 if (ensoniq->irq < 0)
1921 goto __hw_end;
1922 #ifdef CHIP1370
1923 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1924 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1925 #else
1926 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1927 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1928 #endif
1929 if (ensoniq->irq >= 0)
1930 synchronize_irq(ensoniq->irq);
1931 pci_set_power_state(ensoniq->pci, 3);
1932 __hw_end:
1933 #ifdef CHIP1370
1934 if (ensoniq->dma_bug.area)
1935 snd_dma_free_pages(&ensoniq->dma_bug);
1936 #endif
1937 if (ensoniq->irq >= 0)
1938 free_irq(ensoniq->irq, ensoniq);
1939 pci_release_regions(ensoniq->pci);
1940 pci_disable_device(ensoniq->pci);
1941 kfree(ensoniq);
1942 return 0;
1943 }
1944
1945 static int snd_ensoniq_dev_free(struct snd_device *device)
1946 {
1947 struct ensoniq *ensoniq = device->device_data;
1948 return snd_ensoniq_free(ensoniq);
1949 }
1950
1951 #ifdef CHIP1371
1952 static struct snd_pci_quirk es1371_amplifier_hack[] __devinitdata = {
1953 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */
1954 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */
1955 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */
1956 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */
1957 { } /* end */
1958 };
1959
1960 static struct es1371_quirk es1371_ac97_reset_hack[] = {
1961 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1962 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1963 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1964 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1965 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1966 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1967 };
1968 #endif
1969
1970 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1971 {
1972 #ifdef CHIP1371
1973 int idx;
1974 #endif
1975 /* this code was part of snd_ensoniq_create before intruduction
1976 * of suspend/resume
1977 */
1978 #ifdef CHIP1370
1979 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1980 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1981 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1982 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1983 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1984 #else
1985 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1986 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1987 outl(0, ES_REG(ensoniq, 1371_LEGACY));
1988 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1989 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1990 /* need to delay around 20ms(bleech) to give
1991 some CODECs enough time to wakeup */
1992 msleep(20);
1993 }
1994 /* AC'97 warm reset to start the bitclk */
1995 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1996 inl(ES_REG(ensoniq, CONTROL));
1997 udelay(20);
1998 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1999 /* Init the sample rate converter */
2000 snd_es1371_wait_src_ready(ensoniq);
2001 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2002 for (idx = 0; idx < 0x80; idx++)
2003 snd_es1371_src_write(ensoniq, idx, 0);
2004 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2005 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2006 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2007 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2008 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2009 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2010 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2011 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2012 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2013 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2014 snd_es1371_adc_rate(ensoniq, 22050);
2015 snd_es1371_dac1_rate(ensoniq, 22050);
2016 snd_es1371_dac2_rate(ensoniq, 22050);
2017 /* WARNING:
2018 * enabling the sample rate converter without properly programming
2019 * its parameters causes the chip to lock up (the SRC busy bit will
2020 * be stuck high, and I've found no way to rectify this other than
2021 * power cycle) - Thomas Sailer
2022 */
2023 snd_es1371_wait_src_ready(ensoniq);
2024 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2025 /* try reset codec directly */
2026 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2027 #endif
2028 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2029 outb(0x00, ES_REG(ensoniq, UART_RES));
2030 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2031 synchronize_irq(ensoniq->irq);
2032 }
2033
2034 #ifdef CONFIG_PM
2035 static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state)
2036 {
2037 struct snd_card *card = pci_get_drvdata(pci);
2038 struct ensoniq *ensoniq = card->private_data;
2039
2040 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2041
2042 snd_pcm_suspend_all(ensoniq->pcm1);
2043 snd_pcm_suspend_all(ensoniq->pcm2);
2044
2045 #ifdef CHIP1371
2046 snd_ac97_suspend(ensoniq->u.es1371.ac97);
2047 #else
2048 /* try to reset AK4531 */
2049 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2050 inw(ES_REG(ensoniq, 1370_CODEC));
2051 udelay(100);
2052 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2053 inw(ES_REG(ensoniq, 1370_CODEC));
2054 udelay(100);
2055 snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2056 #endif
2057
2058 pci_disable_device(pci);
2059 pci_save_state(pci);
2060 pci_set_power_state(pci, pci_choose_state(pci, state));
2061 return 0;
2062 }
2063
2064 static int snd_ensoniq_resume(struct pci_dev *pci)
2065 {
2066 struct snd_card *card = pci_get_drvdata(pci);
2067 struct ensoniq *ensoniq = card->private_data;
2068
2069 pci_set_power_state(pci, PCI_D0);
2070 pci_restore_state(pci);
2071 if (pci_enable_device(pci) < 0) {
2072 printk(KERN_ERR DRIVER_NAME ": pci_enable_device failed, "
2073 "disabling device\n");
2074 snd_card_disconnect(card);
2075 return -EIO;
2076 }
2077 pci_set_master(pci);
2078
2079 snd_ensoniq_chip_init(ensoniq);
2080
2081 #ifdef CHIP1371
2082 snd_ac97_resume(ensoniq->u.es1371.ac97);
2083 #else
2084 snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2085 #endif
2086 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2087 return 0;
2088 }
2089 #endif /* CONFIG_PM */
2090
2091
2092 static int __devinit snd_ensoniq_create(struct snd_card *card,
2093 struct pci_dev *pci,
2094 struct ensoniq ** rensoniq)
2095 {
2096 struct ensoniq *ensoniq;
2097 int err;
2098 static struct snd_device_ops ops = {
2099 .dev_free = snd_ensoniq_dev_free,
2100 };
2101
2102 *rensoniq = NULL;
2103 if ((err = pci_enable_device(pci)) < 0)
2104 return err;
2105 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2106 if (ensoniq == NULL) {
2107 pci_disable_device(pci);
2108 return -ENOMEM;
2109 }
2110 spin_lock_init(&ensoniq->reg_lock);
2111 mutex_init(&ensoniq->src_mutex);
2112 ensoniq->card = card;
2113 ensoniq->pci = pci;
2114 ensoniq->irq = -1;
2115 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2116 kfree(ensoniq);
2117 pci_disable_device(pci);
2118 return err;
2119 }
2120 ensoniq->port = pci_resource_start(pci, 0);
2121 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED,
2122 "Ensoniq AudioPCI", ensoniq)) {
2123 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2124 snd_ensoniq_free(ensoniq);
2125 return -EBUSY;
2126 }
2127 ensoniq->irq = pci->irq;
2128 #ifdef CHIP1370
2129 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2130 16, &ensoniq->dma_bug) < 0) {
2131 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
2132 snd_ensoniq_free(ensoniq);
2133 return -EBUSY;
2134 }
2135 #endif
2136 pci_set_master(pci);
2137 ensoniq->rev = pci->revision;
2138 #ifdef CHIP1370
2139 #if 0
2140 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2141 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2142 #else /* get microphone working */
2143 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2144 #endif
2145 ensoniq->sctrl = 0;
2146 #else
2147 ensoniq->ctrl = 0;
2148 ensoniq->sctrl = 0;
2149 ensoniq->cssr = 0;
2150 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2151 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2152
2153 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2154 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2155 #endif
2156
2157 snd_ensoniq_chip_init(ensoniq);
2158
2159 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2160 snd_ensoniq_free(ensoniq);
2161 return err;
2162 }
2163
2164 snd_ensoniq_proc_init(ensoniq);
2165
2166 snd_card_set_dev(card, &pci->dev);
2167
2168 *rensoniq = ensoniq;
2169 return 0;
2170 }
2171
2172 /*
2173 * MIDI section
2174 */
2175
2176 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2177 {
2178 struct snd_rawmidi *rmidi = ensoniq->rmidi;
2179 unsigned char status, mask, byte;
2180
2181 if (rmidi == NULL)
2182 return;
2183 /* do Rx at first */
2184 spin_lock(&ensoniq->reg_lock);
2185 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2186 while (mask) {
2187 status = inb(ES_REG(ensoniq, UART_STATUS));
2188 if ((status & mask) == 0)
2189 break;
2190 byte = inb(ES_REG(ensoniq, UART_DATA));
2191 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2192 }
2193 spin_unlock(&ensoniq->reg_lock);
2194
2195 /* do Tx at second */
2196 spin_lock(&ensoniq->reg_lock);
2197 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2198 while (mask) {
2199 status = inb(ES_REG(ensoniq, UART_STATUS));
2200 if ((status & mask) == 0)
2201 break;
2202 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2203 ensoniq->uartc &= ~ES_TXINTENM;
2204 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2205 mask &= ~ES_TXRDY;
2206 } else {
2207 outb(byte, ES_REG(ensoniq, UART_DATA));
2208 }
2209 }
2210 spin_unlock(&ensoniq->reg_lock);
2211 }
2212
2213 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2214 {
2215 struct ensoniq *ensoniq = substream->rmidi->private_data;
2216
2217 spin_lock_irq(&ensoniq->reg_lock);
2218 ensoniq->uartm |= ES_MODE_INPUT;
2219 ensoniq->midi_input = substream;
2220 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2221 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2222 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2223 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2224 }
2225 spin_unlock_irq(&ensoniq->reg_lock);
2226 return 0;
2227 }
2228
2229 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2230 {
2231 struct ensoniq *ensoniq = substream->rmidi->private_data;
2232
2233 spin_lock_irq(&ensoniq->reg_lock);
2234 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2235 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2236 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2237 } else {
2238 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2239 }
2240 ensoniq->midi_input = NULL;
2241 ensoniq->uartm &= ~ES_MODE_INPUT;
2242 spin_unlock_irq(&ensoniq->reg_lock);
2243 return 0;
2244 }
2245
2246 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2247 {
2248 struct ensoniq *ensoniq = substream->rmidi->private_data;
2249
2250 spin_lock_irq(&ensoniq->reg_lock);
2251 ensoniq->uartm |= ES_MODE_OUTPUT;
2252 ensoniq->midi_output = substream;
2253 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2254 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2255 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2256 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2257 }
2258 spin_unlock_irq(&ensoniq->reg_lock);
2259 return 0;
2260 }
2261
2262 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2263 {
2264 struct ensoniq *ensoniq = substream->rmidi->private_data;
2265
2266 spin_lock_irq(&ensoniq->reg_lock);
2267 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2268 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2269 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2270 } else {
2271 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2272 }
2273 ensoniq->midi_output = NULL;
2274 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2275 spin_unlock_irq(&ensoniq->reg_lock);
2276 return 0;
2277 }
2278
2279 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2280 {
2281 unsigned long flags;
2282 struct ensoniq *ensoniq = substream->rmidi->private_data;
2283 int idx;
2284
2285 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2286 if (up) {
2287 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2288 /* empty input FIFO */
2289 for (idx = 0; idx < 32; idx++)
2290 inb(ES_REG(ensoniq, UART_DATA));
2291 ensoniq->uartc |= ES_RXINTEN;
2292 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2293 }
2294 } else {
2295 if (ensoniq->uartc & ES_RXINTEN) {
2296 ensoniq->uartc &= ~ES_RXINTEN;
2297 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2298 }
2299 }
2300 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2301 }
2302
2303 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2304 {
2305 unsigned long flags;
2306 struct ensoniq *ensoniq = substream->rmidi->private_data;
2307 unsigned char byte;
2308
2309 spin_lock_irqsave(&ensoniq->reg_lock, flags);
2310 if (up) {
2311 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2312 ensoniq->uartc |= ES_TXINTENO(1);
2313 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2314 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2315 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2316 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2317 ensoniq->uartc &= ~ES_TXINTENM;
2318 } else {
2319 outb(byte, ES_REG(ensoniq, UART_DATA));
2320 }
2321 }
2322 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2323 }
2324 } else {
2325 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2326 ensoniq->uartc &= ~ES_TXINTENM;
2327 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2328 }
2329 }
2330 spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2331 }
2332
2333 static struct snd_rawmidi_ops snd_ensoniq_midi_output =
2334 {
2335 .open = snd_ensoniq_midi_output_open,
2336 .close = snd_ensoniq_midi_output_close,
2337 .trigger = snd_ensoniq_midi_output_trigger,
2338 };
2339
2340 static struct snd_rawmidi_ops snd_ensoniq_midi_input =
2341 {
2342 .open = snd_ensoniq_midi_input_open,
2343 .close = snd_ensoniq_midi_input_close,
2344 .trigger = snd_ensoniq_midi_input_trigger,
2345 };
2346
2347 static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2348 struct snd_rawmidi **rrawmidi)
2349 {
2350 struct snd_rawmidi *rmidi;
2351 int err;
2352
2353 if (rrawmidi)
2354 *rrawmidi = NULL;
2355 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2356 return err;
2357 #ifdef CHIP1370
2358 strcpy(rmidi->name, "ES1370");
2359 #else
2360 strcpy(rmidi->name, "ES1371");
2361 #endif
2362 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2363 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2364 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2365 SNDRV_RAWMIDI_INFO_DUPLEX;
2366 rmidi->private_data = ensoniq;
2367 ensoniq->rmidi = rmidi;
2368 if (rrawmidi)
2369 *rrawmidi = rmidi;
2370 return 0;
2371 }
2372
2373 /*
2374 * Interrupt handler
2375 */
2376
2377 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2378 {
2379 struct ensoniq *ensoniq = dev_id;
2380 unsigned int status, sctrl;
2381
2382 if (ensoniq == NULL)
2383 return IRQ_NONE;
2384
2385 status = inl(ES_REG(ensoniq, STATUS));
2386 if (!(status & ES_INTR))
2387 return IRQ_NONE;
2388
2389 spin_lock(&ensoniq->reg_lock);
2390 sctrl = ensoniq->sctrl;
2391 if (status & ES_DAC1)
2392 sctrl &= ~ES_P1_INT_EN;
2393 if (status & ES_DAC2)
2394 sctrl &= ~ES_P2_INT_EN;
2395 if (status & ES_ADC)
2396 sctrl &= ~ES_R1_INT_EN;
2397 outl(sctrl, ES_REG(ensoniq, SERIAL));
2398 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2399 spin_unlock(&ensoniq->reg_lock);
2400
2401 if (status & ES_UART)
2402 snd_ensoniq_midi_interrupt(ensoniq);
2403 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2404 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2405 if ((status & ES_ADC) && ensoniq->capture_substream)
2406 snd_pcm_period_elapsed(ensoniq->capture_substream);
2407 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2408 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2409 return IRQ_HANDLED;
2410 }
2411
2412 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2413 const struct pci_device_id *pci_id)
2414 {
2415 static int dev;
2416 struct snd_card *card;
2417 struct ensoniq *ensoniq;
2418 int err, pcm_devs[2];
2419
2420 if (dev >= SNDRV_CARDS)
2421 return -ENODEV;
2422 if (!enable[dev]) {
2423 dev++;
2424 return -ENOENT;
2425 }
2426
2427 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2428 if (card == NULL)
2429 return -ENOMEM;
2430
2431 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2432 snd_card_free(card);
2433 return err;
2434 }
2435 card->private_data = ensoniq;
2436
2437 pcm_devs[0] = 0; pcm_devs[1] = 1;
2438 #ifdef CHIP1370
2439 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2440 snd_card_free(card);
2441 return err;
2442 }
2443 #endif
2444 #ifdef CHIP1371
2445 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2446 snd_card_free(card);
2447 return err;
2448 }
2449 #endif
2450 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2451 snd_card_free(card);
2452 return err;
2453 }
2454 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2455 snd_card_free(card);
2456 return err;
2457 }
2458 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2459 snd_card_free(card);
2460 return err;
2461 }
2462
2463 snd_ensoniq_create_gameport(ensoniq, dev);
2464
2465 strcpy(card->driver, DRIVER_NAME);
2466
2467 strcpy(card->shortname, "Ensoniq AudioPCI");
2468 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2469 card->shortname,
2470 card->driver,
2471 ensoniq->port,
2472 ensoniq->irq);
2473
2474 if ((err = snd_card_register(card)) < 0) {
2475 snd_card_free(card);
2476 return err;
2477 }
2478
2479 pci_set_drvdata(pci, card);
2480 dev++;
2481 return 0;
2482 }
2483
2484 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2485 {
2486 snd_card_free(pci_get_drvdata(pci));
2487 pci_set_drvdata(pci, NULL);
2488 }
2489
2490 static struct pci_driver driver = {
2491 .name = DRIVER_NAME,
2492 .id_table = snd_audiopci_ids,
2493 .probe = snd_audiopci_probe,
2494 .remove = __devexit_p(snd_audiopci_remove),
2495 #ifdef CONFIG_PM
2496 .suspend = snd_ensoniq_suspend,
2497 .resume = snd_ensoniq_resume,
2498 #endif
2499 };
2500
2501 static int __init alsa_card_ens137x_init(void)
2502 {
2503 return pci_register_driver(&driver);
2504 }
2505
2506 static void __exit alsa_card_ens137x_exit(void)
2507 {
2508 pci_unregister_driver(&driver);
2509 }
2510
2511 module_init(alsa_card_ens137x_init)
2512 module_exit(alsa_card_ens137x_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree