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USB: cp210x: fix up set_termios variables
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / soc / sh / fsi.c
blob4a9da6b5f4e1147921185b5a4d65856805d629b8
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
21
22 /* PortA/PortB register */
23 #define REG_DO_FMT 0x0000
24 #define REG_DOFF_CTL 0x0004
25 #define REG_DOFF_ST 0x0008
26 #define REG_DI_FMT 0x000C
27 #define REG_DIFF_CTL 0x0010
28 #define REG_DIFF_ST 0x0014
29 #define REG_CKG1 0x0018
30 #define REG_CKG2 0x001C
31 #define REG_DIDT 0x0020
32 #define REG_DODT 0x0024
33 #define REG_MUTE_ST 0x0028
34 #define REG_OUT_SEL 0x0030
35
36 /* master register */
37 #define MST_CLK_RST 0x0210
38 #define MST_SOFT_RST 0x0214
39 #define MST_FIFO_SZ 0x0218
40
41 /* core register (depend on FSI version) */
42 #define A_MST_CTLR 0x0180
43 #define B_MST_CTLR 0x01A0
44 #define CPU_INT_ST 0x01F4
45 #define CPU_IEMSK 0x01F8
46 #define CPU_IMSK 0x01FC
47 #define INT_ST 0x0200
48 #define IEMSK 0x0204
49 #define IMSK 0x0208
50
51 /* DO_FMT */
52 /* DI_FMT */
53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
56
57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
60
61 #define CR_MONO (0x0 << 4)
62 #define CR_MONO_D (0x1 << 4)
63 #define CR_PCM (0x2 << 4)
64 #define CR_I2S (0x3 << 4)
65 #define CR_TDM (0x4 << 4)
66 #define CR_TDM_D (0x5 << 4)
67
68 /* DOFF_CTL */
69 /* DIFF_CTL */
70 #define IRQ_HALF 0x00100000
71 #define FIFO_CLR 0x00000001
72
73 /* DOFF_ST */
74 #define ERR_OVER 0x00000010
75 #define ERR_UNDER 0x00000001
76 #define ST_ERR (ERR_OVER | ERR_UNDER)
77
78 /* CKG1 */
79 #define ACKMD_MASK 0x00007000
80 #define BPFMD_MASK 0x00000700
81 #define DIMD (1 << 4)
82 #define DOMD (1 << 0)
83
84 /* A/B MST_CTLR */
85 #define BP (1 << 4) /* Fix the signal of Biphase output */
86 #define SE (1 << 0) /* Fix the master clock */
87
88 /* CLK_RST */
89 #define CRB (1 << 4)
90 #define CRA (1 << 0)
91
92 /* IO SHIFT / MACRO */
93 #define BI_SHIFT 12
94 #define BO_SHIFT 8
95 #define AI_SHIFT 4
96 #define AO_SHIFT 0
97 #define AB_IO(param, shift) (param << shift)
98
99 /* SOFT_RST */
100 #define PBSR (1 << 12) /* Port B Software Reset */
101 #define PASR (1 << 8) /* Port A Software Reset */
102 #define IR (1 << 4) /* Interrupt Reset */
103 #define FSISR (1 << 0) /* Software Reset */
104
105 /* OUT_SEL (FSI2) */
106 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
107 /* 1: Biphase and serial */
108
109 /* FIFO_SZ */
110 #define FIFO_SZ_MASK 0x7
111
112 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
113
114 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
115
116 typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable);
117
118 /*
119 * FSI driver use below type name for variable
120 *
121 * xxx_len : data length
122 * xxx_width : data width
123 * xxx_offset : data offset
124 * xxx_num : number of data
125 */
126
127 /*
128 * struct
129 */
130
131 struct fsi_stream {
132 struct snd_pcm_substream *substream;
133
134 int fifo_max_num;
135
136 int buff_offset;
137 int buff_len;
138 int period_len;
139 int period_num;
140
141 int uerr_num;
142 int oerr_num;
143 };
144
145 struct fsi_priv {
146 void __iomem *base;
147 struct fsi_master *master;
148
149 struct fsi_stream playback;
150 struct fsi_stream capture;
151
152 int chan_num:16;
153 int clk_master:1;
154
155 long rate;
156
157 /* for suspend/resume */
158 u32 saved_do_fmt;
159 u32 saved_di_fmt;
160 u32 saved_ckg1;
161 u32 saved_ckg2;
162 u32 saved_out_sel;
163 };
164
165 struct fsi_core {
166 int ver;
167
168 u32 int_st;
169 u32 iemsk;
170 u32 imsk;
171 u32 a_mclk;
172 u32 b_mclk;
173 };
174
175 struct fsi_master {
176 void __iomem *base;
177 int irq;
178 struct fsi_priv fsia;
179 struct fsi_priv fsib;
180 struct fsi_core *core;
181 struct sh_fsi_platform_info *info;
182 spinlock_t lock;
183
184 /* for suspend/resume */
185 u32 saved_a_mclk;
186 u32 saved_b_mclk;
187 u32 saved_iemsk;
188 u32 saved_imsk;
189 u32 saved_clk_rst;
190 u32 saved_soft_rst;
191 };
192
193 /*
194 * basic read write function
195 */
196
197 static void __fsi_reg_write(u32 reg, u32 data)
198 {
199 /* valid data area is 24bit */
200 data &= 0x00ffffff;
201
202 __raw_writel(data, reg);
203 }
204
205 static u32 __fsi_reg_read(u32 reg)
206 {
207 return __raw_readl(reg);
208 }
209
210 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
211 {
212 u32 val = __fsi_reg_read(reg);
213
214 val &= ~mask;
215 val |= data & mask;
216
217 __fsi_reg_write(reg, val);
218 }
219
220 #define fsi_reg_write(p, r, d)\
221 __fsi_reg_write((u32)(p->base + REG_##r), d)
222
223 #define fsi_reg_read(p, r)\
224 __fsi_reg_read((u32)(p->base + REG_##r))
225
226 #define fsi_reg_mask_set(p, r, m, d)\
227 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
228
229 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
230 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
231 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
232 {
233 u32 ret;
234 unsigned long flags;
235
236 spin_lock_irqsave(&master->lock, flags);
237 ret = __fsi_reg_read((u32)(master->base + reg));
238 spin_unlock_irqrestore(&master->lock, flags);
239
240 return ret;
241 }
242
243 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
244 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
245 static void _fsi_master_mask_set(struct fsi_master *master,
246 u32 reg, u32 mask, u32 data)
247 {
248 unsigned long flags;
249
250 spin_lock_irqsave(&master->lock, flags);
251 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
252 spin_unlock_irqrestore(&master->lock, flags);
253 }
254
255 /*
256 * basic function
257 */
258
259 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
260 {
261 return fsi->master;
262 }
263
264 static int fsi_is_clk_master(struct fsi_priv *fsi)
265 {
266 return fsi->clk_master;
267 }
268
269 static int fsi_is_port_a(struct fsi_priv *fsi)
270 {
271 return fsi->master->base == fsi->base;
272 }
273
274 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
275 {
276 struct snd_soc_pcm_runtime *rtd = substream->private_data;
277
278 return rtd->cpu_dai;
279 }
280
281 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
282 {
283 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
284
285 if (dai->id == 0)
286 return &master->fsia;
287 else
288 return &master->fsib;
289 }
290
291 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
292 {
293 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
294 }
295
296 static set_rate_func fsi_get_info_set_rate(struct fsi_master *master)
297 {
298 if (!master->info)
299 return NULL;
300
301 return master->info->set_rate;
302 }
303
304 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
305 {
306 int is_porta = fsi_is_port_a(fsi);
307 struct fsi_master *master = fsi_get_master(fsi);
308
309 if (!master->info)
310 return 0;
311
312 return is_porta ? master->info->porta_flags :
313 master->info->portb_flags;
314 }
315
316 static inline int fsi_stream_is_play(int stream)
317 {
318 return stream == SNDRV_PCM_STREAM_PLAYBACK;
319 }
320
321 static inline int fsi_is_play(struct snd_pcm_substream *substream)
322 {
323 return fsi_stream_is_play(substream->stream);
324 }
325
326 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
327 int is_play)
328 {
329 return is_play ? &fsi->playback : &fsi->capture;
330 }
331
332 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
333 {
334 int is_porta = fsi_is_port_a(fsi);
335 u32 shift;
336
337 if (is_porta)
338 shift = is_play ? AO_SHIFT : AI_SHIFT;
339 else
340 shift = is_play ? BO_SHIFT : BI_SHIFT;
341
342 return shift;
343 }
344
345 static void fsi_stream_push(struct fsi_priv *fsi,
346 int is_play,
347 struct snd_pcm_substream *substream,
348 u32 buffer_len,
349 u32 period_len)
350 {
351 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
352
353 io->substream = substream;
354 io->buff_len = buffer_len;
355 io->buff_offset = 0;
356 io->period_len = period_len;
357 io->period_num = 0;
358 io->oerr_num = -1; /* ignore 1st err */
359 io->uerr_num = -1; /* ignore 1st err */
360 }
361
362 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
363 {
364 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
365 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
366
367
368 if (io->oerr_num > 0)
369 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
370
371 if (io->uerr_num > 0)
372 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
373
374 io->substream = NULL;
375 io->buff_len = 0;
376 io->buff_offset = 0;
377 io->period_len = 0;
378 io->period_num = 0;
379 io->oerr_num = 0;
380 io->uerr_num = 0;
381 }
382
383 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
384 {
385 u32 status;
386 int data_num;
387
388 status = is_play ?
389 fsi_reg_read(fsi, DOFF_ST) :
390 fsi_reg_read(fsi, DIFF_ST);
391
392 data_num = 0x1ff & (status >> 8);
393 data_num *= fsi->chan_num;
394
395 return data_num;
396 }
397
398 static int fsi_len2num(int len, int width)
399 {
400 return len / width;
401 }
402
403 #define fsi_num2offset(a, b) fsi_num2len(a, b)
404 static int fsi_num2len(int num, int width)
405 {
406 return num * width;
407 }
408
409 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play)
410 {
411 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
412 struct snd_pcm_substream *substream = io->substream;
413 struct snd_pcm_runtime *runtime = substream->runtime;
414
415 return frames_to_bytes(runtime, 1) / fsi->chan_num;
416 }
417
418 static void fsi_count_fifo_err(struct fsi_priv *fsi)
419 {
420 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
421 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
422
423 if (ostatus & ERR_OVER)
424 fsi->playback.oerr_num++;
425
426 if (ostatus & ERR_UNDER)
427 fsi->playback.uerr_num++;
428
429 if (istatus & ERR_OVER)
430 fsi->capture.oerr_num++;
431
432 if (istatus & ERR_UNDER)
433 fsi->capture.uerr_num++;
434
435 fsi_reg_write(fsi, DOFF_ST, 0);
436 fsi_reg_write(fsi, DIFF_ST, 0);
437 }
438
439 /*
440 * dma function
441 */
442
443 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
444 {
445 int is_play = fsi_stream_is_play(stream);
446 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
447
448 return io->substream->runtime->dma_area + io->buff_offset;
449 }
450
451 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
452 {
453 u16 *start;
454 int i;
455
456 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
457
458 for (i = 0; i < num; i++)
459 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
460 }
461
462 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
463 {
464 u16 *start;
465 int i;
466
467 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
468
469
470 for (i = 0; i < num; i++)
471 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
472 }
473
474 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
475 {
476 u32 *start;
477 int i;
478
479 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
480
481
482 for (i = 0; i < num; i++)
483 fsi_reg_write(fsi, DODT, *(start + i));
484 }
485
486 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
487 {
488 u32 *start;
489 int i;
490
491 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
492
493 for (i = 0; i < num; i++)
494 *(start + i) = fsi_reg_read(fsi, DIDT);
495 }
496
497 /*
498 * irq function
499 */
500
501 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
502 {
503 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
504 struct fsi_master *master = fsi_get_master(fsi);
505
506 fsi_core_mask_set(master, imsk, data, data);
507 fsi_core_mask_set(master, iemsk, data, data);
508 }
509
510 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
511 {
512 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
513 struct fsi_master *master = fsi_get_master(fsi);
514
515 fsi_core_mask_set(master, imsk, data, 0);
516 fsi_core_mask_set(master, iemsk, data, 0);
517 }
518
519 static u32 fsi_irq_get_status(struct fsi_master *master)
520 {
521 return fsi_core_read(master, int_st);
522 }
523
524 static void fsi_irq_clear_status(struct fsi_priv *fsi)
525 {
526 u32 data = 0;
527 struct fsi_master *master = fsi_get_master(fsi);
528
529 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
530 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
531
532 /* clear interrupt factor */
533 fsi_core_mask_set(master, int_st, data, 0);
534 }
535
536 /*
537 * SPDIF master clock function
538 *
539 * These functions are used later FSI2
540 */
541 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
542 {
543 struct fsi_master *master = fsi_get_master(fsi);
544 u32 mask, val;
545
546 if (master->core->ver < 2) {
547 pr_err("fsi: register access err (%s)\n", __func__);
548 return;
549 }
550
551 mask = BP | SE;
552 val = enable ? mask : 0;
553
554 fsi_is_port_a(fsi) ?
555 fsi_core_mask_set(master, a_mclk, mask, val) :
556 fsi_core_mask_set(master, b_mclk, mask, val);
557 }
558
559 /*
560 * clock function
561 */
562 #define fsi_module_init(m, d) __fsi_module_clk_ctrl(m, d, 1)
563 #define fsi_module_kill(m, d) __fsi_module_clk_ctrl(m, d, 0)
564 static void __fsi_module_clk_ctrl(struct fsi_master *master,
565 struct device *dev,
566 int enable)
567 {
568 pm_runtime_get_sync(dev);
569
570 if (enable) {
571 /* enable only SR */
572 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
573 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
574 } else {
575 /* clear all registers */
576 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
577 }
578
579 pm_runtime_put_sync(dev);
580 }
581
582 #define fsi_port_start(f) __fsi_port_clk_ctrl(f, 1)
583 #define fsi_port_stop(f) __fsi_port_clk_ctrl(f, 0)
584 static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int enable)
585 {
586 struct fsi_master *master = fsi_get_master(fsi);
587 u32 soft = fsi_is_port_a(fsi) ? PASR : PBSR;
588 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
589 int is_master = fsi_is_clk_master(fsi);
590
591 fsi_master_mask_set(master, SOFT_RST, soft, (enable) ? soft : 0);
592 if (is_master)
593 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
594 }
595
596 /*
597 * ctrl function
598 */
599 static void fsi_fifo_init(struct fsi_priv *fsi,
600 int is_play,
601 struct snd_soc_dai *dai)
602 {
603 struct fsi_master *master = fsi_get_master(fsi);
604 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
605 u32 shift, i;
606
607 /* get on-chip RAM capacity */
608 shift = fsi_master_read(master, FIFO_SZ);
609 shift >>= fsi_get_port_shift(fsi, is_play);
610 shift &= FIFO_SZ_MASK;
611 io->fifo_max_num = 256 << shift;
612 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num);
613
614 /*
615 * The maximum number of sample data varies depending
616 * on the number of channels selected for the format.
617 *
618 * FIFOs are used in 4-channel units in 3-channel mode
619 * and in 8-channel units in 5- to 7-channel mode
620 * meaning that more FIFOs than the required size of DPRAM
621 * are used.
622 *
623 * ex) if 256 words of DP-RAM is connected
624 * 1 channel: 256 (256 x 1 = 256)
625 * 2 channels: 128 (128 x 2 = 256)
626 * 3 channels: 64 ( 64 x 3 = 192)
627 * 4 channels: 64 ( 64 x 4 = 256)
628 * 5 channels: 32 ( 32 x 5 = 160)
629 * 6 channels: 32 ( 32 x 6 = 192)
630 * 7 channels: 32 ( 32 x 7 = 224)
631 * 8 channels: 32 ( 32 x 8 = 256)
632 */
633 for (i = 1; i < fsi->chan_num; i <<= 1)
634 io->fifo_max_num >>= 1;
635 dev_dbg(dai->dev, "%d channel %d store\n",
636 fsi->chan_num, io->fifo_max_num);
637
638 /*
639 * set interrupt generation factor
640 * clear FIFO
641 */
642 if (is_play) {
643 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
644 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
645 } else {
646 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
647 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
648 }
649 }
650
651 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream)
652 {
653 struct snd_pcm_runtime *runtime;
654 struct snd_pcm_substream *substream = NULL;
655 int is_play = fsi_stream_is_play(stream);
656 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
657 int data_residue_num;
658 int data_num;
659 int data_num_max;
660 int ch_width;
661 int over_period;
662 void (*fn)(struct fsi_priv *fsi, int size);
663
664 if (!fsi ||
665 !io->substream ||
666 !io->substream->runtime)
667 return -EINVAL;
668
669 over_period = 0;
670 substream = io->substream;
671 runtime = substream->runtime;
672
673 /* FSI FIFO has limit.
674 * So, this driver can not send periods data at a time
675 */
676 if (io->buff_offset >=
677 fsi_num2offset(io->period_num + 1, io->period_len)) {
678
679 over_period = 1;
680 io->period_num = (io->period_num + 1) % runtime->periods;
681
682 if (0 == io->period_num)
683 io->buff_offset = 0;
684 }
685
686 /* get 1 channel data width */
687 ch_width = fsi_get_frame_width(fsi, is_play);
688
689 /* get residue data number of alsa */
690 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset,
691 ch_width);
692
693 if (is_play) {
694 /*
695 * for play-back
696 *
697 * data_num_max : number of FSI fifo free space
698 * data_num : number of ALSA residue data
699 */
700 data_num_max = io->fifo_max_num * fsi->chan_num;
701 data_num_max -= fsi_get_fifo_data_num(fsi, is_play);
702
703 data_num = data_residue_num;
704
705 switch (ch_width) {
706 case 2:
707 fn = fsi_dma_soft_push16;
708 break;
709 case 4:
710 fn = fsi_dma_soft_push32;
711 break;
712 default:
713 return -EINVAL;
714 }
715 } else {
716 /*
717 * for capture
718 *
719 * data_num_max : number of ALSA free space
720 * data_num : number of data in FSI fifo
721 */
722 data_num_max = data_residue_num;
723 data_num = fsi_get_fifo_data_num(fsi, is_play);
724
725 switch (ch_width) {
726 case 2:
727 fn = fsi_dma_soft_pop16;
728 break;
729 case 4:
730 fn = fsi_dma_soft_pop32;
731 break;
732 default:
733 return -EINVAL;
734 }
735 }
736
737 data_num = min(data_num, data_num_max);
738
739 fn(fsi, data_num);
740
741 /* update buff_offset */
742 io->buff_offset += fsi_num2offset(data_num, ch_width);
743
744 if (over_period)
745 snd_pcm_period_elapsed(substream);
746
747 return 0;
748 }
749
750 static int fsi_data_pop(struct fsi_priv *fsi)
751 {
752 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE);
753 }
754
755 static int fsi_data_push(struct fsi_priv *fsi)
756 {
757 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK);
758 }
759
760 static irqreturn_t fsi_interrupt(int irq, void *data)
761 {
762 struct fsi_master *master = data;
763 u32 int_st = fsi_irq_get_status(master);
764
765 /* clear irq status */
766 fsi_master_mask_set(master, SOFT_RST, IR, 0);
767 fsi_master_mask_set(master, SOFT_RST, IR, IR);
768
769 if (int_st & AB_IO(1, AO_SHIFT))
770 fsi_data_push(&master->fsia);
771 if (int_st & AB_IO(1, BO_SHIFT))
772 fsi_data_push(&master->fsib);
773 if (int_st & AB_IO(1, AI_SHIFT))
774 fsi_data_pop(&master->fsia);
775 if (int_st & AB_IO(1, BI_SHIFT))
776 fsi_data_pop(&master->fsib);
777
778 fsi_count_fifo_err(&master->fsia);
779 fsi_count_fifo_err(&master->fsib);
780
781 fsi_irq_clear_status(&master->fsia);
782 fsi_irq_clear_status(&master->fsib);
783
784 return IRQ_HANDLED;
785 }
786
787 /*
788 * dai ops
789 */
790
791 static int fsi_dai_startup(struct snd_pcm_substream *substream,
792 struct snd_soc_dai *dai)
793 {
794 struct fsi_priv *fsi = fsi_get_priv(substream);
795 u32 flags = fsi_get_info_flags(fsi);
796 u32 data;
797 int is_play = fsi_is_play(substream);
798
799 pm_runtime_get_sync(dai->dev);
800
801
802 /* clock inversion (CKG2) */
803 data = 0;
804 if (SH_FSI_LRM_INV & flags)
805 data |= 1 << 12;
806 if (SH_FSI_BRM_INV & flags)
807 data |= 1 << 8;
808 if (SH_FSI_LRS_INV & flags)
809 data |= 1 << 4;
810 if (SH_FSI_BRS_INV & flags)
811 data |= 1 << 0;
812
813 fsi_reg_write(fsi, CKG2, data);
814
815 /* irq clear */
816 fsi_irq_disable(fsi, is_play);
817 fsi_irq_clear_status(fsi);
818
819 /* fifo init */
820 fsi_fifo_init(fsi, is_play, dai);
821
822 return 0;
823 }
824
825 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
826 struct snd_soc_dai *dai)
827 {
828 struct fsi_priv *fsi = fsi_get_priv(substream);
829 int is_play = fsi_is_play(substream);
830 struct fsi_master *master = fsi_get_master(fsi);
831 set_rate_func set_rate = fsi_get_info_set_rate(master);
832
833 fsi_irq_disable(fsi, is_play);
834
835 if (fsi_is_clk_master(fsi))
836 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0);
837
838 fsi->rate = 0;
839
840 pm_runtime_put_sync(dai->dev);
841 }
842
843 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
844 struct snd_soc_dai *dai)
845 {
846 struct fsi_priv *fsi = fsi_get_priv(substream);
847 struct snd_pcm_runtime *runtime = substream->runtime;
848 int is_play = fsi_is_play(substream);
849 int ret = 0;
850
851 switch (cmd) {
852 case SNDRV_PCM_TRIGGER_START:
853 fsi_stream_push(fsi, is_play, substream,
854 frames_to_bytes(runtime, runtime->buffer_size),
855 frames_to_bytes(runtime, runtime->period_size));
856 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi);
857 fsi_irq_enable(fsi, is_play);
858 fsi_port_start(fsi);
859 break;
860 case SNDRV_PCM_TRIGGER_STOP:
861 fsi_port_stop(fsi);
862 fsi_irq_disable(fsi, is_play);
863 fsi_stream_pop(fsi, is_play);
864 break;
865 }
866
867 return ret;
868 }
869
870 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
871 {
872 u32 data = 0;
873
874 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
875 case SND_SOC_DAIFMT_I2S:
876 data = CR_I2S;
877 fsi->chan_num = 2;
878 break;
879 case SND_SOC_DAIFMT_LEFT_J:
880 data = CR_PCM;
881 fsi->chan_num = 2;
882 break;
883 default:
884 return -EINVAL;
885 }
886
887 fsi_reg_write(fsi, DO_FMT, data);
888 fsi_reg_write(fsi, DI_FMT, data);
889
890 return 0;
891 }
892
893 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
894 {
895 struct fsi_master *master = fsi_get_master(fsi);
896 u32 data = 0;
897
898 if (master->core->ver < 2)
899 return -EINVAL;
900
901 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
902 fsi->chan_num = 2;
903 fsi_spdif_clk_ctrl(fsi, 1);
904 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
905
906 fsi_reg_write(fsi, DO_FMT, data);
907 fsi_reg_write(fsi, DI_FMT, data);
908
909 return 0;
910 }
911
912 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
913 {
914 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
915 struct fsi_master *master = fsi_get_master(fsi);
916 set_rate_func set_rate = fsi_get_info_set_rate(master);
917 u32 flags = fsi_get_info_flags(fsi);
918 u32 data = 0;
919 int ret;
920
921 pm_runtime_get_sync(dai->dev);
922
923 /* set master/slave audio interface */
924 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
925 case SND_SOC_DAIFMT_CBM_CFM:
926 data = DIMD | DOMD;
927 fsi->clk_master = 1;
928 break;
929 case SND_SOC_DAIFMT_CBS_CFS:
930 break;
931 default:
932 ret = -EINVAL;
933 goto set_fmt_exit;
934 }
935
936 if (fsi_is_clk_master(fsi) && !set_rate) {
937 dev_err(dai->dev, "platform doesn't have set_rate\n");
938 ret = -EINVAL;
939 goto set_fmt_exit;
940 }
941
942 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
943
944 /* set format */
945 switch (flags & SH_FSI_FMT_MASK) {
946 case SH_FSI_FMT_DAI:
947 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
948 break;
949 case SH_FSI_FMT_SPDIF:
950 ret = fsi_set_fmt_spdif(fsi);
951 break;
952 default:
953 ret = -EINVAL;
954 }
955
956 set_fmt_exit:
957 pm_runtime_put_sync(dai->dev);
958
959 return ret;
960 }
961
962 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
963 struct snd_pcm_hw_params *params,
964 struct snd_soc_dai *dai)
965 {
966 struct fsi_priv *fsi = fsi_get_priv(substream);
967 struct fsi_master *master = fsi_get_master(fsi);
968 set_rate_func set_rate = fsi_get_info_set_rate(master);
969 int fsi_ver = master->core->ver;
970 long rate = params_rate(params);
971 int ret;
972
973 if (!fsi_is_clk_master(fsi))
974 return 0;
975
976 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1);
977 if (ret < 0) /* error */
978 return ret;
979
980 fsi->rate = rate;
981 if (ret > 0) {
982 u32 data = 0;
983
984 switch (ret & SH_FSI_ACKMD_MASK) {
985 default:
986 /* FALL THROUGH */
987 case SH_FSI_ACKMD_512:
988 data |= (0x0 << 12);
989 break;
990 case SH_FSI_ACKMD_256:
991 data |= (0x1 << 12);
992 break;
993 case SH_FSI_ACKMD_128:
994 data |= (0x2 << 12);
995 break;
996 case SH_FSI_ACKMD_64:
997 data |= (0x3 << 12);
998 break;
999 case SH_FSI_ACKMD_32:
1000 if (fsi_ver < 2)
1001 dev_err(dai->dev, "unsupported ACKMD\n");
1002 else
1003 data |= (0x4 << 12);
1004 break;
1005 }
1006
1007 switch (ret & SH_FSI_BPFMD_MASK) {
1008 default:
1009 /* FALL THROUGH */
1010 case SH_FSI_BPFMD_32:
1011 data |= (0x0 << 8);
1012 break;
1013 case SH_FSI_BPFMD_64:
1014 data |= (0x1 << 8);
1015 break;
1016 case SH_FSI_BPFMD_128:
1017 data |= (0x2 << 8);
1018 break;
1019 case SH_FSI_BPFMD_256:
1020 data |= (0x3 << 8);
1021 break;
1022 case SH_FSI_BPFMD_512:
1023 data |= (0x4 << 8);
1024 break;
1025 case SH_FSI_BPFMD_16:
1026 if (fsi_ver < 2)
1027 dev_err(dai->dev, "unsupported ACKMD\n");
1028 else
1029 data |= (0x7 << 8);
1030 break;
1031 }
1032
1033 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
1034 udelay(10);
1035 ret = 0;
1036 }
1037
1038 return ret;
1039
1040 }
1041
1042 static struct snd_soc_dai_ops fsi_dai_ops = {
1043 .startup = fsi_dai_startup,
1044 .shutdown = fsi_dai_shutdown,
1045 .trigger = fsi_dai_trigger,
1046 .set_fmt = fsi_dai_set_fmt,
1047 .hw_params = fsi_dai_hw_params,
1048 };
1049
1050 /*
1051 * pcm ops
1052 */
1053
1054 static struct snd_pcm_hardware fsi_pcm_hardware = {
1055 .info = SNDRV_PCM_INFO_INTERLEAVED |
1056 SNDRV_PCM_INFO_MMAP |
1057 SNDRV_PCM_INFO_MMAP_VALID |
1058 SNDRV_PCM_INFO_PAUSE,
1059 .formats = FSI_FMTS,
1060 .rates = FSI_RATES,
1061 .rate_min = 8000,
1062 .rate_max = 192000,
1063 .channels_min = 1,
1064 .channels_max = 2,
1065 .buffer_bytes_max = 64 * 1024,
1066 .period_bytes_min = 32,
1067 .period_bytes_max = 8192,
1068 .periods_min = 1,
1069 .periods_max = 32,
1070 .fifo_size = 256,
1071 };
1072
1073 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1074 {
1075 struct snd_pcm_runtime *runtime = substream->runtime;
1076 int ret = 0;
1077
1078 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1079
1080 ret = snd_pcm_hw_constraint_integer(runtime,
1081 SNDRV_PCM_HW_PARAM_PERIODS);
1082
1083 return ret;
1084 }
1085
1086 static int fsi_hw_params(struct snd_pcm_substream *substream,
1087 struct snd_pcm_hw_params *hw_params)
1088 {
1089 return snd_pcm_lib_malloc_pages(substream,
1090 params_buffer_bytes(hw_params));
1091 }
1092
1093 static int fsi_hw_free(struct snd_pcm_substream *substream)
1094 {
1095 return snd_pcm_lib_free_pages(substream);
1096 }
1097
1098 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1099 {
1100 struct snd_pcm_runtime *runtime = substream->runtime;
1101 struct fsi_priv *fsi = fsi_get_priv(substream);
1102 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1103 long location;
1104
1105 location = (io->buff_offset - 1);
1106 if (location < 0)
1107 location = 0;
1108
1109 return bytes_to_frames(runtime, location);
1110 }
1111
1112 static struct snd_pcm_ops fsi_pcm_ops = {
1113 .open = fsi_pcm_open,
1114 .ioctl = snd_pcm_lib_ioctl,
1115 .hw_params = fsi_hw_params,
1116 .hw_free = fsi_hw_free,
1117 .pointer = fsi_pointer,
1118 };
1119
1120 /*
1121 * snd_soc_platform
1122 */
1123
1124 #define PREALLOC_BUFFER (32 * 1024)
1125 #define PREALLOC_BUFFER_MAX (32 * 1024)
1126
1127 static void fsi_pcm_free(struct snd_pcm *pcm)
1128 {
1129 snd_pcm_lib_preallocate_free_for_all(pcm);
1130 }
1131
1132 static int fsi_pcm_new(struct snd_card *card,
1133 struct snd_soc_dai *dai,
1134 struct snd_pcm *pcm)
1135 {
1136 /*
1137 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1138 * in MMAP mode (i.e. aplay -M)
1139 */
1140 return snd_pcm_lib_preallocate_pages_for_all(
1141 pcm,
1142 SNDRV_DMA_TYPE_CONTINUOUS,
1143 snd_dma_continuous_data(GFP_KERNEL),
1144 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1145 }
1146
1147 /*
1148 * alsa struct
1149 */
1150
1151 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1152 {
1153 .name = "fsia-dai",
1154 .playback = {
1155 .rates = FSI_RATES,
1156 .formats = FSI_FMTS,
1157 .channels_min = 1,
1158 .channels_max = 8,
1159 },
1160 .capture = {
1161 .rates = FSI_RATES,
1162 .formats = FSI_FMTS,
1163 .channels_min = 1,
1164 .channels_max = 8,
1165 },
1166 .ops = &fsi_dai_ops,
1167 },
1168 {
1169 .name = "fsib-dai",
1170 .playback = {
1171 .rates = FSI_RATES,
1172 .formats = FSI_FMTS,
1173 .channels_min = 1,
1174 .channels_max = 8,
1175 },
1176 .capture = {
1177 .rates = FSI_RATES,
1178 .formats = FSI_FMTS,
1179 .channels_min = 1,
1180 .channels_max = 8,
1181 },
1182 .ops = &fsi_dai_ops,
1183 },
1184 };
1185
1186 static struct snd_soc_platform_driver fsi_soc_platform = {
1187 .ops = &fsi_pcm_ops,
1188 .pcm_new = fsi_pcm_new,
1189 .pcm_free = fsi_pcm_free,
1190 };
1191
1192 /*
1193 * platform function
1194 */
1195
1196 static int fsi_probe(struct platform_device *pdev)
1197 {
1198 struct fsi_master *master;
1199 const struct platform_device_id *id_entry;
1200 struct resource *res;
1201 unsigned int irq;
1202 int ret;
1203
1204 id_entry = pdev->id_entry;
1205 if (!id_entry) {
1206 dev_err(&pdev->dev, "unknown fsi device\n");
1207 return -ENODEV;
1208 }
1209
1210 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1211 irq = platform_get_irq(pdev, 0);
1212 if (!res || (int)irq <= 0) {
1213 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1214 ret = -ENODEV;
1215 goto exit;
1216 }
1217
1218 master = kzalloc(sizeof(*master), GFP_KERNEL);
1219 if (!master) {
1220 dev_err(&pdev->dev, "Could not allocate master\n");
1221 ret = -ENOMEM;
1222 goto exit;
1223 }
1224
1225 master->base = ioremap_nocache(res->start, resource_size(res));
1226 if (!master->base) {
1227 ret = -ENXIO;
1228 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1229 goto exit_kfree;
1230 }
1231
1232 /* master setting */
1233 master->irq = irq;
1234 master->info = pdev->dev.platform_data;
1235 master->core = (struct fsi_core *)id_entry->driver_data;
1236 spin_lock_init(&master->lock);
1237
1238 /* FSI A setting */
1239 master->fsia.base = master->base;
1240 master->fsia.master = master;
1241
1242 /* FSI B setting */
1243 master->fsib.base = master->base + 0x40;
1244 master->fsib.master = master;
1245
1246 pm_runtime_enable(&pdev->dev);
1247 dev_set_drvdata(&pdev->dev, master);
1248
1249 fsi_module_init(master, &pdev->dev);
1250
1251 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1252 id_entry->name, master);
1253 if (ret) {
1254 dev_err(&pdev->dev, "irq request err\n");
1255 goto exit_iounmap;
1256 }
1257
1258 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1259 if (ret < 0) {
1260 dev_err(&pdev->dev, "cannot snd soc register\n");
1261 goto exit_free_irq;
1262 }
1263
1264 ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai,
1265 ARRAY_SIZE(fsi_soc_dai));
1266 if (ret < 0) {
1267 dev_err(&pdev->dev, "cannot snd dai register\n");
1268 goto exit_snd_soc;
1269 }
1270
1271 return ret;
1272
1273 exit_snd_soc:
1274 snd_soc_unregister_platform(&pdev->dev);
1275 exit_free_irq:
1276 free_irq(irq, master);
1277 exit_iounmap:
1278 iounmap(master->base);
1279 pm_runtime_disable(&pdev->dev);
1280 exit_kfree:
1281 kfree(master);
1282 master = NULL;
1283 exit:
1284 return ret;
1285 }
1286
1287 static int fsi_remove(struct platform_device *pdev)
1288 {
1289 struct fsi_master *master;
1290
1291 master = dev_get_drvdata(&pdev->dev);
1292
1293 fsi_module_kill(master, &pdev->dev);
1294
1295 free_irq(master->irq, master);
1296 pm_runtime_disable(&pdev->dev);
1297
1298 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1299 snd_soc_unregister_platform(&pdev->dev);
1300
1301 iounmap(master->base);
1302 kfree(master);
1303
1304 return 0;
1305 }
1306
1307 static void __fsi_suspend(struct fsi_priv *fsi,
1308 struct device *dev,
1309 set_rate_func set_rate)
1310 {
1311 fsi->saved_do_fmt = fsi_reg_read(fsi, DO_FMT);
1312 fsi->saved_di_fmt = fsi_reg_read(fsi, DI_FMT);
1313 fsi->saved_ckg1 = fsi_reg_read(fsi, CKG1);
1314 fsi->saved_ckg2 = fsi_reg_read(fsi, CKG2);
1315 fsi->saved_out_sel = fsi_reg_read(fsi, OUT_SEL);
1316
1317 if (fsi_is_clk_master(fsi))
1318 set_rate(dev, fsi_is_port_a(fsi), fsi->rate, 0);
1319 }
1320
1321 static void __fsi_resume(struct fsi_priv *fsi,
1322 struct device *dev,
1323 set_rate_func set_rate)
1324 {
1325 fsi_reg_write(fsi, DO_FMT, fsi->saved_do_fmt);
1326 fsi_reg_write(fsi, DI_FMT, fsi->saved_di_fmt);
1327 fsi_reg_write(fsi, CKG1, fsi->saved_ckg1);
1328 fsi_reg_write(fsi, CKG2, fsi->saved_ckg2);
1329 fsi_reg_write(fsi, OUT_SEL, fsi->saved_out_sel);
1330
1331 if (fsi_is_clk_master(fsi))
1332 set_rate(dev, fsi_is_port_a(fsi), fsi->rate, 1);
1333 }
1334
1335 static int fsi_suspend(struct device *dev)
1336 {
1337 struct fsi_master *master = dev_get_drvdata(dev);
1338 set_rate_func set_rate = fsi_get_info_set_rate(master);
1339
1340 pm_runtime_get_sync(dev);
1341
1342 __fsi_suspend(&master->fsia, dev, set_rate);
1343 __fsi_suspend(&master->fsib, dev, set_rate);
1344
1345 master->saved_a_mclk = fsi_core_read(master, a_mclk);
1346 master->saved_b_mclk = fsi_core_read(master, b_mclk);
1347 master->saved_iemsk = fsi_core_read(master, iemsk);
1348 master->saved_imsk = fsi_core_read(master, imsk);
1349 master->saved_clk_rst = fsi_master_read(master, CLK_RST);
1350 master->saved_soft_rst = fsi_master_read(master, SOFT_RST);
1351
1352 fsi_module_kill(master, dev);
1353
1354 pm_runtime_put_sync(dev);
1355
1356 return 0;
1357 }
1358
1359 static int fsi_resume(struct device *dev)
1360 {
1361 struct fsi_master *master = dev_get_drvdata(dev);
1362 set_rate_func set_rate = fsi_get_info_set_rate(master);
1363
1364 pm_runtime_get_sync(dev);
1365
1366 fsi_module_init(master, dev);
1367
1368 fsi_master_mask_set(master, SOFT_RST, 0xffff, master->saved_soft_rst);
1369 fsi_master_mask_set(master, CLK_RST, 0xffff, master->saved_clk_rst);
1370 fsi_core_mask_set(master, a_mclk, 0xffff, master->saved_a_mclk);
1371 fsi_core_mask_set(master, b_mclk, 0xffff, master->saved_b_mclk);
1372 fsi_core_mask_set(master, iemsk, 0xffff, master->saved_iemsk);
1373 fsi_core_mask_set(master, imsk, 0xffff, master->saved_imsk);
1374
1375 __fsi_resume(&master->fsia, dev, set_rate);
1376 __fsi_resume(&master->fsib, dev, set_rate);
1377
1378 pm_runtime_put_sync(dev);
1379
1380 return 0;
1381 }
1382
1383 static int fsi_runtime_nop(struct device *dev)
1384 {
1385 /* Runtime PM callback shared between ->runtime_suspend()
1386 * and ->runtime_resume(). Simply returns success.
1387 *
1388 * This driver re-initializes all registers after
1389 * pm_runtime_get_sync() anyway so there is no need
1390 * to save and restore registers here.
1391 */
1392 return 0;
1393 }
1394
1395 static struct dev_pm_ops fsi_pm_ops = {
1396 .suspend = fsi_suspend,
1397 .resume = fsi_resume,
1398 .runtime_suspend = fsi_runtime_nop,
1399 .runtime_resume = fsi_runtime_nop,
1400 };
1401
1402 static struct fsi_core fsi1_core = {
1403 .ver = 1,
1404
1405 /* Interrupt */
1406 .int_st = INT_ST,
1407 .iemsk = IEMSK,
1408 .imsk = IMSK,
1409 };
1410
1411 static struct fsi_core fsi2_core = {
1412 .ver = 2,
1413
1414 /* Interrupt */
1415 .int_st = CPU_INT_ST,
1416 .iemsk = CPU_IEMSK,
1417 .imsk = CPU_IMSK,
1418 .a_mclk = A_MST_CTLR,
1419 .b_mclk = B_MST_CTLR,
1420 };
1421
1422 static struct platform_device_id fsi_id_table[] = {
1423 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1424 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1425 {},
1426 };
1427 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1428
1429 static struct platform_driver fsi_driver = {
1430 .driver = {
1431 .name = "fsi-pcm-audio",
1432 .pm = &fsi_pm_ops,
1433 },
1434 .probe = fsi_probe,
1435 .remove = fsi_remove,
1436 .id_table = fsi_id_table,
1437 };
1438
1439 static int __init fsi_mobile_init(void)
1440 {
1441 return platform_driver_register(&fsi_driver);
1442 }
1443
1444 static void __exit fsi_mobile_exit(void)
1445 {
1446 platform_driver_unregister(&fsi_driver);
1447 }
1448
1449 module_init(fsi_mobile_init);
1450 module_exit(fsi_mobile_exit);
1451
1452 MODULE_LICENSE("GPL");
1453 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1454 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
1455 MODULE_ALIAS("platform:fsi-pcm-audio");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree