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ARM: PL08x: ensure loops use cpu_relax()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / tg3.c
blob30ccbb6d097af220dced34f430723a3b3c5a9dca
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
39 #include <linux/ip.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
45
46 #include <net/checksum.h>
47 #include <net/ip.h>
48
49 #include <asm/system.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
53
54 #ifdef CONFIG_SPARC
55 #include <asm/idprom.h>
56 #include <asm/prom.h>
57 #endif
58
59 #define BAR_0 0
60 #define BAR_2 2
61
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
64 #else
65 #define TG3_VLAN_TAG_USED 0
66 #endif
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME "tg3"
71 #define TG3_MAJ_NUM 3
72 #define TG3_MIN_NUM 115
73 #define DRV_MODULE_VERSION \
74 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE "October 14, 2010"
76
77 #define TG3_DEF_MAC_MODE 0
78 #define TG3_DEF_RX_MODE 0
79 #define TG3_DEF_TX_MODE 0
80 #define TG3_DEF_MSG_ENABLE \
81 (NETIF_MSG_DRV | \
82 NETIF_MSG_PROBE | \
83 NETIF_MSG_LINK | \
84 NETIF_MSG_TIMER | \
85 NETIF_MSG_IFDOWN | \
86 NETIF_MSG_IFUP | \
87 NETIF_MSG_RX_ERR | \
88 NETIF_MSG_TX_ERR)
89
90 /* length of time before we decide the hardware is borked,
91 * and dev->tx_timeout() should be called to fix the problem
92 */
93 #define TG3_TX_TIMEOUT (5 * HZ)
94
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU 60
97 #define TG3_MAX_MTU(tp) \
98 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
99
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101 * You can't change the ring sizes, but you can change where you place
102 * them in the NIC onboard memory.
103 */
104 #define TG3_RX_STD_RING_SIZE(tp) \
105 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
107 RX_STD_MAX_SIZE_5717 : 512)
108 #define TG3_DEF_RX_RING_PENDING 200
109 #define TG3_RX_JMB_RING_SIZE(tp) \
110 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
112 1024 : 256)
113 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
114 #define TG3_RSS_INDIR_TBL_SIZE 128
115
116 /* Do not place this n-ring entries value into the tp struct itself,
117 * we really want to expose these constants to GCC so that modulo et
118 * al. operations are done with shifts and masks instead of with
119 * hw multiply/modulo instructions. Another solution would be to
120 * replace things like '% foo' with '& (foo - 1)'.
121 */
122
123 #define TG3_TX_RING_SIZE 512
124 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
125
126 #define TG3_RX_STD_RING_BYTES(tp) \
127 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
128 #define TG3_RX_JMB_RING_BYTES(tp) \
129 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
130 #define TG3_RX_RCB_RING_BYTES(tp) \
131 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
132 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
133 TG3_TX_RING_SIZE)
134 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
135
136 #define TG3_RX_DMA_ALIGN 16
137 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
138
139 #define TG3_DMA_BYTE_ENAB 64
140
141 #define TG3_RX_STD_DMA_SZ 1536
142 #define TG3_RX_JMB_DMA_SZ 9046
143
144 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
145
146 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
147 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
148
149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
150 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
151
152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
153 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
154
155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
156 * that are at least dword aligned when used in PCIX mode. The driver
157 * works around this bug by double copying the packet. This workaround
158 * is built into the normal double copy length check for efficiency.
159 *
160 * However, the double copy is only necessary on those architectures
161 * where unaligned memory accesses are inefficient. For those architectures
162 * where unaligned memory accesses incur little penalty, we can reintegrate
163 * the 5701 in the normal rx path. Doing so saves a device structure
164 * dereference by hardcoding the double copy threshold in place.
165 */
166 #define TG3_RX_COPY_THRESHOLD 256
167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
168 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
169 #else
170 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
171 #endif
172
173 /* minimum number of free TX descriptors required to wake up TX process */
174 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
175
176 #define TG3_RAW_IP_ALIGN 2
177
178 /* number of ETHTOOL_GSTATS u64's */
179 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
180
181 #define TG3_NUM_TEST 6
182
183 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
184
185 #define FIRMWARE_TG3 "tigon/tg3.bin"
186 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
187 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
188
189 static char version[] __devinitdata =
190 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
191
192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
194 MODULE_LICENSE("GPL");
195 MODULE_VERSION(DRV_MODULE_VERSION);
196 MODULE_FIRMWARE(FIRMWARE_TG3);
197 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
199
200 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
201 module_param(tg3_debug, int, 0);
202 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
203
204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
277 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
278 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
279 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
281 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
282 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
283 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
284 {}
285 };
286
287 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
288
289 static const struct {
290 const char string[ETH_GSTRING_LEN];
291 } ethtool_stats_keys[TG3_NUM_STATS] = {
292 { "rx_octets" },
293 { "rx_fragments" },
294 { "rx_ucast_packets" },
295 { "rx_mcast_packets" },
296 { "rx_bcast_packets" },
297 { "rx_fcs_errors" },
298 { "rx_align_errors" },
299 { "rx_xon_pause_rcvd" },
300 { "rx_xoff_pause_rcvd" },
301 { "rx_mac_ctrl_rcvd" },
302 { "rx_xoff_entered" },
303 { "rx_frame_too_long_errors" },
304 { "rx_jabbers" },
305 { "rx_undersize_packets" },
306 { "rx_in_length_errors" },
307 { "rx_out_length_errors" },
308 { "rx_64_or_less_octet_packets" },
309 { "rx_65_to_127_octet_packets" },
310 { "rx_128_to_255_octet_packets" },
311 { "rx_256_to_511_octet_packets" },
312 { "rx_512_to_1023_octet_packets" },
313 { "rx_1024_to_1522_octet_packets" },
314 { "rx_1523_to_2047_octet_packets" },
315 { "rx_2048_to_4095_octet_packets" },
316 { "rx_4096_to_8191_octet_packets" },
317 { "rx_8192_to_9022_octet_packets" },
318
319 { "tx_octets" },
320 { "tx_collisions" },
321
322 { "tx_xon_sent" },
323 { "tx_xoff_sent" },
324 { "tx_flow_control" },
325 { "tx_mac_errors" },
326 { "tx_single_collisions" },
327 { "tx_mult_collisions" },
328 { "tx_deferred" },
329 { "tx_excessive_collisions" },
330 { "tx_late_collisions" },
331 { "tx_collide_2times" },
332 { "tx_collide_3times" },
333 { "tx_collide_4times" },
334 { "tx_collide_5times" },
335 { "tx_collide_6times" },
336 { "tx_collide_7times" },
337 { "tx_collide_8times" },
338 { "tx_collide_9times" },
339 { "tx_collide_10times" },
340 { "tx_collide_11times" },
341 { "tx_collide_12times" },
342 { "tx_collide_13times" },
343 { "tx_collide_14times" },
344 { "tx_collide_15times" },
345 { "tx_ucast_packets" },
346 { "tx_mcast_packets" },
347 { "tx_bcast_packets" },
348 { "tx_carrier_sense_errors" },
349 { "tx_discards" },
350 { "tx_errors" },
351
352 { "dma_writeq_full" },
353 { "dma_write_prioq_full" },
354 { "rxbds_empty" },
355 { "rx_discards" },
356 { "rx_errors" },
357 { "rx_threshold_hit" },
358
359 { "dma_readq_full" },
360 { "dma_read_prioq_full" },
361 { "tx_comp_queue_full" },
362
363 { "ring_set_send_prod_index" },
364 { "ring_status_update" },
365 { "nic_irqs" },
366 { "nic_avoided_irqs" },
367 { "nic_tx_threshold_hit" }
368 };
369
370 static const struct {
371 const char string[ETH_GSTRING_LEN];
372 } ethtool_test_keys[TG3_NUM_TEST] = {
373 { "nvram test (online) " },
374 { "link test (online) " },
375 { "register test (offline)" },
376 { "memory test (offline)" },
377 { "loopback test (offline)" },
378 { "interrupt test (offline)" },
379 };
380
381 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
382 {
383 writel(val, tp->regs + off);
384 }
385
386 static u32 tg3_read32(struct tg3 *tp, u32 off)
387 {
388 return readl(tp->regs + off);
389 }
390
391 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
392 {
393 writel(val, tp->aperegs + off);
394 }
395
396 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
397 {
398 return readl(tp->aperegs + off);
399 }
400
401 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
402 {
403 unsigned long flags;
404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409 }
410
411 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
412 {
413 writel(val, tp->regs + off);
414 readl(tp->regs + off);
415 }
416
417 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
418 {
419 unsigned long flags;
420 u32 val;
421
422 spin_lock_irqsave(&tp->indirect_lock, flags);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
424 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425 spin_unlock_irqrestore(&tp->indirect_lock, flags);
426 return val;
427 }
428
429 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
430 {
431 unsigned long flags;
432
433 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
434 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
435 TG3_64BIT_REG_LOW, val);
436 return;
437 }
438 if (off == TG3_RX_STD_PROD_IDX_REG) {
439 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
440 TG3_64BIT_REG_LOW, val);
441 return;
442 }
443
444 spin_lock_irqsave(&tp->indirect_lock, flags);
445 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
446 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
447 spin_unlock_irqrestore(&tp->indirect_lock, flags);
448
449 /* In indirect mode when disabling interrupts, we also need
450 * to clear the interrupt bit in the GRC local ctrl register.
451 */
452 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
453 (val == 0x1)) {
454 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
455 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
456 }
457 }
458
459 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
460 {
461 unsigned long flags;
462 u32 val;
463
464 spin_lock_irqsave(&tp->indirect_lock, flags);
465 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
466 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
467 spin_unlock_irqrestore(&tp->indirect_lock, flags);
468 return val;
469 }
470
471 /* usec_wait specifies the wait time in usec when writing to certain registers
472 * where it is unsafe to read back the register without some delay.
473 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
474 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
475 */
476 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
477 {
478 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
479 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
480 /* Non-posted methods */
481 tp->write32(tp, off, val);
482 else {
483 /* Posted method */
484 tg3_write32(tp, off, val);
485 if (usec_wait)
486 udelay(usec_wait);
487 tp->read32(tp, off);
488 }
489 /* Wait again after the read for the posted method to guarantee that
490 * the wait time is met.
491 */
492 if (usec_wait)
493 udelay(usec_wait);
494 }
495
496 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
497 {
498 tp->write32_mbox(tp, off, val);
499 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
500 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
501 tp->read32_mbox(tp, off);
502 }
503
504 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
505 {
506 void __iomem *mbox = tp->regs + off;
507 writel(val, mbox);
508 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
509 writel(val, mbox);
510 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
511 readl(mbox);
512 }
513
514 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
515 {
516 return readl(tp->regs + off + GRCMBOX_BASE);
517 }
518
519 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
520 {
521 writel(val, tp->regs + off + GRCMBOX_BASE);
522 }
523
524 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
525 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
526 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
527 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
528 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
529
530 #define tw32(reg, val) tp->write32(tp, reg, val)
531 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
532 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
533 #define tr32(reg) tp->read32(tp, reg)
534
535 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
536 {
537 unsigned long flags;
538
539 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
540 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
541 return;
542
543 spin_lock_irqsave(&tp->indirect_lock, flags);
544 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
545 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
547
548 /* Always leave this as zero. */
549 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
550 } else {
551 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
552 tw32_f(TG3PCI_MEM_WIN_DATA, val);
553
554 /* Always leave this as zero. */
555 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
556 }
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 }
559
560 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
561 {
562 unsigned long flags;
563
564 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
565 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
566 *val = 0;
567 return;
568 }
569
570 spin_lock_irqsave(&tp->indirect_lock, flags);
571 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
572 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
573 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
574
575 /* Always leave this as zero. */
576 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
577 } else {
578 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
579 *val = tr32(TG3PCI_MEM_WIN_DATA);
580
581 /* Always leave this as zero. */
582 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
583 }
584 spin_unlock_irqrestore(&tp->indirect_lock, flags);
585 }
586
587 static void tg3_ape_lock_init(struct tg3 *tp)
588 {
589 int i;
590 u32 regbase;
591
592 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
593 regbase = TG3_APE_LOCK_GRANT;
594 else
595 regbase = TG3_APE_PER_LOCK_GRANT;
596
597 /* Make sure the driver hasn't any stale locks. */
598 for (i = 0; i < 8; i++)
599 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
600 }
601
602 static int tg3_ape_lock(struct tg3 *tp, int locknum)
603 {
604 int i, off;
605 int ret = 0;
606 u32 status, req, gnt;
607
608 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
609 return 0;
610
611 switch (locknum) {
612 case TG3_APE_LOCK_GRC:
613 case TG3_APE_LOCK_MEM:
614 break;
615 default:
616 return -EINVAL;
617 }
618
619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
620 req = TG3_APE_LOCK_REQ;
621 gnt = TG3_APE_LOCK_GRANT;
622 } else {
623 req = TG3_APE_PER_LOCK_REQ;
624 gnt = TG3_APE_PER_LOCK_GRANT;
625 }
626
627 off = 4 * locknum;
628
629 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
630
631 /* Wait for up to 1 millisecond to acquire lock. */
632 for (i = 0; i < 100; i++) {
633 status = tg3_ape_read32(tp, gnt + off);
634 if (status == APE_LOCK_GRANT_DRIVER)
635 break;
636 udelay(10);
637 }
638
639 if (status != APE_LOCK_GRANT_DRIVER) {
640 /* Revoke the lock request. */
641 tg3_ape_write32(tp, gnt + off,
642 APE_LOCK_GRANT_DRIVER);
643
644 ret = -EBUSY;
645 }
646
647 return ret;
648 }
649
650 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
651 {
652 u32 gnt;
653
654 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
655 return;
656
657 switch (locknum) {
658 case TG3_APE_LOCK_GRC:
659 case TG3_APE_LOCK_MEM:
660 break;
661 default:
662 return;
663 }
664
665 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
666 gnt = TG3_APE_LOCK_GRANT;
667 else
668 gnt = TG3_APE_PER_LOCK_GRANT;
669
670 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
671 }
672
673 static void tg3_disable_ints(struct tg3 *tp)
674 {
675 int i;
676
677 tw32(TG3PCI_MISC_HOST_CTRL,
678 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
679 for (i = 0; i < tp->irq_max; i++)
680 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
681 }
682
683 static void tg3_enable_ints(struct tg3 *tp)
684 {
685 int i;
686
687 tp->irq_sync = 0;
688 wmb();
689
690 tw32(TG3PCI_MISC_HOST_CTRL,
691 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
692
693 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
694 for (i = 0; i < tp->irq_cnt; i++) {
695 struct tg3_napi *tnapi = &tp->napi[i];
696
697 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
698 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
699 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
700
701 tp->coal_now |= tnapi->coal_now;
702 }
703
704 /* Force an initial interrupt */
705 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
706 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
707 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
708 else
709 tw32(HOSTCC_MODE, tp->coal_now);
710
711 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
712 }
713
714 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
715 {
716 struct tg3 *tp = tnapi->tp;
717 struct tg3_hw_status *sblk = tnapi->hw_status;
718 unsigned int work_exists = 0;
719
720 /* check for phy events */
721 if (!(tp->tg3_flags &
722 (TG3_FLAG_USE_LINKCHG_REG |
723 TG3_FLAG_POLL_SERDES))) {
724 if (sblk->status & SD_STATUS_LINK_CHG)
725 work_exists = 1;
726 }
727 /* check for RX/TX work to do */
728 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
729 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
730 work_exists = 1;
731
732 return work_exists;
733 }
734
735 /* tg3_int_reenable
736 * similar to tg3_enable_ints, but it accurately determines whether there
737 * is new work pending and can return without flushing the PIO write
738 * which reenables interrupts
739 */
740 static void tg3_int_reenable(struct tg3_napi *tnapi)
741 {
742 struct tg3 *tp = tnapi->tp;
743
744 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
745 mmiowb();
746
747 /* When doing tagged status, this work check is unnecessary.
748 * The last_tag we write above tells the chip which piece of
749 * work we've completed.
750 */
751 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
752 tg3_has_work(tnapi))
753 tw32(HOSTCC_MODE, tp->coalesce_mode |
754 HOSTCC_MODE_ENABLE | tnapi->coal_now);
755 }
756
757 static void tg3_switch_clocks(struct tg3 *tp)
758 {
759 u32 clock_ctrl;
760 u32 orig_clock_ctrl;
761
762 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
763 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
764 return;
765
766 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
767
768 orig_clock_ctrl = clock_ctrl;
769 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
770 CLOCK_CTRL_CLKRUN_OENABLE |
771 0x1f);
772 tp->pci_clock_ctrl = clock_ctrl;
773
774 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
775 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
776 tw32_wait_f(TG3PCI_CLOCK_CTRL,
777 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
778 }
779 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
780 tw32_wait_f(TG3PCI_CLOCK_CTRL,
781 clock_ctrl |
782 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
783 40);
784 tw32_wait_f(TG3PCI_CLOCK_CTRL,
785 clock_ctrl | (CLOCK_CTRL_ALTCLK),
786 40);
787 }
788 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
789 }
790
791 #define PHY_BUSY_LOOPS 5000
792
793 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
794 {
795 u32 frame_val;
796 unsigned int loops;
797 int ret;
798
799 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800 tw32_f(MAC_MI_MODE,
801 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
802 udelay(80);
803 }
804
805 *val = 0x0;
806
807 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
808 MI_COM_PHY_ADDR_MASK);
809 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
810 MI_COM_REG_ADDR_MASK);
811 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
812
813 tw32_f(MAC_MI_COM, frame_val);
814
815 loops = PHY_BUSY_LOOPS;
816 while (loops != 0) {
817 udelay(10);
818 frame_val = tr32(MAC_MI_COM);
819
820 if ((frame_val & MI_COM_BUSY) == 0) {
821 udelay(5);
822 frame_val = tr32(MAC_MI_COM);
823 break;
824 }
825 loops -= 1;
826 }
827
828 ret = -EBUSY;
829 if (loops != 0) {
830 *val = frame_val & MI_COM_DATA_MASK;
831 ret = 0;
832 }
833
834 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
835 tw32_f(MAC_MI_MODE, tp->mi_mode);
836 udelay(80);
837 }
838
839 return ret;
840 }
841
842 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
843 {
844 u32 frame_val;
845 unsigned int loops;
846 int ret;
847
848 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
849 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
850 return 0;
851
852 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
853 tw32_f(MAC_MI_MODE,
854 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
855 udelay(80);
856 }
857
858 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
859 MI_COM_PHY_ADDR_MASK);
860 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
861 MI_COM_REG_ADDR_MASK);
862 frame_val |= (val & MI_COM_DATA_MASK);
863 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
864
865 tw32_f(MAC_MI_COM, frame_val);
866
867 loops = PHY_BUSY_LOOPS;
868 while (loops != 0) {
869 udelay(10);
870 frame_val = tr32(MAC_MI_COM);
871 if ((frame_val & MI_COM_BUSY) == 0) {
872 udelay(5);
873 frame_val = tr32(MAC_MI_COM);
874 break;
875 }
876 loops -= 1;
877 }
878
879 ret = -EBUSY;
880 if (loops != 0)
881 ret = 0;
882
883 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
884 tw32_f(MAC_MI_MODE, tp->mi_mode);
885 udelay(80);
886 }
887
888 return ret;
889 }
890
891 static int tg3_bmcr_reset(struct tg3 *tp)
892 {
893 u32 phy_control;
894 int limit, err;
895
896 /* OK, reset it, and poll the BMCR_RESET bit until it
897 * clears or we time out.
898 */
899 phy_control = BMCR_RESET;
900 err = tg3_writephy(tp, MII_BMCR, phy_control);
901 if (err != 0)
902 return -EBUSY;
903
904 limit = 5000;
905 while (limit--) {
906 err = tg3_readphy(tp, MII_BMCR, &phy_control);
907 if (err != 0)
908 return -EBUSY;
909
910 if ((phy_control & BMCR_RESET) == 0) {
911 udelay(40);
912 break;
913 }
914 udelay(10);
915 }
916 if (limit < 0)
917 return -EBUSY;
918
919 return 0;
920 }
921
922 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
923 {
924 struct tg3 *tp = bp->priv;
925 u32 val;
926
927 spin_lock_bh(&tp->lock);
928
929 if (tg3_readphy(tp, reg, &val))
930 val = -EIO;
931
932 spin_unlock_bh(&tp->lock);
933
934 return val;
935 }
936
937 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
938 {
939 struct tg3 *tp = bp->priv;
940 u32 ret = 0;
941
942 spin_lock_bh(&tp->lock);
943
944 if (tg3_writephy(tp, reg, val))
945 ret = -EIO;
946
947 spin_unlock_bh(&tp->lock);
948
949 return ret;
950 }
951
952 static int tg3_mdio_reset(struct mii_bus *bp)
953 {
954 return 0;
955 }
956
957 static void tg3_mdio_config_5785(struct tg3 *tp)
958 {
959 u32 val;
960 struct phy_device *phydev;
961
962 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
963 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
964 case PHY_ID_BCM50610:
965 case PHY_ID_BCM50610M:
966 val = MAC_PHYCFG2_50610_LED_MODES;
967 break;
968 case PHY_ID_BCMAC131:
969 val = MAC_PHYCFG2_AC131_LED_MODES;
970 break;
971 case PHY_ID_RTL8211C:
972 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
973 break;
974 case PHY_ID_RTL8201E:
975 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
976 break;
977 default:
978 return;
979 }
980
981 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
982 tw32(MAC_PHYCFG2, val);
983
984 val = tr32(MAC_PHYCFG1);
985 val &= ~(MAC_PHYCFG1_RGMII_INT |
986 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
987 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
988 tw32(MAC_PHYCFG1, val);
989
990 return;
991 }
992
993 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
994 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
995 MAC_PHYCFG2_FMODE_MASK_MASK |
996 MAC_PHYCFG2_GMODE_MASK_MASK |
997 MAC_PHYCFG2_ACT_MASK_MASK |
998 MAC_PHYCFG2_QUAL_MASK_MASK |
999 MAC_PHYCFG2_INBAND_ENABLE;
1000
1001 tw32(MAC_PHYCFG2, val);
1002
1003 val = tr32(MAC_PHYCFG1);
1004 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1005 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1006 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1007 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1008 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1009 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1010 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1011 }
1012 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1013 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1014 tw32(MAC_PHYCFG1, val);
1015
1016 val = tr32(MAC_EXT_RGMII_MODE);
1017 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1018 MAC_RGMII_MODE_RX_QUALITY |
1019 MAC_RGMII_MODE_RX_ACTIVITY |
1020 MAC_RGMII_MODE_RX_ENG_DET |
1021 MAC_RGMII_MODE_TX_ENABLE |
1022 MAC_RGMII_MODE_TX_LOWPWR |
1023 MAC_RGMII_MODE_TX_RESET);
1024 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1025 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1026 val |= MAC_RGMII_MODE_RX_INT_B |
1027 MAC_RGMII_MODE_RX_QUALITY |
1028 MAC_RGMII_MODE_RX_ACTIVITY |
1029 MAC_RGMII_MODE_RX_ENG_DET;
1030 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1031 val |= MAC_RGMII_MODE_TX_ENABLE |
1032 MAC_RGMII_MODE_TX_LOWPWR |
1033 MAC_RGMII_MODE_TX_RESET;
1034 }
1035 tw32(MAC_EXT_RGMII_MODE, val);
1036 }
1037
1038 static void tg3_mdio_start(struct tg3 *tp)
1039 {
1040 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1041 tw32_f(MAC_MI_MODE, tp->mi_mode);
1042 udelay(80);
1043
1044 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1046 tg3_mdio_config_5785(tp);
1047 }
1048
1049 static int tg3_mdio_init(struct tg3 *tp)
1050 {
1051 int i;
1052 u32 reg;
1053 struct phy_device *phydev;
1054
1055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1057 u32 is_serdes;
1058
1059 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1060
1061 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1062 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063 else
1064 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1065 TG3_CPMU_PHY_STRAP_IS_SERDES;
1066 if (is_serdes)
1067 tp->phy_addr += 7;
1068 } else
1069 tp->phy_addr = TG3_PHY_MII_ADDR;
1070
1071 tg3_mdio_start(tp);
1072
1073 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1074 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1075 return 0;
1076
1077 tp->mdio_bus = mdiobus_alloc();
1078 if (tp->mdio_bus == NULL)
1079 return -ENOMEM;
1080
1081 tp->mdio_bus->name = "tg3 mdio bus";
1082 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1083 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1084 tp->mdio_bus->priv = tp;
1085 tp->mdio_bus->parent = &tp->pdev->dev;
1086 tp->mdio_bus->read = &tg3_mdio_read;
1087 tp->mdio_bus->write = &tg3_mdio_write;
1088 tp->mdio_bus->reset = &tg3_mdio_reset;
1089 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1090 tp->mdio_bus->irq = &tp->mdio_irq[0];
1091
1092 for (i = 0; i < PHY_MAX_ADDR; i++)
1093 tp->mdio_bus->irq[i] = PHY_POLL;
1094
1095 /* The bus registration will look for all the PHYs on the mdio bus.
1096 * Unfortunately, it does not ensure the PHY is powered up before
1097 * accessing the PHY ID registers. A chip reset is the
1098 * quickest way to bring the device back to an operational state..
1099 */
1100 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1101 tg3_bmcr_reset(tp);
1102
1103 i = mdiobus_register(tp->mdio_bus);
1104 if (i) {
1105 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1106 mdiobus_free(tp->mdio_bus);
1107 return i;
1108 }
1109
1110 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111
1112 if (!phydev || !phydev->drv) {
1113 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1114 mdiobus_unregister(tp->mdio_bus);
1115 mdiobus_free(tp->mdio_bus);
1116 return -ENODEV;
1117 }
1118
1119 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1120 case PHY_ID_BCM57780:
1121 phydev->interface = PHY_INTERFACE_MODE_GMII;
1122 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123 break;
1124 case PHY_ID_BCM50610:
1125 case PHY_ID_BCM50610M:
1126 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1127 PHY_BRCM_RX_REFCLK_UNUSED |
1128 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1129 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1130 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1131 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1132 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1133 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1134 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1135 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136 /* fallthru */
1137 case PHY_ID_RTL8211C:
1138 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139 break;
1140 case PHY_ID_RTL8201E:
1141 case PHY_ID_BCMAC131:
1142 phydev->interface = PHY_INTERFACE_MODE_MII;
1143 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1144 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145 break;
1146 }
1147
1148 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149
1150 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1151 tg3_mdio_config_5785(tp);
1152
1153 return 0;
1154 }
1155
1156 static void tg3_mdio_fini(struct tg3 *tp)
1157 {
1158 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1159 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1160 mdiobus_unregister(tp->mdio_bus);
1161 mdiobus_free(tp->mdio_bus);
1162 }
1163 }
1164
1165 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1166 {
1167 int err;
1168
1169 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1170 if (err)
1171 goto done;
1172
1173 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1174 if (err)
1175 goto done;
1176
1177 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1178 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1179 if (err)
1180 goto done;
1181
1182 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1183
1184 done:
1185 return err;
1186 }
1187
1188 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1189 {
1190 int err;
1191
1192 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1193 if (err)
1194 goto done;
1195
1196 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1197 if (err)
1198 goto done;
1199
1200 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1201 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1202 if (err)
1203 goto done;
1204
1205 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1206
1207 done:
1208 return err;
1209 }
1210
1211 /* tp->lock is held. */
1212 static inline void tg3_generate_fw_event(struct tg3 *tp)
1213 {
1214 u32 val;
1215
1216 val = tr32(GRC_RX_CPU_EVENT);
1217 val |= GRC_RX_CPU_DRIVER_EVENT;
1218 tw32_f(GRC_RX_CPU_EVENT, val);
1219
1220 tp->last_event_jiffies = jiffies;
1221 }
1222
1223 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1224
1225 /* tp->lock is held. */
1226 static void tg3_wait_for_event_ack(struct tg3 *tp)
1227 {
1228 int i;
1229 unsigned int delay_cnt;
1230 long time_remain;
1231
1232 /* If enough time has passed, no wait is necessary. */
1233 time_remain = (long)(tp->last_event_jiffies + 1 +
1234 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1235 (long)jiffies;
1236 if (time_remain < 0)
1237 return;
1238
1239 /* Check if we can shorten the wait time. */
1240 delay_cnt = jiffies_to_usecs(time_remain);
1241 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1242 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1243 delay_cnt = (delay_cnt >> 3) + 1;
1244
1245 for (i = 0; i < delay_cnt; i++) {
1246 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1247 break;
1248 udelay(8);
1249 }
1250 }
1251
1252 /* tp->lock is held. */
1253 static void tg3_ump_link_report(struct tg3 *tp)
1254 {
1255 u32 reg;
1256 u32 val;
1257
1258 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1259 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1260 return;
1261
1262 tg3_wait_for_event_ack(tp);
1263
1264 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1265
1266 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1267
1268 val = 0;
1269 if (!tg3_readphy(tp, MII_BMCR, &reg))
1270 val = reg << 16;
1271 if (!tg3_readphy(tp, MII_BMSR, &reg))
1272 val |= (reg & 0xffff);
1273 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1274
1275 val = 0;
1276 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1277 val = reg << 16;
1278 if (!tg3_readphy(tp, MII_LPA, &reg))
1279 val |= (reg & 0xffff);
1280 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1281
1282 val = 0;
1283 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1284 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1285 val = reg << 16;
1286 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1287 val |= (reg & 0xffff);
1288 }
1289 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1290
1291 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1292 val = reg << 16;
1293 else
1294 val = 0;
1295 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1296
1297 tg3_generate_fw_event(tp);
1298 }
1299
1300 static void tg3_link_report(struct tg3 *tp)
1301 {
1302 if (!netif_carrier_ok(tp->dev)) {
1303 netif_info(tp, link, tp->dev, "Link is down\n");
1304 tg3_ump_link_report(tp);
1305 } else if (netif_msg_link(tp)) {
1306 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1307 (tp->link_config.active_speed == SPEED_1000 ?
1308 1000 :
1309 (tp->link_config.active_speed == SPEED_100 ?
1310 100 : 10)),
1311 (tp->link_config.active_duplex == DUPLEX_FULL ?
1312 "full" : "half"));
1313
1314 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1315 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1316 "on" : "off",
1317 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1318 "on" : "off");
1319 tg3_ump_link_report(tp);
1320 }
1321 }
1322
1323 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1324 {
1325 u16 miireg;
1326
1327 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1328 miireg = ADVERTISE_PAUSE_CAP;
1329 else if (flow_ctrl & FLOW_CTRL_TX)
1330 miireg = ADVERTISE_PAUSE_ASYM;
1331 else if (flow_ctrl & FLOW_CTRL_RX)
1332 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1333 else
1334 miireg = 0;
1335
1336 return miireg;
1337 }
1338
1339 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1340 {
1341 u16 miireg;
1342
1343 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1344 miireg = ADVERTISE_1000XPAUSE;
1345 else if (flow_ctrl & FLOW_CTRL_TX)
1346 miireg = ADVERTISE_1000XPSE_ASYM;
1347 else if (flow_ctrl & FLOW_CTRL_RX)
1348 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1349 else
1350 miireg = 0;
1351
1352 return miireg;
1353 }
1354
1355 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1356 {
1357 u8 cap = 0;
1358
1359 if (lcladv & ADVERTISE_1000XPAUSE) {
1360 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361 if (rmtadv & LPA_1000XPAUSE)
1362 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1363 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1364 cap = FLOW_CTRL_RX;
1365 } else {
1366 if (rmtadv & LPA_1000XPAUSE)
1367 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1368 }
1369 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1370 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1371 cap = FLOW_CTRL_TX;
1372 }
1373
1374 return cap;
1375 }
1376
1377 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1378 {
1379 u8 autoneg;
1380 u8 flowctrl = 0;
1381 u32 old_rx_mode = tp->rx_mode;
1382 u32 old_tx_mode = tp->tx_mode;
1383
1384 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1385 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1386 else
1387 autoneg = tp->link_config.autoneg;
1388
1389 if (autoneg == AUTONEG_ENABLE &&
1390 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1391 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1392 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1393 else
1394 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1395 } else
1396 flowctrl = tp->link_config.flowctrl;
1397
1398 tp->link_config.active_flowctrl = flowctrl;
1399
1400 if (flowctrl & FLOW_CTRL_RX)
1401 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1402 else
1403 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1404
1405 if (old_rx_mode != tp->rx_mode)
1406 tw32_f(MAC_RX_MODE, tp->rx_mode);
1407
1408 if (flowctrl & FLOW_CTRL_TX)
1409 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1410 else
1411 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1412
1413 if (old_tx_mode != tp->tx_mode)
1414 tw32_f(MAC_TX_MODE, tp->tx_mode);
1415 }
1416
1417 static void tg3_adjust_link(struct net_device *dev)
1418 {
1419 u8 oldflowctrl, linkmesg = 0;
1420 u32 mac_mode, lcl_adv, rmt_adv;
1421 struct tg3 *tp = netdev_priv(dev);
1422 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1423
1424 spin_lock_bh(&tp->lock);
1425
1426 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1427 MAC_MODE_HALF_DUPLEX);
1428
1429 oldflowctrl = tp->link_config.active_flowctrl;
1430
1431 if (phydev->link) {
1432 lcl_adv = 0;
1433 rmt_adv = 0;
1434
1435 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1436 mac_mode |= MAC_MODE_PORT_MODE_MII;
1437 else if (phydev->speed == SPEED_1000 ||
1438 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1439 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1440 else
1441 mac_mode |= MAC_MODE_PORT_MODE_MII;
1442
1443 if (phydev->duplex == DUPLEX_HALF)
1444 mac_mode |= MAC_MODE_HALF_DUPLEX;
1445 else {
1446 lcl_adv = tg3_advert_flowctrl_1000T(
1447 tp->link_config.flowctrl);
1448
1449 if (phydev->pause)
1450 rmt_adv = LPA_PAUSE_CAP;
1451 if (phydev->asym_pause)
1452 rmt_adv |= LPA_PAUSE_ASYM;
1453 }
1454
1455 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1456 } else
1457 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1458
1459 if (mac_mode != tp->mac_mode) {
1460 tp->mac_mode = mac_mode;
1461 tw32_f(MAC_MODE, tp->mac_mode);
1462 udelay(40);
1463 }
1464
1465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1466 if (phydev->speed == SPEED_10)
1467 tw32(MAC_MI_STAT,
1468 MAC_MI_STAT_10MBPS_MODE |
1469 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1470 else
1471 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1472 }
1473
1474 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1475 tw32(MAC_TX_LENGTHS,
1476 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1477 (6 << TX_LENGTHS_IPG_SHIFT) |
1478 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1479 else
1480 tw32(MAC_TX_LENGTHS,
1481 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1482 (6 << TX_LENGTHS_IPG_SHIFT) |
1483 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1484
1485 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1486 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1487 phydev->speed != tp->link_config.active_speed ||
1488 phydev->duplex != tp->link_config.active_duplex ||
1489 oldflowctrl != tp->link_config.active_flowctrl)
1490 linkmesg = 1;
1491
1492 tp->link_config.active_speed = phydev->speed;
1493 tp->link_config.active_duplex = phydev->duplex;
1494
1495 spin_unlock_bh(&tp->lock);
1496
1497 if (linkmesg)
1498 tg3_link_report(tp);
1499 }
1500
1501 static int tg3_phy_init(struct tg3 *tp)
1502 {
1503 struct phy_device *phydev;
1504
1505 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1506 return 0;
1507
1508 /* Bring the PHY back to a known state. */
1509 tg3_bmcr_reset(tp);
1510
1511 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1512
1513 /* Attach the MAC to the PHY. */
1514 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1515 phydev->dev_flags, phydev->interface);
1516 if (IS_ERR(phydev)) {
1517 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1518 return PTR_ERR(phydev);
1519 }
1520
1521 /* Mask with MAC supported features. */
1522 switch (phydev->interface) {
1523 case PHY_INTERFACE_MODE_GMII:
1524 case PHY_INTERFACE_MODE_RGMII:
1525 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1526 phydev->supported &= (PHY_GBIT_FEATURES |
1527 SUPPORTED_Pause |
1528 SUPPORTED_Asym_Pause);
1529 break;
1530 }
1531 /* fallthru */
1532 case PHY_INTERFACE_MODE_MII:
1533 phydev->supported &= (PHY_BASIC_FEATURES |
1534 SUPPORTED_Pause |
1535 SUPPORTED_Asym_Pause);
1536 break;
1537 default:
1538 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539 return -EINVAL;
1540 }
1541
1542 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1543
1544 phydev->advertising = phydev->supported;
1545
1546 return 0;
1547 }
1548
1549 static void tg3_phy_start(struct tg3 *tp)
1550 {
1551 struct phy_device *phydev;
1552
1553 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1554 return;
1555
1556 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1557
1558 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1559 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1560 phydev->speed = tp->link_config.orig_speed;
1561 phydev->duplex = tp->link_config.orig_duplex;
1562 phydev->autoneg = tp->link_config.orig_autoneg;
1563 phydev->advertising = tp->link_config.orig_advertising;
1564 }
1565
1566 phy_start(phydev);
1567
1568 phy_start_aneg(phydev);
1569 }
1570
1571 static void tg3_phy_stop(struct tg3 *tp)
1572 {
1573 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1574 return;
1575
1576 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1577 }
1578
1579 static void tg3_phy_fini(struct tg3 *tp)
1580 {
1581 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1582 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1583 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1584 }
1585 }
1586
1587 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1588 {
1589 int err;
1590
1591 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592 if (!err)
1593 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595 return err;
1596 }
1597
1598 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1599 {
1600 int err;
1601
1602 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1603 if (!err)
1604 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1605
1606 return err;
1607 }
1608
1609 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1610 {
1611 u32 phytest;
1612
1613 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1614 u32 phy;
1615
1616 tg3_writephy(tp, MII_TG3_FET_TEST,
1617 phytest | MII_TG3_FET_SHADOW_EN);
1618 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1619 if (enable)
1620 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1621 else
1622 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1623 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1624 }
1625 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1626 }
1627 }
1628
1629 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1630 {
1631 u32 reg;
1632
1633 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1634 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1635 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1636 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1637 return;
1638
1639 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1640 tg3_phy_fet_toggle_apd(tp, enable);
1641 return;
1642 }
1643
1644 reg = MII_TG3_MISC_SHDW_WREN |
1645 MII_TG3_MISC_SHDW_SCR5_SEL |
1646 MII_TG3_MISC_SHDW_SCR5_LPED |
1647 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1648 MII_TG3_MISC_SHDW_SCR5_SDTL |
1649 MII_TG3_MISC_SHDW_SCR5_C125OE;
1650 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1651 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1652
1653 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1654
1655
1656 reg = MII_TG3_MISC_SHDW_WREN |
1657 MII_TG3_MISC_SHDW_APD_SEL |
1658 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1659 if (enable)
1660 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1661
1662 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1663 }
1664
1665 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1666 {
1667 u32 phy;
1668
1669 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1670 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1671 return;
1672
1673 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1674 u32 ephy;
1675
1676 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1677 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1678
1679 tg3_writephy(tp, MII_TG3_FET_TEST,
1680 ephy | MII_TG3_FET_SHADOW_EN);
1681 if (!tg3_readphy(tp, reg, &phy)) {
1682 if (enable)
1683 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1684 else
1685 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1686 tg3_writephy(tp, reg, phy);
1687 }
1688 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1689 }
1690 } else {
1691 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1692 MII_TG3_AUXCTL_SHDWSEL_MISC;
1693 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1694 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1695 if (enable)
1696 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1697 else
1698 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1699 phy |= MII_TG3_AUXCTL_MISC_WREN;
1700 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1701 }
1702 }
1703 }
1704
1705 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1706 {
1707 u32 val;
1708
1709 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1710 return;
1711
1712 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1713 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1714 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1715 (val | (1 << 15) | (1 << 4)));
1716 }
1717
1718 static void tg3_phy_apply_otp(struct tg3 *tp)
1719 {
1720 u32 otp, phy;
1721
1722 if (!tp->phy_otp)
1723 return;
1724
1725 otp = tp->phy_otp;
1726
1727 /* Enable SM_DSP clock and tx 6dB coding. */
1728 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1730 MII_TG3_AUXCTL_ACTL_TX_6DB;
1731 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1732
1733 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1734 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1735 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1736
1737 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1738 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1739 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1740
1741 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1742 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1743 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1744
1745 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1746 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1747
1748 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1749 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1750
1751 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1752 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1753 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1754
1755 /* Turn off SM_DSP clock. */
1756 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1757 MII_TG3_AUXCTL_ACTL_TX_6DB;
1758 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1759 }
1760
1761 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1762 {
1763 u32 val;
1764
1765 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1766 return;
1767
1768 tp->setlpicnt = 0;
1769
1770 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1771 current_link_up == 1 &&
1772 (tp->link_config.active_speed == SPEED_1000 ||
1773 (tp->link_config.active_speed == SPEED_100 &&
1774 tp->link_config.active_duplex == DUPLEX_FULL))) {
1775 u32 eeectl;
1776
1777 if (tp->link_config.active_speed == SPEED_1000)
1778 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1779 else
1780 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1781
1782 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1783
1784 tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val);
1785
1786 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1787 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1788 tp->setlpicnt = 2;
1789 }
1790
1791 if (!tp->setlpicnt) {
1792 val = tr32(TG3_CPMU_EEE_MODE);
1793 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1794 }
1795 }
1796
1797 static int tg3_wait_macro_done(struct tg3 *tp)
1798 {
1799 int limit = 100;
1800
1801 while (limit--) {
1802 u32 tmp32;
1803
1804 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1805 if ((tmp32 & 0x1000) == 0)
1806 break;
1807 }
1808 }
1809 if (limit < 0)
1810 return -EBUSY;
1811
1812 return 0;
1813 }
1814
1815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1816 {
1817 static const u32 test_pat[4][6] = {
1818 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1819 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1820 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1821 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1822 };
1823 int chan;
1824
1825 for (chan = 0; chan < 4; chan++) {
1826 int i;
1827
1828 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1829 (chan * 0x2000) | 0x0200);
1830 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1831
1832 for (i = 0; i < 6; i++)
1833 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1834 test_pat[chan][i]);
1835
1836 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1837 if (tg3_wait_macro_done(tp)) {
1838 *resetp = 1;
1839 return -EBUSY;
1840 }
1841
1842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1843 (chan * 0x2000) | 0x0200);
1844 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1845 if (tg3_wait_macro_done(tp)) {
1846 *resetp = 1;
1847 return -EBUSY;
1848 }
1849
1850 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1851 if (tg3_wait_macro_done(tp)) {
1852 *resetp = 1;
1853 return -EBUSY;
1854 }
1855
1856 for (i = 0; i < 6; i += 2) {
1857 u32 low, high;
1858
1859 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1860 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1861 tg3_wait_macro_done(tp)) {
1862 *resetp = 1;
1863 return -EBUSY;
1864 }
1865 low &= 0x7fff;
1866 high &= 0x000f;
1867 if (low != test_pat[chan][i] ||
1868 high != test_pat[chan][i+1]) {
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1871 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1872
1873 return -EBUSY;
1874 }
1875 }
1876 }
1877
1878 return 0;
1879 }
1880
1881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1882 {
1883 int chan;
1884
1885 for (chan = 0; chan < 4; chan++) {
1886 int i;
1887
1888 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1889 (chan * 0x2000) | 0x0200);
1890 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1891 for (i = 0; i < 6; i++)
1892 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1893 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1894 if (tg3_wait_macro_done(tp))
1895 return -EBUSY;
1896 }
1897
1898 return 0;
1899 }
1900
1901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1902 {
1903 u32 reg32, phy9_orig;
1904 int retries, do_phy_reset, err;
1905
1906 retries = 10;
1907 do_phy_reset = 1;
1908 do {
1909 if (do_phy_reset) {
1910 err = tg3_bmcr_reset(tp);
1911 if (err)
1912 return err;
1913 do_phy_reset = 0;
1914 }
1915
1916 /* Disable transmitter and interrupt. */
1917 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1918 continue;
1919
1920 reg32 |= 0x3000;
1921 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1922
1923 /* Set full-duplex, 1000 mbps. */
1924 tg3_writephy(tp, MII_BMCR,
1925 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1926
1927 /* Set to master mode. */
1928 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1929 continue;
1930
1931 tg3_writephy(tp, MII_TG3_CTRL,
1932 (MII_TG3_CTRL_AS_MASTER |
1933 MII_TG3_CTRL_ENABLE_AS_MASTER));
1934
1935 /* Enable SM_DSP_CLOCK and 6dB. */
1936 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1937
1938 /* Block the PHY control access. */
1939 tg3_phydsp_write(tp, 0x8005, 0x0800);
1940
1941 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1942 if (!err)
1943 break;
1944 } while (--retries);
1945
1946 err = tg3_phy_reset_chanpat(tp);
1947 if (err)
1948 return err;
1949
1950 tg3_phydsp_write(tp, 0x8005, 0x0000);
1951
1952 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1953 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1954
1955 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1956 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1957 /* Set Extended packet length bit for jumbo frames */
1958 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1959 } else {
1960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1961 }
1962
1963 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1964
1965 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1966 reg32 &= ~0x3000;
1967 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1968 } else if (!err)
1969 err = -EBUSY;
1970
1971 return err;
1972 }
1973
1974 /* This will reset the tigon3 PHY if there is no valid
1975 * link unless the FORCE argument is non-zero.
1976 */
1977 static int tg3_phy_reset(struct tg3 *tp)
1978 {
1979 u32 val, cpmuctrl;
1980 int err;
1981
1982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1983 val = tr32(GRC_MISC_CFG);
1984 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1985 udelay(40);
1986 }
1987 err = tg3_readphy(tp, MII_BMSR, &val);
1988 err |= tg3_readphy(tp, MII_BMSR, &val);
1989 if (err != 0)
1990 return -EBUSY;
1991
1992 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1993 netif_carrier_off(tp->dev);
1994 tg3_link_report(tp);
1995 }
1996
1997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2000 err = tg3_phy_reset_5703_4_5(tp);
2001 if (err)
2002 return err;
2003 goto out;
2004 }
2005
2006 cpmuctrl = 0;
2007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2008 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2009 cpmuctrl = tr32(TG3_CPMU_CTRL);
2010 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2011 tw32(TG3_CPMU_CTRL,
2012 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2013 }
2014
2015 err = tg3_bmcr_reset(tp);
2016 if (err)
2017 return err;
2018
2019 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2020 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2021 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2022
2023 tw32(TG3_CPMU_CTRL, cpmuctrl);
2024 }
2025
2026 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2027 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2028 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2029 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2030 CPMU_LSPD_1000MB_MACCLK_12_5) {
2031 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2032 udelay(40);
2033 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2034 }
2035 }
2036
2037 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2039 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2040 return 0;
2041
2042 tg3_phy_apply_otp(tp);
2043
2044 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2045 tg3_phy_toggle_apd(tp, true);
2046 else
2047 tg3_phy_toggle_apd(tp, false);
2048
2049 out:
2050 if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2051 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2052 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2053 tg3_phydsp_write(tp, 0x000a, 0x0323);
2054 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2055 }
2056 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2057 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2058 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2059 }
2060 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2061 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2062 tg3_phydsp_write(tp, 0x000a, 0x310b);
2063 tg3_phydsp_write(tp, 0x201f, 0x9506);
2064 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2065 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2066 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2067 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2068 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2069 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2070 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2071 tg3_writephy(tp, MII_TG3_TEST1,
2072 MII_TG3_TEST1_TRIM_EN | 0x4);
2073 } else
2074 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2075 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2076 }
2077 /* Set Extended packet length bit (bit 14) on all chips that */
2078 /* support jumbo frames */
2079 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2080 /* Cannot do read-modify-write on 5401 */
2081 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2082 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2083 /* Set bit 14 with read-modify-write to preserve other bits */
2084 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2085 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2086 tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2087 }
2088
2089 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2090 * jumbo frames transmission.
2091 */
2092 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2093 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2094 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2095 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2096 }
2097
2098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2099 /* adjust output voltage */
2100 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2101 }
2102
2103 tg3_phy_toggle_automdix(tp, 1);
2104 tg3_phy_set_wirespeed(tp);
2105 return 0;
2106 }
2107
2108 static void tg3_frob_aux_power(struct tg3 *tp)
2109 {
2110 struct tg3 *tp_peer = tp;
2111
2112 /* The GPIOs do something completely different on 57765. */
2113 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2114 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2115 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2116 return;
2117
2118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2119 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2120 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2121 struct net_device *dev_peer;
2122
2123 dev_peer = pci_get_drvdata(tp->pdev_peer);
2124 /* remove_one() may have been run on the peer. */
2125 if (!dev_peer)
2126 tp_peer = tp;
2127 else
2128 tp_peer = netdev_priv(dev_peer);
2129 }
2130
2131 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2132 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2133 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2134 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2135 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2137 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2138 (GRC_LCLCTRL_GPIO_OE0 |
2139 GRC_LCLCTRL_GPIO_OE1 |
2140 GRC_LCLCTRL_GPIO_OE2 |
2141 GRC_LCLCTRL_GPIO_OUTPUT0 |
2142 GRC_LCLCTRL_GPIO_OUTPUT1),
2143 100);
2144 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2145 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2146 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2147 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2148 GRC_LCLCTRL_GPIO_OE1 |
2149 GRC_LCLCTRL_GPIO_OE2 |
2150 GRC_LCLCTRL_GPIO_OUTPUT0 |
2151 GRC_LCLCTRL_GPIO_OUTPUT1 |
2152 tp->grc_local_ctrl;
2153 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2154
2155 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2156 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2157
2158 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2159 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2160 } else {
2161 u32 no_gpio2;
2162 u32 grc_local_ctrl = 0;
2163
2164 if (tp_peer != tp &&
2165 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2166 return;
2167
2168 /* Workaround to prevent overdrawing Amps. */
2169 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2170 ASIC_REV_5714) {
2171 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2172 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2173 grc_local_ctrl, 100);
2174 }
2175
2176 /* On 5753 and variants, GPIO2 cannot be used. */
2177 no_gpio2 = tp->nic_sram_data_cfg &
2178 NIC_SRAM_DATA_CFG_NO_GPIO2;
2179
2180 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2181 GRC_LCLCTRL_GPIO_OE1 |
2182 GRC_LCLCTRL_GPIO_OE2 |
2183 GRC_LCLCTRL_GPIO_OUTPUT1 |
2184 GRC_LCLCTRL_GPIO_OUTPUT2;
2185 if (no_gpio2) {
2186 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2187 GRC_LCLCTRL_GPIO_OUTPUT2);
2188 }
2189 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2190 grc_local_ctrl, 100);
2191
2192 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2193
2194 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2195 grc_local_ctrl, 100);
2196
2197 if (!no_gpio2) {
2198 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2199 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2200 grc_local_ctrl, 100);
2201 }
2202 }
2203 } else {
2204 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2205 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2206 if (tp_peer != tp &&
2207 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2208 return;
2209
2210 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211 (GRC_LCLCTRL_GPIO_OE1 |
2212 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2213
2214 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215 GRC_LCLCTRL_GPIO_OE1, 100);
2216
2217 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2218 (GRC_LCLCTRL_GPIO_OE1 |
2219 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2220 }
2221 }
2222 }
2223
2224 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2225 {
2226 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2227 return 1;
2228 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2229 if (speed != SPEED_10)
2230 return 1;
2231 } else if (speed == SPEED_10)
2232 return 1;
2233
2234 return 0;
2235 }
2236
2237 static int tg3_setup_phy(struct tg3 *, int);
2238
2239 #define RESET_KIND_SHUTDOWN 0
2240 #define RESET_KIND_INIT 1
2241 #define RESET_KIND_SUSPEND 2
2242
2243 static void tg3_write_sig_post_reset(struct tg3 *, int);
2244 static int tg3_halt_cpu(struct tg3 *, u32);
2245
2246 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2247 {
2248 u32 val;
2249
2250 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2251 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2252 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2253 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2254
2255 sg_dig_ctrl |=
2256 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2257 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2258 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2259 }
2260 return;
2261 }
2262
2263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2264 tg3_bmcr_reset(tp);
2265 val = tr32(GRC_MISC_CFG);
2266 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2267 udelay(40);
2268 return;
2269 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2270 u32 phytest;
2271 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2272 u32 phy;
2273
2274 tg3_writephy(tp, MII_ADVERTISE, 0);
2275 tg3_writephy(tp, MII_BMCR,
2276 BMCR_ANENABLE | BMCR_ANRESTART);
2277
2278 tg3_writephy(tp, MII_TG3_FET_TEST,
2279 phytest | MII_TG3_FET_SHADOW_EN);
2280 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2281 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2282 tg3_writephy(tp,
2283 MII_TG3_FET_SHDW_AUXMODE4,
2284 phy);
2285 }
2286 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2287 }
2288 return;
2289 } else if (do_low_power) {
2290 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2291 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2292
2293 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2294 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2295 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2296 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2297 MII_TG3_AUXCTL_PCTL_VREG_11V);
2298 }
2299
2300 /* The PHY should not be powered down on some chips because
2301 * of bugs.
2302 */
2303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2304 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2305 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2306 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2307 return;
2308
2309 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2310 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2311 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2312 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2313 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2314 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2315 }
2316
2317 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2318 }
2319
2320 /* tp->lock is held. */
2321 static int tg3_nvram_lock(struct tg3 *tp)
2322 {
2323 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2324 int i;
2325
2326 if (tp->nvram_lock_cnt == 0) {
2327 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2328 for (i = 0; i < 8000; i++) {
2329 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2330 break;
2331 udelay(20);
2332 }
2333 if (i == 8000) {
2334 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2335 return -ENODEV;
2336 }
2337 }
2338 tp->nvram_lock_cnt++;
2339 }
2340 return 0;
2341 }
2342
2343 /* tp->lock is held. */
2344 static void tg3_nvram_unlock(struct tg3 *tp)
2345 {
2346 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2347 if (tp->nvram_lock_cnt > 0)
2348 tp->nvram_lock_cnt--;
2349 if (tp->nvram_lock_cnt == 0)
2350 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2351 }
2352 }
2353
2354 /* tp->lock is held. */
2355 static void tg3_enable_nvram_access(struct tg3 *tp)
2356 {
2357 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2358 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2359 u32 nvaccess = tr32(NVRAM_ACCESS);
2360
2361 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2362 }
2363 }
2364
2365 /* tp->lock is held. */
2366 static void tg3_disable_nvram_access(struct tg3 *tp)
2367 {
2368 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2369 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2370 u32 nvaccess = tr32(NVRAM_ACCESS);
2371
2372 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2373 }
2374 }
2375
2376 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2377 u32 offset, u32 *val)
2378 {
2379 u32 tmp;
2380 int i;
2381
2382 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2383 return -EINVAL;
2384
2385 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2386 EEPROM_ADDR_DEVID_MASK |
2387 EEPROM_ADDR_READ);
2388 tw32(GRC_EEPROM_ADDR,
2389 tmp |
2390 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2391 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2392 EEPROM_ADDR_ADDR_MASK) |
2393 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2394
2395 for (i = 0; i < 1000; i++) {
2396 tmp = tr32(GRC_EEPROM_ADDR);
2397
2398 if (tmp & EEPROM_ADDR_COMPLETE)
2399 break;
2400 msleep(1);
2401 }
2402 if (!(tmp & EEPROM_ADDR_COMPLETE))
2403 return -EBUSY;
2404
2405 tmp = tr32(GRC_EEPROM_DATA);
2406
2407 /*
2408 * The data will always be opposite the native endian
2409 * format. Perform a blind byteswap to compensate.
2410 */
2411 *val = swab32(tmp);
2412
2413 return 0;
2414 }
2415
2416 #define NVRAM_CMD_TIMEOUT 10000
2417
2418 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2419 {
2420 int i;
2421
2422 tw32(NVRAM_CMD, nvram_cmd);
2423 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2424 udelay(10);
2425 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2426 udelay(10);
2427 break;
2428 }
2429 }
2430
2431 if (i == NVRAM_CMD_TIMEOUT)
2432 return -EBUSY;
2433
2434 return 0;
2435 }
2436
2437 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2438 {
2439 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2440 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2441 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2442 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2443 (tp->nvram_jedecnum == JEDEC_ATMEL))
2444
2445 addr = ((addr / tp->nvram_pagesize) <<
2446 ATMEL_AT45DB0X1B_PAGE_POS) +
2447 (addr % tp->nvram_pagesize);
2448
2449 return addr;
2450 }
2451
2452 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2453 {
2454 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2455 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2456 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2457 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2458 (tp->nvram_jedecnum == JEDEC_ATMEL))
2459
2460 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2461 tp->nvram_pagesize) +
2462 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2463
2464 return addr;
2465 }
2466
2467 /* NOTE: Data read in from NVRAM is byteswapped according to
2468 * the byteswapping settings for all other register accesses.
2469 * tg3 devices are BE devices, so on a BE machine, the data
2470 * returned will be exactly as it is seen in NVRAM. On a LE
2471 * machine, the 32-bit value will be byteswapped.
2472 */
2473 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2474 {
2475 int ret;
2476
2477 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2478 return tg3_nvram_read_using_eeprom(tp, offset, val);
2479
2480 offset = tg3_nvram_phys_addr(tp, offset);
2481
2482 if (offset > NVRAM_ADDR_MSK)
2483 return -EINVAL;
2484
2485 ret = tg3_nvram_lock(tp);
2486 if (ret)
2487 return ret;
2488
2489 tg3_enable_nvram_access(tp);
2490
2491 tw32(NVRAM_ADDR, offset);
2492 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2493 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2494
2495 if (ret == 0)
2496 *val = tr32(NVRAM_RDDATA);
2497
2498 tg3_disable_nvram_access(tp);
2499
2500 tg3_nvram_unlock(tp);
2501
2502 return ret;
2503 }
2504
2505 /* Ensures NVRAM data is in bytestream format. */
2506 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2507 {
2508 u32 v;
2509 int res = tg3_nvram_read(tp, offset, &v);
2510 if (!res)
2511 *val = cpu_to_be32(v);
2512 return res;
2513 }
2514
2515 /* tp->lock is held. */
2516 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2517 {
2518 u32 addr_high, addr_low;
2519 int i;
2520
2521 addr_high = ((tp->dev->dev_addr[0] << 8) |
2522 tp->dev->dev_addr[1]);
2523 addr_low = ((tp->dev->dev_addr[2] << 24) |
2524 (tp->dev->dev_addr[3] << 16) |
2525 (tp->dev->dev_addr[4] << 8) |
2526 (tp->dev->dev_addr[5] << 0));
2527 for (i = 0; i < 4; i++) {
2528 if (i == 1 && skip_mac_1)
2529 continue;
2530 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2531 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2532 }
2533
2534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2535 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2536 for (i = 0; i < 12; i++) {
2537 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2538 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2539 }
2540 }
2541
2542 addr_high = (tp->dev->dev_addr[0] +
2543 tp->dev->dev_addr[1] +
2544 tp->dev->dev_addr[2] +
2545 tp->dev->dev_addr[3] +
2546 tp->dev->dev_addr[4] +
2547 tp->dev->dev_addr[5]) &
2548 TX_BACKOFF_SEED_MASK;
2549 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2550 }
2551
2552 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2553 {
2554 u32 misc_host_ctrl;
2555 bool device_should_wake, do_low_power;
2556
2557 /* Make sure register accesses (indirect or otherwise)
2558 * will function correctly.
2559 */
2560 pci_write_config_dword(tp->pdev,
2561 TG3PCI_MISC_HOST_CTRL,
2562 tp->misc_host_ctrl);
2563
2564 switch (state) {
2565 case PCI_D0:
2566 pci_enable_wake(tp->pdev, state, false);
2567 pci_set_power_state(tp->pdev, PCI_D0);
2568
2569 /* Switch out of Vaux if it is a NIC */
2570 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2571 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2572
2573 return 0;
2574
2575 case PCI_D1:
2576 case PCI_D2:
2577 case PCI_D3hot:
2578 break;
2579
2580 default:
2581 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2582 state);
2583 return -EINVAL;
2584 }
2585
2586 /* Restore the CLKREQ setting. */
2587 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2588 u16 lnkctl;
2589
2590 pci_read_config_word(tp->pdev,
2591 tp->pcie_cap + PCI_EXP_LNKCTL,
2592 &lnkctl);
2593 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2594 pci_write_config_word(tp->pdev,
2595 tp->pcie_cap + PCI_EXP_LNKCTL,
2596 lnkctl);
2597 }
2598
2599 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2600 tw32(TG3PCI_MISC_HOST_CTRL,
2601 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2602
2603 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2604 device_may_wakeup(&tp->pdev->dev) &&
2605 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2606
2607 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2608 do_low_power = false;
2609 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2610 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2611 struct phy_device *phydev;
2612 u32 phyid, advertising;
2613
2614 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2615
2616 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2617
2618 tp->link_config.orig_speed = phydev->speed;
2619 tp->link_config.orig_duplex = phydev->duplex;
2620 tp->link_config.orig_autoneg = phydev->autoneg;
2621 tp->link_config.orig_advertising = phydev->advertising;
2622
2623 advertising = ADVERTISED_TP |
2624 ADVERTISED_Pause |
2625 ADVERTISED_Autoneg |
2626 ADVERTISED_10baseT_Half;
2627
2628 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2629 device_should_wake) {
2630 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2631 advertising |=
2632 ADVERTISED_100baseT_Half |
2633 ADVERTISED_100baseT_Full |
2634 ADVERTISED_10baseT_Full;
2635 else
2636 advertising |= ADVERTISED_10baseT_Full;
2637 }
2638
2639 phydev->advertising = advertising;
2640
2641 phy_start_aneg(phydev);
2642
2643 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2644 if (phyid != PHY_ID_BCMAC131) {
2645 phyid &= PHY_BCM_OUI_MASK;
2646 if (phyid == PHY_BCM_OUI_1 ||
2647 phyid == PHY_BCM_OUI_2 ||
2648 phyid == PHY_BCM_OUI_3)
2649 do_low_power = true;
2650 }
2651 }
2652 } else {
2653 do_low_power = true;
2654
2655 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2656 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2657 tp->link_config.orig_speed = tp->link_config.speed;
2658 tp->link_config.orig_duplex = tp->link_config.duplex;
2659 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2660 }
2661
2662 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2663 tp->link_config.speed = SPEED_10;
2664 tp->link_config.duplex = DUPLEX_HALF;
2665 tp->link_config.autoneg = AUTONEG_ENABLE;
2666 tg3_setup_phy(tp, 0);
2667 }
2668 }
2669
2670 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2671 u32 val;
2672
2673 val = tr32(GRC_VCPU_EXT_CTRL);
2674 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2675 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2676 int i;
2677 u32 val;
2678
2679 for (i = 0; i < 200; i++) {
2680 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2681 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2682 break;
2683 msleep(1);
2684 }
2685 }
2686 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2687 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2688 WOL_DRV_STATE_SHUTDOWN |
2689 WOL_DRV_WOL |
2690 WOL_SET_MAGIC_PKT);
2691
2692 if (device_should_wake) {
2693 u32 mac_mode;
2694
2695 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2696 if (do_low_power) {
2697 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2698 udelay(40);
2699 }
2700
2701 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2702 mac_mode = MAC_MODE_PORT_MODE_GMII;
2703 else
2704 mac_mode = MAC_MODE_PORT_MODE_MII;
2705
2706 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2707 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2708 ASIC_REV_5700) {
2709 u32 speed = (tp->tg3_flags &
2710 TG3_FLAG_WOL_SPEED_100MB) ?
2711 SPEED_100 : SPEED_10;
2712 if (tg3_5700_link_polarity(tp, speed))
2713 mac_mode |= MAC_MODE_LINK_POLARITY;
2714 else
2715 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2716 }
2717 } else {
2718 mac_mode = MAC_MODE_PORT_MODE_TBI;
2719 }
2720
2721 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2722 tw32(MAC_LED_CTRL, tp->led_ctrl);
2723
2724 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2725 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2726 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2727 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2728 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2729 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2730
2731 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2732 mac_mode |= tp->mac_mode &
2733 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2734 if (mac_mode & MAC_MODE_APE_TX_EN)
2735 mac_mode |= MAC_MODE_TDE_ENABLE;
2736 }
2737
2738 tw32_f(MAC_MODE, mac_mode);
2739 udelay(100);
2740
2741 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2742 udelay(10);
2743 }
2744
2745 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2746 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2747 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2748 u32 base_val;
2749
2750 base_val = tp->pci_clock_ctrl;
2751 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2752 CLOCK_CTRL_TXCLK_DISABLE);
2753
2754 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2755 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2756 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2757 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2758 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2759 /* do nothing */
2760 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2761 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2762 u32 newbits1, newbits2;
2763
2764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2765 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2766 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2767 CLOCK_CTRL_TXCLK_DISABLE |
2768 CLOCK_CTRL_ALTCLK);
2769 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2770 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2771 newbits1 = CLOCK_CTRL_625_CORE;
2772 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2773 } else {
2774 newbits1 = CLOCK_CTRL_ALTCLK;
2775 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2776 }
2777
2778 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2779 40);
2780
2781 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2782 40);
2783
2784 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2785 u32 newbits3;
2786
2787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2788 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2789 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2790 CLOCK_CTRL_TXCLK_DISABLE |
2791 CLOCK_CTRL_44MHZ_CORE);
2792 } else {
2793 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2794 }
2795
2796 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2797 tp->pci_clock_ctrl | newbits3, 40);
2798 }
2799 }
2800
2801 if (!(device_should_wake) &&
2802 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2803 tg3_power_down_phy(tp, do_low_power);
2804
2805 tg3_frob_aux_power(tp);
2806
2807 /* Workaround for unstable PLL clock */
2808 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2809 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2810 u32 val = tr32(0x7d00);
2811
2812 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2813 tw32(0x7d00, val);
2814 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2815 int err;
2816
2817 err = tg3_nvram_lock(tp);
2818 tg3_halt_cpu(tp, RX_CPU_BASE);
2819 if (!err)
2820 tg3_nvram_unlock(tp);
2821 }
2822 }
2823
2824 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2825
2826 if (device_should_wake)
2827 pci_enable_wake(tp->pdev, state, true);
2828
2829 /* Finally, set the new power state. */
2830 pci_set_power_state(tp->pdev, state);
2831
2832 return 0;
2833 }
2834
2835 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2836 {
2837 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2838 case MII_TG3_AUX_STAT_10HALF:
2839 *speed = SPEED_10;
2840 *duplex = DUPLEX_HALF;
2841 break;
2842
2843 case MII_TG3_AUX_STAT_10FULL:
2844 *speed = SPEED_10;
2845 *duplex = DUPLEX_FULL;
2846 break;
2847
2848 case MII_TG3_AUX_STAT_100HALF:
2849 *speed = SPEED_100;
2850 *duplex = DUPLEX_HALF;
2851 break;
2852
2853 case MII_TG3_AUX_STAT_100FULL:
2854 *speed = SPEED_100;
2855 *duplex = DUPLEX_FULL;
2856 break;
2857
2858 case MII_TG3_AUX_STAT_1000HALF:
2859 *speed = SPEED_1000;
2860 *duplex = DUPLEX_HALF;
2861 break;
2862
2863 case MII_TG3_AUX_STAT_1000FULL:
2864 *speed = SPEED_1000;
2865 *duplex = DUPLEX_FULL;
2866 break;
2867
2868 default:
2869 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2870 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2871 SPEED_10;
2872 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2873 DUPLEX_HALF;
2874 break;
2875 }
2876 *speed = SPEED_INVALID;
2877 *duplex = DUPLEX_INVALID;
2878 break;
2879 }
2880 }
2881
2882 static void tg3_phy_copper_begin(struct tg3 *tp)
2883 {
2884 u32 new_adv;
2885 int i;
2886
2887 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2888 /* Entering low power mode. Disable gigabit and
2889 * 100baseT advertisements.
2890 */
2891 tg3_writephy(tp, MII_TG3_CTRL, 0);
2892
2893 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2894 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2895 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2896 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2897
2898 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2899 } else if (tp->link_config.speed == SPEED_INVALID) {
2900 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2901 tp->link_config.advertising &=
2902 ~(ADVERTISED_1000baseT_Half |
2903 ADVERTISED_1000baseT_Full);
2904
2905 new_adv = ADVERTISE_CSMA;
2906 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2907 new_adv |= ADVERTISE_10HALF;
2908 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2909 new_adv |= ADVERTISE_10FULL;
2910 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2911 new_adv |= ADVERTISE_100HALF;
2912 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2913 new_adv |= ADVERTISE_100FULL;
2914
2915 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2916
2917 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2918
2919 if (tp->link_config.advertising &
2920 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2921 new_adv = 0;
2922 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2923 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2924 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2925 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2926 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2927 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2928 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2929 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2930 MII_TG3_CTRL_ENABLE_AS_MASTER);
2931 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2932 } else {
2933 tg3_writephy(tp, MII_TG3_CTRL, 0);
2934 }
2935 } else {
2936 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2937 new_adv |= ADVERTISE_CSMA;
2938
2939 /* Asking for a specific link mode. */
2940 if (tp->link_config.speed == SPEED_1000) {
2941 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2942
2943 if (tp->link_config.duplex == DUPLEX_FULL)
2944 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2945 else
2946 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2947 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2948 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2949 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2950 MII_TG3_CTRL_ENABLE_AS_MASTER);
2951 } else {
2952 if (tp->link_config.speed == SPEED_100) {
2953 if (tp->link_config.duplex == DUPLEX_FULL)
2954 new_adv |= ADVERTISE_100FULL;
2955 else
2956 new_adv |= ADVERTISE_100HALF;
2957 } else {
2958 if (tp->link_config.duplex == DUPLEX_FULL)
2959 new_adv |= ADVERTISE_10FULL;
2960 else
2961 new_adv |= ADVERTISE_10HALF;
2962 }
2963 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2964
2965 new_adv = 0;
2966 }
2967
2968 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2969 }
2970
2971 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2972 u32 val = 0;
2973
2974 tw32(TG3_CPMU_EEE_MODE,
2975 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2976
2977 /* Enable SM_DSP clock and tx 6dB coding. */
2978 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2979 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2980 MII_TG3_AUXCTL_ACTL_TX_6DB;
2981 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2982
2983 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2985 !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2986 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2987 val | MII_TG3_DSP_CH34TP2_HIBW01);
2988
2989 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2990 /* Advertise 100-BaseTX EEE ability */
2991 if (tp->link_config.advertising &
2992 (ADVERTISED_100baseT_Half |
2993 ADVERTISED_100baseT_Full))
2994 val |= TG3_CL45_D7_EEEADV_CAP_100TX;
2995 /* Advertise 1000-BaseT EEE ability */
2996 if (tp->link_config.advertising &
2997 (ADVERTISED_1000baseT_Half |
2998 ADVERTISED_1000baseT_Full))
2999 val |= TG3_CL45_D7_EEEADV_CAP_1000T;
3000 }
3001 tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val);
3002
3003 /* Turn off SM_DSP clock. */
3004 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3005 MII_TG3_AUXCTL_ACTL_TX_6DB;
3006 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3007 }
3008
3009 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3010 tp->link_config.speed != SPEED_INVALID) {
3011 u32 bmcr, orig_bmcr;
3012
3013 tp->link_config.active_speed = tp->link_config.speed;
3014 tp->link_config.active_duplex = tp->link_config.duplex;
3015
3016 bmcr = 0;
3017 switch (tp->link_config.speed) {
3018 default:
3019 case SPEED_10:
3020 break;
3021
3022 case SPEED_100:
3023 bmcr |= BMCR_SPEED100;
3024 break;
3025
3026 case SPEED_1000:
3027 bmcr |= TG3_BMCR_SPEED1000;
3028 break;
3029 }
3030
3031 if (tp->link_config.duplex == DUPLEX_FULL)
3032 bmcr |= BMCR_FULLDPLX;
3033
3034 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3035 (bmcr != orig_bmcr)) {
3036 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3037 for (i = 0; i < 1500; i++) {
3038 u32 tmp;
3039
3040 udelay(10);
3041 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3042 tg3_readphy(tp, MII_BMSR, &tmp))
3043 continue;
3044 if (!(tmp & BMSR_LSTATUS)) {
3045 udelay(40);
3046 break;
3047 }
3048 }
3049 tg3_writephy(tp, MII_BMCR, bmcr);
3050 udelay(40);
3051 }
3052 } else {
3053 tg3_writephy(tp, MII_BMCR,
3054 BMCR_ANENABLE | BMCR_ANRESTART);
3055 }
3056 }
3057
3058 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3059 {
3060 int err;
3061
3062 /* Turn off tap power management. */
3063 /* Set Extended packet length bit */
3064 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3065
3066 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3067 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3068 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3069 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3070 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3071
3072 udelay(40);
3073
3074 return err;
3075 }
3076
3077 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3078 {
3079 u32 adv_reg, all_mask = 0;
3080
3081 if (mask & ADVERTISED_10baseT_Half)
3082 all_mask |= ADVERTISE_10HALF;
3083 if (mask & ADVERTISED_10baseT_Full)
3084 all_mask |= ADVERTISE_10FULL;
3085 if (mask & ADVERTISED_100baseT_Half)
3086 all_mask |= ADVERTISE_100HALF;
3087 if (mask & ADVERTISED_100baseT_Full)
3088 all_mask |= ADVERTISE_100FULL;
3089
3090 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3091 return 0;
3092
3093 if ((adv_reg & all_mask) != all_mask)
3094 return 0;
3095 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3096 u32 tg3_ctrl;
3097
3098 all_mask = 0;
3099 if (mask & ADVERTISED_1000baseT_Half)
3100 all_mask |= ADVERTISE_1000HALF;
3101 if (mask & ADVERTISED_1000baseT_Full)
3102 all_mask |= ADVERTISE_1000FULL;
3103
3104 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3105 return 0;
3106
3107 if ((tg3_ctrl & all_mask) != all_mask)
3108 return 0;
3109 }
3110 return 1;
3111 }
3112
3113 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3114 {
3115 u32 curadv, reqadv;
3116
3117 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3118 return 1;
3119
3120 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3121 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3122
3123 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3124 if (curadv != reqadv)
3125 return 0;
3126
3127 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3128 tg3_readphy(tp, MII_LPA, rmtadv);
3129 } else {
3130 /* Reprogram the advertisement register, even if it
3131 * does not affect the current link. If the link
3132 * gets renegotiated in the future, we can save an
3133 * additional renegotiation cycle by advertising
3134 * it correctly in the first place.
3135 */
3136 if (curadv != reqadv) {
3137 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3138 ADVERTISE_PAUSE_ASYM);
3139 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3140 }
3141 }
3142
3143 return 1;
3144 }
3145
3146 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3147 {
3148 int current_link_up;
3149 u32 bmsr, val;
3150 u32 lcl_adv, rmt_adv;
3151 u16 current_speed;
3152 u8 current_duplex;
3153 int i, err;
3154
3155 tw32(MAC_EVENT, 0);
3156
3157 tw32_f(MAC_STATUS,
3158 (MAC_STATUS_SYNC_CHANGED |
3159 MAC_STATUS_CFG_CHANGED |
3160 MAC_STATUS_MI_COMPLETION |
3161 MAC_STATUS_LNKSTATE_CHANGED));
3162 udelay(40);
3163
3164 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3165 tw32_f(MAC_MI_MODE,
3166 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3167 udelay(80);
3168 }
3169
3170 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3171
3172 /* Some third-party PHYs need to be reset on link going
3173 * down.
3174 */
3175 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3176 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3177 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3178 netif_carrier_ok(tp->dev)) {
3179 tg3_readphy(tp, MII_BMSR, &bmsr);
3180 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3181 !(bmsr & BMSR_LSTATUS))
3182 force_reset = 1;
3183 }
3184 if (force_reset)
3185 tg3_phy_reset(tp);
3186
3187 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3188 tg3_readphy(tp, MII_BMSR, &bmsr);
3189 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3190 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3191 bmsr = 0;
3192
3193 if (!(bmsr & BMSR_LSTATUS)) {
3194 err = tg3_init_5401phy_dsp(tp);
3195 if (err)
3196 return err;
3197
3198 tg3_readphy(tp, MII_BMSR, &bmsr);
3199 for (i = 0; i < 1000; i++) {
3200 udelay(10);
3201 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3202 (bmsr & BMSR_LSTATUS)) {
3203 udelay(40);
3204 break;
3205 }
3206 }
3207
3208 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3209 TG3_PHY_REV_BCM5401_B0 &&
3210 !(bmsr & BMSR_LSTATUS) &&
3211 tp->link_config.active_speed == SPEED_1000) {
3212 err = tg3_phy_reset(tp);
3213 if (!err)
3214 err = tg3_init_5401phy_dsp(tp);
3215 if (err)
3216 return err;
3217 }
3218 }
3219 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3220 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3221 /* 5701 {A0,B0} CRC bug workaround */
3222 tg3_writephy(tp, 0x15, 0x0a75);
3223 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3224 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3225 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3226 }
3227
3228 /* Clear pending interrupts... */
3229 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3230 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3231
3232 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3233 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3234 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3235 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3236
3237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3239 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3240 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3241 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3242 else
3243 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3244 }
3245
3246 current_link_up = 0;
3247 current_speed = SPEED_INVALID;
3248 current_duplex = DUPLEX_INVALID;
3249
3250 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3251 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3252 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3253 if (!(val & (1 << 10))) {
3254 val |= (1 << 10);
3255 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3256 goto relink;
3257 }
3258 }
3259
3260 bmsr = 0;
3261 for (i = 0; i < 100; i++) {
3262 tg3_readphy(tp, MII_BMSR, &bmsr);
3263 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3264 (bmsr & BMSR_LSTATUS))
3265 break;
3266 udelay(40);
3267 }
3268
3269 if (bmsr & BMSR_LSTATUS) {
3270 u32 aux_stat, bmcr;
3271
3272 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3273 for (i = 0; i < 2000; i++) {
3274 udelay(10);
3275 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3276 aux_stat)
3277 break;
3278 }
3279
3280 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3281 &current_speed,
3282 &current_duplex);
3283
3284 bmcr = 0;
3285 for (i = 0; i < 200; i++) {
3286 tg3_readphy(tp, MII_BMCR, &bmcr);
3287 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3288 continue;
3289 if (bmcr && bmcr != 0x7fff)
3290 break;
3291 udelay(10);
3292 }
3293
3294 lcl_adv = 0;
3295 rmt_adv = 0;
3296
3297 tp->link_config.active_speed = current_speed;
3298 tp->link_config.active_duplex = current_duplex;
3299
3300 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3301 if ((bmcr & BMCR_ANENABLE) &&
3302 tg3_copper_is_advertising_all(tp,
3303 tp->link_config.advertising)) {
3304 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3305 &rmt_adv))
3306 current_link_up = 1;
3307 }
3308 } else {
3309 if (!(bmcr & BMCR_ANENABLE) &&
3310 tp->link_config.speed == current_speed &&
3311 tp->link_config.duplex == current_duplex &&
3312 tp->link_config.flowctrl ==
3313 tp->link_config.active_flowctrl) {
3314 current_link_up = 1;
3315 }
3316 }
3317
3318 if (current_link_up == 1 &&
3319 tp->link_config.active_duplex == DUPLEX_FULL)
3320 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3321 }
3322
3323 relink:
3324 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3325 tg3_phy_copper_begin(tp);
3326
3327 tg3_readphy(tp, MII_BMSR, &bmsr);
3328 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3329 (bmsr & BMSR_LSTATUS))
3330 current_link_up = 1;
3331 }
3332
3333 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3334 if (current_link_up == 1) {
3335 if (tp->link_config.active_speed == SPEED_100 ||
3336 tp->link_config.active_speed == SPEED_10)
3337 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3338 else
3339 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3340 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3341 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3342 else
3343 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3344
3345 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3346 if (tp->link_config.active_duplex == DUPLEX_HALF)
3347 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3348
3349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3350 if (current_link_up == 1 &&
3351 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3352 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3353 else
3354 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3355 }
3356
3357 /* ??? Without this setting Netgear GA302T PHY does not
3358 * ??? send/receive packets...
3359 */
3360 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3361 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3362 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3363 tw32_f(MAC_MI_MODE, tp->mi_mode);
3364 udelay(80);
3365 }
3366
3367 tw32_f(MAC_MODE, tp->mac_mode);
3368 udelay(40);
3369
3370 tg3_phy_eee_adjust(tp, current_link_up);
3371
3372 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3373 /* Polled via timer. */
3374 tw32_f(MAC_EVENT, 0);
3375 } else {
3376 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3377 }
3378 udelay(40);
3379
3380 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3381 current_link_up == 1 &&
3382 tp->link_config.active_speed == SPEED_1000 &&
3383 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3384 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3385 udelay(120);
3386 tw32_f(MAC_STATUS,
3387 (MAC_STATUS_SYNC_CHANGED |
3388 MAC_STATUS_CFG_CHANGED));
3389 udelay(40);
3390 tg3_write_mem(tp,
3391 NIC_SRAM_FIRMWARE_MBOX,
3392 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3393 }
3394
3395 /* Prevent send BD corruption. */
3396 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3397 u16 oldlnkctl, newlnkctl;
3398
3399 pci_read_config_word(tp->pdev,
3400 tp->pcie_cap + PCI_EXP_LNKCTL,
3401 &oldlnkctl);
3402 if (tp->link_config.active_speed == SPEED_100 ||
3403 tp->link_config.active_speed == SPEED_10)
3404 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3405 else
3406 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3407 if (newlnkctl != oldlnkctl)
3408 pci_write_config_word(tp->pdev,
3409 tp->pcie_cap + PCI_EXP_LNKCTL,
3410 newlnkctl);
3411 }
3412
3413 if (current_link_up != netif_carrier_ok(tp->dev)) {
3414 if (current_link_up)
3415 netif_carrier_on(tp->dev);
3416 else
3417 netif_carrier_off(tp->dev);
3418 tg3_link_report(tp);
3419 }
3420
3421 return 0;
3422 }
3423
3424 struct tg3_fiber_aneginfo {
3425 int state;
3426 #define ANEG_STATE_UNKNOWN 0
3427 #define ANEG_STATE_AN_ENABLE 1
3428 #define ANEG_STATE_RESTART_INIT 2
3429 #define ANEG_STATE_RESTART 3
3430 #define ANEG_STATE_DISABLE_LINK_OK 4
3431 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3432 #define ANEG_STATE_ABILITY_DETECT 6
3433 #define ANEG_STATE_ACK_DETECT_INIT 7
3434 #define ANEG_STATE_ACK_DETECT 8
3435 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3436 #define ANEG_STATE_COMPLETE_ACK 10
3437 #define ANEG_STATE_IDLE_DETECT_INIT 11
3438 #define ANEG_STATE_IDLE_DETECT 12
3439 #define ANEG_STATE_LINK_OK 13
3440 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3441 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3442
3443 u32 flags;
3444 #define MR_AN_ENABLE 0x00000001
3445 #define MR_RESTART_AN 0x00000002
3446 #define MR_AN_COMPLETE 0x00000004
3447 #define MR_PAGE_RX 0x00000008
3448 #define MR_NP_LOADED 0x00000010
3449 #define MR_TOGGLE_TX 0x00000020
3450 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3451 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3452 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3453 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3454 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3455 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3456 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3457 #define MR_TOGGLE_RX 0x00002000
3458 #define MR_NP_RX 0x00004000
3459
3460 #define MR_LINK_OK 0x80000000
3461
3462 unsigned long link_time, cur_time;
3463
3464 u32 ability_match_cfg;
3465 int ability_match_count;
3466
3467 char ability_match, idle_match, ack_match;
3468
3469 u32 txconfig, rxconfig;
3470 #define ANEG_CFG_NP 0x00000080
3471 #define ANEG_CFG_ACK 0x00000040
3472 #define ANEG_CFG_RF2 0x00000020
3473 #define ANEG_CFG_RF1 0x00000010
3474 #define ANEG_CFG_PS2 0x00000001
3475 #define ANEG_CFG_PS1 0x00008000
3476 #define ANEG_CFG_HD 0x00004000
3477 #define ANEG_CFG_FD 0x00002000
3478 #define ANEG_CFG_INVAL 0x00001f06
3479
3480 };
3481 #define ANEG_OK 0
3482 #define ANEG_DONE 1
3483 #define ANEG_TIMER_ENAB 2
3484 #define ANEG_FAILED -1
3485
3486 #define ANEG_STATE_SETTLE_TIME 10000
3487
3488 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3489 struct tg3_fiber_aneginfo *ap)
3490 {
3491 u16 flowctrl;
3492 unsigned long delta;
3493 u32 rx_cfg_reg;
3494 int ret;
3495
3496 if (ap->state == ANEG_STATE_UNKNOWN) {
3497 ap->rxconfig = 0;
3498 ap->link_time = 0;
3499 ap->cur_time = 0;
3500 ap->ability_match_cfg = 0;
3501 ap->ability_match_count = 0;
3502 ap->ability_match = 0;
3503 ap->idle_match = 0;
3504 ap->ack_match = 0;
3505 }
3506 ap->cur_time++;
3507
3508 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3509 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3510
3511 if (rx_cfg_reg != ap->ability_match_cfg) {
3512 ap->ability_match_cfg = rx_cfg_reg;
3513 ap->ability_match = 0;
3514 ap->ability_match_count = 0;
3515 } else {
3516 if (++ap->ability_match_count > 1) {
3517 ap->ability_match = 1;
3518 ap->ability_match_cfg = rx_cfg_reg;
3519 }
3520 }
3521 if (rx_cfg_reg & ANEG_CFG_ACK)
3522 ap->ack_match = 1;
3523 else
3524 ap->ack_match = 0;
3525
3526 ap->idle_match = 0;
3527 } else {
3528 ap->idle_match = 1;
3529 ap->ability_match_cfg = 0;
3530 ap->ability_match_count = 0;
3531 ap->ability_match = 0;
3532 ap->ack_match = 0;
3533
3534 rx_cfg_reg = 0;
3535 }
3536
3537 ap->rxconfig = rx_cfg_reg;
3538 ret = ANEG_OK;
3539
3540 switch (ap->state) {
3541 case ANEG_STATE_UNKNOWN:
3542 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3543 ap->state = ANEG_STATE_AN_ENABLE;
3544
3545 /* fallthru */
3546 case ANEG_STATE_AN_ENABLE:
3547 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3548 if (ap->flags & MR_AN_ENABLE) {
3549 ap->link_time = 0;
3550 ap->cur_time = 0;
3551 ap->ability_match_cfg = 0;
3552 ap->ability_match_count = 0;
3553 ap->ability_match = 0;
3554 ap->idle_match = 0;
3555 ap->ack_match = 0;
3556
3557 ap->state = ANEG_STATE_RESTART_INIT;
3558 } else {
3559 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3560 }
3561 break;
3562
3563 case ANEG_STATE_RESTART_INIT:
3564 ap->link_time = ap->cur_time;
3565 ap->flags &= ~(MR_NP_LOADED);
3566 ap->txconfig = 0;
3567 tw32(MAC_TX_AUTO_NEG, 0);
3568 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3569 tw32_f(MAC_MODE, tp->mac_mode);
3570 udelay(40);
3571
3572 ret = ANEG_TIMER_ENAB;
3573 ap->state = ANEG_STATE_RESTART;
3574
3575 /* fallthru */
3576 case ANEG_STATE_RESTART:
3577 delta = ap->cur_time - ap->link_time;
3578 if (delta > ANEG_STATE_SETTLE_TIME)
3579 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3580 else
3581 ret = ANEG_TIMER_ENAB;
3582 break;
3583
3584 case ANEG_STATE_DISABLE_LINK_OK:
3585 ret = ANEG_DONE;
3586 break;
3587
3588 case ANEG_STATE_ABILITY_DETECT_INIT:
3589 ap->flags &= ~(MR_TOGGLE_TX);
3590 ap->txconfig = ANEG_CFG_FD;
3591 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3592 if (flowctrl & ADVERTISE_1000XPAUSE)
3593 ap->txconfig |= ANEG_CFG_PS1;
3594 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3595 ap->txconfig |= ANEG_CFG_PS2;
3596 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3597 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3598 tw32_f(MAC_MODE, tp->mac_mode);
3599 udelay(40);
3600
3601 ap->state = ANEG_STATE_ABILITY_DETECT;
3602 break;
3603
3604 case ANEG_STATE_ABILITY_DETECT:
3605 if (ap->ability_match != 0 && ap->rxconfig != 0)
3606 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3607 break;
3608
3609 case ANEG_STATE_ACK_DETECT_INIT:
3610 ap->txconfig |= ANEG_CFG_ACK;
3611 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3612 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3613 tw32_f(MAC_MODE, tp->mac_mode);
3614 udelay(40);
3615
3616 ap->state = ANEG_STATE_ACK_DETECT;
3617
3618 /* fallthru */
3619 case ANEG_STATE_ACK_DETECT:
3620 if (ap->ack_match != 0) {
3621 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3622 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3623 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3624 } else {
3625 ap->state = ANEG_STATE_AN_ENABLE;
3626 }
3627 } else if (ap->ability_match != 0 &&
3628 ap->rxconfig == 0) {
3629 ap->state = ANEG_STATE_AN_ENABLE;
3630 }
3631 break;
3632
3633 case ANEG_STATE_COMPLETE_ACK_INIT:
3634 if (ap->rxconfig & ANEG_CFG_INVAL) {
3635 ret = ANEG_FAILED;
3636 break;
3637 }
3638 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3639 MR_LP_ADV_HALF_DUPLEX |
3640 MR_LP_ADV_SYM_PAUSE |
3641 MR_LP_ADV_ASYM_PAUSE |
3642 MR_LP_ADV_REMOTE_FAULT1 |
3643 MR_LP_ADV_REMOTE_FAULT2 |
3644 MR_LP_ADV_NEXT_PAGE |
3645 MR_TOGGLE_RX |
3646 MR_NP_RX);
3647 if (ap->rxconfig & ANEG_CFG_FD)
3648 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3649 if (ap->rxconfig & ANEG_CFG_HD)
3650 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3651 if (ap->rxconfig & ANEG_CFG_PS1)
3652 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3653 if (ap->rxconfig & ANEG_CFG_PS2)
3654 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3655 if (ap->rxconfig & ANEG_CFG_RF1)
3656 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3657 if (ap->rxconfig & ANEG_CFG_RF2)
3658 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3659 if (ap->rxconfig & ANEG_CFG_NP)
3660 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3661
3662 ap->link_time = ap->cur_time;
3663
3664 ap->flags ^= (MR_TOGGLE_TX);
3665 if (ap->rxconfig & 0x0008)
3666 ap->flags |= MR_TOGGLE_RX;
3667 if (ap->rxconfig & ANEG_CFG_NP)
3668 ap->flags |= MR_NP_RX;
3669 ap->flags |= MR_PAGE_RX;
3670
3671 ap->state = ANEG_STATE_COMPLETE_ACK;
3672 ret = ANEG_TIMER_ENAB;
3673 break;
3674
3675 case ANEG_STATE_COMPLETE_ACK:
3676 if (ap->ability_match != 0 &&
3677 ap->rxconfig == 0) {
3678 ap->state = ANEG_STATE_AN_ENABLE;
3679 break;
3680 }
3681 delta = ap->cur_time - ap->link_time;
3682 if (delta > ANEG_STATE_SETTLE_TIME) {
3683 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3684 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3685 } else {
3686 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3687 !(ap->flags & MR_NP_RX)) {
3688 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3689 } else {
3690 ret = ANEG_FAILED;
3691 }
3692 }
3693 }
3694 break;
3695
3696 case ANEG_STATE_IDLE_DETECT_INIT:
3697 ap->link_time = ap->cur_time;
3698 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3699 tw32_f(MAC_MODE, tp->mac_mode);
3700 udelay(40);
3701
3702 ap->state = ANEG_STATE_IDLE_DETECT;
3703 ret = ANEG_TIMER_ENAB;
3704 break;
3705
3706 case ANEG_STATE_IDLE_DETECT:
3707 if (ap->ability_match != 0 &&
3708 ap->rxconfig == 0) {
3709 ap->state = ANEG_STATE_AN_ENABLE;
3710 break;
3711 }
3712 delta = ap->cur_time - ap->link_time;
3713 if (delta > ANEG_STATE_SETTLE_TIME) {
3714 /* XXX another gem from the Broadcom driver :( */
3715 ap->state = ANEG_STATE_LINK_OK;
3716 }
3717 break;
3718
3719 case ANEG_STATE_LINK_OK:
3720 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3721 ret = ANEG_DONE;
3722 break;
3723
3724 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3725 /* ??? unimplemented */
3726 break;
3727
3728 case ANEG_STATE_NEXT_PAGE_WAIT:
3729 /* ??? unimplemented */
3730 break;
3731
3732 default:
3733 ret = ANEG_FAILED;
3734 break;
3735 }
3736
3737 return ret;
3738 }
3739
3740 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3741 {
3742 int res = 0;
3743 struct tg3_fiber_aneginfo aninfo;
3744 int status = ANEG_FAILED;
3745 unsigned int tick;
3746 u32 tmp;
3747
3748 tw32_f(MAC_TX_AUTO_NEG, 0);
3749
3750 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3751 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3752 udelay(40);
3753
3754 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3755 udelay(40);
3756
3757 memset(&aninfo, 0, sizeof(aninfo));
3758 aninfo.flags |= MR_AN_ENABLE;
3759 aninfo.state = ANEG_STATE_UNKNOWN;
3760 aninfo.cur_time = 0;
3761 tick = 0;
3762 while (++tick < 195000) {
3763 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3764 if (status == ANEG_DONE || status == ANEG_FAILED)
3765 break;
3766
3767 udelay(1);
3768 }
3769
3770 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3771 tw32_f(MAC_MODE, tp->mac_mode);
3772 udelay(40);
3773
3774 *txflags = aninfo.txconfig;
3775 *rxflags = aninfo.flags;
3776
3777 if (status == ANEG_DONE &&
3778 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3779 MR_LP_ADV_FULL_DUPLEX)))
3780 res = 1;
3781
3782 return res;
3783 }
3784
3785 static void tg3_init_bcm8002(struct tg3 *tp)
3786 {
3787 u32 mac_status = tr32(MAC_STATUS);
3788 int i;
3789
3790 /* Reset when initting first time or we have a link. */
3791 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3792 !(mac_status & MAC_STATUS_PCS_SYNCED))
3793 return;
3794
3795 /* Set PLL lock range. */
3796 tg3_writephy(tp, 0x16, 0x8007);
3797
3798 /* SW reset */
3799 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3800
3801 /* Wait for reset to complete. */
3802 /* XXX schedule_timeout() ... */
3803 for (i = 0; i < 500; i++)
3804 udelay(10);
3805
3806 /* Config mode; select PMA/Ch 1 regs. */
3807 tg3_writephy(tp, 0x10, 0x8411);
3808
3809 /* Enable auto-lock and comdet, select txclk for tx. */
3810 tg3_writephy(tp, 0x11, 0x0a10);
3811
3812 tg3_writephy(tp, 0x18, 0x00a0);
3813 tg3_writephy(tp, 0x16, 0x41ff);
3814
3815 /* Assert and deassert POR. */
3816 tg3_writephy(tp, 0x13, 0x0400);
3817 udelay(40);
3818 tg3_writephy(tp, 0x13, 0x0000);
3819
3820 tg3_writephy(tp, 0x11, 0x0a50);
3821 udelay(40);
3822 tg3_writephy(tp, 0x11, 0x0a10);
3823
3824 /* Wait for signal to stabilize */
3825 /* XXX schedule_timeout() ... */
3826 for (i = 0; i < 15000; i++)
3827 udelay(10);
3828
3829 /* Deselect the channel register so we can read the PHYID
3830 * later.
3831 */
3832 tg3_writephy(tp, 0x10, 0x8011);
3833 }
3834
3835 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3836 {
3837 u16 flowctrl;
3838 u32 sg_dig_ctrl, sg_dig_status;
3839 u32 serdes_cfg, expected_sg_dig_ctrl;
3840 int workaround, port_a;
3841 int current_link_up;
3842
3843 serdes_cfg = 0;
3844 expected_sg_dig_ctrl = 0;
3845 workaround = 0;
3846 port_a = 1;
3847 current_link_up = 0;
3848
3849 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3850 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3851 workaround = 1;
3852 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3853 port_a = 0;
3854
3855 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3856 /* preserve bits 20-23 for voltage regulator */
3857 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3858 }
3859
3860 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3861
3862 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3863 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3864 if (workaround) {
3865 u32 val = serdes_cfg;
3866
3867 if (port_a)
3868 val |= 0xc010000;
3869 else
3870 val |= 0x4010000;
3871 tw32_f(MAC_SERDES_CFG, val);
3872 }
3873
3874 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3875 }
3876 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3877 tg3_setup_flow_control(tp, 0, 0);
3878 current_link_up = 1;
3879 }
3880 goto out;
3881 }
3882
3883 /* Want auto-negotiation. */
3884 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3885
3886 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3887 if (flowctrl & ADVERTISE_1000XPAUSE)
3888 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3889 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3890 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3891
3892 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3893 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3894 tp->serdes_counter &&
3895 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3896 MAC_STATUS_RCVD_CFG)) ==
3897 MAC_STATUS_PCS_SYNCED)) {
3898 tp->serdes_counter--;
3899 current_link_up = 1;
3900 goto out;
3901 }
3902 restart_autoneg:
3903 if (workaround)
3904 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3905 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3906 udelay(5);
3907 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3908
3909 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3910 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3911 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3912 MAC_STATUS_SIGNAL_DET)) {
3913 sg_dig_status = tr32(SG_DIG_STATUS);
3914 mac_status = tr32(MAC_STATUS);
3915
3916 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3917 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3918 u32 local_adv = 0, remote_adv = 0;
3919
3920 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3921 local_adv |= ADVERTISE_1000XPAUSE;
3922 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3923 local_adv |= ADVERTISE_1000XPSE_ASYM;
3924
3925 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3926 remote_adv |= LPA_1000XPAUSE;
3927 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3928 remote_adv |= LPA_1000XPAUSE_ASYM;
3929
3930 tg3_setup_flow_control(tp, local_adv, remote_adv);
3931 current_link_up = 1;
3932 tp->serdes_counter = 0;
3933 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3934 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3935 if (tp->serdes_counter)
3936 tp->serdes_counter--;
3937 else {
3938 if (workaround) {
3939 u32 val = serdes_cfg;
3940
3941 if (port_a)
3942 val |= 0xc010000;
3943 else
3944 val |= 0x4010000;
3945
3946 tw32_f(MAC_SERDES_CFG, val);
3947 }
3948
3949 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3950 udelay(40);
3951
3952 /* Link parallel detection - link is up */
3953 /* only if we have PCS_SYNC and not */
3954 /* receiving config code words */
3955 mac_status = tr32(MAC_STATUS);
3956 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3957 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3958 tg3_setup_flow_control(tp, 0, 0);
3959 current_link_up = 1;
3960 tp->phy_flags |=
3961 TG3_PHYFLG_PARALLEL_DETECT;
3962 tp->serdes_counter =
3963 SERDES_PARALLEL_DET_TIMEOUT;
3964 } else
3965 goto restart_autoneg;
3966 }
3967 }
3968 } else {
3969 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3970 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3971 }
3972
3973 out:
3974 return current_link_up;
3975 }
3976
3977 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3978 {
3979 int current_link_up = 0;
3980
3981 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3982 goto out;
3983
3984 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3985 u32 txflags, rxflags;
3986 int i;
3987
3988 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3989 u32 local_adv = 0, remote_adv = 0;
3990
3991 if (txflags & ANEG_CFG_PS1)
3992 local_adv |= ADVERTISE_1000XPAUSE;
3993 if (txflags & ANEG_CFG_PS2)
3994 local_adv |= ADVERTISE_1000XPSE_ASYM;
3995
3996 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3997 remote_adv |= LPA_1000XPAUSE;
3998 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3999 remote_adv |= LPA_1000XPAUSE_ASYM;
4000
4001 tg3_setup_flow_control(tp, local_adv, remote_adv);
4002
4003 current_link_up = 1;
4004 }
4005 for (i = 0; i < 30; i++) {
4006 udelay(20);
4007 tw32_f(MAC_STATUS,
4008 (MAC_STATUS_SYNC_CHANGED |
4009 MAC_STATUS_CFG_CHANGED));
4010 udelay(40);
4011 if ((tr32(MAC_STATUS) &
4012 (MAC_STATUS_SYNC_CHANGED |
4013 MAC_STATUS_CFG_CHANGED)) == 0)
4014 break;
4015 }
4016
4017 mac_status = tr32(MAC_STATUS);
4018 if (current_link_up == 0 &&
4019 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4020 !(mac_status & MAC_STATUS_RCVD_CFG))
4021 current_link_up = 1;
4022 } else {
4023 tg3_setup_flow_control(tp, 0, 0);
4024
4025 /* Forcing 1000FD link up. */
4026 current_link_up = 1;
4027
4028 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4029 udelay(40);
4030
4031 tw32_f(MAC_MODE, tp->mac_mode);
4032 udelay(40);
4033 }
4034
4035 out:
4036 return current_link_up;
4037 }
4038
4039 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4040 {
4041 u32 orig_pause_cfg;
4042 u16 orig_active_speed;
4043 u8 orig_active_duplex;
4044 u32 mac_status;
4045 int current_link_up;
4046 int i;
4047
4048 orig_pause_cfg = tp->link_config.active_flowctrl;
4049 orig_active_speed = tp->link_config.active_speed;
4050 orig_active_duplex = tp->link_config.active_duplex;
4051
4052 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4053 netif_carrier_ok(tp->dev) &&
4054 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4055 mac_status = tr32(MAC_STATUS);
4056 mac_status &= (MAC_STATUS_PCS_SYNCED |
4057 MAC_STATUS_SIGNAL_DET |
4058 MAC_STATUS_CFG_CHANGED |
4059 MAC_STATUS_RCVD_CFG);
4060 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4061 MAC_STATUS_SIGNAL_DET)) {
4062 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4063 MAC_STATUS_CFG_CHANGED));
4064 return 0;
4065 }
4066 }
4067
4068 tw32_f(MAC_TX_AUTO_NEG, 0);
4069
4070 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4071 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4072 tw32_f(MAC_MODE, tp->mac_mode);
4073 udelay(40);
4074
4075 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4076 tg3_init_bcm8002(tp);
4077
4078 /* Enable link change event even when serdes polling. */
4079 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4080 udelay(40);
4081
4082 current_link_up = 0;
4083 mac_status = tr32(MAC_STATUS);
4084
4085 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4086 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4087 else
4088 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4089
4090 tp->napi[0].hw_status->status =
4091 (SD_STATUS_UPDATED |
4092 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4093
4094 for (i = 0; i < 100; i++) {
4095 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4096 MAC_STATUS_CFG_CHANGED));
4097 udelay(5);
4098 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4099 MAC_STATUS_CFG_CHANGED |
4100 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4101 break;
4102 }
4103
4104 mac_status = tr32(MAC_STATUS);
4105 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4106 current_link_up = 0;
4107 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4108 tp->serdes_counter == 0) {
4109 tw32_f(MAC_MODE, (tp->mac_mode |
4110 MAC_MODE_SEND_CONFIGS));
4111 udelay(1);
4112 tw32_f(MAC_MODE, tp->mac_mode);
4113 }
4114 }
4115
4116 if (current_link_up == 1) {
4117 tp->link_config.active_speed = SPEED_1000;
4118 tp->link_config.active_duplex = DUPLEX_FULL;
4119 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4120 LED_CTRL_LNKLED_OVERRIDE |
4121 LED_CTRL_1000MBPS_ON));
4122 } else {
4123 tp->link_config.active_speed = SPEED_INVALID;
4124 tp->link_config.active_duplex = DUPLEX_INVALID;
4125 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4126 LED_CTRL_LNKLED_OVERRIDE |
4127 LED_CTRL_TRAFFIC_OVERRIDE));
4128 }
4129
4130 if (current_link_up != netif_carrier_ok(tp->dev)) {
4131 if (current_link_up)
4132 netif_carrier_on(tp->dev);
4133 else
4134 netif_carrier_off(tp->dev);
4135 tg3_link_report(tp);
4136 } else {
4137 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4138 if (orig_pause_cfg != now_pause_cfg ||
4139 orig_active_speed != tp->link_config.active_speed ||
4140 orig_active_duplex != tp->link_config.active_duplex)
4141 tg3_link_report(tp);
4142 }
4143
4144 return 0;
4145 }
4146
4147 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4148 {
4149 int current_link_up, err = 0;
4150 u32 bmsr, bmcr;
4151 u16 current_speed;
4152 u8 current_duplex;
4153 u32 local_adv, remote_adv;
4154
4155 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4156 tw32_f(MAC_MODE, tp->mac_mode);
4157 udelay(40);
4158
4159 tw32(MAC_EVENT, 0);
4160
4161 tw32_f(MAC_STATUS,
4162 (MAC_STATUS_SYNC_CHANGED |
4163 MAC_STATUS_CFG_CHANGED |
4164 MAC_STATUS_MI_COMPLETION |
4165 MAC_STATUS_LNKSTATE_CHANGED));
4166 udelay(40);
4167
4168 if (force_reset)
4169 tg3_phy_reset(tp);
4170
4171 current_link_up = 0;
4172 current_speed = SPEED_INVALID;
4173 current_duplex = DUPLEX_INVALID;
4174
4175 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4176 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4177 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4178 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4179 bmsr |= BMSR_LSTATUS;
4180 else
4181 bmsr &= ~BMSR_LSTATUS;
4182 }
4183
4184 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4185
4186 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4187 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4188 /* do nothing, just check for link up at the end */
4189 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4190 u32 adv, new_adv;
4191
4192 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4193 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4194 ADVERTISE_1000XPAUSE |
4195 ADVERTISE_1000XPSE_ASYM |
4196 ADVERTISE_SLCT);
4197
4198 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4199
4200 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4201 new_adv |= ADVERTISE_1000XHALF;
4202 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4203 new_adv |= ADVERTISE_1000XFULL;
4204
4205 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4206 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4207 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4208 tg3_writephy(tp, MII_BMCR, bmcr);
4209
4210 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4211 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4212 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4213
4214 return err;
4215 }
4216 } else {
4217 u32 new_bmcr;
4218
4219 bmcr &= ~BMCR_SPEED1000;
4220 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4221
4222 if (tp->link_config.duplex == DUPLEX_FULL)
4223 new_bmcr |= BMCR_FULLDPLX;
4224
4225 if (new_bmcr != bmcr) {
4226 /* BMCR_SPEED1000 is a reserved bit that needs
4227 * to be set on write.
4228 */
4229 new_bmcr |= BMCR_SPEED1000;
4230
4231 /* Force a linkdown */
4232 if (netif_carrier_ok(tp->dev)) {
4233 u32 adv;
4234
4235 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4236 adv &= ~(ADVERTISE_1000XFULL |
4237 ADVERTISE_1000XHALF |
4238 ADVERTISE_SLCT);
4239 tg3_writephy(tp, MII_ADVERTISE, adv);
4240 tg3_writephy(tp, MII_BMCR, bmcr |
4241 BMCR_ANRESTART |
4242 BMCR_ANENABLE);
4243 udelay(10);
4244 netif_carrier_off(tp->dev);
4245 }
4246 tg3_writephy(tp, MII_BMCR, new_bmcr);
4247 bmcr = new_bmcr;
4248 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4249 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4250 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4251 ASIC_REV_5714) {
4252 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4253 bmsr |= BMSR_LSTATUS;
4254 else
4255 bmsr &= ~BMSR_LSTATUS;
4256 }
4257 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4258 }
4259 }
4260
4261 if (bmsr & BMSR_LSTATUS) {
4262 current_speed = SPEED_1000;
4263 current_link_up = 1;
4264 if (bmcr & BMCR_FULLDPLX)
4265 current_duplex = DUPLEX_FULL;
4266 else
4267 current_duplex = DUPLEX_HALF;
4268
4269 local_adv = 0;
4270 remote_adv = 0;
4271
4272 if (bmcr & BMCR_ANENABLE) {
4273 u32 common;
4274
4275 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4276 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4277 common = local_adv & remote_adv;
4278 if (common & (ADVERTISE_1000XHALF |
4279 ADVERTISE_1000XFULL)) {
4280 if (common & ADVERTISE_1000XFULL)
4281 current_duplex = DUPLEX_FULL;
4282 else
4283 current_duplex = DUPLEX_HALF;
4284 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4285 /* Link is up via parallel detect */
4286 } else {
4287 current_link_up = 0;
4288 }
4289 }
4290 }
4291
4292 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4293 tg3_setup_flow_control(tp, local_adv, remote_adv);
4294
4295 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4296 if (tp->link_config.active_duplex == DUPLEX_HALF)
4297 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4298
4299 tw32_f(MAC_MODE, tp->mac_mode);
4300 udelay(40);
4301
4302 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4303
4304 tp->link_config.active_speed = current_speed;
4305 tp->link_config.active_duplex = current_duplex;
4306
4307 if (current_link_up != netif_carrier_ok(tp->dev)) {
4308 if (current_link_up)
4309 netif_carrier_on(tp->dev);
4310 else {
4311 netif_carrier_off(tp->dev);
4312 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4313 }
4314 tg3_link_report(tp);
4315 }
4316 return err;
4317 }
4318
4319 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4320 {
4321 if (tp->serdes_counter) {
4322 /* Give autoneg time to complete. */
4323 tp->serdes_counter--;
4324 return;
4325 }
4326
4327 if (!netif_carrier_ok(tp->dev) &&
4328 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4329 u32 bmcr;
4330
4331 tg3_readphy(tp, MII_BMCR, &bmcr);
4332 if (bmcr & BMCR_ANENABLE) {
4333 u32 phy1, phy2;
4334
4335 /* Select shadow register 0x1f */
4336 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4337 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4338
4339 /* Select expansion interrupt status register */
4340 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4341 MII_TG3_DSP_EXP1_INT_STAT);
4342 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4343 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4344
4345 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4346 /* We have signal detect and not receiving
4347 * config code words, link is up by parallel
4348 * detection.
4349 */
4350
4351 bmcr &= ~BMCR_ANENABLE;
4352 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4353 tg3_writephy(tp, MII_BMCR, bmcr);
4354 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4355 }
4356 }
4357 } else if (netif_carrier_ok(tp->dev) &&
4358 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4359 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4360 u32 phy2;
4361
4362 /* Select expansion interrupt status register */
4363 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4364 MII_TG3_DSP_EXP1_INT_STAT);
4365 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4366 if (phy2 & 0x20) {
4367 u32 bmcr;
4368
4369 /* Config code words received, turn on autoneg. */
4370 tg3_readphy(tp, MII_BMCR, &bmcr);
4371 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4372
4373 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4374
4375 }
4376 }
4377 }
4378
4379 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4380 {
4381 int err;
4382
4383 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4384 err = tg3_setup_fiber_phy(tp, force_reset);
4385 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4386 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4387 else
4388 err = tg3_setup_copper_phy(tp, force_reset);
4389
4390 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4391 u32 val, scale;
4392
4393 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4394 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4395 scale = 65;
4396 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4397 scale = 6;
4398 else
4399 scale = 12;
4400
4401 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4402 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4403 tw32(GRC_MISC_CFG, val);
4404 }
4405
4406 if (tp->link_config.active_speed == SPEED_1000 &&
4407 tp->link_config.active_duplex == DUPLEX_HALF)
4408 tw32(MAC_TX_LENGTHS,
4409 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4410 (6 << TX_LENGTHS_IPG_SHIFT) |
4411 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4412 else
4413 tw32(MAC_TX_LENGTHS,
4414 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4415 (6 << TX_LENGTHS_IPG_SHIFT) |
4416 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4417
4418 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4419 if (netif_carrier_ok(tp->dev)) {
4420 tw32(HOSTCC_STAT_COAL_TICKS,
4421 tp->coal.stats_block_coalesce_usecs);
4422 } else {
4423 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4424 }
4425 }
4426
4427 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4428 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4429 if (!netif_carrier_ok(tp->dev))
4430 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4431 tp->pwrmgmt_thresh;
4432 else
4433 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4434 tw32(PCIE_PWR_MGMT_THRESH, val);
4435 }
4436
4437 return err;
4438 }
4439
4440 static inline int tg3_irq_sync(struct tg3 *tp)
4441 {
4442 return tp->irq_sync;
4443 }
4444
4445 /* This is called whenever we suspect that the system chipset is re-
4446 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4447 * is bogus tx completions. We try to recover by setting the
4448 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4449 * in the workqueue.
4450 */
4451 static void tg3_tx_recover(struct tg3 *tp)
4452 {
4453 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4454 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4455
4456 netdev_warn(tp->dev,
4457 "The system may be re-ordering memory-mapped I/O "
4458 "cycles to the network device, attempting to recover. "
4459 "Please report the problem to the driver maintainer "
4460 "and include system chipset information.\n");
4461
4462 spin_lock(&tp->lock);
4463 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4464 spin_unlock(&tp->lock);
4465 }
4466
4467 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4468 {
4469 /* Tell compiler to fetch tx indices from memory. */
4470 barrier();
4471 return tnapi->tx_pending -
4472 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4473 }
4474
4475 /* Tigon3 never reports partial packet sends. So we do not
4476 * need special logic to handle SKBs that have not had all
4477 * of their frags sent yet, like SunGEM does.
4478 */
4479 static void tg3_tx(struct tg3_napi *tnapi)
4480 {
4481 struct tg3 *tp = tnapi->tp;
4482 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4483 u32 sw_idx = tnapi->tx_cons;
4484 struct netdev_queue *txq;
4485 int index = tnapi - tp->napi;
4486
4487 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4488 index--;
4489
4490 txq = netdev_get_tx_queue(tp->dev, index);
4491
4492 while (sw_idx != hw_idx) {
4493 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4494 struct sk_buff *skb = ri->skb;
4495 int i, tx_bug = 0;
4496
4497 if (unlikely(skb == NULL)) {
4498 tg3_tx_recover(tp);
4499 return;
4500 }
4501
4502 pci_unmap_single(tp->pdev,
4503 dma_unmap_addr(ri, mapping),
4504 skb_headlen(skb),
4505 PCI_DMA_TODEVICE);
4506
4507 ri->skb = NULL;
4508
4509 sw_idx = NEXT_TX(sw_idx);
4510
4511 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4512 ri = &tnapi->tx_buffers[sw_idx];
4513 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4514 tx_bug = 1;
4515
4516 pci_unmap_page(tp->pdev,
4517 dma_unmap_addr(ri, mapping),
4518 skb_shinfo(skb)->frags[i].size,
4519 PCI_DMA_TODEVICE);
4520 sw_idx = NEXT_TX(sw_idx);
4521 }
4522
4523 dev_kfree_skb(skb);
4524
4525 if (unlikely(tx_bug)) {
4526 tg3_tx_recover(tp);
4527 return;
4528 }
4529 }
4530
4531 tnapi->tx_cons = sw_idx;
4532
4533 /* Need to make the tx_cons update visible to tg3_start_xmit()
4534 * before checking for netif_queue_stopped(). Without the
4535 * memory barrier, there is a small possibility that tg3_start_xmit()
4536 * will miss it and cause the queue to be stopped forever.
4537 */
4538 smp_mb();
4539
4540 if (unlikely(netif_tx_queue_stopped(txq) &&
4541 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4542 __netif_tx_lock(txq, smp_processor_id());
4543 if (netif_tx_queue_stopped(txq) &&
4544 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4545 netif_tx_wake_queue(txq);
4546 __netif_tx_unlock(txq);
4547 }
4548 }
4549
4550 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4551 {
4552 if (!ri->skb)
4553 return;
4554
4555 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4556 map_sz, PCI_DMA_FROMDEVICE);
4557 dev_kfree_skb_any(ri->skb);
4558 ri->skb = NULL;
4559 }
4560
4561 /* Returns size of skb allocated or < 0 on error.
4562 *
4563 * We only need to fill in the address because the other members
4564 * of the RX descriptor are invariant, see tg3_init_rings.
4565 *
4566 * Note the purposeful assymetry of cpu vs. chip accesses. For
4567 * posting buffers we only dirty the first cache line of the RX
4568 * descriptor (containing the address). Whereas for the RX status
4569 * buffers the cpu only reads the last cacheline of the RX descriptor
4570 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4571 */
4572 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4573 u32 opaque_key, u32 dest_idx_unmasked)
4574 {
4575 struct tg3_rx_buffer_desc *desc;
4576 struct ring_info *map;
4577 struct sk_buff *skb;
4578 dma_addr_t mapping;
4579 int skb_size, dest_idx;
4580
4581 switch (opaque_key) {
4582 case RXD_OPAQUE_RING_STD:
4583 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4584 desc = &tpr->rx_std[dest_idx];
4585 map = &tpr->rx_std_buffers[dest_idx];
4586 skb_size = tp->rx_pkt_map_sz;
4587 break;
4588
4589 case RXD_OPAQUE_RING_JUMBO:
4590 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4591 desc = &tpr->rx_jmb[dest_idx].std;
4592 map = &tpr->rx_jmb_buffers[dest_idx];
4593 skb_size = TG3_RX_JMB_MAP_SZ;
4594 break;
4595
4596 default:
4597 return -EINVAL;
4598 }
4599
4600 /* Do not overwrite any of the map or rp information
4601 * until we are sure we can commit to a new buffer.
4602 *
4603 * Callers depend upon this behavior and assume that
4604 * we leave everything unchanged if we fail.
4605 */
4606 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4607 if (skb == NULL)
4608 return -ENOMEM;
4609
4610 skb_reserve(skb, tp->rx_offset);
4611
4612 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4613 PCI_DMA_FROMDEVICE);
4614 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4615 dev_kfree_skb(skb);
4616 return -EIO;
4617 }
4618
4619 map->skb = skb;
4620 dma_unmap_addr_set(map, mapping, mapping);
4621
4622 desc->addr_hi = ((u64)mapping >> 32);
4623 desc->addr_lo = ((u64)mapping & 0xffffffff);
4624
4625 return skb_size;
4626 }
4627
4628 /* We only need to move over in the address because the other
4629 * members of the RX descriptor are invariant. See notes above
4630 * tg3_alloc_rx_skb for full details.
4631 */
4632 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4633 struct tg3_rx_prodring_set *dpr,
4634 u32 opaque_key, int src_idx,
4635 u32 dest_idx_unmasked)
4636 {
4637 struct tg3 *tp = tnapi->tp;
4638 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4639 struct ring_info *src_map, *dest_map;
4640 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4641 int dest_idx;
4642
4643 switch (opaque_key) {
4644 case RXD_OPAQUE_RING_STD:
4645 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4646 dest_desc = &dpr->rx_std[dest_idx];
4647 dest_map = &dpr->rx_std_buffers[dest_idx];
4648 src_desc = &spr->rx_std[src_idx];
4649 src_map = &spr->rx_std_buffers[src_idx];
4650 break;
4651
4652 case RXD_OPAQUE_RING_JUMBO:
4653 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4654 dest_desc = &dpr->rx_jmb[dest_idx].std;
4655 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4656 src_desc = &spr->rx_jmb[src_idx].std;
4657 src_map = &spr->rx_jmb_buffers[src_idx];
4658 break;
4659
4660 default:
4661 return;
4662 }
4663
4664 dest_map->skb = src_map->skb;
4665 dma_unmap_addr_set(dest_map, mapping,
4666 dma_unmap_addr(src_map, mapping));
4667 dest_desc->addr_hi = src_desc->addr_hi;
4668 dest_desc->addr_lo = src_desc->addr_lo;
4669
4670 /* Ensure that the update to the skb happens after the physical
4671 * addresses have been transferred to the new BD location.
4672 */
4673 smp_wmb();
4674
4675 src_map->skb = NULL;
4676 }
4677
4678 /* The RX ring scheme is composed of multiple rings which post fresh
4679 * buffers to the chip, and one special ring the chip uses to report
4680 * status back to the host.
4681 *
4682 * The special ring reports the status of received packets to the
4683 * host. The chip does not write into the original descriptor the
4684 * RX buffer was obtained from. The chip simply takes the original
4685 * descriptor as provided by the host, updates the status and length
4686 * field, then writes this into the next status ring entry.
4687 *
4688 * Each ring the host uses to post buffers to the chip is described
4689 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4690 * it is first placed into the on-chip ram. When the packet's length
4691 * is known, it walks down the TG3_BDINFO entries to select the ring.
4692 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4693 * which is within the range of the new packet's length is chosen.
4694 *
4695 * The "separate ring for rx status" scheme may sound queer, but it makes
4696 * sense from a cache coherency perspective. If only the host writes
4697 * to the buffer post rings, and only the chip writes to the rx status
4698 * rings, then cache lines never move beyond shared-modified state.
4699 * If both the host and chip were to write into the same ring, cache line
4700 * eviction could occur since both entities want it in an exclusive state.
4701 */
4702 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4703 {
4704 struct tg3 *tp = tnapi->tp;
4705 u32 work_mask, rx_std_posted = 0;
4706 u32 std_prod_idx, jmb_prod_idx;
4707 u32 sw_idx = tnapi->rx_rcb_ptr;
4708 u16 hw_idx;
4709 int received;
4710 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4711
4712 hw_idx = *(tnapi->rx_rcb_prod_idx);
4713 /*
4714 * We need to order the read of hw_idx and the read of
4715 * the opaque cookie.
4716 */
4717 rmb();
4718 work_mask = 0;
4719 received = 0;
4720 std_prod_idx = tpr->rx_std_prod_idx;
4721 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4722 while (sw_idx != hw_idx && budget > 0) {
4723 struct ring_info *ri;
4724 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4725 unsigned int len;
4726 struct sk_buff *skb;
4727 dma_addr_t dma_addr;
4728 u32 opaque_key, desc_idx, *post_ptr;
4729 bool hw_vlan __maybe_unused = false;
4730 u16 vtag __maybe_unused = 0;
4731
4732 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4733 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4734 if (opaque_key == RXD_OPAQUE_RING_STD) {
4735 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4736 dma_addr = dma_unmap_addr(ri, mapping);
4737 skb = ri->skb;
4738 post_ptr = &std_prod_idx;
4739 rx_std_posted++;
4740 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4741 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4742 dma_addr = dma_unmap_addr(ri, mapping);
4743 skb = ri->skb;
4744 post_ptr = &jmb_prod_idx;
4745 } else
4746 goto next_pkt_nopost;
4747
4748 work_mask |= opaque_key;
4749
4750 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4751 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4752 drop_it:
4753 tg3_recycle_rx(tnapi, tpr, opaque_key,
4754 desc_idx, *post_ptr);
4755 drop_it_no_recycle:
4756 /* Other statistics kept track of by card. */
4757 tp->rx_dropped++;
4758 goto next_pkt;
4759 }
4760
4761 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4762 ETH_FCS_LEN;
4763
4764 if (len > TG3_RX_COPY_THRESH(tp)) {
4765 int skb_size;
4766
4767 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4768 *post_ptr);
4769 if (skb_size < 0)
4770 goto drop_it;
4771
4772 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4773 PCI_DMA_FROMDEVICE);
4774
4775 /* Ensure that the update to the skb happens
4776 * after the usage of the old DMA mapping.
4777 */
4778 smp_wmb();
4779
4780 ri->skb = NULL;
4781
4782 skb_put(skb, len);
4783 } else {
4784 struct sk_buff *copy_skb;
4785
4786 tg3_recycle_rx(tnapi, tpr, opaque_key,
4787 desc_idx, *post_ptr);
4788
4789 copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4790 TG3_RAW_IP_ALIGN);
4791 if (copy_skb == NULL)
4792 goto drop_it_no_recycle;
4793
4794 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4795 skb_put(copy_skb, len);
4796 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4797 skb_copy_from_linear_data(skb, copy_skb->data, len);
4798 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4799
4800 /* We'll reuse the original ring buffer. */
4801 skb = copy_skb;
4802 }
4803
4804 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4805 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4806 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4807 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4808 skb->ip_summed = CHECKSUM_UNNECESSARY;
4809 else
4810 skb_checksum_none_assert(skb);
4811
4812 skb->protocol = eth_type_trans(skb, tp->dev);
4813
4814 if (len > (tp->dev->mtu + ETH_HLEN) &&
4815 skb->protocol != htons(ETH_P_8021Q)) {
4816 dev_kfree_skb(skb);
4817 goto drop_it_no_recycle;
4818 }
4819
4820 if (desc->type_flags & RXD_FLAG_VLAN &&
4821 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4822 vtag = desc->err_vlan & RXD_VLAN_MASK;
4823 #if TG3_VLAN_TAG_USED
4824 if (tp->vlgrp)
4825 hw_vlan = true;
4826 else
4827 #endif
4828 {
4829 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4830 __skb_push(skb, VLAN_HLEN);
4831
4832 memmove(ve, skb->data + VLAN_HLEN,
4833 ETH_ALEN * 2);
4834 ve->h_vlan_proto = htons(ETH_P_8021Q);
4835 ve->h_vlan_TCI = htons(vtag);
4836 }
4837 }
4838
4839 #if TG3_VLAN_TAG_USED
4840 if (hw_vlan)
4841 vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4842 else
4843 #endif
4844 napi_gro_receive(&tnapi->napi, skb);
4845
4846 received++;
4847 budget--;
4848
4849 next_pkt:
4850 (*post_ptr)++;
4851
4852 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4853 tpr->rx_std_prod_idx = std_prod_idx &
4854 tp->rx_std_ring_mask;
4855 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4856 tpr->rx_std_prod_idx);
4857 work_mask &= ~RXD_OPAQUE_RING_STD;
4858 rx_std_posted = 0;
4859 }
4860 next_pkt_nopost:
4861 sw_idx++;
4862 sw_idx &= tp->rx_ret_ring_mask;
4863
4864 /* Refresh hw_idx to see if there is new work */
4865 if (sw_idx == hw_idx) {
4866 hw_idx = *(tnapi->rx_rcb_prod_idx);
4867 rmb();
4868 }
4869 }
4870
4871 /* ACK the status ring. */
4872 tnapi->rx_rcb_ptr = sw_idx;
4873 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4874
4875 /* Refill RX ring(s). */
4876 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4877 if (work_mask & RXD_OPAQUE_RING_STD) {
4878 tpr->rx_std_prod_idx = std_prod_idx &
4879 tp->rx_std_ring_mask;
4880 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4881 tpr->rx_std_prod_idx);
4882 }
4883 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4884 tpr->rx_jmb_prod_idx = jmb_prod_idx &
4885 tp->rx_jmb_ring_mask;
4886 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4887 tpr->rx_jmb_prod_idx);
4888 }
4889 mmiowb();
4890 } else if (work_mask) {
4891 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4892 * updated before the producer indices can be updated.
4893 */
4894 smp_wmb();
4895
4896 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4897 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4898
4899 if (tnapi != &tp->napi[1])
4900 napi_schedule(&tp->napi[1].napi);
4901 }
4902
4903 return received;
4904 }
4905
4906 static void tg3_poll_link(struct tg3 *tp)
4907 {
4908 /* handle link change and other phy events */
4909 if (!(tp->tg3_flags &
4910 (TG3_FLAG_USE_LINKCHG_REG |
4911 TG3_FLAG_POLL_SERDES))) {
4912 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4913
4914 if (sblk->status & SD_STATUS_LINK_CHG) {
4915 sblk->status = SD_STATUS_UPDATED |
4916 (sblk->status & ~SD_STATUS_LINK_CHG);
4917 spin_lock(&tp->lock);
4918 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4919 tw32_f(MAC_STATUS,
4920 (MAC_STATUS_SYNC_CHANGED |
4921 MAC_STATUS_CFG_CHANGED |
4922 MAC_STATUS_MI_COMPLETION |
4923 MAC_STATUS_LNKSTATE_CHANGED));
4924 udelay(40);
4925 } else
4926 tg3_setup_phy(tp, 0);
4927 spin_unlock(&tp->lock);
4928 }
4929 }
4930 }
4931
4932 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4933 struct tg3_rx_prodring_set *dpr,
4934 struct tg3_rx_prodring_set *spr)
4935 {
4936 u32 si, di, cpycnt, src_prod_idx;
4937 int i, err = 0;
4938
4939 while (1) {
4940 src_prod_idx = spr->rx_std_prod_idx;
4941
4942 /* Make sure updates to the rx_std_buffers[] entries and the
4943 * standard producer index are seen in the correct order.
4944 */
4945 smp_rmb();
4946
4947 if (spr->rx_std_cons_idx == src_prod_idx)
4948 break;
4949
4950 if (spr->rx_std_cons_idx < src_prod_idx)
4951 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4952 else
4953 cpycnt = tp->rx_std_ring_mask + 1 -
4954 spr->rx_std_cons_idx;
4955
4956 cpycnt = min(cpycnt,
4957 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4958
4959 si = spr->rx_std_cons_idx;
4960 di = dpr->rx_std_prod_idx;
4961
4962 for (i = di; i < di + cpycnt; i++) {
4963 if (dpr->rx_std_buffers[i].skb) {
4964 cpycnt = i - di;
4965 err = -ENOSPC;
4966 break;
4967 }
4968 }
4969
4970 if (!cpycnt)
4971 break;
4972
4973 /* Ensure that updates to the rx_std_buffers ring and the
4974 * shadowed hardware producer ring from tg3_recycle_skb() are
4975 * ordered correctly WRT the skb check above.
4976 */
4977 smp_rmb();
4978
4979 memcpy(&dpr->rx_std_buffers[di],
4980 &spr->rx_std_buffers[si],
4981 cpycnt * sizeof(struct ring_info));
4982
4983 for (i = 0; i < cpycnt; i++, di++, si++) {
4984 struct tg3_rx_buffer_desc *sbd, *dbd;
4985 sbd = &spr->rx_std[si];
4986 dbd = &dpr->rx_std[di];
4987 dbd->addr_hi = sbd->addr_hi;
4988 dbd->addr_lo = sbd->addr_lo;
4989 }
4990
4991 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4992 tp->rx_std_ring_mask;
4993 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4994 tp->rx_std_ring_mask;
4995 }
4996
4997 while (1) {
4998 src_prod_idx = spr->rx_jmb_prod_idx;
4999
5000 /* Make sure updates to the rx_jmb_buffers[] entries and
5001 * the jumbo producer index are seen in the correct order.
5002 */
5003 smp_rmb();
5004
5005 if (spr->rx_jmb_cons_idx == src_prod_idx)
5006 break;
5007
5008 if (spr->rx_jmb_cons_idx < src_prod_idx)
5009 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5010 else
5011 cpycnt = tp->rx_jmb_ring_mask + 1 -
5012 spr->rx_jmb_cons_idx;
5013
5014 cpycnt = min(cpycnt,
5015 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5016
5017 si = spr->rx_jmb_cons_idx;
5018 di = dpr->rx_jmb_prod_idx;
5019
5020 for (i = di; i < di + cpycnt; i++) {
5021 if (dpr->rx_jmb_buffers[i].skb) {
5022 cpycnt = i - di;
5023 err = -ENOSPC;
5024 break;
5025 }
5026 }
5027
5028 if (!cpycnt)
5029 break;
5030
5031 /* Ensure that updates to the rx_jmb_buffers ring and the
5032 * shadowed hardware producer ring from tg3_recycle_skb() are
5033 * ordered correctly WRT the skb check above.
5034 */
5035 smp_rmb();
5036
5037 memcpy(&dpr->rx_jmb_buffers[di],
5038 &spr->rx_jmb_buffers[si],
5039 cpycnt * sizeof(struct ring_info));
5040
5041 for (i = 0; i < cpycnt; i++, di++, si++) {
5042 struct tg3_rx_buffer_desc *sbd, *dbd;
5043 sbd = &spr->rx_jmb[si].std;
5044 dbd = &dpr->rx_jmb[di].std;
5045 dbd->addr_hi = sbd->addr_hi;
5046 dbd->addr_lo = sbd->addr_lo;
5047 }
5048
5049 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5050 tp->rx_jmb_ring_mask;
5051 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5052 tp->rx_jmb_ring_mask;
5053 }
5054
5055 return err;
5056 }
5057
5058 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5059 {
5060 struct tg3 *tp = tnapi->tp;
5061
5062 /* run TX completion thread */
5063 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5064 tg3_tx(tnapi);
5065 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5066 return work_done;
5067 }
5068
5069 /* run RX thread, within the bounds set by NAPI.
5070 * All RX "locking" is done by ensuring outside
5071 * code synchronizes with tg3->napi.poll()
5072 */
5073 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5074 work_done += tg3_rx(tnapi, budget - work_done);
5075
5076 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5077 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5078 int i, err = 0;
5079 u32 std_prod_idx = dpr->rx_std_prod_idx;
5080 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5081
5082 for (i = 1; i < tp->irq_cnt; i++)
5083 err |= tg3_rx_prodring_xfer(tp, dpr,
5084 &tp->napi[i].prodring);
5085
5086 wmb();
5087
5088 if (std_prod_idx != dpr->rx_std_prod_idx)
5089 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5090 dpr->rx_std_prod_idx);
5091
5092 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5093 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5094 dpr->rx_jmb_prod_idx);
5095
5096 mmiowb();
5097
5098 if (err)
5099 tw32_f(HOSTCC_MODE, tp->coal_now);
5100 }
5101
5102 return work_done;
5103 }
5104
5105 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5106 {
5107 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5108 struct tg3 *tp = tnapi->tp;
5109 int work_done = 0;
5110 struct tg3_hw_status *sblk = tnapi->hw_status;
5111
5112 while (1) {
5113 work_done = tg3_poll_work(tnapi, work_done, budget);
5114
5115 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5116 goto tx_recovery;
5117
5118 if (unlikely(work_done >= budget))
5119 break;
5120
5121 /* tp->last_tag is used in tg3_int_reenable() below
5122 * to tell the hw how much work has been processed,
5123 * so we must read it before checking for more work.
5124 */
5125 tnapi->last_tag = sblk->status_tag;
5126 tnapi->last_irq_tag = tnapi->last_tag;
5127 rmb();
5128
5129 /* check for RX/TX work to do */
5130 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5131 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5132 napi_complete(napi);
5133 /* Reenable interrupts. */
5134 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5135 mmiowb();
5136 break;
5137 }
5138 }
5139
5140 return work_done;
5141
5142 tx_recovery:
5143 /* work_done is guaranteed to be less than budget. */
5144 napi_complete(napi);
5145 schedule_work(&tp->reset_task);
5146 return work_done;
5147 }
5148
5149 static int tg3_poll(struct napi_struct *napi, int budget)
5150 {
5151 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5152 struct tg3 *tp = tnapi->tp;
5153 int work_done = 0;
5154 struct tg3_hw_status *sblk = tnapi->hw_status;
5155
5156 while (1) {
5157 tg3_poll_link(tp);
5158
5159 work_done = tg3_poll_work(tnapi, work_done, budget);
5160
5161 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5162 goto tx_recovery;
5163
5164 if (unlikely(work_done >= budget))
5165 break;
5166
5167 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5168 /* tp->last_tag is used in tg3_int_reenable() below
5169 * to tell the hw how much work has been processed,
5170 * so we must read it before checking for more work.
5171 */
5172 tnapi->last_tag = sblk->status_tag;
5173 tnapi->last_irq_tag = tnapi->last_tag;
5174 rmb();
5175 } else
5176 sblk->status &= ~SD_STATUS_UPDATED;
5177
5178 if (likely(!tg3_has_work(tnapi))) {
5179 napi_complete(napi);
5180 tg3_int_reenable(tnapi);
5181 break;
5182 }
5183 }
5184
5185 return work_done;
5186
5187 tx_recovery:
5188 /* work_done is guaranteed to be less than budget. */
5189 napi_complete(napi);
5190 schedule_work(&tp->reset_task);
5191 return work_done;
5192 }
5193
5194 static void tg3_napi_disable(struct tg3 *tp)
5195 {
5196 int i;
5197
5198 for (i = tp->irq_cnt - 1; i >= 0; i--)
5199 napi_disable(&tp->napi[i].napi);
5200 }
5201
5202 static void tg3_napi_enable(struct tg3 *tp)
5203 {
5204 int i;
5205
5206 for (i = 0; i < tp->irq_cnt; i++)
5207 napi_enable(&tp->napi[i].napi);
5208 }
5209
5210 static void tg3_napi_init(struct tg3 *tp)
5211 {
5212 int i;
5213
5214 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5215 for (i = 1; i < tp->irq_cnt; i++)
5216 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5217 }
5218
5219 static void tg3_napi_fini(struct tg3 *tp)
5220 {
5221 int i;
5222
5223 for (i = 0; i < tp->irq_cnt; i++)
5224 netif_napi_del(&tp->napi[i].napi);
5225 }
5226
5227 static inline void tg3_netif_stop(struct tg3 *tp)
5228 {
5229 tp->dev->trans_start = jiffies; /* prevent tx timeout */
5230 tg3_napi_disable(tp);
5231 netif_tx_disable(tp->dev);
5232 }
5233
5234 static inline void tg3_netif_start(struct tg3 *tp)
5235 {
5236 /* NOTE: unconditional netif_tx_wake_all_queues is only
5237 * appropriate so long as all callers are assured to
5238 * have free tx slots (such as after tg3_init_hw)
5239 */
5240 netif_tx_wake_all_queues(tp->dev);
5241
5242 tg3_napi_enable(tp);
5243 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5244 tg3_enable_ints(tp);
5245 }
5246
5247 static void tg3_irq_quiesce(struct tg3 *tp)
5248 {
5249 int i;
5250
5251 BUG_ON(tp->irq_sync);
5252
5253 tp->irq_sync = 1;
5254 smp_mb();
5255
5256 for (i = 0; i < tp->irq_cnt; i++)
5257 synchronize_irq(tp->napi[i].irq_vec);
5258 }
5259
5260 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5261 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5262 * with as well. Most of the time, this is not necessary except when
5263 * shutting down the device.
5264 */
5265 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5266 {
5267 spin_lock_bh(&tp->lock);
5268 if (irq_sync)
5269 tg3_irq_quiesce(tp);
5270 }
5271
5272 static inline void tg3_full_unlock(struct tg3 *tp)
5273 {
5274 spin_unlock_bh(&tp->lock);
5275 }
5276
5277 /* One-shot MSI handler - Chip automatically disables interrupt
5278 * after sending MSI so driver doesn't have to do it.
5279 */
5280 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5281 {
5282 struct tg3_napi *tnapi = dev_id;
5283 struct tg3 *tp = tnapi->tp;
5284
5285 prefetch(tnapi->hw_status);
5286 if (tnapi->rx_rcb)
5287 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5288
5289 if (likely(!tg3_irq_sync(tp)))
5290 napi_schedule(&tnapi->napi);
5291
5292 return IRQ_HANDLED;
5293 }
5294
5295 /* MSI ISR - No need to check for interrupt sharing and no need to
5296 * flush status block and interrupt mailbox. PCI ordering rules
5297 * guarantee that MSI will arrive after the status block.
5298 */
5299 static irqreturn_t tg3_msi(int irq, void *dev_id)
5300 {
5301 struct tg3_napi *tnapi = dev_id;
5302 struct tg3 *tp = tnapi->tp;
5303
5304 prefetch(tnapi->hw_status);
5305 if (tnapi->rx_rcb)
5306 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5307 /*
5308 * Writing any value to intr-mbox-0 clears PCI INTA# and
5309 * chip-internal interrupt pending events.
5310 * Writing non-zero to intr-mbox-0 additional tells the
5311 * NIC to stop sending us irqs, engaging "in-intr-handler"
5312 * event coalescing.
5313 */
5314 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5315 if (likely(!tg3_irq_sync(tp)))
5316 napi_schedule(&tnapi->napi);
5317
5318 return IRQ_RETVAL(1);
5319 }
5320
5321 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5322 {
5323 struct tg3_napi *tnapi = dev_id;
5324 struct tg3 *tp = tnapi->tp;
5325 struct tg3_hw_status *sblk = tnapi->hw_status;
5326 unsigned int handled = 1;
5327
5328 /* In INTx mode, it is possible for the interrupt to arrive at
5329 * the CPU before the status block posted prior to the interrupt.
5330 * Reading the PCI State register will confirm whether the
5331 * interrupt is ours and will flush the status block.
5332 */
5333 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5334 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5335 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5336 handled = 0;
5337 goto out;
5338 }
5339 }
5340
5341 /*
5342 * Writing any value to intr-mbox-0 clears PCI INTA# and
5343 * chip-internal interrupt pending events.
5344 * Writing non-zero to intr-mbox-0 additional tells the
5345 * NIC to stop sending us irqs, engaging "in-intr-handler"
5346 * event coalescing.
5347 *
5348 * Flush the mailbox to de-assert the IRQ immediately to prevent
5349 * spurious interrupts. The flush impacts performance but
5350 * excessive spurious interrupts can be worse in some cases.
5351 */
5352 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5353 if (tg3_irq_sync(tp))
5354 goto out;
5355 sblk->status &= ~SD_STATUS_UPDATED;
5356 if (likely(tg3_has_work(tnapi))) {
5357 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5358 napi_schedule(&tnapi->napi);
5359 } else {
5360 /* No work, shared interrupt perhaps? re-enable
5361 * interrupts, and flush that PCI write
5362 */
5363 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5364 0x00000000);
5365 }
5366 out:
5367 return IRQ_RETVAL(handled);
5368 }
5369
5370 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5371 {
5372 struct tg3_napi *tnapi = dev_id;
5373 struct tg3 *tp = tnapi->tp;
5374 struct tg3_hw_status *sblk = tnapi->hw_status;
5375 unsigned int handled = 1;
5376
5377 /* In INTx mode, it is possible for the interrupt to arrive at
5378 * the CPU before the status block posted prior to the interrupt.
5379 * Reading the PCI State register will confirm whether the
5380 * interrupt is ours and will flush the status block.
5381 */
5382 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5383 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5384 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5385 handled = 0;
5386 goto out;
5387 }
5388 }
5389
5390 /*
5391 * writing any value to intr-mbox-0 clears PCI INTA# and
5392 * chip-internal interrupt pending events.
5393 * writing non-zero to intr-mbox-0 additional tells the
5394 * NIC to stop sending us irqs, engaging "in-intr-handler"
5395 * event coalescing.
5396 *
5397 * Flush the mailbox to de-assert the IRQ immediately to prevent
5398 * spurious interrupts. The flush impacts performance but
5399 * excessive spurious interrupts can be worse in some cases.
5400 */
5401 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5402
5403 /*
5404 * In a shared interrupt configuration, sometimes other devices'
5405 * interrupts will scream. We record the current status tag here
5406 * so that the above check can report that the screaming interrupts
5407 * are unhandled. Eventually they will be silenced.
5408 */
5409 tnapi->last_irq_tag = sblk->status_tag;
5410
5411 if (tg3_irq_sync(tp))
5412 goto out;
5413
5414 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5415
5416 napi_schedule(&tnapi->napi);
5417
5418 out:
5419 return IRQ_RETVAL(handled);
5420 }
5421
5422 /* ISR for interrupt test */
5423 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5424 {
5425 struct tg3_napi *tnapi = dev_id;
5426 struct tg3 *tp = tnapi->tp;
5427 struct tg3_hw_status *sblk = tnapi->hw_status;
5428
5429 if ((sblk->status & SD_STATUS_UPDATED) ||
5430 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5431 tg3_disable_ints(tp);
5432 return IRQ_RETVAL(1);
5433 }
5434 return IRQ_RETVAL(0);
5435 }
5436
5437 static int tg3_init_hw(struct tg3 *, int);
5438 static int tg3_halt(struct tg3 *, int, int);
5439
5440 /* Restart hardware after configuration changes, self-test, etc.
5441 * Invoked with tp->lock held.
5442 */
5443 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5444 __releases(tp->lock)
5445 __acquires(tp->lock)
5446 {
5447 int err;
5448
5449 err = tg3_init_hw(tp, reset_phy);
5450 if (err) {
5451 netdev_err(tp->dev,
5452 "Failed to re-initialize device, aborting\n");
5453 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5454 tg3_full_unlock(tp);
5455 del_timer_sync(&tp->timer);
5456 tp->irq_sync = 0;
5457 tg3_napi_enable(tp);
5458 dev_close(tp->dev);
5459 tg3_full_lock(tp, 0);
5460 }
5461 return err;
5462 }
5463
5464 #ifdef CONFIG_NET_POLL_CONTROLLER
5465 static void tg3_poll_controller(struct net_device *dev)
5466 {
5467 int i;
5468 struct tg3 *tp = netdev_priv(dev);
5469
5470 for (i = 0; i < tp->irq_cnt; i++)
5471 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5472 }
5473 #endif
5474
5475 static void tg3_reset_task(struct work_struct *work)
5476 {
5477 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5478 int err;
5479 unsigned int restart_timer;
5480
5481 tg3_full_lock(tp, 0);
5482
5483 if (!netif_running(tp->dev)) {
5484 tg3_full_unlock(tp);
5485 return;
5486 }
5487
5488 tg3_full_unlock(tp);
5489
5490 tg3_phy_stop(tp);
5491
5492 tg3_netif_stop(tp);
5493
5494 tg3_full_lock(tp, 1);
5495
5496 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5497 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5498
5499 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5500 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5501 tp->write32_rx_mbox = tg3_write_flush_reg32;
5502 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5503 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5504 }
5505
5506 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5507 err = tg3_init_hw(tp, 1);
5508 if (err)
5509 goto out;
5510
5511 tg3_netif_start(tp);
5512
5513 if (restart_timer)
5514 mod_timer(&tp->timer, jiffies + 1);
5515
5516 out:
5517 tg3_full_unlock(tp);
5518
5519 if (!err)
5520 tg3_phy_start(tp);
5521 }
5522
5523 static void tg3_dump_short_state(struct tg3 *tp)
5524 {
5525 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5526 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5527 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5528 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5529 }
5530
5531 static void tg3_tx_timeout(struct net_device *dev)
5532 {
5533 struct tg3 *tp = netdev_priv(dev);
5534
5535 if (netif_msg_tx_err(tp)) {
5536 netdev_err(dev, "transmit timed out, resetting\n");
5537 tg3_dump_short_state(tp);
5538 }
5539
5540 schedule_work(&tp->reset_task);
5541 }
5542
5543 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5544 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5545 {
5546 u32 base = (u32) mapping & 0xffffffff;
5547
5548 return (base > 0xffffdcc0) && (base + len + 8 < base);
5549 }
5550
5551 /* Test for DMA addresses > 40-bit */
5552 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5553 int len)
5554 {
5555 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5556 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5557 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5558 return 0;
5559 #else
5560 return 0;
5561 #endif
5562 }
5563
5564 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5565
5566 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5567 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5568 struct sk_buff *skb, u32 last_plus_one,
5569 u32 *start, u32 base_flags, u32 mss)
5570 {
5571 struct tg3 *tp = tnapi->tp;
5572 struct sk_buff *new_skb;
5573 dma_addr_t new_addr = 0;
5574 u32 entry = *start;
5575 int i, ret = 0;
5576
5577 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5578 new_skb = skb_copy(skb, GFP_ATOMIC);
5579 else {
5580 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5581
5582 new_skb = skb_copy_expand(skb,
5583 skb_headroom(skb) + more_headroom,
5584 skb_tailroom(skb), GFP_ATOMIC);
5585 }
5586
5587 if (!new_skb) {
5588 ret = -1;
5589 } else {
5590 /* New SKB is guaranteed to be linear. */
5591 entry = *start;
5592 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5593 PCI_DMA_TODEVICE);
5594 /* Make sure the mapping succeeded */
5595 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5596 ret = -1;
5597 dev_kfree_skb(new_skb);
5598 new_skb = NULL;
5599
5600 /* Make sure new skb does not cross any 4G boundaries.
5601 * Drop the packet if it does.
5602 */
5603 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5604 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5605 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5606 PCI_DMA_TODEVICE);
5607 ret = -1;
5608 dev_kfree_skb(new_skb);
5609 new_skb = NULL;
5610 } else {
5611 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5612 base_flags, 1 | (mss << 1));
5613 *start = NEXT_TX(entry);
5614 }
5615 }
5616
5617 /* Now clean up the sw ring entries. */
5618 i = 0;
5619 while (entry != last_plus_one) {
5620 int len;
5621
5622 if (i == 0)
5623 len = skb_headlen(skb);
5624 else
5625 len = skb_shinfo(skb)->frags[i-1].size;
5626
5627 pci_unmap_single(tp->pdev,
5628 dma_unmap_addr(&tnapi->tx_buffers[entry],
5629 mapping),
5630 len, PCI_DMA_TODEVICE);
5631 if (i == 0) {
5632 tnapi->tx_buffers[entry].skb = new_skb;
5633 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5634 new_addr);
5635 } else {
5636 tnapi->tx_buffers[entry].skb = NULL;
5637 }
5638 entry = NEXT_TX(entry);
5639 i++;
5640 }
5641
5642 dev_kfree_skb(skb);
5643
5644 return ret;
5645 }
5646
5647 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5648 dma_addr_t mapping, int len, u32 flags,
5649 u32 mss_and_is_end)
5650 {
5651 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5652 int is_end = (mss_and_is_end & 0x1);
5653 u32 mss = (mss_and_is_end >> 1);
5654 u32 vlan_tag = 0;
5655
5656 if (is_end)
5657 flags |= TXD_FLAG_END;
5658 if (flags & TXD_FLAG_VLAN) {
5659 vlan_tag = flags >> 16;
5660 flags &= 0xffff;
5661 }
5662 vlan_tag |= (mss << TXD_MSS_SHIFT);
5663
5664 txd->addr_hi = ((u64) mapping >> 32);
5665 txd->addr_lo = ((u64) mapping & 0xffffffff);
5666 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5667 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5668 }
5669
5670 /* hard_start_xmit for devices that don't have any bugs and
5671 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5672 */
5673 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5674 struct net_device *dev)
5675 {
5676 struct tg3 *tp = netdev_priv(dev);
5677 u32 len, entry, base_flags, mss;
5678 dma_addr_t mapping;
5679 struct tg3_napi *tnapi;
5680 struct netdev_queue *txq;
5681 unsigned int i, last;
5682
5683 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5684 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5685 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5686 tnapi++;
5687
5688 /* We are running in BH disabled context with netif_tx_lock
5689 * and TX reclaim runs via tp->napi.poll inside of a software
5690 * interrupt. Furthermore, IRQ processing runs lockless so we have
5691 * no IRQ context deadlocks to worry about either. Rejoice!
5692 */
5693 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5694 if (!netif_tx_queue_stopped(txq)) {
5695 netif_tx_stop_queue(txq);
5696
5697 /* This is a hard error, log it. */
5698 netdev_err(dev,
5699 "BUG! Tx Ring full when queue awake!\n");
5700 }
5701 return NETDEV_TX_BUSY;
5702 }
5703
5704 entry = tnapi->tx_prod;
5705 base_flags = 0;
5706 mss = skb_shinfo(skb)->gso_size;
5707 if (mss) {
5708 int tcp_opt_len, ip_tcp_len;
5709 u32 hdrlen;
5710
5711 if (skb_header_cloned(skb) &&
5712 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5713 dev_kfree_skb(skb);
5714 goto out_unlock;
5715 }
5716
5717 if (skb_is_gso_v6(skb)) {
5718 hdrlen = skb_headlen(skb) - ETH_HLEN;
5719 } else {
5720 struct iphdr *iph = ip_hdr(skb);
5721
5722 tcp_opt_len = tcp_optlen(skb);
5723 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5724
5725 iph->check = 0;
5726 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5727 hdrlen = ip_tcp_len + tcp_opt_len;
5728 }
5729
5730 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5731 mss |= (hdrlen & 0xc) << 12;
5732 if (hdrlen & 0x10)
5733 base_flags |= 0x00000010;
5734 base_flags |= (hdrlen & 0x3e0) << 5;
5735 } else
5736 mss |= hdrlen << 9;
5737
5738 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5739 TXD_FLAG_CPU_POST_DMA);
5740
5741 tcp_hdr(skb)->check = 0;
5742
5743 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5744 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5745 }
5746
5747 #if TG3_VLAN_TAG_USED
5748 if (vlan_tx_tag_present(skb))
5749 base_flags |= (TXD_FLAG_VLAN |
5750 (vlan_tx_tag_get(skb) << 16));
5751 #endif
5752
5753 len = skb_headlen(skb);
5754
5755 /* Queue skb data, a.k.a. the main skb fragment. */
5756 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5757 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5758 dev_kfree_skb(skb);
5759 goto out_unlock;
5760 }
5761
5762 tnapi->tx_buffers[entry].skb = skb;
5763 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5764
5765 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5766 !mss && skb->len > ETH_DATA_LEN)
5767 base_flags |= TXD_FLAG_JMB_PKT;
5768
5769 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5770 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5771
5772 entry = NEXT_TX(entry);
5773
5774 /* Now loop through additional data fragments, and queue them. */
5775 if (skb_shinfo(skb)->nr_frags > 0) {
5776 last = skb_shinfo(skb)->nr_frags - 1;
5777 for (i = 0; i <= last; i++) {
5778 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5779
5780 len = frag->size;
5781 mapping = pci_map_page(tp->pdev,
5782 frag->page,
5783 frag->page_offset,
5784 len, PCI_DMA_TODEVICE);
5785 if (pci_dma_mapping_error(tp->pdev, mapping))
5786 goto dma_error;
5787
5788 tnapi->tx_buffers[entry].skb = NULL;
5789 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5790 mapping);
5791
5792 tg3_set_txd(tnapi, entry, mapping, len,
5793 base_flags, (i == last) | (mss << 1));
5794
5795 entry = NEXT_TX(entry);
5796 }
5797 }
5798
5799 /* Packets are ready, update Tx producer idx local and on card. */
5800 tw32_tx_mbox(tnapi->prodmbox, entry);
5801
5802 tnapi->tx_prod = entry;
5803 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5804 netif_tx_stop_queue(txq);
5805
5806 /* netif_tx_stop_queue() must be done before checking
5807 * checking tx index in tg3_tx_avail() below, because in
5808 * tg3_tx(), we update tx index before checking for
5809 * netif_tx_queue_stopped().
5810 */
5811 smp_mb();
5812 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5813 netif_tx_wake_queue(txq);
5814 }
5815
5816 out_unlock:
5817 mmiowb();
5818
5819 return NETDEV_TX_OK;
5820
5821 dma_error:
5822 last = i;
5823 entry = tnapi->tx_prod;
5824 tnapi->tx_buffers[entry].skb = NULL;
5825 pci_unmap_single(tp->pdev,
5826 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5827 skb_headlen(skb),
5828 PCI_DMA_TODEVICE);
5829 for (i = 0; i <= last; i++) {
5830 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5831 entry = NEXT_TX(entry);
5832
5833 pci_unmap_page(tp->pdev,
5834 dma_unmap_addr(&tnapi->tx_buffers[entry],
5835 mapping),
5836 frag->size, PCI_DMA_TODEVICE);
5837 }
5838
5839 dev_kfree_skb(skb);
5840 return NETDEV_TX_OK;
5841 }
5842
5843 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5844 struct net_device *);
5845
5846 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5847 * TSO header is greater than 80 bytes.
5848 */
5849 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5850 {
5851 struct sk_buff *segs, *nskb;
5852 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5853
5854 /* Estimate the number of fragments in the worst case */
5855 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5856 netif_stop_queue(tp->dev);
5857
5858 /* netif_tx_stop_queue() must be done before checking
5859 * checking tx index in tg3_tx_avail() below, because in
5860 * tg3_tx(), we update tx index before checking for
5861 * netif_tx_queue_stopped().
5862 */
5863 smp_mb();
5864 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5865 return NETDEV_TX_BUSY;
5866
5867 netif_wake_queue(tp->dev);
5868 }
5869
5870 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5871 if (IS_ERR(segs))
5872 goto tg3_tso_bug_end;
5873
5874 do {
5875 nskb = segs;
5876 segs = segs->next;
5877 nskb->next = NULL;
5878 tg3_start_xmit_dma_bug(nskb, tp->dev);
5879 } while (segs);
5880
5881 tg3_tso_bug_end:
5882 dev_kfree_skb(skb);
5883
5884 return NETDEV_TX_OK;
5885 }
5886
5887 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5888 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5889 */
5890 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5891 struct net_device *dev)
5892 {
5893 struct tg3 *tp = netdev_priv(dev);
5894 u32 len, entry, base_flags, mss;
5895 int would_hit_hwbug;
5896 dma_addr_t mapping;
5897 struct tg3_napi *tnapi;
5898 struct netdev_queue *txq;
5899 unsigned int i, last;
5900
5901 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5902 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5903 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5904 tnapi++;
5905
5906 /* We are running in BH disabled context with netif_tx_lock
5907 * and TX reclaim runs via tp->napi.poll inside of a software
5908 * interrupt. Furthermore, IRQ processing runs lockless so we have
5909 * no IRQ context deadlocks to worry about either. Rejoice!
5910 */
5911 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5912 if (!netif_tx_queue_stopped(txq)) {
5913 netif_tx_stop_queue(txq);
5914
5915 /* This is a hard error, log it. */
5916 netdev_err(dev,
5917 "BUG! Tx Ring full when queue awake!\n");
5918 }
5919 return NETDEV_TX_BUSY;
5920 }
5921
5922 entry = tnapi->tx_prod;
5923 base_flags = 0;
5924 if (skb->ip_summed == CHECKSUM_PARTIAL)
5925 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5926
5927 mss = skb_shinfo(skb)->gso_size;
5928 if (mss) {
5929 struct iphdr *iph;
5930 u32 tcp_opt_len, hdr_len;
5931
5932 if (skb_header_cloned(skb) &&
5933 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5934 dev_kfree_skb(skb);
5935 goto out_unlock;
5936 }
5937
5938 iph = ip_hdr(skb);
5939 tcp_opt_len = tcp_optlen(skb);
5940
5941 if (skb_is_gso_v6(skb)) {
5942 hdr_len = skb_headlen(skb) - ETH_HLEN;
5943 } else {
5944 u32 ip_tcp_len;
5945
5946 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5947 hdr_len = ip_tcp_len + tcp_opt_len;
5948
5949 iph->check = 0;
5950 iph->tot_len = htons(mss + hdr_len);
5951 }
5952
5953 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5954 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5955 return tg3_tso_bug(tp, skb);
5956
5957 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5958 TXD_FLAG_CPU_POST_DMA);
5959
5960 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5961 tcp_hdr(skb)->check = 0;
5962 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5963 } else
5964 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5965 iph->daddr, 0,
5966 IPPROTO_TCP,
5967 0);
5968
5969 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5970 mss |= (hdr_len & 0xc) << 12;
5971 if (hdr_len & 0x10)
5972 base_flags |= 0x00000010;
5973 base_flags |= (hdr_len & 0x3e0) << 5;
5974 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5975 mss |= hdr_len << 9;
5976 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5978 if (tcp_opt_len || iph->ihl > 5) {
5979 int tsflags;
5980
5981 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5982 mss |= (tsflags << 11);
5983 }
5984 } else {
5985 if (tcp_opt_len || iph->ihl > 5) {
5986 int tsflags;
5987
5988 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5989 base_flags |= tsflags << 12;
5990 }
5991 }
5992 }
5993 #if TG3_VLAN_TAG_USED
5994 if (vlan_tx_tag_present(skb))
5995 base_flags |= (TXD_FLAG_VLAN |
5996 (vlan_tx_tag_get(skb) << 16));
5997 #endif
5998
5999 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
6000 !mss && skb->len > ETH_DATA_LEN)
6001 base_flags |= TXD_FLAG_JMB_PKT;
6002
6003 len = skb_headlen(skb);
6004
6005 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6006 if (pci_dma_mapping_error(tp->pdev, mapping)) {
6007 dev_kfree_skb(skb);
6008 goto out_unlock;
6009 }
6010
6011 tnapi->tx_buffers[entry].skb = skb;
6012 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6013
6014 would_hit_hwbug = 0;
6015
6016 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6017 would_hit_hwbug = 1;
6018
6019 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6020 tg3_4g_overflow_test(mapping, len))
6021 would_hit_hwbug = 1;
6022
6023 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6024 tg3_40bit_overflow_test(tp, mapping, len))
6025 would_hit_hwbug = 1;
6026
6027 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6028 would_hit_hwbug = 1;
6029
6030 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6031 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6032
6033 entry = NEXT_TX(entry);
6034
6035 /* Now loop through additional data fragments, and queue them. */
6036 if (skb_shinfo(skb)->nr_frags > 0) {
6037 last = skb_shinfo(skb)->nr_frags - 1;
6038 for (i = 0; i <= last; i++) {
6039 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6040
6041 len = frag->size;
6042 mapping = pci_map_page(tp->pdev,
6043 frag->page,
6044 frag->page_offset,
6045 len, PCI_DMA_TODEVICE);
6046
6047 tnapi->tx_buffers[entry].skb = NULL;
6048 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6049 mapping);
6050 if (pci_dma_mapping_error(tp->pdev, mapping))
6051 goto dma_error;
6052
6053 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6054 len <= 8)
6055 would_hit_hwbug = 1;
6056
6057 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6058 tg3_4g_overflow_test(mapping, len))
6059 would_hit_hwbug = 1;
6060
6061 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6062 tg3_40bit_overflow_test(tp, mapping, len))
6063 would_hit_hwbug = 1;
6064
6065 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6066 tg3_set_txd(tnapi, entry, mapping, len,
6067 base_flags, (i == last)|(mss << 1));
6068 else
6069 tg3_set_txd(tnapi, entry, mapping, len,
6070 base_flags, (i == last));
6071
6072 entry = NEXT_TX(entry);
6073 }
6074 }
6075
6076 if (would_hit_hwbug) {
6077 u32 last_plus_one = entry;
6078 u32 start;
6079
6080 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6081 start &= (TG3_TX_RING_SIZE - 1);
6082
6083 /* If the workaround fails due to memory/mapping
6084 * failure, silently drop this packet.
6085 */
6086 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6087 &start, base_flags, mss))
6088 goto out_unlock;
6089
6090 entry = start;
6091 }
6092
6093 /* Packets are ready, update Tx producer idx local and on card. */
6094 tw32_tx_mbox(tnapi->prodmbox, entry);
6095
6096 tnapi->tx_prod = entry;
6097 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6098 netif_tx_stop_queue(txq);
6099
6100 /* netif_tx_stop_queue() must be done before checking
6101 * checking tx index in tg3_tx_avail() below, because in
6102 * tg3_tx(), we update tx index before checking for
6103 * netif_tx_queue_stopped().
6104 */
6105 smp_mb();
6106 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6107 netif_tx_wake_queue(txq);
6108 }
6109
6110 out_unlock:
6111 mmiowb();
6112
6113 return NETDEV_TX_OK;
6114
6115 dma_error:
6116 last = i;
6117 entry = tnapi->tx_prod;
6118 tnapi->tx_buffers[entry].skb = NULL;
6119 pci_unmap_single(tp->pdev,
6120 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6121 skb_headlen(skb),
6122 PCI_DMA_TODEVICE);
6123 for (i = 0; i <= last; i++) {
6124 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6125 entry = NEXT_TX(entry);
6126
6127 pci_unmap_page(tp->pdev,
6128 dma_unmap_addr(&tnapi->tx_buffers[entry],
6129 mapping),
6130 frag->size, PCI_DMA_TODEVICE);
6131 }
6132
6133 dev_kfree_skb(skb);
6134 return NETDEV_TX_OK;
6135 }
6136
6137 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6138 int new_mtu)
6139 {
6140 dev->mtu = new_mtu;
6141
6142 if (new_mtu > ETH_DATA_LEN) {
6143 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6144 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6145 ethtool_op_set_tso(dev, 0);
6146 } else {
6147 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6148 }
6149 } else {
6150 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6151 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6152 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6153 }
6154 }
6155
6156 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6157 {
6158 struct tg3 *tp = netdev_priv(dev);
6159 int err;
6160
6161 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6162 return -EINVAL;
6163
6164 if (!netif_running(dev)) {
6165 /* We'll just catch it later when the
6166 * device is up'd.
6167 */
6168 tg3_set_mtu(dev, tp, new_mtu);
6169 return 0;
6170 }
6171
6172 tg3_phy_stop(tp);
6173
6174 tg3_netif_stop(tp);
6175
6176 tg3_full_lock(tp, 1);
6177
6178 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6179
6180 tg3_set_mtu(dev, tp, new_mtu);
6181
6182 err = tg3_restart_hw(tp, 0);
6183
6184 if (!err)
6185 tg3_netif_start(tp);
6186
6187 tg3_full_unlock(tp);
6188
6189 if (!err)
6190 tg3_phy_start(tp);
6191
6192 return err;
6193 }
6194
6195 static void tg3_rx_prodring_free(struct tg3 *tp,
6196 struct tg3_rx_prodring_set *tpr)
6197 {
6198 int i;
6199
6200 if (tpr != &tp->napi[0].prodring) {
6201 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6202 i = (i + 1) & tp->rx_std_ring_mask)
6203 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6204 tp->rx_pkt_map_sz);
6205
6206 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6207 for (i = tpr->rx_jmb_cons_idx;
6208 i != tpr->rx_jmb_prod_idx;
6209 i = (i + 1) & tp->rx_jmb_ring_mask) {
6210 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6211 TG3_RX_JMB_MAP_SZ);
6212 }
6213 }
6214
6215 return;
6216 }
6217
6218 for (i = 0; i <= tp->rx_std_ring_mask; i++)
6219 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6220 tp->rx_pkt_map_sz);
6221
6222 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6223 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6224 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6225 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6226 TG3_RX_JMB_MAP_SZ);
6227 }
6228 }
6229
6230 /* Initialize rx rings for packet processing.
6231 *
6232 * The chip has been shut down and the driver detached from
6233 * the networking, so no interrupts or new tx packets will
6234 * end up in the driver. tp->{tx,}lock are held and thus
6235 * we may not sleep.
6236 */
6237 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6238 struct tg3_rx_prodring_set *tpr)
6239 {
6240 u32 i, rx_pkt_dma_sz;
6241
6242 tpr->rx_std_cons_idx = 0;
6243 tpr->rx_std_prod_idx = 0;
6244 tpr->rx_jmb_cons_idx = 0;
6245 tpr->rx_jmb_prod_idx = 0;
6246
6247 if (tpr != &tp->napi[0].prodring) {
6248 memset(&tpr->rx_std_buffers[0], 0,
6249 TG3_RX_STD_BUFF_RING_SIZE(tp));
6250 if (tpr->rx_jmb_buffers)
6251 memset(&tpr->rx_jmb_buffers[0], 0,
6252 TG3_RX_JMB_BUFF_RING_SIZE(tp));
6253 goto done;
6254 }
6255
6256 /* Zero out all descriptors. */
6257 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6258
6259 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6260 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6261 tp->dev->mtu > ETH_DATA_LEN)
6262 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6263 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6264
6265 /* Initialize invariants of the rings, we only set this
6266 * stuff once. This works because the card does not
6267 * write into the rx buffer posting rings.
6268 */
6269 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6270 struct tg3_rx_buffer_desc *rxd;
6271
6272 rxd = &tpr->rx_std[i];
6273 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6274 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6275 rxd->opaque = (RXD_OPAQUE_RING_STD |
6276 (i << RXD_OPAQUE_INDEX_SHIFT));
6277 }
6278
6279 /* Now allocate fresh SKBs for each rx ring. */
6280 for (i = 0; i < tp->rx_pending; i++) {
6281 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6282 netdev_warn(tp->dev,
6283 "Using a smaller RX standard ring. Only "
6284 "%d out of %d buffers were allocated "
6285 "successfully\n", i, tp->rx_pending);
6286 if (i == 0)
6287 goto initfail;
6288 tp->rx_pending = i;
6289 break;
6290 }
6291 }
6292
6293 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6294 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6295 goto done;
6296
6297 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6298
6299 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6300 goto done;
6301
6302 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6303 struct tg3_rx_buffer_desc *rxd;
6304
6305 rxd = &tpr->rx_jmb[i].std;
6306 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6307 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6308 RXD_FLAG_JUMBO;
6309 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6310 (i << RXD_OPAQUE_INDEX_SHIFT));
6311 }
6312
6313 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6314 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6315 netdev_warn(tp->dev,
6316 "Using a smaller RX jumbo ring. Only %d "
6317 "out of %d buffers were allocated "
6318 "successfully\n", i, tp->rx_jumbo_pending);
6319 if (i == 0)
6320 goto initfail;
6321 tp->rx_jumbo_pending = i;
6322 break;
6323 }
6324 }
6325
6326 done:
6327 return 0;
6328
6329 initfail:
6330 tg3_rx_prodring_free(tp, tpr);
6331 return -ENOMEM;
6332 }
6333
6334 static void tg3_rx_prodring_fini(struct tg3 *tp,
6335 struct tg3_rx_prodring_set *tpr)
6336 {
6337 kfree(tpr->rx_std_buffers);
6338 tpr->rx_std_buffers = NULL;
6339 kfree(tpr->rx_jmb_buffers);
6340 tpr->rx_jmb_buffers = NULL;
6341 if (tpr->rx_std) {
6342 pci_free_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6343 tpr->rx_std, tpr->rx_std_mapping);
6344 tpr->rx_std = NULL;
6345 }
6346 if (tpr->rx_jmb) {
6347 pci_free_consistent(tp->pdev, TG3_RX_JMB_RING_BYTES(tp),
6348 tpr->rx_jmb, tpr->rx_jmb_mapping);
6349 tpr->rx_jmb = NULL;
6350 }
6351 }
6352
6353 static int tg3_rx_prodring_init(struct tg3 *tp,
6354 struct tg3_rx_prodring_set *tpr)
6355 {
6356 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6357 GFP_KERNEL);
6358 if (!tpr->rx_std_buffers)
6359 return -ENOMEM;
6360
6361 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6362 &tpr->rx_std_mapping);
6363 if (!tpr->rx_std)
6364 goto err_out;
6365
6366 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6367 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6368 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6369 GFP_KERNEL);
6370 if (!tpr->rx_jmb_buffers)
6371 goto err_out;
6372
6373 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6374 TG3_RX_JMB_RING_BYTES(tp),
6375 &tpr->rx_jmb_mapping);
6376 if (!tpr->rx_jmb)
6377 goto err_out;
6378 }
6379
6380 return 0;
6381
6382 err_out:
6383 tg3_rx_prodring_fini(tp, tpr);
6384 return -ENOMEM;
6385 }
6386
6387 /* Free up pending packets in all rx/tx rings.
6388 *
6389 * The chip has been shut down and the driver detached from
6390 * the networking, so no interrupts or new tx packets will
6391 * end up in the driver. tp->{tx,}lock is not held and we are not
6392 * in an interrupt context and thus may sleep.
6393 */
6394 static void tg3_free_rings(struct tg3 *tp)
6395 {
6396 int i, j;
6397
6398 for (j = 0; j < tp->irq_cnt; j++) {
6399 struct tg3_napi *tnapi = &tp->napi[j];
6400
6401 tg3_rx_prodring_free(tp, &tnapi->prodring);
6402
6403 if (!tnapi->tx_buffers)
6404 continue;
6405
6406 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6407 struct ring_info *txp;
6408 struct sk_buff *skb;
6409 unsigned int k;
6410
6411 txp = &tnapi->tx_buffers[i];
6412 skb = txp->skb;
6413
6414 if (skb == NULL) {
6415 i++;
6416 continue;
6417 }
6418
6419 pci_unmap_single(tp->pdev,
6420 dma_unmap_addr(txp, mapping),
6421 skb_headlen(skb),
6422 PCI_DMA_TODEVICE);
6423 txp->skb = NULL;
6424
6425 i++;
6426
6427 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6428 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6429 pci_unmap_page(tp->pdev,
6430 dma_unmap_addr(txp, mapping),
6431 skb_shinfo(skb)->frags[k].size,
6432 PCI_DMA_TODEVICE);
6433 i++;
6434 }
6435
6436 dev_kfree_skb_any(skb);
6437 }
6438 }
6439 }
6440
6441 /* Initialize tx/rx rings for packet processing.
6442 *
6443 * The chip has been shut down and the driver detached from
6444 * the networking, so no interrupts or new tx packets will
6445 * end up in the driver. tp->{tx,}lock are held and thus
6446 * we may not sleep.
6447 */
6448 static int tg3_init_rings(struct tg3 *tp)
6449 {
6450 int i;
6451
6452 /* Free up all the SKBs. */
6453 tg3_free_rings(tp);
6454
6455 for (i = 0; i < tp->irq_cnt; i++) {
6456 struct tg3_napi *tnapi = &tp->napi[i];
6457
6458 tnapi->last_tag = 0;
6459 tnapi->last_irq_tag = 0;
6460 tnapi->hw_status->status = 0;
6461 tnapi->hw_status->status_tag = 0;
6462 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6463
6464 tnapi->tx_prod = 0;
6465 tnapi->tx_cons = 0;
6466 if (tnapi->tx_ring)
6467 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6468
6469 tnapi->rx_rcb_ptr = 0;
6470 if (tnapi->rx_rcb)
6471 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6472
6473 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6474 tg3_free_rings(tp);
6475 return -ENOMEM;
6476 }
6477 }
6478
6479 return 0;
6480 }
6481
6482 /*
6483 * Must not be invoked with interrupt sources disabled and
6484 * the hardware shutdown down.
6485 */
6486 static void tg3_free_consistent(struct tg3 *tp)
6487 {
6488 int i;
6489
6490 for (i = 0; i < tp->irq_cnt; i++) {
6491 struct tg3_napi *tnapi = &tp->napi[i];
6492
6493 if (tnapi->tx_ring) {
6494 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6495 tnapi->tx_ring, tnapi->tx_desc_mapping);
6496 tnapi->tx_ring = NULL;
6497 }
6498
6499 kfree(tnapi->tx_buffers);
6500 tnapi->tx_buffers = NULL;
6501
6502 if (tnapi->rx_rcb) {
6503 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6504 tnapi->rx_rcb,
6505 tnapi->rx_rcb_mapping);
6506 tnapi->rx_rcb = NULL;
6507 }
6508
6509 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6510
6511 if (tnapi->hw_status) {
6512 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6513 tnapi->hw_status,
6514 tnapi->status_mapping);
6515 tnapi->hw_status = NULL;
6516 }
6517 }
6518
6519 if (tp->hw_stats) {
6520 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6521 tp->hw_stats, tp->stats_mapping);
6522 tp->hw_stats = NULL;
6523 }
6524 }
6525
6526 /*
6527 * Must not be invoked with interrupt sources disabled and
6528 * the hardware shutdown down. Can sleep.
6529 */
6530 static int tg3_alloc_consistent(struct tg3 *tp)
6531 {
6532 int i;
6533
6534 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6535 sizeof(struct tg3_hw_stats),
6536 &tp->stats_mapping);
6537 if (!tp->hw_stats)
6538 goto err_out;
6539
6540 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6541
6542 for (i = 0; i < tp->irq_cnt; i++) {
6543 struct tg3_napi *tnapi = &tp->napi[i];
6544 struct tg3_hw_status *sblk;
6545
6546 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6547 TG3_HW_STATUS_SIZE,
6548 &tnapi->status_mapping);
6549 if (!tnapi->hw_status)
6550 goto err_out;
6551
6552 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6553 sblk = tnapi->hw_status;
6554
6555 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6556 goto err_out;
6557
6558 /* If multivector TSS is enabled, vector 0 does not handle
6559 * tx interrupts. Don't allocate any resources for it.
6560 */
6561 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6562 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6563 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6564 TG3_TX_RING_SIZE,
6565 GFP_KERNEL);
6566 if (!tnapi->tx_buffers)
6567 goto err_out;
6568
6569 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6570 TG3_TX_RING_BYTES,
6571 &tnapi->tx_desc_mapping);
6572 if (!tnapi->tx_ring)
6573 goto err_out;
6574 }
6575
6576 /*
6577 * When RSS is enabled, the status block format changes
6578 * slightly. The "rx_jumbo_consumer", "reserved",
6579 * and "rx_mini_consumer" members get mapped to the
6580 * other three rx return ring producer indexes.
6581 */
6582 switch (i) {
6583 default:
6584 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6585 break;
6586 case 2:
6587 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6588 break;
6589 case 3:
6590 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6591 break;
6592 case 4:
6593 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6594 break;
6595 }
6596
6597 /*
6598 * If multivector RSS is enabled, vector 0 does not handle
6599 * rx or tx interrupts. Don't allocate any resources for it.
6600 */
6601 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6602 continue;
6603
6604 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6605 TG3_RX_RCB_RING_BYTES(tp),
6606 &tnapi->rx_rcb_mapping);
6607 if (!tnapi->rx_rcb)
6608 goto err_out;
6609
6610 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6611 }
6612
6613 return 0;
6614
6615 err_out:
6616 tg3_free_consistent(tp);
6617 return -ENOMEM;
6618 }
6619
6620 #define MAX_WAIT_CNT 1000
6621
6622 /* To stop a block, clear the enable bit and poll till it
6623 * clears. tp->lock is held.
6624 */
6625 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6626 {
6627 unsigned int i;
6628 u32 val;
6629
6630 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6631 switch (ofs) {
6632 case RCVLSC_MODE:
6633 case DMAC_MODE:
6634 case MBFREE_MODE:
6635 case BUFMGR_MODE:
6636 case MEMARB_MODE:
6637 /* We can't enable/disable these bits of the
6638 * 5705/5750, just say success.
6639 */
6640 return 0;
6641
6642 default:
6643 break;
6644 }
6645 }
6646
6647 val = tr32(ofs);
6648 val &= ~enable_bit;
6649 tw32_f(ofs, val);
6650
6651 for (i = 0; i < MAX_WAIT_CNT; i++) {
6652 udelay(100);
6653 val = tr32(ofs);
6654 if ((val & enable_bit) == 0)
6655 break;
6656 }
6657
6658 if (i == MAX_WAIT_CNT && !silent) {
6659 dev_err(&tp->pdev->dev,
6660 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6661 ofs, enable_bit);
6662 return -ENODEV;
6663 }
6664
6665 return 0;
6666 }
6667
6668 /* tp->lock is held. */
6669 static int tg3_abort_hw(struct tg3 *tp, int silent)
6670 {
6671 int i, err;
6672
6673 tg3_disable_ints(tp);
6674
6675 tp->rx_mode &= ~RX_MODE_ENABLE;
6676 tw32_f(MAC_RX_MODE, tp->rx_mode);
6677 udelay(10);
6678
6679 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6680 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6681 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6682 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6683 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6684 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6685
6686 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6687 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6688 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6689 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6690 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6691 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6692 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6693
6694 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6695 tw32_f(MAC_MODE, tp->mac_mode);
6696 udelay(40);
6697
6698 tp->tx_mode &= ~TX_MODE_ENABLE;
6699 tw32_f(MAC_TX_MODE, tp->tx_mode);
6700
6701 for (i = 0; i < MAX_WAIT_CNT; i++) {
6702 udelay(100);
6703 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6704 break;
6705 }
6706 if (i >= MAX_WAIT_CNT) {
6707 dev_err(&tp->pdev->dev,
6708 "%s timed out, TX_MODE_ENABLE will not clear "
6709 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6710 err |= -ENODEV;
6711 }
6712
6713 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6714 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6715 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6716
6717 tw32(FTQ_RESET, 0xffffffff);
6718 tw32(FTQ_RESET, 0x00000000);
6719
6720 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6721 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6722
6723 for (i = 0; i < tp->irq_cnt; i++) {
6724 struct tg3_napi *tnapi = &tp->napi[i];
6725 if (tnapi->hw_status)
6726 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6727 }
6728 if (tp->hw_stats)
6729 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6730
6731 return err;
6732 }
6733
6734 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6735 {
6736 int i;
6737 u32 apedata;
6738
6739 /* NCSI does not support APE events */
6740 if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6741 return;
6742
6743 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6744 if (apedata != APE_SEG_SIG_MAGIC)
6745 return;
6746
6747 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6748 if (!(apedata & APE_FW_STATUS_READY))
6749 return;
6750
6751 /* Wait for up to 1 millisecond for APE to service previous event. */
6752 for (i = 0; i < 10; i++) {
6753 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6754 return;
6755
6756 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6757
6758 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6759 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6760 event | APE_EVENT_STATUS_EVENT_PENDING);
6761
6762 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6763
6764 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6765 break;
6766
6767 udelay(100);
6768 }
6769
6770 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6771 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6772 }
6773
6774 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6775 {
6776 u32 event;
6777 u32 apedata;
6778
6779 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6780 return;
6781
6782 switch (kind) {
6783 case RESET_KIND_INIT:
6784 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6785 APE_HOST_SEG_SIG_MAGIC);
6786 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6787 APE_HOST_SEG_LEN_MAGIC);
6788 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6789 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6790 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6791 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6792 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6793 APE_HOST_BEHAV_NO_PHYLOCK);
6794 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6795 TG3_APE_HOST_DRVR_STATE_START);
6796
6797 event = APE_EVENT_STATUS_STATE_START;
6798 break;
6799 case RESET_KIND_SHUTDOWN:
6800 /* With the interface we are currently using,
6801 * APE does not track driver state. Wiping
6802 * out the HOST SEGMENT SIGNATURE forces
6803 * the APE to assume OS absent status.
6804 */
6805 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6806
6807 if (device_may_wakeup(&tp->pdev->dev) &&
6808 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6809 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6810 TG3_APE_HOST_WOL_SPEED_AUTO);
6811 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6812 } else
6813 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6814
6815 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6816
6817 event = APE_EVENT_STATUS_STATE_UNLOAD;
6818 break;
6819 case RESET_KIND_SUSPEND:
6820 event = APE_EVENT_STATUS_STATE_SUSPEND;
6821 break;
6822 default:
6823 return;
6824 }
6825
6826 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6827
6828 tg3_ape_send_event(tp, event);
6829 }
6830
6831 /* tp->lock is held. */
6832 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6833 {
6834 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6835 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6836
6837 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6838 switch (kind) {
6839 case RESET_KIND_INIT:
6840 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6841 DRV_STATE_START);
6842 break;
6843
6844 case RESET_KIND_SHUTDOWN:
6845 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6846 DRV_STATE_UNLOAD);
6847 break;
6848
6849 case RESET_KIND_SUSPEND:
6850 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6851 DRV_STATE_SUSPEND);
6852 break;
6853
6854 default:
6855 break;
6856 }
6857 }
6858
6859 if (kind == RESET_KIND_INIT ||
6860 kind == RESET_KIND_SUSPEND)
6861 tg3_ape_driver_state_change(tp, kind);
6862 }
6863
6864 /* tp->lock is held. */
6865 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6866 {
6867 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6868 switch (kind) {
6869 case RESET_KIND_INIT:
6870 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6871 DRV_STATE_START_DONE);
6872 break;
6873
6874 case RESET_KIND_SHUTDOWN:
6875 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6876 DRV_STATE_UNLOAD_DONE);
6877 break;
6878
6879 default:
6880 break;
6881 }
6882 }
6883
6884 if (kind == RESET_KIND_SHUTDOWN)
6885 tg3_ape_driver_state_change(tp, kind);
6886 }
6887
6888 /* tp->lock is held. */
6889 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6890 {
6891 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6892 switch (kind) {
6893 case RESET_KIND_INIT:
6894 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6895 DRV_STATE_START);
6896 break;
6897
6898 case RESET_KIND_SHUTDOWN:
6899 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6900 DRV_STATE_UNLOAD);
6901 break;
6902
6903 case RESET_KIND_SUSPEND:
6904 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6905 DRV_STATE_SUSPEND);
6906 break;
6907
6908 default:
6909 break;
6910 }
6911 }
6912 }
6913
6914 static int tg3_poll_fw(struct tg3 *tp)
6915 {
6916 int i;
6917 u32 val;
6918
6919 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6920 /* Wait up to 20ms for init done. */
6921 for (i = 0; i < 200; i++) {
6922 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6923 return 0;
6924 udelay(100);
6925 }
6926 return -ENODEV;
6927 }
6928
6929 /* Wait for firmware initialization to complete. */
6930 for (i = 0; i < 100000; i++) {
6931 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6932 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6933 break;
6934 udelay(10);
6935 }
6936
6937 /* Chip might not be fitted with firmware. Some Sun onboard
6938 * parts are configured like that. So don't signal the timeout
6939 * of the above loop as an error, but do report the lack of
6940 * running firmware once.
6941 */
6942 if (i >= 100000 &&
6943 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6944 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6945
6946 netdev_info(tp->dev, "No firmware running\n");
6947 }
6948
6949 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6950 /* The 57765 A0 needs a little more
6951 * time to do some important work.
6952 */
6953 mdelay(10);
6954 }
6955
6956 return 0;
6957 }
6958
6959 /* Save PCI command register before chip reset */
6960 static void tg3_save_pci_state(struct tg3 *tp)
6961 {
6962 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6963 }
6964
6965 /* Restore PCI state after chip reset */
6966 static void tg3_restore_pci_state(struct tg3 *tp)
6967 {
6968 u32 val;
6969
6970 /* Re-enable indirect register accesses. */
6971 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6972 tp->misc_host_ctrl);
6973
6974 /* Set MAX PCI retry to zero. */
6975 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6976 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6977 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6978 val |= PCISTATE_RETRY_SAME_DMA;
6979 /* Allow reads and writes to the APE register and memory space. */
6980 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6981 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6982 PCISTATE_ALLOW_APE_SHMEM_WR |
6983 PCISTATE_ALLOW_APE_PSPACE_WR;
6984 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6985
6986 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6987
6988 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6989 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6990 pcie_set_readrq(tp->pdev, 4096);
6991 else {
6992 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6993 tp->pci_cacheline_sz);
6994 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6995 tp->pci_lat_timer);
6996 }
6997 }
6998
6999 /* Make sure PCI-X relaxed ordering bit is clear. */
7000 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7001 u16 pcix_cmd;
7002
7003 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7004 &pcix_cmd);
7005 pcix_cmd &= ~PCI_X_CMD_ERO;
7006 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7007 pcix_cmd);
7008 }
7009
7010 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7011
7012 /* Chip reset on 5780 will reset MSI enable bit,
7013 * so need to restore it.
7014 */
7015 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7016 u16 ctrl;
7017
7018 pci_read_config_word(tp->pdev,
7019 tp->msi_cap + PCI_MSI_FLAGS,
7020 &ctrl);
7021 pci_write_config_word(tp->pdev,
7022 tp->msi_cap + PCI_MSI_FLAGS,
7023 ctrl | PCI_MSI_FLAGS_ENABLE);
7024 val = tr32(MSGINT_MODE);
7025 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7026 }
7027 }
7028 }
7029
7030 static void tg3_stop_fw(struct tg3 *);
7031
7032 /* tp->lock is held. */
7033 static int tg3_chip_reset(struct tg3 *tp)
7034 {
7035 u32 val;
7036 void (*write_op)(struct tg3 *, u32, u32);
7037 int i, err;
7038
7039 tg3_nvram_lock(tp);
7040
7041 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7042
7043 /* No matching tg3_nvram_unlock() after this because
7044 * chip reset below will undo the nvram lock.
7045 */
7046 tp->nvram_lock_cnt = 0;
7047
7048 /* GRC_MISC_CFG core clock reset will clear the memory
7049 * enable bit in PCI register 4 and the MSI enable bit
7050 * on some chips, so we save relevant registers here.
7051 */
7052 tg3_save_pci_state(tp);
7053
7054 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7055 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7056 tw32(GRC_FASTBOOT_PC, 0);
7057
7058 /*
7059 * We must avoid the readl() that normally takes place.
7060 * It locks machines, causes machine checks, and other
7061 * fun things. So, temporarily disable the 5701
7062 * hardware workaround, while we do the reset.
7063 */
7064 write_op = tp->write32;
7065 if (write_op == tg3_write_flush_reg32)
7066 tp->write32 = tg3_write32;
7067
7068 /* Prevent the irq handler from reading or writing PCI registers
7069 * during chip reset when the memory enable bit in the PCI command
7070 * register may be cleared. The chip does not generate interrupt
7071 * at this time, but the irq handler may still be called due to irq
7072 * sharing or irqpoll.
7073 */
7074 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7075 for (i = 0; i < tp->irq_cnt; i++) {
7076 struct tg3_napi *tnapi = &tp->napi[i];
7077 if (tnapi->hw_status) {
7078 tnapi->hw_status->status = 0;
7079 tnapi->hw_status->status_tag = 0;
7080 }
7081 tnapi->last_tag = 0;
7082 tnapi->last_irq_tag = 0;
7083 }
7084 smp_mb();
7085
7086 for (i = 0; i < tp->irq_cnt; i++)
7087 synchronize_irq(tp->napi[i].irq_vec);
7088
7089 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7090 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7091 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7092 }
7093
7094 /* do the reset */
7095 val = GRC_MISC_CFG_CORECLK_RESET;
7096
7097 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7098 /* Force PCIe 1.0a mode */
7099 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7100 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7101 tr32(TG3_PCIE_PHY_TSTCTL) ==
7102 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7103 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7104
7105 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7106 tw32(GRC_MISC_CFG, (1 << 29));
7107 val |= (1 << 29);
7108 }
7109 }
7110
7111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7112 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7113 tw32(GRC_VCPU_EXT_CTRL,
7114 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7115 }
7116
7117 /* Manage gphy power for all CPMU absent PCIe devices. */
7118 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7119 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7120 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7121
7122 tw32(GRC_MISC_CFG, val);
7123
7124 /* restore 5701 hardware bug workaround write method */
7125 tp->write32 = write_op;
7126
7127 /* Unfortunately, we have to delay before the PCI read back.
7128 * Some 575X chips even will not respond to a PCI cfg access
7129 * when the reset command is given to the chip.
7130 *
7131 * How do these hardware designers expect things to work
7132 * properly if the PCI write is posted for a long period
7133 * of time? It is always necessary to have some method by
7134 * which a register read back can occur to push the write
7135 * out which does the reset.
7136 *
7137 * For most tg3 variants the trick below was working.
7138 * Ho hum...
7139 */
7140 udelay(120);
7141
7142 /* Flush PCI posted writes. The normal MMIO registers
7143 * are inaccessible at this time so this is the only
7144 * way to make this reliably (actually, this is no longer
7145 * the case, see above). I tried to use indirect
7146 * register read/write but this upset some 5701 variants.
7147 */
7148 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7149
7150 udelay(120);
7151
7152 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7153 u16 val16;
7154
7155 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7156 int i;
7157 u32 cfg_val;
7158
7159 /* Wait for link training to complete. */
7160 for (i = 0; i < 5000; i++)
7161 udelay(100);
7162
7163 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7164 pci_write_config_dword(tp->pdev, 0xc4,
7165 cfg_val | (1 << 15));
7166 }
7167
7168 /* Clear the "no snoop" and "relaxed ordering" bits. */
7169 pci_read_config_word(tp->pdev,
7170 tp->pcie_cap + PCI_EXP_DEVCTL,
7171 &val16);
7172 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7173 PCI_EXP_DEVCTL_NOSNOOP_EN);
7174 /*
7175 * Older PCIe devices only support the 128 byte
7176 * MPS setting. Enforce the restriction.
7177 */
7178 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7179 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7180 pci_write_config_word(tp->pdev,
7181 tp->pcie_cap + PCI_EXP_DEVCTL,
7182 val16);
7183
7184 pcie_set_readrq(tp->pdev, 4096);
7185
7186 /* Clear error status */
7187 pci_write_config_word(tp->pdev,
7188 tp->pcie_cap + PCI_EXP_DEVSTA,
7189 PCI_EXP_DEVSTA_CED |
7190 PCI_EXP_DEVSTA_NFED |
7191 PCI_EXP_DEVSTA_FED |
7192 PCI_EXP_DEVSTA_URD);
7193 }
7194
7195 tg3_restore_pci_state(tp);
7196
7197 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7198
7199 val = 0;
7200 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7201 val = tr32(MEMARB_MODE);
7202 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7203
7204 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7205 tg3_stop_fw(tp);
7206 tw32(0x5000, 0x400);
7207 }
7208
7209 tw32(GRC_MODE, tp->grc_mode);
7210
7211 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7212 val = tr32(0xc4);
7213
7214 tw32(0xc4, val | (1 << 15));
7215 }
7216
7217 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7218 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7219 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7220 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7221 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7222 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7223 }
7224
7225 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7226 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7227 tw32_f(MAC_MODE, tp->mac_mode);
7228 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7229 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7230 tw32_f(MAC_MODE, tp->mac_mode);
7231 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7232 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7233 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7234 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7235 tw32_f(MAC_MODE, tp->mac_mode);
7236 } else
7237 tw32_f(MAC_MODE, 0);
7238 udelay(40);
7239
7240 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7241
7242 err = tg3_poll_fw(tp);
7243 if (err)
7244 return err;
7245
7246 tg3_mdio_start(tp);
7247
7248 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7249 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7250 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7251 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7252 val = tr32(0x7c00);
7253
7254 tw32(0x7c00, val | (1 << 25));
7255 }
7256
7257 /* Reprobe ASF enable state. */
7258 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7259 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7260 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7261 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7262 u32 nic_cfg;
7263
7264 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7265 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7266 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7267 tp->last_event_jiffies = jiffies;
7268 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7269 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7270 }
7271 }
7272
7273 return 0;
7274 }
7275
7276 /* tp->lock is held. */
7277 static void tg3_stop_fw(struct tg3 *tp)
7278 {
7279 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7280 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7281 /* Wait for RX cpu to ACK the previous event. */
7282 tg3_wait_for_event_ack(tp);
7283
7284 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7285
7286 tg3_generate_fw_event(tp);
7287
7288 /* Wait for RX cpu to ACK this event. */
7289 tg3_wait_for_event_ack(tp);
7290 }
7291 }
7292
7293 /* tp->lock is held. */
7294 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7295 {
7296 int err;
7297
7298 tg3_stop_fw(tp);
7299
7300 tg3_write_sig_pre_reset(tp, kind);
7301
7302 tg3_abort_hw(tp, silent);
7303 err = tg3_chip_reset(tp);
7304
7305 __tg3_set_mac_addr(tp, 0);
7306
7307 tg3_write_sig_legacy(tp, kind);
7308 tg3_write_sig_post_reset(tp, kind);
7309
7310 if (err)
7311 return err;
7312
7313 return 0;
7314 }
7315
7316 #define RX_CPU_SCRATCH_BASE 0x30000
7317 #define RX_CPU_SCRATCH_SIZE 0x04000
7318 #define TX_CPU_SCRATCH_BASE 0x34000
7319 #define TX_CPU_SCRATCH_SIZE 0x04000
7320
7321 /* tp->lock is held. */
7322 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7323 {
7324 int i;
7325
7326 BUG_ON(offset == TX_CPU_BASE &&
7327 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7328
7329 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7330 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7331
7332 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7333 return 0;
7334 }
7335 if (offset == RX_CPU_BASE) {
7336 for (i = 0; i < 10000; i++) {
7337 tw32(offset + CPU_STATE, 0xffffffff);
7338 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7339 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7340 break;
7341 }
7342
7343 tw32(offset + CPU_STATE, 0xffffffff);
7344 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7345 udelay(10);
7346 } else {
7347 for (i = 0; i < 10000; i++) {
7348 tw32(offset + CPU_STATE, 0xffffffff);
7349 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7350 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7351 break;
7352 }
7353 }
7354
7355 if (i >= 10000) {
7356 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7357 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7358 return -ENODEV;
7359 }
7360
7361 /* Clear firmware's nvram arbitration. */
7362 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7363 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7364 return 0;
7365 }
7366
7367 struct fw_info {
7368 unsigned int fw_base;
7369 unsigned int fw_len;
7370 const __be32 *fw_data;
7371 };
7372
7373 /* tp->lock is held. */
7374 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7375 int cpu_scratch_size, struct fw_info *info)
7376 {
7377 int err, lock_err, i;
7378 void (*write_op)(struct tg3 *, u32, u32);
7379
7380 if (cpu_base == TX_CPU_BASE &&
7381 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7382 netdev_err(tp->dev,
7383 "%s: Trying to load TX cpu firmware which is 5705\n",
7384 __func__);
7385 return -EINVAL;
7386 }
7387
7388 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7389 write_op = tg3_write_mem;
7390 else
7391 write_op = tg3_write_indirect_reg32;
7392
7393 /* It is possible that bootcode is still loading at this point.
7394 * Get the nvram lock first before halting the cpu.
7395 */
7396 lock_err = tg3_nvram_lock(tp);
7397 err = tg3_halt_cpu(tp, cpu_base);
7398 if (!lock_err)
7399 tg3_nvram_unlock(tp);
7400 if (err)
7401 goto out;
7402
7403 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7404 write_op(tp, cpu_scratch_base + i, 0);
7405 tw32(cpu_base + CPU_STATE, 0xffffffff);
7406 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7407 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7408 write_op(tp, (cpu_scratch_base +
7409 (info->fw_base & 0xffff) +
7410 (i * sizeof(u32))),
7411 be32_to_cpu(info->fw_data[i]));
7412
7413 err = 0;
7414
7415 out:
7416 return err;
7417 }
7418
7419 /* tp->lock is held. */
7420 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7421 {
7422 struct fw_info info;
7423 const __be32 *fw_data;
7424 int err, i;
7425
7426 fw_data = (void *)tp->fw->data;
7427
7428 /* Firmware blob starts with version numbers, followed by
7429 start address and length. We are setting complete length.
7430 length = end_address_of_bss - start_address_of_text.
7431 Remainder is the blob to be loaded contiguously
7432 from start address. */
7433
7434 info.fw_base = be32_to_cpu(fw_data[1]);
7435 info.fw_len = tp->fw->size - 12;
7436 info.fw_data = &fw_data[3];
7437
7438 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7439 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7440 &info);
7441 if (err)
7442 return err;
7443
7444 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7445 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7446 &info);
7447 if (err)
7448 return err;
7449
7450 /* Now startup only the RX cpu. */
7451 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7452 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7453
7454 for (i = 0; i < 5; i++) {
7455 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7456 break;
7457 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7458 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7459 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7460 udelay(1000);
7461 }
7462 if (i >= 5) {
7463 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7464 "should be %08x\n", __func__,
7465 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7466 return -ENODEV;
7467 }
7468 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7469 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7470
7471 return 0;
7472 }
7473
7474 /* 5705 needs a special version of the TSO firmware. */
7475
7476 /* tp->lock is held. */
7477 static int tg3_load_tso_firmware(struct tg3 *tp)
7478 {
7479 struct fw_info info;
7480 const __be32 *fw_data;
7481 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7482 int err, i;
7483
7484 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7485 return 0;
7486
7487 fw_data = (void *)tp->fw->data;
7488
7489 /* Firmware blob starts with version numbers, followed by
7490 start address and length. We are setting complete length.
7491 length = end_address_of_bss - start_address_of_text.
7492 Remainder is the blob to be loaded contiguously
7493 from start address. */
7494
7495 info.fw_base = be32_to_cpu(fw_data[1]);
7496 cpu_scratch_size = tp->fw_len;
7497 info.fw_len = tp->fw->size - 12;
7498 info.fw_data = &fw_data[3];
7499
7500 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7501 cpu_base = RX_CPU_BASE;
7502 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7503 } else {
7504 cpu_base = TX_CPU_BASE;
7505 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7506 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7507 }
7508
7509 err = tg3_load_firmware_cpu(tp, cpu_base,
7510 cpu_scratch_base, cpu_scratch_size,
7511 &info);
7512 if (err)
7513 return err;
7514
7515 /* Now startup the cpu. */
7516 tw32(cpu_base + CPU_STATE, 0xffffffff);
7517 tw32_f(cpu_base + CPU_PC, info.fw_base);
7518
7519 for (i = 0; i < 5; i++) {
7520 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7521 break;
7522 tw32(cpu_base + CPU_STATE, 0xffffffff);
7523 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7524 tw32_f(cpu_base + CPU_PC, info.fw_base);
7525 udelay(1000);
7526 }
7527 if (i >= 5) {
7528 netdev_err(tp->dev,
7529 "%s fails to set CPU PC, is %08x should be %08x\n",
7530 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7531 return -ENODEV;
7532 }
7533 tw32(cpu_base + CPU_STATE, 0xffffffff);
7534 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7535 return 0;
7536 }
7537
7538
7539 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7540 {
7541 struct tg3 *tp = netdev_priv(dev);
7542 struct sockaddr *addr = p;
7543 int err = 0, skip_mac_1 = 0;
7544
7545 if (!is_valid_ether_addr(addr->sa_data))
7546 return -EINVAL;
7547
7548 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7549
7550 if (!netif_running(dev))
7551 return 0;
7552
7553 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7554 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7555
7556 addr0_high = tr32(MAC_ADDR_0_HIGH);
7557 addr0_low = tr32(MAC_ADDR_0_LOW);
7558 addr1_high = tr32(MAC_ADDR_1_HIGH);
7559 addr1_low = tr32(MAC_ADDR_1_LOW);
7560
7561 /* Skip MAC addr 1 if ASF is using it. */
7562 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7563 !(addr1_high == 0 && addr1_low == 0))
7564 skip_mac_1 = 1;
7565 }
7566 spin_lock_bh(&tp->lock);
7567 __tg3_set_mac_addr(tp, skip_mac_1);
7568 spin_unlock_bh(&tp->lock);
7569
7570 return err;
7571 }
7572
7573 /* tp->lock is held. */
7574 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7575 dma_addr_t mapping, u32 maxlen_flags,
7576 u32 nic_addr)
7577 {
7578 tg3_write_mem(tp,
7579 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7580 ((u64) mapping >> 32));
7581 tg3_write_mem(tp,
7582 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7583 ((u64) mapping & 0xffffffff));
7584 tg3_write_mem(tp,
7585 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7586 maxlen_flags);
7587
7588 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7589 tg3_write_mem(tp,
7590 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7591 nic_addr);
7592 }
7593
7594 static void __tg3_set_rx_mode(struct net_device *);
7595 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7596 {
7597 int i;
7598
7599 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7600 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7601 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7602 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7603 } else {
7604 tw32(HOSTCC_TXCOL_TICKS, 0);
7605 tw32(HOSTCC_TXMAX_FRAMES, 0);
7606 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7607 }
7608
7609 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7610 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7611 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7612 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7613 } else {
7614 tw32(HOSTCC_RXCOL_TICKS, 0);
7615 tw32(HOSTCC_RXMAX_FRAMES, 0);
7616 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7617 }
7618
7619 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7620 u32 val = ec->stats_block_coalesce_usecs;
7621
7622 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7623 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7624
7625 if (!netif_carrier_ok(tp->dev))
7626 val = 0;
7627
7628 tw32(HOSTCC_STAT_COAL_TICKS, val);
7629 }
7630
7631 for (i = 0; i < tp->irq_cnt - 1; i++) {
7632 u32 reg;
7633
7634 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7635 tw32(reg, ec->rx_coalesce_usecs);
7636 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7637 tw32(reg, ec->rx_max_coalesced_frames);
7638 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7639 tw32(reg, ec->rx_max_coalesced_frames_irq);
7640
7641 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7642 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7643 tw32(reg, ec->tx_coalesce_usecs);
7644 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7645 tw32(reg, ec->tx_max_coalesced_frames);
7646 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7647 tw32(reg, ec->tx_max_coalesced_frames_irq);
7648 }
7649 }
7650
7651 for (; i < tp->irq_max - 1; i++) {
7652 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7653 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7654 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7655
7656 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7657 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7658 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7659 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7660 }
7661 }
7662 }
7663
7664 /* tp->lock is held. */
7665 static void tg3_rings_reset(struct tg3 *tp)
7666 {
7667 int i;
7668 u32 stblk, txrcb, rxrcb, limit;
7669 struct tg3_napi *tnapi = &tp->napi[0];
7670
7671 /* Disable all transmit rings but the first. */
7672 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7673 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7674 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7675 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7676 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7677 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7678 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7679 else
7680 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7681
7682 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7683 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7684 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7685 BDINFO_FLAGS_DISABLED);
7686
7687
7688 /* Disable all receive return rings but the first. */
7689 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7690 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7691 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7692 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7693 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7694 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7695 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7696 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7697 else
7698 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7699
7700 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7701 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7702 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7703 BDINFO_FLAGS_DISABLED);
7704
7705 /* Disable interrupts */
7706 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7707
7708 /* Zero mailbox registers. */
7709 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7710 for (i = 1; i < tp->irq_max; i++) {
7711 tp->napi[i].tx_prod = 0;
7712 tp->napi[i].tx_cons = 0;
7713 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7714 tw32_mailbox(tp->napi[i].prodmbox, 0);
7715 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7716 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7717 }
7718 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7719 tw32_mailbox(tp->napi[0].prodmbox, 0);
7720 } else {
7721 tp->napi[0].tx_prod = 0;
7722 tp->napi[0].tx_cons = 0;
7723 tw32_mailbox(tp->napi[0].prodmbox, 0);
7724 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7725 }
7726
7727 /* Make sure the NIC-based send BD rings are disabled. */
7728 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7729 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7730 for (i = 0; i < 16; i++)
7731 tw32_tx_mbox(mbox + i * 8, 0);
7732 }
7733
7734 txrcb = NIC_SRAM_SEND_RCB;
7735 rxrcb = NIC_SRAM_RCV_RET_RCB;
7736
7737 /* Clear status block in ram. */
7738 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7739
7740 /* Set status block DMA address */
7741 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7742 ((u64) tnapi->status_mapping >> 32));
7743 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7744 ((u64) tnapi->status_mapping & 0xffffffff));
7745
7746 if (tnapi->tx_ring) {
7747 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7748 (TG3_TX_RING_SIZE <<
7749 BDINFO_FLAGS_MAXLEN_SHIFT),
7750 NIC_SRAM_TX_BUFFER_DESC);
7751 txrcb += TG3_BDINFO_SIZE;
7752 }
7753
7754 if (tnapi->rx_rcb) {
7755 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7756 (tp->rx_ret_ring_mask + 1) <<
7757 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7758 rxrcb += TG3_BDINFO_SIZE;
7759 }
7760
7761 stblk = HOSTCC_STATBLCK_RING1;
7762
7763 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7764 u64 mapping = (u64)tnapi->status_mapping;
7765 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7766 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7767
7768 /* Clear status block in ram. */
7769 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7770
7771 if (tnapi->tx_ring) {
7772 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7773 (TG3_TX_RING_SIZE <<
7774 BDINFO_FLAGS_MAXLEN_SHIFT),
7775 NIC_SRAM_TX_BUFFER_DESC);
7776 txrcb += TG3_BDINFO_SIZE;
7777 }
7778
7779 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7780 ((tp->rx_ret_ring_mask + 1) <<
7781 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7782
7783 stblk += 8;
7784 rxrcb += TG3_BDINFO_SIZE;
7785 }
7786 }
7787
7788 /* tp->lock is held. */
7789 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7790 {
7791 u32 val, rdmac_mode;
7792 int i, err, limit;
7793 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7794
7795 tg3_disable_ints(tp);
7796
7797 tg3_stop_fw(tp);
7798
7799 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7800
7801 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7802 tg3_abort_hw(tp, 1);
7803
7804 if (reset_phy)
7805 tg3_phy_reset(tp);
7806
7807 err = tg3_chip_reset(tp);
7808 if (err)
7809 return err;
7810
7811 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7812
7813 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7814 val = tr32(TG3_CPMU_CTRL);
7815 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7816 tw32(TG3_CPMU_CTRL, val);
7817
7818 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7819 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7820 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7821 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7822
7823 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7824 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7825 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7826 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7827
7828 val = tr32(TG3_CPMU_HST_ACC);
7829 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7830 val |= CPMU_HST_ACC_MACCLK_6_25;
7831 tw32(TG3_CPMU_HST_ACC, val);
7832 }
7833
7834 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7835 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7836 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7837 PCIE_PWR_MGMT_L1_THRESH_4MS;
7838 tw32(PCIE_PWR_MGMT_THRESH, val);
7839
7840 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7841 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7842
7843 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7844
7845 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7846 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7847 }
7848
7849 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7850 u32 grc_mode = tr32(GRC_MODE);
7851
7852 /* Access the lower 1K of PL PCIE block registers. */
7853 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7854 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7855
7856 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7857 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7858 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7859
7860 tw32(GRC_MODE, grc_mode);
7861 }
7862
7863 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7864 u32 grc_mode = tr32(GRC_MODE);
7865
7866 /* Access the lower 1K of PL PCIE block registers. */
7867 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7868 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7869
7870 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7871 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7872 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7873
7874 tw32(GRC_MODE, grc_mode);
7875
7876 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7877 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7878 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7879 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7880 }
7881
7882 /* Enable MAC control of LPI */
7883 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7884 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7885 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7886 TG3_CPMU_EEE_LNKIDL_UART_IDL);
7887
7888 tw32_f(TG3_CPMU_EEE_CTRL,
7889 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7890
7891 tw32_f(TG3_CPMU_EEE_MODE,
7892 TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7893 TG3_CPMU_EEEMD_LPI_IN_TX |
7894 TG3_CPMU_EEEMD_LPI_IN_RX |
7895 TG3_CPMU_EEEMD_EEE_ENABLE);
7896 }
7897
7898 /* This works around an issue with Athlon chipsets on
7899 * B3 tigon3 silicon. This bit has no effect on any
7900 * other revision. But do not set this on PCI Express
7901 * chips and don't even touch the clocks if the CPMU is present.
7902 */
7903 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7904 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7905 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7906 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7907 }
7908
7909 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7910 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7911 val = tr32(TG3PCI_PCISTATE);
7912 val |= PCISTATE_RETRY_SAME_DMA;
7913 tw32(TG3PCI_PCISTATE, val);
7914 }
7915
7916 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7917 /* Allow reads and writes to the
7918 * APE register and memory space.
7919 */
7920 val = tr32(TG3PCI_PCISTATE);
7921 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7922 PCISTATE_ALLOW_APE_SHMEM_WR |
7923 PCISTATE_ALLOW_APE_PSPACE_WR;
7924 tw32(TG3PCI_PCISTATE, val);
7925 }
7926
7927 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7928 /* Enable some hw fixes. */
7929 val = tr32(TG3PCI_MSI_DATA);
7930 val |= (1 << 26) | (1 << 28) | (1 << 29);
7931 tw32(TG3PCI_MSI_DATA, val);
7932 }
7933
7934 /* Descriptor ring init may make accesses to the
7935 * NIC SRAM area to setup the TX descriptors, so we
7936 * can only do this after the hardware has been
7937 * successfully reset.
7938 */
7939 err = tg3_init_rings(tp);
7940 if (err)
7941 return err;
7942
7943 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7944 val = tr32(TG3PCI_DMA_RW_CTRL) &
7945 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7946 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7947 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7948 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7949 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7950 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7951 /* This value is determined during the probe time DMA
7952 * engine test, tg3_test_dma.
7953 */
7954 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7955 }
7956
7957 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7958 GRC_MODE_4X_NIC_SEND_RINGS |
7959 GRC_MODE_NO_TX_PHDR_CSUM |
7960 GRC_MODE_NO_RX_PHDR_CSUM);
7961 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7962
7963 /* Pseudo-header checksum is done by hardware logic and not
7964 * the offload processers, so make the chip do the pseudo-
7965 * header checksums on receive. For transmit it is more
7966 * convenient to do the pseudo-header checksum in software
7967 * as Linux does that on transmit for us in all cases.
7968 */
7969 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7970
7971 tw32(GRC_MODE,
7972 tp->grc_mode |
7973 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7974
7975 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7976 val = tr32(GRC_MISC_CFG);
7977 val &= ~0xff;
7978 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7979 tw32(GRC_MISC_CFG, val);
7980
7981 /* Initialize MBUF/DESC pool. */
7982 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7983 /* Do nothing. */
7984 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7985 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7986 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7987 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7988 else
7989 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7990 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7991 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7992 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7993 int fw_len;
7994
7995 fw_len = tp->fw_len;
7996 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7997 tw32(BUFMGR_MB_POOL_ADDR,
7998 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7999 tw32(BUFMGR_MB_POOL_SIZE,
8000 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8001 }
8002
8003 if (tp->dev->mtu <= ETH_DATA_LEN) {
8004 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8005 tp->bufmgr_config.mbuf_read_dma_low_water);
8006 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8007 tp->bufmgr_config.mbuf_mac_rx_low_water);
8008 tw32(BUFMGR_MB_HIGH_WATER,
8009 tp->bufmgr_config.mbuf_high_water);
8010 } else {
8011 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8012 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8013 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8014 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8015 tw32(BUFMGR_MB_HIGH_WATER,
8016 tp->bufmgr_config.mbuf_high_water_jumbo);
8017 }
8018 tw32(BUFMGR_DMA_LOW_WATER,
8019 tp->bufmgr_config.dma_low_water);
8020 tw32(BUFMGR_DMA_HIGH_WATER,
8021 tp->bufmgr_config.dma_high_water);
8022
8023 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8025 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8026 tw32(BUFMGR_MODE, val);
8027 for (i = 0; i < 2000; i++) {
8028 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8029 break;
8030 udelay(10);
8031 }
8032 if (i >= 2000) {
8033 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8034 return -ENODEV;
8035 }
8036
8037 /* Setup replenish threshold. */
8038 val = tp->rx_pending / 8;
8039 if (val == 0)
8040 val = 1;
8041 else if (val > tp->rx_std_max_post)
8042 val = tp->rx_std_max_post;
8043 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8044 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8045 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8046
8047 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8048 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8049 }
8050
8051 tw32(RCVBDI_STD_THRESH, val);
8052
8053 /* Initialize TG3_BDINFO's at:
8054 * RCVDBDI_STD_BD: standard eth size rx ring
8055 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8056 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8057 *
8058 * like so:
8059 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8060 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8061 * ring attribute flags
8062 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8063 *
8064 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8065 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8066 *
8067 * The size of each ring is fixed in the firmware, but the location is
8068 * configurable.
8069 */
8070 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8071 ((u64) tpr->rx_std_mapping >> 32));
8072 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8073 ((u64) tpr->rx_std_mapping & 0xffffffff));
8074 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8075 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
8076 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8077 NIC_SRAM_RX_BUFFER_DESC);
8078
8079 /* Disable the mini ring */
8080 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8081 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8082 BDINFO_FLAGS_DISABLED);
8083
8084 /* Program the jumbo buffer descriptor ring control
8085 * blocks on those devices that have them.
8086 */
8087 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8088 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8089 /* Setup replenish threshold. */
8090 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8091
8092 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8093 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8094 ((u64) tpr->rx_jmb_mapping >> 32));
8095 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8096 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8097 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8098 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
8099 BDINFO_FLAGS_USE_EXT_RECV);
8100 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8102 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8103 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8104 } else {
8105 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8106 BDINFO_FLAGS_DISABLED);
8107 }
8108
8109 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8111 val = RX_STD_MAX_SIZE_5705;
8112 else
8113 val = RX_STD_MAX_SIZE_5717;
8114 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8115 val |= (TG3_RX_STD_DMA_SZ << 2);
8116 } else
8117 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8118 } else
8119 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
8120
8121 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8122
8123 tpr->rx_std_prod_idx = tp->rx_pending;
8124 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8125
8126 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8127 tp->rx_jumbo_pending : 0;
8128 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8129
8130 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8131 tw32(STD_REPLENISH_LWM, 32);
8132 tw32(JMB_REPLENISH_LWM, 16);
8133 }
8134
8135 tg3_rings_reset(tp);
8136
8137 /* Initialize MAC address and backoff seed. */
8138 __tg3_set_mac_addr(tp, 0);
8139
8140 /* MTU + ethernet header + FCS + optional VLAN tag */
8141 tw32(MAC_RX_MTU_SIZE,
8142 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8143
8144 /* The slot time is changed by tg3_setup_phy if we
8145 * run at gigabit with half duplex.
8146 */
8147 tw32(MAC_TX_LENGTHS,
8148 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8149 (6 << TX_LENGTHS_IPG_SHIFT) |
8150 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8151
8152 /* Receive rules. */
8153 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8154 tw32(RCVLPC_CONFIG, 0x0181);
8155
8156 /* Calculate RDMAC_MODE setting early, we need it to determine
8157 * the RCVLPC_STATE_ENABLE mask.
8158 */
8159 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8160 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8161 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8162 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8163 RDMAC_MODE_LNGREAD_ENAB);
8164
8165 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8166 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8167 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8168
8169 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8170 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8171 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8172 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8173 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8174 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8175
8176 /* If statement applies to 5705 and 5750 PCI devices only */
8177 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8178 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8179 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8180 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8181 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8182 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8183 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8184 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8185 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8186 }
8187 }
8188
8189 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8190 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8191
8192 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8193 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8194
8195 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8196 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8197 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8198 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8199
8200 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8201 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8202 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8203 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8204 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8205 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8206 tw32(TG3_RDMA_RSRVCTRL_REG,
8207 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8208 }
8209
8210 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8211 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8212 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8213 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8214 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8215 }
8216
8217 /* Receive/send statistics. */
8218 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8219 val = tr32(RCVLPC_STATS_ENABLE);
8220 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8221 tw32(RCVLPC_STATS_ENABLE, val);
8222 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8223 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8224 val = tr32(RCVLPC_STATS_ENABLE);
8225 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8226 tw32(RCVLPC_STATS_ENABLE, val);
8227 } else {
8228 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8229 }
8230 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8231 tw32(SNDDATAI_STATSENAB, 0xffffff);
8232 tw32(SNDDATAI_STATSCTRL,
8233 (SNDDATAI_SCTRL_ENABLE |
8234 SNDDATAI_SCTRL_FASTUPD));
8235
8236 /* Setup host coalescing engine. */
8237 tw32(HOSTCC_MODE, 0);
8238 for (i = 0; i < 2000; i++) {
8239 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8240 break;
8241 udelay(10);
8242 }
8243
8244 __tg3_set_coalesce(tp, &tp->coal);
8245
8246 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8247 /* Status/statistics block address. See tg3_timer,
8248 * the tg3_periodic_fetch_stats call there, and
8249 * tg3_get_stats to see how this works for 5705/5750 chips.
8250 */
8251 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8252 ((u64) tp->stats_mapping >> 32));
8253 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8254 ((u64) tp->stats_mapping & 0xffffffff));
8255 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8256
8257 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8258
8259 /* Clear statistics and status block memory areas */
8260 for (i = NIC_SRAM_STATS_BLK;
8261 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8262 i += sizeof(u32)) {
8263 tg3_write_mem(tp, i, 0);
8264 udelay(40);
8265 }
8266 }
8267
8268 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8269
8270 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8271 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8272 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8273 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8274
8275 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8276 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8277 /* reset to prevent losing 1st rx packet intermittently */
8278 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8279 udelay(10);
8280 }
8281
8282 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8283 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8284 else
8285 tp->mac_mode = 0;
8286 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8287 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8288 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8289 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8290 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8291 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8292 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8293 udelay(40);
8294
8295 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8296 * If TG3_FLG2_IS_NIC is zero, we should read the
8297 * register to preserve the GPIO settings for LOMs. The GPIOs,
8298 * whether used as inputs or outputs, are set by boot code after
8299 * reset.
8300 */
8301 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8302 u32 gpio_mask;
8303
8304 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8305 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8306 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8307
8308 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8309 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8310 GRC_LCLCTRL_GPIO_OUTPUT3;
8311
8312 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8313 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8314
8315 tp->grc_local_ctrl &= ~gpio_mask;
8316 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8317
8318 /* GPIO1 must be driven high for eeprom write protect */
8319 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8320 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8321 GRC_LCLCTRL_GPIO_OUTPUT1);
8322 }
8323 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8324 udelay(100);
8325
8326 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8327 val = tr32(MSGINT_MODE);
8328 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8329 tw32(MSGINT_MODE, val);
8330 }
8331
8332 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8333 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8334 udelay(40);
8335 }
8336
8337 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8338 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8339 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8340 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8341 WDMAC_MODE_LNGREAD_ENAB);
8342
8343 /* If statement applies to 5705 and 5750 PCI devices only */
8344 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8345 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8346 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8347 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8348 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8349 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8350 /* nothing */
8351 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8352 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8353 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8354 val |= WDMAC_MODE_RX_ACCEL;
8355 }
8356 }
8357
8358 /* Enable host coalescing bug fix */
8359 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8360 val |= WDMAC_MODE_STATUS_TAG_FIX;
8361
8362 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8363 val |= WDMAC_MODE_BURST_ALL_DATA;
8364
8365 tw32_f(WDMAC_MODE, val);
8366 udelay(40);
8367
8368 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8369 u16 pcix_cmd;
8370
8371 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8372 &pcix_cmd);
8373 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8374 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8375 pcix_cmd |= PCI_X_CMD_READ_2K;
8376 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8377 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8378 pcix_cmd |= PCI_X_CMD_READ_2K;
8379 }
8380 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8381 pcix_cmd);
8382 }
8383
8384 tw32_f(RDMAC_MODE, rdmac_mode);
8385 udelay(40);
8386
8387 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8388 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8389 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8390
8391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8392 tw32(SNDDATAC_MODE,
8393 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8394 else
8395 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8396
8397 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8398 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8399 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8400 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8401 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8402 val |= RCVDBDI_MODE_LRG_RING_SZ;
8403 tw32(RCVDBDI_MODE, val);
8404 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8405 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8406 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8407 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8408 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8409 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8410 tw32(SNDBDI_MODE, val);
8411 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8412
8413 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8414 err = tg3_load_5701_a0_firmware_fix(tp);
8415 if (err)
8416 return err;
8417 }
8418
8419 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8420 err = tg3_load_tso_firmware(tp);
8421 if (err)
8422 return err;
8423 }
8424
8425 tp->tx_mode = TX_MODE_ENABLE;
8426 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8428 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8429 tw32_f(MAC_TX_MODE, tp->tx_mode);
8430 udelay(100);
8431
8432 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8433 u32 reg = MAC_RSS_INDIR_TBL_0;
8434 u8 *ent = (u8 *)&val;
8435
8436 /* Setup the indirection table */
8437 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8438 int idx = i % sizeof(val);
8439
8440 ent[idx] = i % (tp->irq_cnt - 1);
8441 if (idx == sizeof(val) - 1) {
8442 tw32(reg, val);
8443 reg += 4;
8444 }
8445 }
8446
8447 /* Setup the "secret" hash key. */
8448 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8449 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8450 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8451 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8452 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8453 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8454 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8455 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8456 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8457 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8458 }
8459
8460 tp->rx_mode = RX_MODE_ENABLE;
8461 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8462 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8463
8464 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8465 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8466 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8467 RX_MODE_RSS_IPV6_HASH_EN |
8468 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8469 RX_MODE_RSS_IPV4_HASH_EN |
8470 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8471
8472 tw32_f(MAC_RX_MODE, tp->rx_mode);
8473 udelay(10);
8474
8475 tw32(MAC_LED_CTRL, tp->led_ctrl);
8476
8477 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8478 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8479 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8480 udelay(10);
8481 }
8482 tw32_f(MAC_RX_MODE, tp->rx_mode);
8483 udelay(10);
8484
8485 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8486 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8487 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8488 /* Set drive transmission level to 1.2V */
8489 /* only if the signal pre-emphasis bit is not set */
8490 val = tr32(MAC_SERDES_CFG);
8491 val &= 0xfffff000;
8492 val |= 0x880;
8493 tw32(MAC_SERDES_CFG, val);
8494 }
8495 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8496 tw32(MAC_SERDES_CFG, 0x616000);
8497 }
8498
8499 /* Prevent chip from dropping frames when flow control
8500 * is enabled.
8501 */
8502 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8503 val = 1;
8504 else
8505 val = 2;
8506 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8507
8508 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8509 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8510 /* Use hardware link auto-negotiation */
8511 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8512 }
8513
8514 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8515 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8516 u32 tmp;
8517
8518 tmp = tr32(SERDES_RX_CTRL);
8519 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8520 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8521 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8522 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8523 }
8524
8525 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8526 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8527 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8528 tp->link_config.speed = tp->link_config.orig_speed;
8529 tp->link_config.duplex = tp->link_config.orig_duplex;
8530 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8531 }
8532
8533 err = tg3_setup_phy(tp, 0);
8534 if (err)
8535 return err;
8536
8537 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8538 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8539 u32 tmp;
8540
8541 /* Clear CRC stats. */
8542 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8543 tg3_writephy(tp, MII_TG3_TEST1,
8544 tmp | MII_TG3_TEST1_CRC_EN);
8545 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8546 }
8547 }
8548 }
8549
8550 __tg3_set_rx_mode(tp->dev);
8551
8552 /* Initialize receive rules. */
8553 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8554 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8555 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8556 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8557
8558 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8559 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8560 limit = 8;
8561 else
8562 limit = 16;
8563 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8564 limit -= 4;
8565 switch (limit) {
8566 case 16:
8567 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8568 case 15:
8569 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8570 case 14:
8571 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8572 case 13:
8573 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8574 case 12:
8575 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8576 case 11:
8577 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8578 case 10:
8579 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8580 case 9:
8581 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8582 case 8:
8583 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8584 case 7:
8585 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8586 case 6:
8587 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8588 case 5:
8589 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8590 case 4:
8591 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8592 case 3:
8593 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8594 case 2:
8595 case 1:
8596
8597 default:
8598 break;
8599 }
8600
8601 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8602 /* Write our heartbeat update interval to APE. */
8603 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8604 APE_HOST_HEARTBEAT_INT_DISABLE);
8605
8606 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8607
8608 return 0;
8609 }
8610
8611 /* Called at device open time to get the chip ready for
8612 * packet processing. Invoked with tp->lock held.
8613 */
8614 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8615 {
8616 tg3_switch_clocks(tp);
8617
8618 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8619
8620 return tg3_reset_hw(tp, reset_phy);
8621 }
8622
8623 #define TG3_STAT_ADD32(PSTAT, REG) \
8624 do { u32 __val = tr32(REG); \
8625 (PSTAT)->low += __val; \
8626 if ((PSTAT)->low < __val) \
8627 (PSTAT)->high += 1; \
8628 } while (0)
8629
8630 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8631 {
8632 struct tg3_hw_stats *sp = tp->hw_stats;
8633
8634 if (!netif_carrier_ok(tp->dev))
8635 return;
8636
8637 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8638 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8639 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8640 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8641 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8642 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8643 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8644 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8645 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8646 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8647 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8648 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8649 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8650
8651 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8652 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8653 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8654 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8655 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8656 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8657 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8658 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8659 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8660 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8661 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8662 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8663 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8664 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8665
8666 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8667 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8668 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8669 }
8670
8671 static void tg3_timer(unsigned long __opaque)
8672 {
8673 struct tg3 *tp = (struct tg3 *) __opaque;
8674
8675 if (tp->irq_sync)
8676 goto restart_timer;
8677
8678 spin_lock(&tp->lock);
8679
8680 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8681 /* All of this garbage is because when using non-tagged
8682 * IRQ status the mailbox/status_block protocol the chip
8683 * uses with the cpu is race prone.
8684 */
8685 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8686 tw32(GRC_LOCAL_CTRL,
8687 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8688 } else {
8689 tw32(HOSTCC_MODE, tp->coalesce_mode |
8690 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8691 }
8692
8693 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8694 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8695 spin_unlock(&tp->lock);
8696 schedule_work(&tp->reset_task);
8697 return;
8698 }
8699 }
8700
8701 /* This part only runs once per second. */
8702 if (!--tp->timer_counter) {
8703 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8704 tg3_periodic_fetch_stats(tp);
8705
8706 if (tp->setlpicnt && !--tp->setlpicnt) {
8707 u32 val = tr32(TG3_CPMU_EEE_MODE);
8708 tw32(TG3_CPMU_EEE_MODE,
8709 val | TG3_CPMU_EEEMD_LPI_ENABLE);
8710 }
8711
8712 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8713 u32 mac_stat;
8714 int phy_event;
8715
8716 mac_stat = tr32(MAC_STATUS);
8717
8718 phy_event = 0;
8719 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8720 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8721 phy_event = 1;
8722 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8723 phy_event = 1;
8724
8725 if (phy_event)
8726 tg3_setup_phy(tp, 0);
8727 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8728 u32 mac_stat = tr32(MAC_STATUS);
8729 int need_setup = 0;
8730
8731 if (netif_carrier_ok(tp->dev) &&
8732 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8733 need_setup = 1;
8734 }
8735 if (!netif_carrier_ok(tp->dev) &&
8736 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8737 MAC_STATUS_SIGNAL_DET))) {
8738 need_setup = 1;
8739 }
8740 if (need_setup) {
8741 if (!tp->serdes_counter) {
8742 tw32_f(MAC_MODE,
8743 (tp->mac_mode &
8744 ~MAC_MODE_PORT_MODE_MASK));
8745 udelay(40);
8746 tw32_f(MAC_MODE, tp->mac_mode);
8747 udelay(40);
8748 }
8749 tg3_setup_phy(tp, 0);
8750 }
8751 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8752 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8753 tg3_serdes_parallel_detect(tp);
8754 }
8755
8756 tp->timer_counter = tp->timer_multiplier;
8757 }
8758
8759 /* Heartbeat is only sent once every 2 seconds.
8760 *
8761 * The heartbeat is to tell the ASF firmware that the host
8762 * driver is still alive. In the event that the OS crashes,
8763 * ASF needs to reset the hardware to free up the FIFO space
8764 * that may be filled with rx packets destined for the host.
8765 * If the FIFO is full, ASF will no longer function properly.
8766 *
8767 * Unintended resets have been reported on real time kernels
8768 * where the timer doesn't run on time. Netpoll will also have
8769 * same problem.
8770 *
8771 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8772 * to check the ring condition when the heartbeat is expiring
8773 * before doing the reset. This will prevent most unintended
8774 * resets.
8775 */
8776 if (!--tp->asf_counter) {
8777 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8778 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8779 tg3_wait_for_event_ack(tp);
8780
8781 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8782 FWCMD_NICDRV_ALIVE3);
8783 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8784 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8785 TG3_FW_UPDATE_TIMEOUT_SEC);
8786
8787 tg3_generate_fw_event(tp);
8788 }
8789 tp->asf_counter = tp->asf_multiplier;
8790 }
8791
8792 spin_unlock(&tp->lock);
8793
8794 restart_timer:
8795 tp->timer.expires = jiffies + tp->timer_offset;
8796 add_timer(&tp->timer);
8797 }
8798
8799 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8800 {
8801 irq_handler_t fn;
8802 unsigned long flags;
8803 char *name;
8804 struct tg3_napi *tnapi = &tp->napi[irq_num];
8805
8806 if (tp->irq_cnt == 1)
8807 name = tp->dev->name;
8808 else {
8809 name = &tnapi->irq_lbl[0];
8810 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8811 name[IFNAMSIZ-1] = 0;
8812 }
8813
8814 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8815 fn = tg3_msi;
8816 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8817 fn = tg3_msi_1shot;
8818 flags = IRQF_SAMPLE_RANDOM;
8819 } else {
8820 fn = tg3_interrupt;
8821 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8822 fn = tg3_interrupt_tagged;
8823 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8824 }
8825
8826 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8827 }
8828
8829 static int tg3_test_interrupt(struct tg3 *tp)
8830 {
8831 struct tg3_napi *tnapi = &tp->napi[0];
8832 struct net_device *dev = tp->dev;
8833 int err, i, intr_ok = 0;
8834 u32 val;
8835
8836 if (!netif_running(dev))
8837 return -ENODEV;
8838
8839 tg3_disable_ints(tp);
8840
8841 free_irq(tnapi->irq_vec, tnapi);
8842
8843 /*
8844 * Turn off MSI one shot mode. Otherwise this test has no
8845 * observable way to know whether the interrupt was delivered.
8846 */
8847 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8848 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8849 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8850 tw32(MSGINT_MODE, val);
8851 }
8852
8853 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8854 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8855 if (err)
8856 return err;
8857
8858 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8859 tg3_enable_ints(tp);
8860
8861 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8862 tnapi->coal_now);
8863
8864 for (i = 0; i < 5; i++) {
8865 u32 int_mbox, misc_host_ctrl;
8866
8867 int_mbox = tr32_mailbox(tnapi->int_mbox);
8868 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8869
8870 if ((int_mbox != 0) ||
8871 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8872 intr_ok = 1;
8873 break;
8874 }
8875
8876 msleep(10);
8877 }
8878
8879 tg3_disable_ints(tp);
8880
8881 free_irq(tnapi->irq_vec, tnapi);
8882
8883 err = tg3_request_irq(tp, 0);
8884
8885 if (err)
8886 return err;
8887
8888 if (intr_ok) {
8889 /* Reenable MSI one shot mode. */
8890 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8891 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8892 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8893 tw32(MSGINT_MODE, val);
8894 }
8895 return 0;
8896 }
8897
8898 return -EIO;
8899 }
8900
8901 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8902 * successfully restored
8903 */
8904 static int tg3_test_msi(struct tg3 *tp)
8905 {
8906 int err;
8907 u16 pci_cmd;
8908
8909 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8910 return 0;
8911
8912 /* Turn off SERR reporting in case MSI terminates with Master
8913 * Abort.
8914 */
8915 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8916 pci_write_config_word(tp->pdev, PCI_COMMAND,
8917 pci_cmd & ~PCI_COMMAND_SERR);
8918
8919 err = tg3_test_interrupt(tp);
8920
8921 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8922
8923 if (!err)
8924 return 0;
8925
8926 /* other failures */
8927 if (err != -EIO)
8928 return err;
8929
8930 /* MSI test failed, go back to INTx mode */
8931 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8932 "to INTx mode. Please report this failure to the PCI "
8933 "maintainer and include system chipset information\n");
8934
8935 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8936
8937 pci_disable_msi(tp->pdev);
8938
8939 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8940 tp->napi[0].irq_vec = tp->pdev->irq;
8941
8942 err = tg3_request_irq(tp, 0);
8943 if (err)
8944 return err;
8945
8946 /* Need to reset the chip because the MSI cycle may have terminated
8947 * with Master Abort.
8948 */
8949 tg3_full_lock(tp, 1);
8950
8951 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8952 err = tg3_init_hw(tp, 1);
8953
8954 tg3_full_unlock(tp);
8955
8956 if (err)
8957 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8958
8959 return err;
8960 }
8961
8962 static int tg3_request_firmware(struct tg3 *tp)
8963 {
8964 const __be32 *fw_data;
8965
8966 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8967 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8968 tp->fw_needed);
8969 return -ENOENT;
8970 }
8971
8972 fw_data = (void *)tp->fw->data;
8973
8974 /* Firmware blob starts with version numbers, followed by
8975 * start address and _full_ length including BSS sections
8976 * (which must be longer than the actual data, of course
8977 */
8978
8979 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8980 if (tp->fw_len < (tp->fw->size - 12)) {
8981 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8982 tp->fw_len, tp->fw_needed);
8983 release_firmware(tp->fw);
8984 tp->fw = NULL;
8985 return -EINVAL;
8986 }
8987
8988 /* We no longer need firmware; we have it. */
8989 tp->fw_needed = NULL;
8990 return 0;
8991 }
8992
8993 static bool tg3_enable_msix(struct tg3 *tp)
8994 {
8995 int i, rc, cpus = num_online_cpus();
8996 struct msix_entry msix_ent[tp->irq_max];
8997
8998 if (cpus == 1)
8999 /* Just fallback to the simpler MSI mode. */
9000 return false;
9001
9002 /*
9003 * We want as many rx rings enabled as there are cpus.
9004 * The first MSIX vector only deals with link interrupts, etc,
9005 * so we add one to the number of vectors we are requesting.
9006 */
9007 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9008
9009 for (i = 0; i < tp->irq_max; i++) {
9010 msix_ent[i].entry = i;
9011 msix_ent[i].vector = 0;
9012 }
9013
9014 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9015 if (rc < 0) {
9016 return false;
9017 } else if (rc != 0) {
9018 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9019 return false;
9020 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9021 tp->irq_cnt, rc);
9022 tp->irq_cnt = rc;
9023 }
9024
9025 for (i = 0; i < tp->irq_max; i++)
9026 tp->napi[i].irq_vec = msix_ent[i].vector;
9027
9028 netif_set_real_num_tx_queues(tp->dev, 1);
9029 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9030 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9031 pci_disable_msix(tp->pdev);
9032 return false;
9033 }
9034 if (tp->irq_cnt > 1)
9035 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9036
9037 return true;
9038 }
9039
9040 static void tg3_ints_init(struct tg3 *tp)
9041 {
9042 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9043 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9044 /* All MSI supporting chips should support tagged
9045 * status. Assert that this is the case.
9046 */
9047 netdev_warn(tp->dev,
9048 "MSI without TAGGED_STATUS? Not using MSI\n");
9049 goto defcfg;
9050 }
9051
9052 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9053 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9054 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9055 pci_enable_msi(tp->pdev) == 0)
9056 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9057
9058 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9059 u32 msi_mode = tr32(MSGINT_MODE);
9060 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9061 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9062 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9063 }
9064 defcfg:
9065 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9066 tp->irq_cnt = 1;
9067 tp->napi[0].irq_vec = tp->pdev->irq;
9068 netif_set_real_num_tx_queues(tp->dev, 1);
9069 netif_set_real_num_rx_queues(tp->dev, 1);
9070 }
9071 }
9072
9073 static void tg3_ints_fini(struct tg3 *tp)
9074 {
9075 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9076 pci_disable_msix(tp->pdev);
9077 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9078 pci_disable_msi(tp->pdev);
9079 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9080 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9081 }
9082
9083 static int tg3_open(struct net_device *dev)
9084 {
9085 struct tg3 *tp = netdev_priv(dev);
9086 int i, err;
9087
9088 if (tp->fw_needed) {
9089 err = tg3_request_firmware(tp);
9090 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9091 if (err)
9092 return err;
9093 } else if (err) {
9094 netdev_warn(tp->dev, "TSO capability disabled\n");
9095 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9096 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9097 netdev_notice(tp->dev, "TSO capability restored\n");
9098 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9099 }
9100 }
9101
9102 netif_carrier_off(tp->dev);
9103
9104 err = tg3_set_power_state(tp, PCI_D0);
9105 if (err)
9106 return err;
9107
9108 tg3_full_lock(tp, 0);
9109
9110 tg3_disable_ints(tp);
9111 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9112
9113 tg3_full_unlock(tp);
9114
9115 /*
9116 * Setup interrupts first so we know how
9117 * many NAPI resources to allocate
9118 */
9119 tg3_ints_init(tp);
9120
9121 /* The placement of this call is tied
9122 * to the setup and use of Host TX descriptors.
9123 */
9124 err = tg3_alloc_consistent(tp);
9125 if (err)
9126 goto err_out1;
9127
9128 tg3_napi_init(tp);
9129
9130 tg3_napi_enable(tp);
9131
9132 for (i = 0; i < tp->irq_cnt; i++) {
9133 struct tg3_napi *tnapi = &tp->napi[i];
9134 err = tg3_request_irq(tp, i);
9135 if (err) {
9136 for (i--; i >= 0; i--)
9137 free_irq(tnapi->irq_vec, tnapi);
9138 break;
9139 }
9140 }
9141
9142 if (err)
9143 goto err_out2;
9144
9145 tg3_full_lock(tp, 0);
9146
9147 err = tg3_init_hw(tp, 1);
9148 if (err) {
9149 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9150 tg3_free_rings(tp);
9151 } else {
9152 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9153 tp->timer_offset = HZ;
9154 else
9155 tp->timer_offset = HZ / 10;
9156
9157 BUG_ON(tp->timer_offset > HZ);
9158 tp->timer_counter = tp->timer_multiplier =
9159 (HZ / tp->timer_offset);
9160 tp->asf_counter = tp->asf_multiplier =
9161 ((HZ / tp->timer_offset) * 2);
9162
9163 init_timer(&tp->timer);
9164 tp->timer.expires = jiffies + tp->timer_offset;
9165 tp->timer.data = (unsigned long) tp;
9166 tp->timer.function = tg3_timer;
9167 }
9168
9169 tg3_full_unlock(tp);
9170
9171 if (err)
9172 goto err_out3;
9173
9174 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9175 err = tg3_test_msi(tp);
9176
9177 if (err) {
9178 tg3_full_lock(tp, 0);
9179 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9180 tg3_free_rings(tp);
9181 tg3_full_unlock(tp);
9182
9183 goto err_out2;
9184 }
9185
9186 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9187 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9188 u32 val = tr32(PCIE_TRANSACTION_CFG);
9189
9190 tw32(PCIE_TRANSACTION_CFG,
9191 val | PCIE_TRANS_CFG_1SHOT_MSI);
9192 }
9193 }
9194
9195 tg3_phy_start(tp);
9196
9197 tg3_full_lock(tp, 0);
9198
9199 add_timer(&tp->timer);
9200 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9201 tg3_enable_ints(tp);
9202
9203 tg3_full_unlock(tp);
9204
9205 netif_tx_start_all_queues(dev);
9206
9207 return 0;
9208
9209 err_out3:
9210 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9211 struct tg3_napi *tnapi = &tp->napi[i];
9212 free_irq(tnapi->irq_vec, tnapi);
9213 }
9214
9215 err_out2:
9216 tg3_napi_disable(tp);
9217 tg3_napi_fini(tp);
9218 tg3_free_consistent(tp);
9219
9220 err_out1:
9221 tg3_ints_fini(tp);
9222 return err;
9223 }
9224
9225 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9226 struct rtnl_link_stats64 *);
9227 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9228
9229 static int tg3_close(struct net_device *dev)
9230 {
9231 int i;
9232 struct tg3 *tp = netdev_priv(dev);
9233
9234 tg3_napi_disable(tp);
9235 cancel_work_sync(&tp->reset_task);
9236
9237 netif_tx_stop_all_queues(dev);
9238
9239 del_timer_sync(&tp->timer);
9240
9241 tg3_phy_stop(tp);
9242
9243 tg3_full_lock(tp, 1);
9244
9245 tg3_disable_ints(tp);
9246
9247 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9248 tg3_free_rings(tp);
9249 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9250
9251 tg3_full_unlock(tp);
9252
9253 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9254 struct tg3_napi *tnapi = &tp->napi[i];
9255 free_irq(tnapi->irq_vec, tnapi);
9256 }
9257
9258 tg3_ints_fini(tp);
9259
9260 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9261
9262 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9263 sizeof(tp->estats_prev));
9264
9265 tg3_napi_fini(tp);
9266
9267 tg3_free_consistent(tp);
9268
9269 tg3_set_power_state(tp, PCI_D3hot);
9270
9271 netif_carrier_off(tp->dev);
9272
9273 return 0;
9274 }
9275
9276 static inline u64 get_stat64(tg3_stat64_t *val)
9277 {
9278 return ((u64)val->high << 32) | ((u64)val->low);
9279 }
9280
9281 static u64 calc_crc_errors(struct tg3 *tp)
9282 {
9283 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9284
9285 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9286 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9287 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9288 u32 val;
9289
9290 spin_lock_bh(&tp->lock);
9291 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9292 tg3_writephy(tp, MII_TG3_TEST1,
9293 val | MII_TG3_TEST1_CRC_EN);
9294 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9295 } else
9296 val = 0;
9297 spin_unlock_bh(&tp->lock);
9298
9299 tp->phy_crc_errors += val;
9300
9301 return tp->phy_crc_errors;
9302 }
9303
9304 return get_stat64(&hw_stats->rx_fcs_errors);
9305 }
9306
9307 #define ESTAT_ADD(member) \
9308 estats->member = old_estats->member + \
9309 get_stat64(&hw_stats->member)
9310
9311 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9312 {
9313 struct tg3_ethtool_stats *estats = &tp->estats;
9314 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9315 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9316
9317 if (!hw_stats)
9318 return old_estats;
9319
9320 ESTAT_ADD(rx_octets);
9321 ESTAT_ADD(rx_fragments);
9322 ESTAT_ADD(rx_ucast_packets);
9323 ESTAT_ADD(rx_mcast_packets);
9324 ESTAT_ADD(rx_bcast_packets);
9325 ESTAT_ADD(rx_fcs_errors);
9326 ESTAT_ADD(rx_align_errors);
9327 ESTAT_ADD(rx_xon_pause_rcvd);
9328 ESTAT_ADD(rx_xoff_pause_rcvd);
9329 ESTAT_ADD(rx_mac_ctrl_rcvd);
9330 ESTAT_ADD(rx_xoff_entered);
9331 ESTAT_ADD(rx_frame_too_long_errors);
9332 ESTAT_ADD(rx_jabbers);
9333 ESTAT_ADD(rx_undersize_packets);
9334 ESTAT_ADD(rx_in_length_errors);
9335 ESTAT_ADD(rx_out_length_errors);
9336 ESTAT_ADD(rx_64_or_less_octet_packets);
9337 ESTAT_ADD(rx_65_to_127_octet_packets);
9338 ESTAT_ADD(rx_128_to_255_octet_packets);
9339 ESTAT_ADD(rx_256_to_511_octet_packets);
9340 ESTAT_ADD(rx_512_to_1023_octet_packets);
9341 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9342 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9343 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9344 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9345 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9346
9347 ESTAT_ADD(tx_octets);
9348 ESTAT_ADD(tx_collisions);
9349 ESTAT_ADD(tx_xon_sent);
9350 ESTAT_ADD(tx_xoff_sent);
9351 ESTAT_ADD(tx_flow_control);
9352 ESTAT_ADD(tx_mac_errors);
9353 ESTAT_ADD(tx_single_collisions);
9354 ESTAT_ADD(tx_mult_collisions);
9355 ESTAT_ADD(tx_deferred);
9356 ESTAT_ADD(tx_excessive_collisions);
9357 ESTAT_ADD(tx_late_collisions);
9358 ESTAT_ADD(tx_collide_2times);
9359 ESTAT_ADD(tx_collide_3times);
9360 ESTAT_ADD(tx_collide_4times);
9361 ESTAT_ADD(tx_collide_5times);
9362 ESTAT_ADD(tx_collide_6times);
9363 ESTAT_ADD(tx_collide_7times);
9364 ESTAT_ADD(tx_collide_8times);
9365 ESTAT_ADD(tx_collide_9times);
9366 ESTAT_ADD(tx_collide_10times);
9367 ESTAT_ADD(tx_collide_11times);
9368 ESTAT_ADD(tx_collide_12times);
9369 ESTAT_ADD(tx_collide_13times);
9370 ESTAT_ADD(tx_collide_14times);
9371 ESTAT_ADD(tx_collide_15times);
9372 ESTAT_ADD(tx_ucast_packets);
9373 ESTAT_ADD(tx_mcast_packets);
9374 ESTAT_ADD(tx_bcast_packets);
9375 ESTAT_ADD(tx_carrier_sense_errors);
9376 ESTAT_ADD(tx_discards);
9377 ESTAT_ADD(tx_errors);
9378
9379 ESTAT_ADD(dma_writeq_full);
9380 ESTAT_ADD(dma_write_prioq_full);
9381 ESTAT_ADD(rxbds_empty);
9382 ESTAT_ADD(rx_discards);
9383 ESTAT_ADD(rx_errors);
9384 ESTAT_ADD(rx_threshold_hit);
9385
9386 ESTAT_ADD(dma_readq_full);
9387 ESTAT_ADD(dma_read_prioq_full);
9388 ESTAT_ADD(tx_comp_queue_full);
9389
9390 ESTAT_ADD(ring_set_send_prod_index);
9391 ESTAT_ADD(ring_status_update);
9392 ESTAT_ADD(nic_irqs);
9393 ESTAT_ADD(nic_avoided_irqs);
9394 ESTAT_ADD(nic_tx_threshold_hit);
9395
9396 return estats;
9397 }
9398
9399 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9400 struct rtnl_link_stats64 *stats)
9401 {
9402 struct tg3 *tp = netdev_priv(dev);
9403 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9404 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9405
9406 if (!hw_stats)
9407 return old_stats;
9408
9409 stats->rx_packets = old_stats->rx_packets +
9410 get_stat64(&hw_stats->rx_ucast_packets) +
9411 get_stat64(&hw_stats->rx_mcast_packets) +
9412 get_stat64(&hw_stats->rx_bcast_packets);
9413
9414 stats->tx_packets = old_stats->tx_packets +
9415 get_stat64(&hw_stats->tx_ucast_packets) +
9416 get_stat64(&hw_stats->tx_mcast_packets) +
9417 get_stat64(&hw_stats->tx_bcast_packets);
9418
9419 stats->rx_bytes = old_stats->rx_bytes +
9420 get_stat64(&hw_stats->rx_octets);
9421 stats->tx_bytes = old_stats->tx_bytes +
9422 get_stat64(&hw_stats->tx_octets);
9423
9424 stats->rx_errors = old_stats->rx_errors +
9425 get_stat64(&hw_stats->rx_errors);
9426 stats->tx_errors = old_stats->tx_errors +
9427 get_stat64(&hw_stats->tx_errors) +
9428 get_stat64(&hw_stats->tx_mac_errors) +
9429 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9430 get_stat64(&hw_stats->tx_discards);
9431
9432 stats->multicast = old_stats->multicast +
9433 get_stat64(&hw_stats->rx_mcast_packets);
9434 stats->collisions = old_stats->collisions +
9435 get_stat64(&hw_stats->tx_collisions);
9436
9437 stats->rx_length_errors = old_stats->rx_length_errors +
9438 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9439 get_stat64(&hw_stats->rx_undersize_packets);
9440
9441 stats->rx_over_errors = old_stats->rx_over_errors +
9442 get_stat64(&hw_stats->rxbds_empty);
9443 stats->rx_frame_errors = old_stats->rx_frame_errors +
9444 get_stat64(&hw_stats->rx_align_errors);
9445 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9446 get_stat64(&hw_stats->tx_discards);
9447 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9448 get_stat64(&hw_stats->tx_carrier_sense_errors);
9449
9450 stats->rx_crc_errors = old_stats->rx_crc_errors +
9451 calc_crc_errors(tp);
9452
9453 stats->rx_missed_errors = old_stats->rx_missed_errors +
9454 get_stat64(&hw_stats->rx_discards);
9455
9456 stats->rx_dropped = tp->rx_dropped;
9457
9458 return stats;
9459 }
9460
9461 static inline u32 calc_crc(unsigned char *buf, int len)
9462 {
9463 u32 reg;
9464 u32 tmp;
9465 int j, k;
9466
9467 reg = 0xffffffff;
9468
9469 for (j = 0; j < len; j++) {
9470 reg ^= buf[j];
9471
9472 for (k = 0; k < 8; k++) {
9473 tmp = reg & 0x01;
9474
9475 reg >>= 1;
9476
9477 if (tmp)
9478 reg ^= 0xedb88320;
9479 }
9480 }
9481
9482 return ~reg;
9483 }
9484
9485 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9486 {
9487 /* accept or reject all multicast frames */
9488 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9489 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9490 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9491 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9492 }
9493
9494 static void __tg3_set_rx_mode(struct net_device *dev)
9495 {
9496 struct tg3 *tp = netdev_priv(dev);
9497 u32 rx_mode;
9498
9499 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9500 RX_MODE_KEEP_VLAN_TAG);
9501
9502 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9503 * flag clear.
9504 */
9505 #if TG3_VLAN_TAG_USED
9506 if (!tp->vlgrp &&
9507 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9508 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9509 #else
9510 /* By definition, VLAN is disabled always in this
9511 * case.
9512 */
9513 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9514 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9515 #endif
9516
9517 if (dev->flags & IFF_PROMISC) {
9518 /* Promiscuous mode. */
9519 rx_mode |= RX_MODE_PROMISC;
9520 } else if (dev->flags & IFF_ALLMULTI) {
9521 /* Accept all multicast. */
9522 tg3_set_multi(tp, 1);
9523 } else if (netdev_mc_empty(dev)) {
9524 /* Reject all multicast. */
9525 tg3_set_multi(tp, 0);
9526 } else {
9527 /* Accept one or more multicast(s). */
9528 struct netdev_hw_addr *ha;
9529 u32 mc_filter[4] = { 0, };
9530 u32 regidx;
9531 u32 bit;
9532 u32 crc;
9533
9534 netdev_for_each_mc_addr(ha, dev) {
9535 crc = calc_crc(ha->addr, ETH_ALEN);
9536 bit = ~crc & 0x7f;
9537 regidx = (bit & 0x60) >> 5;
9538 bit &= 0x1f;
9539 mc_filter[regidx] |= (1 << bit);
9540 }
9541
9542 tw32(MAC_HASH_REG_0, mc_filter[0]);
9543 tw32(MAC_HASH_REG_1, mc_filter[1]);
9544 tw32(MAC_HASH_REG_2, mc_filter[2]);
9545 tw32(MAC_HASH_REG_3, mc_filter[3]);
9546 }
9547
9548 if (rx_mode != tp->rx_mode) {
9549 tp->rx_mode = rx_mode;
9550 tw32_f(MAC_RX_MODE, rx_mode);
9551 udelay(10);
9552 }
9553 }
9554
9555 static void tg3_set_rx_mode(struct net_device *dev)
9556 {
9557 struct tg3 *tp = netdev_priv(dev);
9558
9559 if (!netif_running(dev))
9560 return;
9561
9562 tg3_full_lock(tp, 0);
9563 __tg3_set_rx_mode(dev);
9564 tg3_full_unlock(tp);
9565 }
9566
9567 #define TG3_REGDUMP_LEN (32 * 1024)
9568
9569 static int tg3_get_regs_len(struct net_device *dev)
9570 {
9571 return TG3_REGDUMP_LEN;
9572 }
9573
9574 static void tg3_get_regs(struct net_device *dev,
9575 struct ethtool_regs *regs, void *_p)
9576 {
9577 u32 *p = _p;
9578 struct tg3 *tp = netdev_priv(dev);
9579 u8 *orig_p = _p;
9580 int i;
9581
9582 regs->version = 0;
9583
9584 memset(p, 0, TG3_REGDUMP_LEN);
9585
9586 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9587 return;
9588
9589 tg3_full_lock(tp, 0);
9590
9591 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9592 #define GET_REG32_LOOP(base, len) \
9593 do { p = (u32 *)(orig_p + (base)); \
9594 for (i = 0; i < len; i += 4) \
9595 __GET_REG32((base) + i); \
9596 } while (0)
9597 #define GET_REG32_1(reg) \
9598 do { p = (u32 *)(orig_p + (reg)); \
9599 __GET_REG32((reg)); \
9600 } while (0)
9601
9602 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9603 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9604 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9605 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9606 GET_REG32_1(SNDDATAC_MODE);
9607 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9608 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9609 GET_REG32_1(SNDBDC_MODE);
9610 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9611 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9612 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9613 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9614 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9615 GET_REG32_1(RCVDCC_MODE);
9616 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9617 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9618 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9619 GET_REG32_1(MBFREE_MODE);
9620 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9621 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9622 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9623 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9624 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9625 GET_REG32_1(RX_CPU_MODE);
9626 GET_REG32_1(RX_CPU_STATE);
9627 GET_REG32_1(RX_CPU_PGMCTR);
9628 GET_REG32_1(RX_CPU_HWBKPT);
9629 GET_REG32_1(TX_CPU_MODE);
9630 GET_REG32_1(TX_CPU_STATE);
9631 GET_REG32_1(TX_CPU_PGMCTR);
9632 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9633 GET_REG32_LOOP(FTQ_RESET, 0x120);
9634 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9635 GET_REG32_1(DMAC_MODE);
9636 GET_REG32_LOOP(GRC_MODE, 0x4c);
9637 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9638 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9639
9640 #undef __GET_REG32
9641 #undef GET_REG32_LOOP
9642 #undef GET_REG32_1
9643
9644 tg3_full_unlock(tp);
9645 }
9646
9647 static int tg3_get_eeprom_len(struct net_device *dev)
9648 {
9649 struct tg3 *tp = netdev_priv(dev);
9650
9651 return tp->nvram_size;
9652 }
9653
9654 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9655 {
9656 struct tg3 *tp = netdev_priv(dev);
9657 int ret;
9658 u8 *pd;
9659 u32 i, offset, len, b_offset, b_count;
9660 __be32 val;
9661
9662 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9663 return -EINVAL;
9664
9665 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9666 return -EAGAIN;
9667
9668 offset = eeprom->offset;
9669 len = eeprom->len;
9670 eeprom->len = 0;
9671
9672 eeprom->magic = TG3_EEPROM_MAGIC;
9673
9674 if (offset & 3) {
9675 /* adjustments to start on required 4 byte boundary */
9676 b_offset = offset & 3;
9677 b_count = 4 - b_offset;
9678 if (b_count > len) {
9679 /* i.e. offset=1 len=2 */
9680 b_count = len;
9681 }
9682 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9683 if (ret)
9684 return ret;
9685 memcpy(data, ((char *)&val) + b_offset, b_count);
9686 len -= b_count;
9687 offset += b_count;
9688 eeprom->len += b_count;
9689 }
9690
9691 /* read bytes upto the last 4 byte boundary */
9692 pd = &data[eeprom->len];
9693 for (i = 0; i < (len - (len & 3)); i += 4) {
9694 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9695 if (ret) {
9696 eeprom->len += i;
9697 return ret;
9698 }
9699 memcpy(pd + i, &val, 4);
9700 }
9701 eeprom->len += i;
9702
9703 if (len & 3) {
9704 /* read last bytes not ending on 4 byte boundary */
9705 pd = &data[eeprom->len];
9706 b_count = len & 3;
9707 b_offset = offset + len - b_count;
9708 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9709 if (ret)
9710 return ret;
9711 memcpy(pd, &val, b_count);
9712 eeprom->len += b_count;
9713 }
9714 return 0;
9715 }
9716
9717 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9718
9719 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9720 {
9721 struct tg3 *tp = netdev_priv(dev);
9722 int ret;
9723 u32 offset, len, b_offset, odd_len;
9724 u8 *buf;
9725 __be32 start, end;
9726
9727 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9728 return -EAGAIN;
9729
9730 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9731 eeprom->magic != TG3_EEPROM_MAGIC)
9732 return -EINVAL;
9733
9734 offset = eeprom->offset;
9735 len = eeprom->len;
9736
9737 if ((b_offset = (offset & 3))) {
9738 /* adjustments to start on required 4 byte boundary */
9739 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9740 if (ret)
9741 return ret;
9742 len += b_offset;
9743 offset &= ~3;
9744 if (len < 4)
9745 len = 4;
9746 }
9747
9748 odd_len = 0;
9749 if (len & 3) {
9750 /* adjustments to end on required 4 byte boundary */
9751 odd_len = 1;
9752 len = (len + 3) & ~3;
9753 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9754 if (ret)
9755 return ret;
9756 }
9757
9758 buf = data;
9759 if (b_offset || odd_len) {
9760 buf = kmalloc(len, GFP_KERNEL);
9761 if (!buf)
9762 return -ENOMEM;
9763 if (b_offset)
9764 memcpy(buf, &start, 4);
9765 if (odd_len)
9766 memcpy(buf+len-4, &end, 4);
9767 memcpy(buf + b_offset, data, eeprom->len);
9768 }
9769
9770 ret = tg3_nvram_write_block(tp, offset, len, buf);
9771
9772 if (buf != data)
9773 kfree(buf);
9774
9775 return ret;
9776 }
9777
9778 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9779 {
9780 struct tg3 *tp = netdev_priv(dev);
9781
9782 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9783 struct phy_device *phydev;
9784 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9785 return -EAGAIN;
9786 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9787 return phy_ethtool_gset(phydev, cmd);
9788 }
9789
9790 cmd->supported = (SUPPORTED_Autoneg);
9791
9792 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9793 cmd->supported |= (SUPPORTED_1000baseT_Half |
9794 SUPPORTED_1000baseT_Full);
9795
9796 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9797 cmd->supported |= (SUPPORTED_100baseT_Half |
9798 SUPPORTED_100baseT_Full |
9799 SUPPORTED_10baseT_Half |
9800 SUPPORTED_10baseT_Full |
9801 SUPPORTED_TP);
9802 cmd->port = PORT_TP;
9803 } else {
9804 cmd->supported |= SUPPORTED_FIBRE;
9805 cmd->port = PORT_FIBRE;
9806 }
9807
9808 cmd->advertising = tp->link_config.advertising;
9809 if (netif_running(dev)) {
9810 cmd->speed = tp->link_config.active_speed;
9811 cmd->duplex = tp->link_config.active_duplex;
9812 } else {
9813 cmd->speed = SPEED_INVALID;
9814 cmd->duplex = DUPLEX_INVALID;
9815 }
9816 cmd->phy_address = tp->phy_addr;
9817 cmd->transceiver = XCVR_INTERNAL;
9818 cmd->autoneg = tp->link_config.autoneg;
9819 cmd->maxtxpkt = 0;
9820 cmd->maxrxpkt = 0;
9821 return 0;
9822 }
9823
9824 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9825 {
9826 struct tg3 *tp = netdev_priv(dev);
9827
9828 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9829 struct phy_device *phydev;
9830 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9831 return -EAGAIN;
9832 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9833 return phy_ethtool_sset(phydev, cmd);
9834 }
9835
9836 if (cmd->autoneg != AUTONEG_ENABLE &&
9837 cmd->autoneg != AUTONEG_DISABLE)
9838 return -EINVAL;
9839
9840 if (cmd->autoneg == AUTONEG_DISABLE &&
9841 cmd->duplex != DUPLEX_FULL &&
9842 cmd->duplex != DUPLEX_HALF)
9843 return -EINVAL;
9844
9845 if (cmd->autoneg == AUTONEG_ENABLE) {
9846 u32 mask = ADVERTISED_Autoneg |
9847 ADVERTISED_Pause |
9848 ADVERTISED_Asym_Pause;
9849
9850 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9851 mask |= ADVERTISED_1000baseT_Half |
9852 ADVERTISED_1000baseT_Full;
9853
9854 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9855 mask |= ADVERTISED_100baseT_Half |
9856 ADVERTISED_100baseT_Full |
9857 ADVERTISED_10baseT_Half |
9858 ADVERTISED_10baseT_Full |
9859 ADVERTISED_TP;
9860 else
9861 mask |= ADVERTISED_FIBRE;
9862
9863 if (cmd->advertising & ~mask)
9864 return -EINVAL;
9865
9866 mask &= (ADVERTISED_1000baseT_Half |
9867 ADVERTISED_1000baseT_Full |
9868 ADVERTISED_100baseT_Half |
9869 ADVERTISED_100baseT_Full |
9870 ADVERTISED_10baseT_Half |
9871 ADVERTISED_10baseT_Full);
9872
9873 cmd->advertising &= mask;
9874 } else {
9875 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9876 if (cmd->speed != SPEED_1000)
9877 return -EINVAL;
9878
9879 if (cmd->duplex != DUPLEX_FULL)
9880 return -EINVAL;
9881 } else {
9882 if (cmd->speed != SPEED_100 &&
9883 cmd->speed != SPEED_10)
9884 return -EINVAL;
9885 }
9886 }
9887
9888 tg3_full_lock(tp, 0);
9889
9890 tp->link_config.autoneg = cmd->autoneg;
9891 if (cmd->autoneg == AUTONEG_ENABLE) {
9892 tp->link_config.advertising = (cmd->advertising |
9893 ADVERTISED_Autoneg);
9894 tp->link_config.speed = SPEED_INVALID;
9895 tp->link_config.duplex = DUPLEX_INVALID;
9896 } else {
9897 tp->link_config.advertising = 0;
9898 tp->link_config.speed = cmd->speed;
9899 tp->link_config.duplex = cmd->duplex;
9900 }
9901
9902 tp->link_config.orig_speed = tp->link_config.speed;
9903 tp->link_config.orig_duplex = tp->link_config.duplex;
9904 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9905
9906 if (netif_running(dev))
9907 tg3_setup_phy(tp, 1);
9908
9909 tg3_full_unlock(tp);
9910
9911 return 0;
9912 }
9913
9914 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9915 {
9916 struct tg3 *tp = netdev_priv(dev);
9917
9918 strcpy(info->driver, DRV_MODULE_NAME);
9919 strcpy(info->version, DRV_MODULE_VERSION);
9920 strcpy(info->fw_version, tp->fw_ver);
9921 strcpy(info->bus_info, pci_name(tp->pdev));
9922 }
9923
9924 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9925 {
9926 struct tg3 *tp = netdev_priv(dev);
9927
9928 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9929 device_can_wakeup(&tp->pdev->dev))
9930 wol->supported = WAKE_MAGIC;
9931 else
9932 wol->supported = 0;
9933 wol->wolopts = 0;
9934 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9935 device_can_wakeup(&tp->pdev->dev))
9936 wol->wolopts = WAKE_MAGIC;
9937 memset(&wol->sopass, 0, sizeof(wol->sopass));
9938 }
9939
9940 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9941 {
9942 struct tg3 *tp = netdev_priv(dev);
9943 struct device *dp = &tp->pdev->dev;
9944
9945 if (wol->wolopts & ~WAKE_MAGIC)
9946 return -EINVAL;
9947 if ((wol->wolopts & WAKE_MAGIC) &&
9948 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9949 return -EINVAL;
9950
9951 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
9952
9953 spin_lock_bh(&tp->lock);
9954 if (device_may_wakeup(dp))
9955 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9956 else
9957 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9958 spin_unlock_bh(&tp->lock);
9959
9960
9961 return 0;
9962 }
9963
9964 static u32 tg3_get_msglevel(struct net_device *dev)
9965 {
9966 struct tg3 *tp = netdev_priv(dev);
9967 return tp->msg_enable;
9968 }
9969
9970 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9971 {
9972 struct tg3 *tp = netdev_priv(dev);
9973 tp->msg_enable = value;
9974 }
9975
9976 static int tg3_set_tso(struct net_device *dev, u32 value)
9977 {
9978 struct tg3 *tp = netdev_priv(dev);
9979
9980 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9981 if (value)
9982 return -EINVAL;
9983 return 0;
9984 }
9985 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9986 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9987 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9988 if (value) {
9989 dev->features |= NETIF_F_TSO6;
9990 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9991 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9992 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9993 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9995 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9996 dev->features |= NETIF_F_TSO_ECN;
9997 } else
9998 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9999 }
10000 return ethtool_op_set_tso(dev, value);
10001 }
10002
10003 static int tg3_nway_reset(struct net_device *dev)
10004 {
10005 struct tg3 *tp = netdev_priv(dev);
10006 int r;
10007
10008 if (!netif_running(dev))
10009 return -EAGAIN;
10010
10011 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10012 return -EINVAL;
10013
10014 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10015 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10016 return -EAGAIN;
10017 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10018 } else {
10019 u32 bmcr;
10020
10021 spin_lock_bh(&tp->lock);
10022 r = -EINVAL;
10023 tg3_readphy(tp, MII_BMCR, &bmcr);
10024 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10025 ((bmcr & BMCR_ANENABLE) ||
10026 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10027 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10028 BMCR_ANENABLE);
10029 r = 0;
10030 }
10031 spin_unlock_bh(&tp->lock);
10032 }
10033
10034 return r;
10035 }
10036
10037 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10038 {
10039 struct tg3 *tp = netdev_priv(dev);
10040
10041 ering->rx_max_pending = tp->rx_std_ring_mask;
10042 ering->rx_mini_max_pending = 0;
10043 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10044 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10045 else
10046 ering->rx_jumbo_max_pending = 0;
10047
10048 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10049
10050 ering->rx_pending = tp->rx_pending;
10051 ering->rx_mini_pending = 0;
10052 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10053 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10054 else
10055 ering->rx_jumbo_pending = 0;
10056
10057 ering->tx_pending = tp->napi[0].tx_pending;
10058 }
10059
10060 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10061 {
10062 struct tg3 *tp = netdev_priv(dev);
10063 int i, irq_sync = 0, err = 0;
10064
10065 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10066 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10067 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10068 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10069 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10070 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10071 return -EINVAL;
10072
10073 if (netif_running(dev)) {
10074 tg3_phy_stop(tp);
10075 tg3_netif_stop(tp);
10076 irq_sync = 1;
10077 }
10078
10079 tg3_full_lock(tp, irq_sync);
10080
10081 tp->rx_pending = ering->rx_pending;
10082
10083 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10084 tp->rx_pending > 63)
10085 tp->rx_pending = 63;
10086 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10087
10088 for (i = 0; i < tp->irq_max; i++)
10089 tp->napi[i].tx_pending = ering->tx_pending;
10090
10091 if (netif_running(dev)) {
10092 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10093 err = tg3_restart_hw(tp, 1);
10094 if (!err)
10095 tg3_netif_start(tp);
10096 }
10097
10098 tg3_full_unlock(tp);
10099
10100 if (irq_sync && !err)
10101 tg3_phy_start(tp);
10102
10103 return err;
10104 }
10105
10106 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10107 {
10108 struct tg3 *tp = netdev_priv(dev);
10109
10110 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10111
10112 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10113 epause->rx_pause = 1;
10114 else
10115 epause->rx_pause = 0;
10116
10117 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10118 epause->tx_pause = 1;
10119 else
10120 epause->tx_pause = 0;
10121 }
10122
10123 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10124 {
10125 struct tg3 *tp = netdev_priv(dev);
10126 int err = 0;
10127
10128 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10129 u32 newadv;
10130 struct phy_device *phydev;
10131
10132 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10133
10134 if (!(phydev->supported & SUPPORTED_Pause) ||
10135 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10136 (epause->rx_pause != epause->tx_pause)))
10137 return -EINVAL;
10138
10139 tp->link_config.flowctrl = 0;
10140 if (epause->rx_pause) {
10141 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10142
10143 if (epause->tx_pause) {
10144 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10145 newadv = ADVERTISED_Pause;
10146 } else
10147 newadv = ADVERTISED_Pause |
10148 ADVERTISED_Asym_Pause;
10149 } else if (epause->tx_pause) {
10150 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10151 newadv = ADVERTISED_Asym_Pause;
10152 } else
10153 newadv = 0;
10154
10155 if (epause->autoneg)
10156 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10157 else
10158 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10159
10160 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10161 u32 oldadv = phydev->advertising &
10162 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10163 if (oldadv != newadv) {
10164 phydev->advertising &=
10165 ~(ADVERTISED_Pause |
10166 ADVERTISED_Asym_Pause);
10167 phydev->advertising |= newadv;
10168 if (phydev->autoneg) {
10169 /*
10170 * Always renegotiate the link to
10171 * inform our link partner of our
10172 * flow control settings, even if the
10173 * flow control is forced. Let
10174 * tg3_adjust_link() do the final
10175 * flow control setup.
10176 */
10177 return phy_start_aneg(phydev);
10178 }
10179 }
10180
10181 if (!epause->autoneg)
10182 tg3_setup_flow_control(tp, 0, 0);
10183 } else {
10184 tp->link_config.orig_advertising &=
10185 ~(ADVERTISED_Pause |
10186 ADVERTISED_Asym_Pause);
10187 tp->link_config.orig_advertising |= newadv;
10188 }
10189 } else {
10190 int irq_sync = 0;
10191
10192 if (netif_running(dev)) {
10193 tg3_netif_stop(tp);
10194 irq_sync = 1;
10195 }
10196
10197 tg3_full_lock(tp, irq_sync);
10198
10199 if (epause->autoneg)
10200 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10201 else
10202 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10203 if (epause->rx_pause)
10204 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10205 else
10206 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10207 if (epause->tx_pause)
10208 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10209 else
10210 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10211
10212 if (netif_running(dev)) {
10213 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10214 err = tg3_restart_hw(tp, 1);
10215 if (!err)
10216 tg3_netif_start(tp);
10217 }
10218
10219 tg3_full_unlock(tp);
10220 }
10221
10222 return err;
10223 }
10224
10225 static u32 tg3_get_rx_csum(struct net_device *dev)
10226 {
10227 struct tg3 *tp = netdev_priv(dev);
10228 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10229 }
10230
10231 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10232 {
10233 struct tg3 *tp = netdev_priv(dev);
10234
10235 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10236 if (data != 0)
10237 return -EINVAL;
10238 return 0;
10239 }
10240
10241 spin_lock_bh(&tp->lock);
10242 if (data)
10243 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10244 else
10245 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10246 spin_unlock_bh(&tp->lock);
10247
10248 return 0;
10249 }
10250
10251 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10252 {
10253 struct tg3 *tp = netdev_priv(dev);
10254
10255 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10256 if (data != 0)
10257 return -EINVAL;
10258 return 0;
10259 }
10260
10261 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10262 ethtool_op_set_tx_ipv6_csum(dev, data);
10263 else
10264 ethtool_op_set_tx_csum(dev, data);
10265
10266 return 0;
10267 }
10268
10269 static int tg3_get_sset_count(struct net_device *dev, int sset)
10270 {
10271 switch (sset) {
10272 case ETH_SS_TEST:
10273 return TG3_NUM_TEST;
10274 case ETH_SS_STATS:
10275 return TG3_NUM_STATS;
10276 default:
10277 return -EOPNOTSUPP;
10278 }
10279 }
10280
10281 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10282 {
10283 switch (stringset) {
10284 case ETH_SS_STATS:
10285 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10286 break;
10287 case ETH_SS_TEST:
10288 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10289 break;
10290 default:
10291 WARN_ON(1); /* we need a WARN() */
10292 break;
10293 }
10294 }
10295
10296 static int tg3_phys_id(struct net_device *dev, u32 data)
10297 {
10298 struct tg3 *tp = netdev_priv(dev);
10299 int i;
10300
10301 if (!netif_running(tp->dev))
10302 return -EAGAIN;
10303
10304 if (data == 0)
10305 data = UINT_MAX / 2;
10306
10307 for (i = 0; i < (data * 2); i++) {
10308 if ((i % 2) == 0)
10309 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10310 LED_CTRL_1000MBPS_ON |
10311 LED_CTRL_100MBPS_ON |
10312 LED_CTRL_10MBPS_ON |
10313 LED_CTRL_TRAFFIC_OVERRIDE |
10314 LED_CTRL_TRAFFIC_BLINK |
10315 LED_CTRL_TRAFFIC_LED);
10316
10317 else
10318 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10319 LED_CTRL_TRAFFIC_OVERRIDE);
10320
10321 if (msleep_interruptible(500))
10322 break;
10323 }
10324 tw32(MAC_LED_CTRL, tp->led_ctrl);
10325 return 0;
10326 }
10327
10328 static void tg3_get_ethtool_stats(struct net_device *dev,
10329 struct ethtool_stats *estats, u64 *tmp_stats)
10330 {
10331 struct tg3 *tp = netdev_priv(dev);
10332 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10333 }
10334
10335 #define NVRAM_TEST_SIZE 0x100
10336 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10337 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10338 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10339 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10340 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10341
10342 static int tg3_test_nvram(struct tg3 *tp)
10343 {
10344 u32 csum, magic;
10345 __be32 *buf;
10346 int i, j, k, err = 0, size;
10347
10348 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10349 return 0;
10350
10351 if (tg3_nvram_read(tp, 0, &magic) != 0)
10352 return -EIO;
10353
10354 if (magic == TG3_EEPROM_MAGIC)
10355 size = NVRAM_TEST_SIZE;
10356 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10357 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10358 TG3_EEPROM_SB_FORMAT_1) {
10359 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10360 case TG3_EEPROM_SB_REVISION_0:
10361 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10362 break;
10363 case TG3_EEPROM_SB_REVISION_2:
10364 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10365 break;
10366 case TG3_EEPROM_SB_REVISION_3:
10367 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10368 break;
10369 default:
10370 return 0;
10371 }
10372 } else
10373 return 0;
10374 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10375 size = NVRAM_SELFBOOT_HW_SIZE;
10376 else
10377 return -EIO;
10378
10379 buf = kmalloc(size, GFP_KERNEL);
10380 if (buf == NULL)
10381 return -ENOMEM;
10382
10383 err = -EIO;
10384 for (i = 0, j = 0; i < size; i += 4, j++) {
10385 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10386 if (err)
10387 break;
10388 }
10389 if (i < size)
10390 goto out;
10391
10392 /* Selfboot format */
10393 magic = be32_to_cpu(buf[0]);
10394 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10395 TG3_EEPROM_MAGIC_FW) {
10396 u8 *buf8 = (u8 *) buf, csum8 = 0;
10397
10398 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10399 TG3_EEPROM_SB_REVISION_2) {
10400 /* For rev 2, the csum doesn't include the MBA. */
10401 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10402 csum8 += buf8[i];
10403 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10404 csum8 += buf8[i];
10405 } else {
10406 for (i = 0; i < size; i++)
10407 csum8 += buf8[i];
10408 }
10409
10410 if (csum8 == 0) {
10411 err = 0;
10412 goto out;
10413 }
10414
10415 err = -EIO;
10416 goto out;
10417 }
10418
10419 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10420 TG3_EEPROM_MAGIC_HW) {
10421 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10422 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10423 u8 *buf8 = (u8 *) buf;
10424
10425 /* Separate the parity bits and the data bytes. */
10426 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10427 if ((i == 0) || (i == 8)) {
10428 int l;
10429 u8 msk;
10430
10431 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10432 parity[k++] = buf8[i] & msk;
10433 i++;
10434 } else if (i == 16) {
10435 int l;
10436 u8 msk;
10437
10438 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10439 parity[k++] = buf8[i] & msk;
10440 i++;
10441
10442 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10443 parity[k++] = buf8[i] & msk;
10444 i++;
10445 }
10446 data[j++] = buf8[i];
10447 }
10448
10449 err = -EIO;
10450 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10451 u8 hw8 = hweight8(data[i]);
10452
10453 if ((hw8 & 0x1) && parity[i])
10454 goto out;
10455 else if (!(hw8 & 0x1) && !parity[i])
10456 goto out;
10457 }
10458 err = 0;
10459 goto out;
10460 }
10461
10462 /* Bootstrap checksum at offset 0x10 */
10463 csum = calc_crc((unsigned char *) buf, 0x10);
10464 if (csum != be32_to_cpu(buf[0x10/4]))
10465 goto out;
10466
10467 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10468 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10469 if (csum != be32_to_cpu(buf[0xfc/4]))
10470 goto out;
10471
10472 err = 0;
10473
10474 out:
10475 kfree(buf);
10476 return err;
10477 }
10478
10479 #define TG3_SERDES_TIMEOUT_SEC 2
10480 #define TG3_COPPER_TIMEOUT_SEC 6
10481
10482 static int tg3_test_link(struct tg3 *tp)
10483 {
10484 int i, max;
10485
10486 if (!netif_running(tp->dev))
10487 return -ENODEV;
10488
10489 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10490 max = TG3_SERDES_TIMEOUT_SEC;
10491 else
10492 max = TG3_COPPER_TIMEOUT_SEC;
10493
10494 for (i = 0; i < max; i++) {
10495 if (netif_carrier_ok(tp->dev))
10496 return 0;
10497
10498 if (msleep_interruptible(1000))
10499 break;
10500 }
10501
10502 return -EIO;
10503 }
10504
10505 /* Only test the commonly used registers */
10506 static int tg3_test_registers(struct tg3 *tp)
10507 {
10508 int i, is_5705, is_5750;
10509 u32 offset, read_mask, write_mask, val, save_val, read_val;
10510 static struct {
10511 u16 offset;
10512 u16 flags;
10513 #define TG3_FL_5705 0x1
10514 #define TG3_FL_NOT_5705 0x2
10515 #define TG3_FL_NOT_5788 0x4
10516 #define TG3_FL_NOT_5750 0x8
10517 u32 read_mask;
10518 u32 write_mask;
10519 } reg_tbl[] = {
10520 /* MAC Control Registers */
10521 { MAC_MODE, TG3_FL_NOT_5705,
10522 0x00000000, 0x00ef6f8c },
10523 { MAC_MODE, TG3_FL_5705,
10524 0x00000000, 0x01ef6b8c },
10525 { MAC_STATUS, TG3_FL_NOT_5705,
10526 0x03800107, 0x00000000 },
10527 { MAC_STATUS, TG3_FL_5705,
10528 0x03800100, 0x00000000 },
10529 { MAC_ADDR_0_HIGH, 0x0000,
10530 0x00000000, 0x0000ffff },
10531 { MAC_ADDR_0_LOW, 0x0000,
10532 0x00000000, 0xffffffff },
10533 { MAC_RX_MTU_SIZE, 0x0000,
10534 0x00000000, 0x0000ffff },
10535 { MAC_TX_MODE, 0x0000,
10536 0x00000000, 0x00000070 },
10537 { MAC_TX_LENGTHS, 0x0000,
10538 0x00000000, 0x00003fff },
10539 { MAC_RX_MODE, TG3_FL_NOT_5705,
10540 0x00000000, 0x000007fc },
10541 { MAC_RX_MODE, TG3_FL_5705,
10542 0x00000000, 0x000007dc },
10543 { MAC_HASH_REG_0, 0x0000,
10544 0x00000000, 0xffffffff },
10545 { MAC_HASH_REG_1, 0x0000,
10546 0x00000000, 0xffffffff },
10547 { MAC_HASH_REG_2, 0x0000,
10548 0x00000000, 0xffffffff },
10549 { MAC_HASH_REG_3, 0x0000,
10550 0x00000000, 0xffffffff },
10551
10552 /* Receive Data and Receive BD Initiator Control Registers. */
10553 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10554 0x00000000, 0xffffffff },
10555 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10556 0x00000000, 0xffffffff },
10557 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10558 0x00000000, 0x00000003 },
10559 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10560 0x00000000, 0xffffffff },
10561 { RCVDBDI_STD_BD+0, 0x0000,
10562 0x00000000, 0xffffffff },
10563 { RCVDBDI_STD_BD+4, 0x0000,
10564 0x00000000, 0xffffffff },
10565 { RCVDBDI_STD_BD+8, 0x0000,
10566 0x00000000, 0xffff0002 },
10567 { RCVDBDI_STD_BD+0xc, 0x0000,
10568 0x00000000, 0xffffffff },
10569
10570 /* Receive BD Initiator Control Registers. */
10571 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10572 0x00000000, 0xffffffff },
10573 { RCVBDI_STD_THRESH, TG3_FL_5705,
10574 0x00000000, 0x000003ff },
10575 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10576 0x00000000, 0xffffffff },
10577
10578 /* Host Coalescing Control Registers. */
10579 { HOSTCC_MODE, TG3_FL_NOT_5705,
10580 0x00000000, 0x00000004 },
10581 { HOSTCC_MODE, TG3_FL_5705,
10582 0x00000000, 0x000000f6 },
10583 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10584 0x00000000, 0xffffffff },
10585 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10586 0x00000000, 0x000003ff },
10587 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10588 0x00000000, 0xffffffff },
10589 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10590 0x00000000, 0x000003ff },
10591 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10592 0x00000000, 0xffffffff },
10593 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10594 0x00000000, 0x000000ff },
10595 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10596 0x00000000, 0xffffffff },
10597 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10598 0x00000000, 0x000000ff },
10599 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10600 0x00000000, 0xffffffff },
10601 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10602 0x00000000, 0xffffffff },
10603 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10604 0x00000000, 0xffffffff },
10605 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10606 0x00000000, 0x000000ff },
10607 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10608 0x00000000, 0xffffffff },
10609 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10610 0x00000000, 0x000000ff },
10611 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10612 0x00000000, 0xffffffff },
10613 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10614 0x00000000, 0xffffffff },
10615 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10616 0x00000000, 0xffffffff },
10617 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10618 0x00000000, 0xffffffff },
10619 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10620 0x00000000, 0xffffffff },
10621 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10622 0xffffffff, 0x00000000 },
10623 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10624 0xffffffff, 0x00000000 },
10625
10626 /* Buffer Manager Control Registers. */
10627 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10628 0x00000000, 0x007fff80 },
10629 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10630 0x00000000, 0x007fffff },
10631 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10632 0x00000000, 0x0000003f },
10633 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10634 0x00000000, 0x000001ff },
10635 { BUFMGR_MB_HIGH_WATER, 0x0000,
10636 0x00000000, 0x000001ff },
10637 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10638 0xffffffff, 0x00000000 },
10639 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10640 0xffffffff, 0x00000000 },
10641
10642 /* Mailbox Registers */
10643 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10644 0x00000000, 0x000001ff },
10645 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10646 0x00000000, 0x000001ff },
10647 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10648 0x00000000, 0x000007ff },
10649 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10650 0x00000000, 0x000001ff },
10651
10652 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10653 };
10654
10655 is_5705 = is_5750 = 0;
10656 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10657 is_5705 = 1;
10658 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10659 is_5750 = 1;
10660 }
10661
10662 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10663 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10664 continue;
10665
10666 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10667 continue;
10668
10669 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10670 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10671 continue;
10672
10673 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10674 continue;
10675
10676 offset = (u32) reg_tbl[i].offset;
10677 read_mask = reg_tbl[i].read_mask;
10678 write_mask = reg_tbl[i].write_mask;
10679
10680 /* Save the original register content */
10681 save_val = tr32(offset);
10682
10683 /* Determine the read-only value. */
10684 read_val = save_val & read_mask;
10685
10686 /* Write zero to the register, then make sure the read-only bits
10687 * are not changed and the read/write bits are all zeros.
10688 */
10689 tw32(offset, 0);
10690
10691 val = tr32(offset);
10692
10693 /* Test the read-only and read/write bits. */
10694 if (((val & read_mask) != read_val) || (val & write_mask))
10695 goto out;
10696
10697 /* Write ones to all the bits defined by RdMask and WrMask, then
10698 * make sure the read-only bits are not changed and the
10699 * read/write bits are all ones.
10700 */
10701 tw32(offset, read_mask | write_mask);
10702
10703 val = tr32(offset);
10704
10705 /* Test the read-only bits. */
10706 if ((val & read_mask) != read_val)
10707 goto out;
10708
10709 /* Test the read/write bits. */
10710 if ((val & write_mask) != write_mask)
10711 goto out;
10712
10713 tw32(offset, save_val);
10714 }
10715
10716 return 0;
10717
10718 out:
10719 if (netif_msg_hw(tp))
10720 netdev_err(tp->dev,
10721 "Register test failed at offset %x\n", offset);
10722 tw32(offset, save_val);
10723 return -EIO;
10724 }
10725
10726 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10727 {
10728 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10729 int i;
10730 u32 j;
10731
10732 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10733 for (j = 0; j < len; j += 4) {
10734 u32 val;
10735
10736 tg3_write_mem(tp, offset + j, test_pattern[i]);
10737 tg3_read_mem(tp, offset + j, &val);
10738 if (val != test_pattern[i])
10739 return -EIO;
10740 }
10741 }
10742 return 0;
10743 }
10744
10745 static int tg3_test_memory(struct tg3 *tp)
10746 {
10747 static struct mem_entry {
10748 u32 offset;
10749 u32 len;
10750 } mem_tbl_570x[] = {
10751 { 0x00000000, 0x00b50},
10752 { 0x00002000, 0x1c000},
10753 { 0xffffffff, 0x00000}
10754 }, mem_tbl_5705[] = {
10755 { 0x00000100, 0x0000c},
10756 { 0x00000200, 0x00008},
10757 { 0x00004000, 0x00800},
10758 { 0x00006000, 0x01000},
10759 { 0x00008000, 0x02000},
10760 { 0x00010000, 0x0e000},
10761 { 0xffffffff, 0x00000}
10762 }, mem_tbl_5755[] = {
10763 { 0x00000200, 0x00008},
10764 { 0x00004000, 0x00800},
10765 { 0x00006000, 0x00800},
10766 { 0x00008000, 0x02000},
10767 { 0x00010000, 0x0c000},
10768 { 0xffffffff, 0x00000}
10769 }, mem_tbl_5906[] = {
10770 { 0x00000200, 0x00008},
10771 { 0x00004000, 0x00400},
10772 { 0x00006000, 0x00400},
10773 { 0x00008000, 0x01000},
10774 { 0x00010000, 0x01000},
10775 { 0xffffffff, 0x00000}
10776 }, mem_tbl_5717[] = {
10777 { 0x00000200, 0x00008},
10778 { 0x00010000, 0x0a000},
10779 { 0x00020000, 0x13c00},
10780 { 0xffffffff, 0x00000}
10781 }, mem_tbl_57765[] = {
10782 { 0x00000200, 0x00008},
10783 { 0x00004000, 0x00800},
10784 { 0x00006000, 0x09800},
10785 { 0x00010000, 0x0a000},
10786 { 0xffffffff, 0x00000}
10787 };
10788 struct mem_entry *mem_tbl;
10789 int err = 0;
10790 int i;
10791
10792 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10793 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10794 mem_tbl = mem_tbl_5717;
10795 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10796 mem_tbl = mem_tbl_57765;
10797 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10798 mem_tbl = mem_tbl_5755;
10799 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10800 mem_tbl = mem_tbl_5906;
10801 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10802 mem_tbl = mem_tbl_5705;
10803 else
10804 mem_tbl = mem_tbl_570x;
10805
10806 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10807 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10808 if (err)
10809 break;
10810 }
10811
10812 return err;
10813 }
10814
10815 #define TG3_MAC_LOOPBACK 0
10816 #define TG3_PHY_LOOPBACK 1
10817
10818 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10819 {
10820 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10821 u32 desc_idx, coal_now;
10822 struct sk_buff *skb, *rx_skb;
10823 u8 *tx_data;
10824 dma_addr_t map;
10825 int num_pkts, tx_len, rx_len, i, err;
10826 struct tg3_rx_buffer_desc *desc;
10827 struct tg3_napi *tnapi, *rnapi;
10828 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10829
10830 tnapi = &tp->napi[0];
10831 rnapi = &tp->napi[0];
10832 if (tp->irq_cnt > 1) {
10833 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10834 rnapi = &tp->napi[1];
10835 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10836 tnapi = &tp->napi[1];
10837 }
10838 coal_now = tnapi->coal_now | rnapi->coal_now;
10839
10840 if (loopback_mode == TG3_MAC_LOOPBACK) {
10841 /* HW errata - mac loopback fails in some cases on 5780.
10842 * Normal traffic and PHY loopback are not affected by
10843 * errata.
10844 */
10845 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10846 return 0;
10847
10848 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10849 MAC_MODE_PORT_INT_LPBACK;
10850 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10851 mac_mode |= MAC_MODE_LINK_POLARITY;
10852 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10853 mac_mode |= MAC_MODE_PORT_MODE_MII;
10854 else
10855 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10856 tw32(MAC_MODE, mac_mode);
10857 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10858 u32 val;
10859
10860 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10861 tg3_phy_fet_toggle_apd(tp, false);
10862 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10863 } else
10864 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10865
10866 tg3_phy_toggle_automdix(tp, 0);
10867
10868 tg3_writephy(tp, MII_BMCR, val);
10869 udelay(40);
10870
10871 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10872 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10873 tg3_writephy(tp, MII_TG3_FET_PTEST,
10874 MII_TG3_FET_PTEST_FRC_TX_LINK |
10875 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10876 /* The write needs to be flushed for the AC131 */
10877 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10878 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10879 mac_mode |= MAC_MODE_PORT_MODE_MII;
10880 } else
10881 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10882
10883 /* reset to prevent losing 1st rx packet intermittently */
10884 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10885 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10886 udelay(10);
10887 tw32_f(MAC_RX_MODE, tp->rx_mode);
10888 }
10889 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10890 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10891 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10892 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10893 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10894 mac_mode |= MAC_MODE_LINK_POLARITY;
10895 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10896 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10897 }
10898 tw32(MAC_MODE, mac_mode);
10899 } else {
10900 return -EINVAL;
10901 }
10902
10903 err = -EIO;
10904
10905 tx_len = 1514;
10906 skb = netdev_alloc_skb(tp->dev, tx_len);
10907 if (!skb)
10908 return -ENOMEM;
10909
10910 tx_data = skb_put(skb, tx_len);
10911 memcpy(tx_data, tp->dev->dev_addr, 6);
10912 memset(tx_data + 6, 0x0, 8);
10913
10914 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10915
10916 for (i = 14; i < tx_len; i++)
10917 tx_data[i] = (u8) (i & 0xff);
10918
10919 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10920 if (pci_dma_mapping_error(tp->pdev, map)) {
10921 dev_kfree_skb(skb);
10922 return -EIO;
10923 }
10924
10925 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10926 rnapi->coal_now);
10927
10928 udelay(10);
10929
10930 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10931
10932 num_pkts = 0;
10933
10934 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10935
10936 tnapi->tx_prod++;
10937 num_pkts++;
10938
10939 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10940 tr32_mailbox(tnapi->prodmbox);
10941
10942 udelay(10);
10943
10944 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10945 for (i = 0; i < 35; i++) {
10946 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10947 coal_now);
10948
10949 udelay(10);
10950
10951 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10952 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10953 if ((tx_idx == tnapi->tx_prod) &&
10954 (rx_idx == (rx_start_idx + num_pkts)))
10955 break;
10956 }
10957
10958 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10959 dev_kfree_skb(skb);
10960
10961 if (tx_idx != tnapi->tx_prod)
10962 goto out;
10963
10964 if (rx_idx != rx_start_idx + num_pkts)
10965 goto out;
10966
10967 desc = &rnapi->rx_rcb[rx_start_idx];
10968 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10969 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10970 if (opaque_key != RXD_OPAQUE_RING_STD)
10971 goto out;
10972
10973 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10974 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10975 goto out;
10976
10977 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10978 if (rx_len != tx_len)
10979 goto out;
10980
10981 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10982
10983 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10984 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10985
10986 for (i = 14; i < tx_len; i++) {
10987 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10988 goto out;
10989 }
10990 err = 0;
10991
10992 /* tg3_free_rings will unmap and free the rx_skb */
10993 out:
10994 return err;
10995 }
10996
10997 #define TG3_MAC_LOOPBACK_FAILED 1
10998 #define TG3_PHY_LOOPBACK_FAILED 2
10999 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
11000 TG3_PHY_LOOPBACK_FAILED)
11001
11002 static int tg3_test_loopback(struct tg3 *tp)
11003 {
11004 int err = 0;
11005 u32 cpmuctrl = 0;
11006
11007 if (!netif_running(tp->dev))
11008 return TG3_LOOPBACK_FAILED;
11009
11010 err = tg3_reset_hw(tp, 1);
11011 if (err)
11012 return TG3_LOOPBACK_FAILED;
11013
11014 /* Turn off gphy autopowerdown. */
11015 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11016 tg3_phy_toggle_apd(tp, false);
11017
11018 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11019 int i;
11020 u32 status;
11021
11022 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11023
11024 /* Wait for up to 40 microseconds to acquire lock. */
11025 for (i = 0; i < 4; i++) {
11026 status = tr32(TG3_CPMU_MUTEX_GNT);
11027 if (status == CPMU_MUTEX_GNT_DRIVER)
11028 break;
11029 udelay(10);
11030 }
11031
11032 if (status != CPMU_MUTEX_GNT_DRIVER)
11033 return TG3_LOOPBACK_FAILED;
11034
11035 /* Turn off link-based power management. */
11036 cpmuctrl = tr32(TG3_CPMU_CTRL);
11037 tw32(TG3_CPMU_CTRL,
11038 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11039 CPMU_CTRL_LINK_AWARE_MODE));
11040 }
11041
11042 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11043 err |= TG3_MAC_LOOPBACK_FAILED;
11044
11045 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11046 tw32(TG3_CPMU_CTRL, cpmuctrl);
11047
11048 /* Release the mutex */
11049 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11050 }
11051
11052 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11053 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11054 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11055 err |= TG3_PHY_LOOPBACK_FAILED;
11056 }
11057
11058 /* Re-enable gphy autopowerdown. */
11059 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11060 tg3_phy_toggle_apd(tp, true);
11061
11062 return err;
11063 }
11064
11065 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11066 u64 *data)
11067 {
11068 struct tg3 *tp = netdev_priv(dev);
11069
11070 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11071 tg3_set_power_state(tp, PCI_D0);
11072
11073 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11074
11075 if (tg3_test_nvram(tp) != 0) {
11076 etest->flags |= ETH_TEST_FL_FAILED;
11077 data[0] = 1;
11078 }
11079 if (tg3_test_link(tp) != 0) {
11080 etest->flags |= ETH_TEST_FL_FAILED;
11081 data[1] = 1;
11082 }
11083 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11084 int err, err2 = 0, irq_sync = 0;
11085
11086 if (netif_running(dev)) {
11087 tg3_phy_stop(tp);
11088 tg3_netif_stop(tp);
11089 irq_sync = 1;
11090 }
11091
11092 tg3_full_lock(tp, irq_sync);
11093
11094 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11095 err = tg3_nvram_lock(tp);
11096 tg3_halt_cpu(tp, RX_CPU_BASE);
11097 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11098 tg3_halt_cpu(tp, TX_CPU_BASE);
11099 if (!err)
11100 tg3_nvram_unlock(tp);
11101
11102 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11103 tg3_phy_reset(tp);
11104
11105 if (tg3_test_registers(tp) != 0) {
11106 etest->flags |= ETH_TEST_FL_FAILED;
11107 data[2] = 1;
11108 }
11109 if (tg3_test_memory(tp) != 0) {
11110 etest->flags |= ETH_TEST_FL_FAILED;
11111 data[3] = 1;
11112 }
11113 if ((data[4] = tg3_test_loopback(tp)) != 0)
11114 etest->flags |= ETH_TEST_FL_FAILED;
11115
11116 tg3_full_unlock(tp);
11117
11118 if (tg3_test_interrupt(tp) != 0) {
11119 etest->flags |= ETH_TEST_FL_FAILED;
11120 data[5] = 1;
11121 }
11122
11123 tg3_full_lock(tp, 0);
11124
11125 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11126 if (netif_running(dev)) {
11127 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11128 err2 = tg3_restart_hw(tp, 1);
11129 if (!err2)
11130 tg3_netif_start(tp);
11131 }
11132
11133 tg3_full_unlock(tp);
11134
11135 if (irq_sync && !err2)
11136 tg3_phy_start(tp);
11137 }
11138 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11139 tg3_set_power_state(tp, PCI_D3hot);
11140
11141 }
11142
11143 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11144 {
11145 struct mii_ioctl_data *data = if_mii(ifr);
11146 struct tg3 *tp = netdev_priv(dev);
11147 int err;
11148
11149 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11150 struct phy_device *phydev;
11151 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11152 return -EAGAIN;
11153 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11154 return phy_mii_ioctl(phydev, ifr, cmd);
11155 }
11156
11157 switch (cmd) {
11158 case SIOCGMIIPHY:
11159 data->phy_id = tp->phy_addr;
11160
11161 /* fallthru */
11162 case SIOCGMIIREG: {
11163 u32 mii_regval;
11164
11165 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11166 break; /* We have no PHY */
11167
11168 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11169 return -EAGAIN;
11170
11171 spin_lock_bh(&tp->lock);
11172 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11173 spin_unlock_bh(&tp->lock);
11174
11175 data->val_out = mii_regval;
11176
11177 return err;
11178 }
11179
11180 case SIOCSMIIREG:
11181 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11182 break; /* We have no PHY */
11183
11184 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11185 return -EAGAIN;
11186
11187 spin_lock_bh(&tp->lock);
11188 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11189 spin_unlock_bh(&tp->lock);
11190
11191 return err;
11192
11193 default:
11194 /* do nothing */
11195 break;
11196 }
11197 return -EOPNOTSUPP;
11198 }
11199
11200 #if TG3_VLAN_TAG_USED
11201 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11202 {
11203 struct tg3 *tp = netdev_priv(dev);
11204
11205 if (!netif_running(dev)) {
11206 tp->vlgrp = grp;
11207 return;
11208 }
11209
11210 tg3_netif_stop(tp);
11211
11212 tg3_full_lock(tp, 0);
11213
11214 tp->vlgrp = grp;
11215
11216 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11217 __tg3_set_rx_mode(dev);
11218
11219 tg3_netif_start(tp);
11220
11221 tg3_full_unlock(tp);
11222 }
11223 #endif
11224
11225 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11226 {
11227 struct tg3 *tp = netdev_priv(dev);
11228
11229 memcpy(ec, &tp->coal, sizeof(*ec));
11230 return 0;
11231 }
11232
11233 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11234 {
11235 struct tg3 *tp = netdev_priv(dev);
11236 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11237 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11238
11239 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11240 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11241 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11242 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11243 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11244 }
11245
11246 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11247 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11248 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11249 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11250 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11251 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11252 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11253 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11254 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11255 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11256 return -EINVAL;
11257
11258 /* No rx interrupts will be generated if both are zero */
11259 if ((ec->rx_coalesce_usecs == 0) &&
11260 (ec->rx_max_coalesced_frames == 0))
11261 return -EINVAL;
11262
11263 /* No tx interrupts will be generated if both are zero */
11264 if ((ec->tx_coalesce_usecs == 0) &&
11265 (ec->tx_max_coalesced_frames == 0))
11266 return -EINVAL;
11267
11268 /* Only copy relevant parameters, ignore all others. */
11269 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11270 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11271 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11272 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11273 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11274 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11275 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11276 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11277 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11278
11279 if (netif_running(dev)) {
11280 tg3_full_lock(tp, 0);
11281 __tg3_set_coalesce(tp, &tp->coal);
11282 tg3_full_unlock(tp);
11283 }
11284 return 0;
11285 }
11286
11287 static const struct ethtool_ops tg3_ethtool_ops = {
11288 .get_settings = tg3_get_settings,
11289 .set_settings = tg3_set_settings,
11290 .get_drvinfo = tg3_get_drvinfo,
11291 .get_regs_len = tg3_get_regs_len,
11292 .get_regs = tg3_get_regs,
11293 .get_wol = tg3_get_wol,
11294 .set_wol = tg3_set_wol,
11295 .get_msglevel = tg3_get_msglevel,
11296 .set_msglevel = tg3_set_msglevel,
11297 .nway_reset = tg3_nway_reset,
11298 .get_link = ethtool_op_get_link,
11299 .get_eeprom_len = tg3_get_eeprom_len,
11300 .get_eeprom = tg3_get_eeprom,
11301 .set_eeprom = tg3_set_eeprom,
11302 .get_ringparam = tg3_get_ringparam,
11303 .set_ringparam = tg3_set_ringparam,
11304 .get_pauseparam = tg3_get_pauseparam,
11305 .set_pauseparam = tg3_set_pauseparam,
11306 .get_rx_csum = tg3_get_rx_csum,
11307 .set_rx_csum = tg3_set_rx_csum,
11308 .set_tx_csum = tg3_set_tx_csum,
11309 .set_sg = ethtool_op_set_sg,
11310 .set_tso = tg3_set_tso,
11311 .self_test = tg3_self_test,
11312 .get_strings = tg3_get_strings,
11313 .phys_id = tg3_phys_id,
11314 .get_ethtool_stats = tg3_get_ethtool_stats,
11315 .get_coalesce = tg3_get_coalesce,
11316 .set_coalesce = tg3_set_coalesce,
11317 .get_sset_count = tg3_get_sset_count,
11318 };
11319
11320 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11321 {
11322 u32 cursize, val, magic;
11323
11324 tp->nvram_size = EEPROM_CHIP_SIZE;
11325
11326 if (tg3_nvram_read(tp, 0, &magic) != 0)
11327 return;
11328
11329 if ((magic != TG3_EEPROM_MAGIC) &&
11330 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11331 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11332 return;
11333
11334 /*
11335 * Size the chip by reading offsets at increasing powers of two.
11336 * When we encounter our validation signature, we know the addressing
11337 * has wrapped around, and thus have our chip size.
11338 */
11339 cursize = 0x10;
11340
11341 while (cursize < tp->nvram_size) {
11342 if (tg3_nvram_read(tp, cursize, &val) != 0)
11343 return;
11344
11345 if (val == magic)
11346 break;
11347
11348 cursize <<= 1;
11349 }
11350
11351 tp->nvram_size = cursize;
11352 }
11353
11354 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11355 {
11356 u32 val;
11357
11358 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11359 tg3_nvram_read(tp, 0, &val) != 0)
11360 return;
11361
11362 /* Selfboot format */
11363 if (val != TG3_EEPROM_MAGIC) {
11364 tg3_get_eeprom_size(tp);
11365 return;
11366 }
11367
11368 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11369 if (val != 0) {
11370 /* This is confusing. We want to operate on the
11371 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11372 * call will read from NVRAM and byteswap the data
11373 * according to the byteswapping settings for all
11374 * other register accesses. This ensures the data we
11375 * want will always reside in the lower 16-bits.
11376 * However, the data in NVRAM is in LE format, which
11377 * means the data from the NVRAM read will always be
11378 * opposite the endianness of the CPU. The 16-bit
11379 * byteswap then brings the data to CPU endianness.
11380 */
11381 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11382 return;
11383 }
11384 }
11385 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11386 }
11387
11388 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11389 {
11390 u32 nvcfg1;
11391
11392 nvcfg1 = tr32(NVRAM_CFG1);
11393 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11394 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11395 } else {
11396 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11397 tw32(NVRAM_CFG1, nvcfg1);
11398 }
11399
11400 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11401 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11402 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11403 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11404 tp->nvram_jedecnum = JEDEC_ATMEL;
11405 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11406 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11407 break;
11408 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11409 tp->nvram_jedecnum = JEDEC_ATMEL;
11410 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11411 break;
11412 case FLASH_VENDOR_ATMEL_EEPROM:
11413 tp->nvram_jedecnum = JEDEC_ATMEL;
11414 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11415 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11416 break;
11417 case FLASH_VENDOR_ST:
11418 tp->nvram_jedecnum = JEDEC_ST;
11419 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11420 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11421 break;
11422 case FLASH_VENDOR_SAIFUN:
11423 tp->nvram_jedecnum = JEDEC_SAIFUN;
11424 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11425 break;
11426 case FLASH_VENDOR_SST_SMALL:
11427 case FLASH_VENDOR_SST_LARGE:
11428 tp->nvram_jedecnum = JEDEC_SST;
11429 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11430 break;
11431 }
11432 } else {
11433 tp->nvram_jedecnum = JEDEC_ATMEL;
11434 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11435 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11436 }
11437 }
11438
11439 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11440 {
11441 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11442 case FLASH_5752PAGE_SIZE_256:
11443 tp->nvram_pagesize = 256;
11444 break;
11445 case FLASH_5752PAGE_SIZE_512:
11446 tp->nvram_pagesize = 512;
11447 break;
11448 case FLASH_5752PAGE_SIZE_1K:
11449 tp->nvram_pagesize = 1024;
11450 break;
11451 case FLASH_5752PAGE_SIZE_2K:
11452 tp->nvram_pagesize = 2048;
11453 break;
11454 case FLASH_5752PAGE_SIZE_4K:
11455 tp->nvram_pagesize = 4096;
11456 break;
11457 case FLASH_5752PAGE_SIZE_264:
11458 tp->nvram_pagesize = 264;
11459 break;
11460 case FLASH_5752PAGE_SIZE_528:
11461 tp->nvram_pagesize = 528;
11462 break;
11463 }
11464 }
11465
11466 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11467 {
11468 u32 nvcfg1;
11469
11470 nvcfg1 = tr32(NVRAM_CFG1);
11471
11472 /* NVRAM protection for TPM */
11473 if (nvcfg1 & (1 << 27))
11474 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11475
11476 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11477 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11478 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11479 tp->nvram_jedecnum = JEDEC_ATMEL;
11480 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11481 break;
11482 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11483 tp->nvram_jedecnum = JEDEC_ATMEL;
11484 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11485 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11486 break;
11487 case FLASH_5752VENDOR_ST_M45PE10:
11488 case FLASH_5752VENDOR_ST_M45PE20:
11489 case FLASH_5752VENDOR_ST_M45PE40:
11490 tp->nvram_jedecnum = JEDEC_ST;
11491 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11492 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11493 break;
11494 }
11495
11496 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11497 tg3_nvram_get_pagesize(tp, nvcfg1);
11498 } else {
11499 /* For eeprom, set pagesize to maximum eeprom size */
11500 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11501
11502 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11503 tw32(NVRAM_CFG1, nvcfg1);
11504 }
11505 }
11506
11507 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11508 {
11509 u32 nvcfg1, protect = 0;
11510
11511 nvcfg1 = tr32(NVRAM_CFG1);
11512
11513 /* NVRAM protection for TPM */
11514 if (nvcfg1 & (1 << 27)) {
11515 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11516 protect = 1;
11517 }
11518
11519 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11520 switch (nvcfg1) {
11521 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11522 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11523 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11524 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11525 tp->nvram_jedecnum = JEDEC_ATMEL;
11526 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11527 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11528 tp->nvram_pagesize = 264;
11529 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11530 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11531 tp->nvram_size = (protect ? 0x3e200 :
11532 TG3_NVRAM_SIZE_512KB);
11533 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11534 tp->nvram_size = (protect ? 0x1f200 :
11535 TG3_NVRAM_SIZE_256KB);
11536 else
11537 tp->nvram_size = (protect ? 0x1f200 :
11538 TG3_NVRAM_SIZE_128KB);
11539 break;
11540 case FLASH_5752VENDOR_ST_M45PE10:
11541 case FLASH_5752VENDOR_ST_M45PE20:
11542 case FLASH_5752VENDOR_ST_M45PE40:
11543 tp->nvram_jedecnum = JEDEC_ST;
11544 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11545 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11546 tp->nvram_pagesize = 256;
11547 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11548 tp->nvram_size = (protect ?
11549 TG3_NVRAM_SIZE_64KB :
11550 TG3_NVRAM_SIZE_128KB);
11551 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11552 tp->nvram_size = (protect ?
11553 TG3_NVRAM_SIZE_64KB :
11554 TG3_NVRAM_SIZE_256KB);
11555 else
11556 tp->nvram_size = (protect ?
11557 TG3_NVRAM_SIZE_128KB :
11558 TG3_NVRAM_SIZE_512KB);
11559 break;
11560 }
11561 }
11562
11563 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11564 {
11565 u32 nvcfg1;
11566
11567 nvcfg1 = tr32(NVRAM_CFG1);
11568
11569 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11570 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11571 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11572 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11573 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11574 tp->nvram_jedecnum = JEDEC_ATMEL;
11575 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11576 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11577
11578 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11579 tw32(NVRAM_CFG1, nvcfg1);
11580 break;
11581 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11582 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11583 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11584 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11585 tp->nvram_jedecnum = JEDEC_ATMEL;
11586 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11587 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11588 tp->nvram_pagesize = 264;
11589 break;
11590 case FLASH_5752VENDOR_ST_M45PE10:
11591 case FLASH_5752VENDOR_ST_M45PE20:
11592 case FLASH_5752VENDOR_ST_M45PE40:
11593 tp->nvram_jedecnum = JEDEC_ST;
11594 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11595 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11596 tp->nvram_pagesize = 256;
11597 break;
11598 }
11599 }
11600
11601 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11602 {
11603 u32 nvcfg1, protect = 0;
11604
11605 nvcfg1 = tr32(NVRAM_CFG1);
11606
11607 /* NVRAM protection for TPM */
11608 if (nvcfg1 & (1 << 27)) {
11609 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11610 protect = 1;
11611 }
11612
11613 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11614 switch (nvcfg1) {
11615 case FLASH_5761VENDOR_ATMEL_ADB021D:
11616 case FLASH_5761VENDOR_ATMEL_ADB041D:
11617 case FLASH_5761VENDOR_ATMEL_ADB081D:
11618 case FLASH_5761VENDOR_ATMEL_ADB161D:
11619 case FLASH_5761VENDOR_ATMEL_MDB021D:
11620 case FLASH_5761VENDOR_ATMEL_MDB041D:
11621 case FLASH_5761VENDOR_ATMEL_MDB081D:
11622 case FLASH_5761VENDOR_ATMEL_MDB161D:
11623 tp->nvram_jedecnum = JEDEC_ATMEL;
11624 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11625 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11626 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11627 tp->nvram_pagesize = 256;
11628 break;
11629 case FLASH_5761VENDOR_ST_A_M45PE20:
11630 case FLASH_5761VENDOR_ST_A_M45PE40:
11631 case FLASH_5761VENDOR_ST_A_M45PE80:
11632 case FLASH_5761VENDOR_ST_A_M45PE16:
11633 case FLASH_5761VENDOR_ST_M_M45PE20:
11634 case FLASH_5761VENDOR_ST_M_M45PE40:
11635 case FLASH_5761VENDOR_ST_M_M45PE80:
11636 case FLASH_5761VENDOR_ST_M_M45PE16:
11637 tp->nvram_jedecnum = JEDEC_ST;
11638 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11639 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11640 tp->nvram_pagesize = 256;
11641 break;
11642 }
11643
11644 if (protect) {
11645 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11646 } else {
11647 switch (nvcfg1) {
11648 case FLASH_5761VENDOR_ATMEL_ADB161D:
11649 case FLASH_5761VENDOR_ATMEL_MDB161D:
11650 case FLASH_5761VENDOR_ST_A_M45PE16:
11651 case FLASH_5761VENDOR_ST_M_M45PE16:
11652 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11653 break;
11654 case FLASH_5761VENDOR_ATMEL_ADB081D:
11655 case FLASH_5761VENDOR_ATMEL_MDB081D:
11656 case FLASH_5761VENDOR_ST_A_M45PE80:
11657 case FLASH_5761VENDOR_ST_M_M45PE80:
11658 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11659 break;
11660 case FLASH_5761VENDOR_ATMEL_ADB041D:
11661 case FLASH_5761VENDOR_ATMEL_MDB041D:
11662 case FLASH_5761VENDOR_ST_A_M45PE40:
11663 case FLASH_5761VENDOR_ST_M_M45PE40:
11664 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11665 break;
11666 case FLASH_5761VENDOR_ATMEL_ADB021D:
11667 case FLASH_5761VENDOR_ATMEL_MDB021D:
11668 case FLASH_5761VENDOR_ST_A_M45PE20:
11669 case FLASH_5761VENDOR_ST_M_M45PE20:
11670 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11671 break;
11672 }
11673 }
11674 }
11675
11676 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11677 {
11678 tp->nvram_jedecnum = JEDEC_ATMEL;
11679 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11680 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11681 }
11682
11683 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11684 {
11685 u32 nvcfg1;
11686
11687 nvcfg1 = tr32(NVRAM_CFG1);
11688
11689 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11690 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11691 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11692 tp->nvram_jedecnum = JEDEC_ATMEL;
11693 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11694 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11695
11696 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11697 tw32(NVRAM_CFG1, nvcfg1);
11698 return;
11699 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11700 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11701 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11702 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11703 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11704 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11705 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11706 tp->nvram_jedecnum = JEDEC_ATMEL;
11707 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11708 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11709
11710 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11711 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11712 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11713 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11714 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11715 break;
11716 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11717 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11718 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11719 break;
11720 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11721 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11722 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11723 break;
11724 }
11725 break;
11726 case FLASH_5752VENDOR_ST_M45PE10:
11727 case FLASH_5752VENDOR_ST_M45PE20:
11728 case FLASH_5752VENDOR_ST_M45PE40:
11729 tp->nvram_jedecnum = JEDEC_ST;
11730 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11731 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11732
11733 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11734 case FLASH_5752VENDOR_ST_M45PE10:
11735 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11736 break;
11737 case FLASH_5752VENDOR_ST_M45PE20:
11738 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11739 break;
11740 case FLASH_5752VENDOR_ST_M45PE40:
11741 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11742 break;
11743 }
11744 break;
11745 default:
11746 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11747 return;
11748 }
11749
11750 tg3_nvram_get_pagesize(tp, nvcfg1);
11751 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11752 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11753 }
11754
11755
11756 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11757 {
11758 u32 nvcfg1;
11759
11760 nvcfg1 = tr32(NVRAM_CFG1);
11761
11762 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11763 case FLASH_5717VENDOR_ATMEL_EEPROM:
11764 case FLASH_5717VENDOR_MICRO_EEPROM:
11765 tp->nvram_jedecnum = JEDEC_ATMEL;
11766 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11767 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11768
11769 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11770 tw32(NVRAM_CFG1, nvcfg1);
11771 return;
11772 case FLASH_5717VENDOR_ATMEL_MDB011D:
11773 case FLASH_5717VENDOR_ATMEL_ADB011B:
11774 case FLASH_5717VENDOR_ATMEL_ADB011D:
11775 case FLASH_5717VENDOR_ATMEL_MDB021D:
11776 case FLASH_5717VENDOR_ATMEL_ADB021B:
11777 case FLASH_5717VENDOR_ATMEL_ADB021D:
11778 case FLASH_5717VENDOR_ATMEL_45USPT:
11779 tp->nvram_jedecnum = JEDEC_ATMEL;
11780 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11781 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11782
11783 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11784 case FLASH_5717VENDOR_ATMEL_MDB021D:
11785 case FLASH_5717VENDOR_ATMEL_ADB021B:
11786 case FLASH_5717VENDOR_ATMEL_ADB021D:
11787 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11788 break;
11789 default:
11790 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11791 break;
11792 }
11793 break;
11794 case FLASH_5717VENDOR_ST_M_M25PE10:
11795 case FLASH_5717VENDOR_ST_A_M25PE10:
11796 case FLASH_5717VENDOR_ST_M_M45PE10:
11797 case FLASH_5717VENDOR_ST_A_M45PE10:
11798 case FLASH_5717VENDOR_ST_M_M25PE20:
11799 case FLASH_5717VENDOR_ST_A_M25PE20:
11800 case FLASH_5717VENDOR_ST_M_M45PE20:
11801 case FLASH_5717VENDOR_ST_A_M45PE20:
11802 case FLASH_5717VENDOR_ST_25USPT:
11803 case FLASH_5717VENDOR_ST_45USPT:
11804 tp->nvram_jedecnum = JEDEC_ST;
11805 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11806 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11807
11808 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11809 case FLASH_5717VENDOR_ST_M_M25PE20:
11810 case FLASH_5717VENDOR_ST_A_M25PE20:
11811 case FLASH_5717VENDOR_ST_M_M45PE20:
11812 case FLASH_5717VENDOR_ST_A_M45PE20:
11813 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11814 break;
11815 default:
11816 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11817 break;
11818 }
11819 break;
11820 default:
11821 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11822 return;
11823 }
11824
11825 tg3_nvram_get_pagesize(tp, nvcfg1);
11826 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11827 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11828 }
11829
11830 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11831 static void __devinit tg3_nvram_init(struct tg3 *tp)
11832 {
11833 tw32_f(GRC_EEPROM_ADDR,
11834 (EEPROM_ADDR_FSM_RESET |
11835 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11836 EEPROM_ADDR_CLKPERD_SHIFT)));
11837
11838 msleep(1);
11839
11840 /* Enable seeprom accesses. */
11841 tw32_f(GRC_LOCAL_CTRL,
11842 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11843 udelay(100);
11844
11845 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11846 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11847 tp->tg3_flags |= TG3_FLAG_NVRAM;
11848
11849 if (tg3_nvram_lock(tp)) {
11850 netdev_warn(tp->dev,
11851 "Cannot get nvram lock, %s failed\n",
11852 __func__);
11853 return;
11854 }
11855 tg3_enable_nvram_access(tp);
11856
11857 tp->nvram_size = 0;
11858
11859 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11860 tg3_get_5752_nvram_info(tp);
11861 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11862 tg3_get_5755_nvram_info(tp);
11863 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11864 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11865 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11866 tg3_get_5787_nvram_info(tp);
11867 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11868 tg3_get_5761_nvram_info(tp);
11869 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11870 tg3_get_5906_nvram_info(tp);
11871 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11872 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11873 tg3_get_57780_nvram_info(tp);
11874 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11875 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11876 tg3_get_5717_nvram_info(tp);
11877 else
11878 tg3_get_nvram_info(tp);
11879
11880 if (tp->nvram_size == 0)
11881 tg3_get_nvram_size(tp);
11882
11883 tg3_disable_nvram_access(tp);
11884 tg3_nvram_unlock(tp);
11885
11886 } else {
11887 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11888
11889 tg3_get_eeprom_size(tp);
11890 }
11891 }
11892
11893 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11894 u32 offset, u32 len, u8 *buf)
11895 {
11896 int i, j, rc = 0;
11897 u32 val;
11898
11899 for (i = 0; i < len; i += 4) {
11900 u32 addr;
11901 __be32 data;
11902
11903 addr = offset + i;
11904
11905 memcpy(&data, buf + i, 4);
11906
11907 /*
11908 * The SEEPROM interface expects the data to always be opposite
11909 * the native endian format. We accomplish this by reversing
11910 * all the operations that would have been performed on the
11911 * data from a call to tg3_nvram_read_be32().
11912 */
11913 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11914
11915 val = tr32(GRC_EEPROM_ADDR);
11916 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11917
11918 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11919 EEPROM_ADDR_READ);
11920 tw32(GRC_EEPROM_ADDR, val |
11921 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11922 (addr & EEPROM_ADDR_ADDR_MASK) |
11923 EEPROM_ADDR_START |
11924 EEPROM_ADDR_WRITE);
11925
11926 for (j = 0; j < 1000; j++) {
11927 val = tr32(GRC_EEPROM_ADDR);
11928
11929 if (val & EEPROM_ADDR_COMPLETE)
11930 break;
11931 msleep(1);
11932 }
11933 if (!(val & EEPROM_ADDR_COMPLETE)) {
11934 rc = -EBUSY;
11935 break;
11936 }
11937 }
11938
11939 return rc;
11940 }
11941
11942 /* offset and length are dword aligned */
11943 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11944 u8 *buf)
11945 {
11946 int ret = 0;
11947 u32 pagesize = tp->nvram_pagesize;
11948 u32 pagemask = pagesize - 1;
11949 u32 nvram_cmd;
11950 u8 *tmp;
11951
11952 tmp = kmalloc(pagesize, GFP_KERNEL);
11953 if (tmp == NULL)
11954 return -ENOMEM;
11955
11956 while (len) {
11957 int j;
11958 u32 phy_addr, page_off, size;
11959
11960 phy_addr = offset & ~pagemask;
11961
11962 for (j = 0; j < pagesize; j += 4) {
11963 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11964 (__be32 *) (tmp + j));
11965 if (ret)
11966 break;
11967 }
11968 if (ret)
11969 break;
11970
11971 page_off = offset & pagemask;
11972 size = pagesize;
11973 if (len < size)
11974 size = len;
11975
11976 len -= size;
11977
11978 memcpy(tmp + page_off, buf, size);
11979
11980 offset = offset + (pagesize - page_off);
11981
11982 tg3_enable_nvram_access(tp);
11983
11984 /*
11985 * Before we can erase the flash page, we need
11986 * to issue a special "write enable" command.
11987 */
11988 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11989
11990 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11991 break;
11992
11993 /* Erase the target page */
11994 tw32(NVRAM_ADDR, phy_addr);
11995
11996 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11997 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11998
11999 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12000 break;
12001
12002 /* Issue another write enable to start the write. */
12003 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12004
12005 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12006 break;
12007
12008 for (j = 0; j < pagesize; j += 4) {
12009 __be32 data;
12010
12011 data = *((__be32 *) (tmp + j));
12012
12013 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12014
12015 tw32(NVRAM_ADDR, phy_addr + j);
12016
12017 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12018 NVRAM_CMD_WR;
12019
12020 if (j == 0)
12021 nvram_cmd |= NVRAM_CMD_FIRST;
12022 else if (j == (pagesize - 4))
12023 nvram_cmd |= NVRAM_CMD_LAST;
12024
12025 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12026 break;
12027 }
12028 if (ret)
12029 break;
12030 }
12031
12032 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12033 tg3_nvram_exec_cmd(tp, nvram_cmd);
12034
12035 kfree(tmp);
12036
12037 return ret;
12038 }
12039
12040 /* offset and length are dword aligned */
12041 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12042 u8 *buf)
12043 {
12044 int i, ret = 0;
12045
12046 for (i = 0; i < len; i += 4, offset += 4) {
12047 u32 page_off, phy_addr, nvram_cmd;
12048 __be32 data;
12049
12050 memcpy(&data, buf + i, 4);
12051 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12052
12053 page_off = offset % tp->nvram_pagesize;
12054
12055 phy_addr = tg3_nvram_phys_addr(tp, offset);
12056
12057 tw32(NVRAM_ADDR, phy_addr);
12058
12059 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12060
12061 if (page_off == 0 || i == 0)
12062 nvram_cmd |= NVRAM_CMD_FIRST;
12063 if (page_off == (tp->nvram_pagesize - 4))
12064 nvram_cmd |= NVRAM_CMD_LAST;
12065
12066 if (i == (len - 4))
12067 nvram_cmd |= NVRAM_CMD_LAST;
12068
12069 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12070 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12071 (tp->nvram_jedecnum == JEDEC_ST) &&
12072 (nvram_cmd & NVRAM_CMD_FIRST)) {
12073
12074 if ((ret = tg3_nvram_exec_cmd(tp,
12075 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12076 NVRAM_CMD_DONE)))
12077
12078 break;
12079 }
12080 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12081 /* We always do complete word writes to eeprom. */
12082 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12083 }
12084
12085 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12086 break;
12087 }
12088 return ret;
12089 }
12090
12091 /* offset and length are dword aligned */
12092 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12093 {
12094 int ret;
12095
12096 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12097 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12098 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12099 udelay(40);
12100 }
12101
12102 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12103 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12104 } else {
12105 u32 grc_mode;
12106
12107 ret = tg3_nvram_lock(tp);
12108 if (ret)
12109 return ret;
12110
12111 tg3_enable_nvram_access(tp);
12112 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12113 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12114 tw32(NVRAM_WRITE1, 0x406);
12115
12116 grc_mode = tr32(GRC_MODE);
12117 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12118
12119 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12120 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12121
12122 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12123 buf);
12124 } else {
12125 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12126 buf);
12127 }
12128
12129 grc_mode = tr32(GRC_MODE);
12130 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12131
12132 tg3_disable_nvram_access(tp);
12133 tg3_nvram_unlock(tp);
12134 }
12135
12136 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12137 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12138 udelay(40);
12139 }
12140
12141 return ret;
12142 }
12143
12144 struct subsys_tbl_ent {
12145 u16 subsys_vendor, subsys_devid;
12146 u32 phy_id;
12147 };
12148
12149 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12150 /* Broadcom boards. */
12151 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12152 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12153 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12154 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12155 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12156 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12157 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12158 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12159 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12160 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12161 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12162 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12163 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12164 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12165 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12166 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12167 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12168 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12169 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12170 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12171 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12172 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12173
12174 /* 3com boards. */
12175 { TG3PCI_SUBVENDOR_ID_3COM,
12176 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12177 { TG3PCI_SUBVENDOR_ID_3COM,
12178 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12179 { TG3PCI_SUBVENDOR_ID_3COM,
12180 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12181 { TG3PCI_SUBVENDOR_ID_3COM,
12182 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12183 { TG3PCI_SUBVENDOR_ID_3COM,
12184 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12185
12186 /* DELL boards. */
12187 { TG3PCI_SUBVENDOR_ID_DELL,
12188 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12189 { TG3PCI_SUBVENDOR_ID_DELL,
12190 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12191 { TG3PCI_SUBVENDOR_ID_DELL,
12192 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12193 { TG3PCI_SUBVENDOR_ID_DELL,
12194 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12195
12196 /* Compaq boards. */
12197 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12198 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12199 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12200 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12201 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12202 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12203 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12204 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12205 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12206 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12207
12208 /* IBM boards. */
12209 { TG3PCI_SUBVENDOR_ID_IBM,
12210 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12211 };
12212
12213 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12214 {
12215 int i;
12216
12217 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12218 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12219 tp->pdev->subsystem_vendor) &&
12220 (subsys_id_to_phy_id[i].subsys_devid ==
12221 tp->pdev->subsystem_device))
12222 return &subsys_id_to_phy_id[i];
12223 }
12224 return NULL;
12225 }
12226
12227 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12228 {
12229 u32 val;
12230 u16 pmcsr;
12231
12232 /* On some early chips the SRAM cannot be accessed in D3hot state,
12233 * so need make sure we're in D0.
12234 */
12235 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12236 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12237 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12238 msleep(1);
12239
12240 /* Make sure register accesses (indirect or otherwise)
12241 * will function correctly.
12242 */
12243 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12244 tp->misc_host_ctrl);
12245
12246 /* The memory arbiter has to be enabled in order for SRAM accesses
12247 * to succeed. Normally on powerup the tg3 chip firmware will make
12248 * sure it is enabled, but other entities such as system netboot
12249 * code might disable it.
12250 */
12251 val = tr32(MEMARB_MODE);
12252 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12253
12254 tp->phy_id = TG3_PHY_ID_INVALID;
12255 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12256
12257 /* Assume an onboard device and WOL capable by default. */
12258 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12259
12260 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12261 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12262 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12263 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12264 }
12265 val = tr32(VCPU_CFGSHDW);
12266 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12267 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12268 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12269 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12270 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12271 goto done;
12272 }
12273
12274 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12275 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12276 u32 nic_cfg, led_cfg;
12277 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12278 int eeprom_phy_serdes = 0;
12279
12280 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12281 tp->nic_sram_data_cfg = nic_cfg;
12282
12283 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12284 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12285 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12286 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12287 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12288 (ver > 0) && (ver < 0x100))
12289 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12290
12291 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12292 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12293
12294 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12295 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12296 eeprom_phy_serdes = 1;
12297
12298 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12299 if (nic_phy_id != 0) {
12300 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12301 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12302
12303 eeprom_phy_id = (id1 >> 16) << 10;
12304 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12305 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12306 } else
12307 eeprom_phy_id = 0;
12308
12309 tp->phy_id = eeprom_phy_id;
12310 if (eeprom_phy_serdes) {
12311 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12312 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12313 else
12314 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12315 }
12316
12317 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12318 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12319 SHASTA_EXT_LED_MODE_MASK);
12320 else
12321 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12322
12323 switch (led_cfg) {
12324 default:
12325 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12326 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12327 break;
12328
12329 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12330 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12331 break;
12332
12333 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12334 tp->led_ctrl = LED_CTRL_MODE_MAC;
12335
12336 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12337 * read on some older 5700/5701 bootcode.
12338 */
12339 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12340 ASIC_REV_5700 ||
12341 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12342 ASIC_REV_5701)
12343 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12344
12345 break;
12346
12347 case SHASTA_EXT_LED_SHARED:
12348 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12349 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12350 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12351 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12352 LED_CTRL_MODE_PHY_2);
12353 break;
12354
12355 case SHASTA_EXT_LED_MAC:
12356 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12357 break;
12358
12359 case SHASTA_EXT_LED_COMBO:
12360 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12361 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12362 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12363 LED_CTRL_MODE_PHY_2);
12364 break;
12365
12366 }
12367
12368 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12369 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12370 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12371 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12372
12373 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12374 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12375
12376 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12377 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12378 if ((tp->pdev->subsystem_vendor ==
12379 PCI_VENDOR_ID_ARIMA) &&
12380 (tp->pdev->subsystem_device == 0x205a ||
12381 tp->pdev->subsystem_device == 0x2063))
12382 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12383 } else {
12384 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12385 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12386 }
12387
12388 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12389 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12390 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12391 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12392 }
12393
12394 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12395 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12396 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12397
12398 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12399 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12400 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12401
12402 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12403 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12404 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12405
12406 if (cfg2 & (1 << 17))
12407 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12408
12409 /* serdes signal pre-emphasis in register 0x590 set by */
12410 /* bootcode if bit 18 is set */
12411 if (cfg2 & (1 << 18))
12412 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12413
12414 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12415 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12416 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12417 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12418
12419 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12420 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12421 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12422 u32 cfg3;
12423
12424 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12425 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12426 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12427 }
12428
12429 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12430 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12431 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12432 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12433 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12434 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12435 }
12436 done:
12437 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12438 device_set_wakeup_enable(&tp->pdev->dev,
12439 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12440 }
12441
12442 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12443 {
12444 int i;
12445 u32 val;
12446
12447 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12448 tw32(OTP_CTRL, cmd);
12449
12450 /* Wait for up to 1 ms for command to execute. */
12451 for (i = 0; i < 100; i++) {
12452 val = tr32(OTP_STATUS);
12453 if (val & OTP_STATUS_CMD_DONE)
12454 break;
12455 udelay(10);
12456 }
12457
12458 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12459 }
12460
12461 /* Read the gphy configuration from the OTP region of the chip. The gphy
12462 * configuration is a 32-bit value that straddles the alignment boundary.
12463 * We do two 32-bit reads and then shift and merge the results.
12464 */
12465 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12466 {
12467 u32 bhalf_otp, thalf_otp;
12468
12469 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12470
12471 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12472 return 0;
12473
12474 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12475
12476 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12477 return 0;
12478
12479 thalf_otp = tr32(OTP_READ_DATA);
12480
12481 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12482
12483 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12484 return 0;
12485
12486 bhalf_otp = tr32(OTP_READ_DATA);
12487
12488 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12489 }
12490
12491 static int __devinit tg3_phy_probe(struct tg3 *tp)
12492 {
12493 u32 hw_phy_id_1, hw_phy_id_2;
12494 u32 hw_phy_id, hw_phy_id_masked;
12495 int err;
12496
12497 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12498 return tg3_phy_init(tp);
12499
12500 /* Reading the PHY ID register can conflict with ASF
12501 * firmware access to the PHY hardware.
12502 */
12503 err = 0;
12504 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12505 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12506 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12507 } else {
12508 /* Now read the physical PHY_ID from the chip and verify
12509 * that it is sane. If it doesn't look good, we fall back
12510 * to either the hard-coded table based PHY_ID and failing
12511 * that the value found in the eeprom area.
12512 */
12513 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12514 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12515
12516 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12517 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12518 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12519
12520 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12521 }
12522
12523 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12524 tp->phy_id = hw_phy_id;
12525 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12526 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12527 else
12528 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12529 } else {
12530 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12531 /* Do nothing, phy ID already set up in
12532 * tg3_get_eeprom_hw_cfg().
12533 */
12534 } else {
12535 struct subsys_tbl_ent *p;
12536
12537 /* No eeprom signature? Try the hardcoded
12538 * subsys device table.
12539 */
12540 p = tg3_lookup_by_subsys(tp);
12541 if (!p)
12542 return -ENODEV;
12543
12544 tp->phy_id = p->phy_id;
12545 if (!tp->phy_id ||
12546 tp->phy_id == TG3_PHY_ID_BCM8002)
12547 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12548 }
12549 }
12550
12551 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12552 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12553 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))
12554 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12555
12556 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12557 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12558 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12559 u32 bmsr, adv_reg, tg3_ctrl, mask;
12560
12561 tg3_readphy(tp, MII_BMSR, &bmsr);
12562 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12563 (bmsr & BMSR_LSTATUS))
12564 goto skip_phy_reset;
12565
12566 err = tg3_phy_reset(tp);
12567 if (err)
12568 return err;
12569
12570 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12571 ADVERTISE_100HALF | ADVERTISE_100FULL |
12572 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12573 tg3_ctrl = 0;
12574 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12575 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12576 MII_TG3_CTRL_ADV_1000_FULL);
12577 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12578 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12579 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12580 MII_TG3_CTRL_ENABLE_AS_MASTER);
12581 }
12582
12583 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12584 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12585 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12586 if (!tg3_copper_is_advertising_all(tp, mask)) {
12587 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12588
12589 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12590 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12591
12592 tg3_writephy(tp, MII_BMCR,
12593 BMCR_ANENABLE | BMCR_ANRESTART);
12594 }
12595 tg3_phy_set_wirespeed(tp);
12596
12597 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12598 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12599 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12600 }
12601
12602 skip_phy_reset:
12603 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12604 err = tg3_init_5401phy_dsp(tp);
12605 if (err)
12606 return err;
12607
12608 err = tg3_init_5401phy_dsp(tp);
12609 }
12610
12611 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12612 tp->link_config.advertising =
12613 (ADVERTISED_1000baseT_Half |
12614 ADVERTISED_1000baseT_Full |
12615 ADVERTISED_Autoneg |
12616 ADVERTISED_FIBRE);
12617 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12618 tp->link_config.advertising &=
12619 ~(ADVERTISED_1000baseT_Half |
12620 ADVERTISED_1000baseT_Full);
12621
12622 return err;
12623 }
12624
12625 static void __devinit tg3_read_vpd(struct tg3 *tp)
12626 {
12627 u8 *vpd_data;
12628 unsigned int block_end, rosize, len;
12629 int j, i = 0;
12630 u32 magic;
12631
12632 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12633 tg3_nvram_read(tp, 0x0, &magic))
12634 goto out_no_vpd;
12635
12636 vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12637 if (!vpd_data)
12638 goto out_no_vpd;
12639
12640 if (magic == TG3_EEPROM_MAGIC) {
12641 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12642 u32 tmp;
12643
12644 /* The data is in little-endian format in NVRAM.
12645 * Use the big-endian read routines to preserve
12646 * the byte order as it exists in NVRAM.
12647 */
12648 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12649 goto out_not_found;
12650
12651 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12652 }
12653 } else {
12654 ssize_t cnt;
12655 unsigned int pos = 0;
12656
12657 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12658 cnt = pci_read_vpd(tp->pdev, pos,
12659 TG3_NVM_VPD_LEN - pos,
12660 &vpd_data[pos]);
12661 if (cnt == -ETIMEDOUT || -EINTR)
12662 cnt = 0;
12663 else if (cnt < 0)
12664 goto out_not_found;
12665 }
12666 if (pos != TG3_NVM_VPD_LEN)
12667 goto out_not_found;
12668 }
12669
12670 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12671 PCI_VPD_LRDT_RO_DATA);
12672 if (i < 0)
12673 goto out_not_found;
12674
12675 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12676 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12677 i += PCI_VPD_LRDT_TAG_SIZE;
12678
12679 if (block_end > TG3_NVM_VPD_LEN)
12680 goto out_not_found;
12681
12682 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12683 PCI_VPD_RO_KEYWORD_MFR_ID);
12684 if (j > 0) {
12685 len = pci_vpd_info_field_size(&vpd_data[j]);
12686
12687 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12688 if (j + len > block_end || len != 4 ||
12689 memcmp(&vpd_data[j], "1028", 4))
12690 goto partno;
12691
12692 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12693 PCI_VPD_RO_KEYWORD_VENDOR0);
12694 if (j < 0)
12695 goto partno;
12696
12697 len = pci_vpd_info_field_size(&vpd_data[j]);
12698
12699 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12700 if (j + len > block_end)
12701 goto partno;
12702
12703 memcpy(tp->fw_ver, &vpd_data[j], len);
12704 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12705 }
12706
12707 partno:
12708 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12709 PCI_VPD_RO_KEYWORD_PARTNO);
12710 if (i < 0)
12711 goto out_not_found;
12712
12713 len = pci_vpd_info_field_size(&vpd_data[i]);
12714
12715 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12716 if (len > TG3_BPN_SIZE ||
12717 (len + i) > TG3_NVM_VPD_LEN)
12718 goto out_not_found;
12719
12720 memcpy(tp->board_part_number, &vpd_data[i], len);
12721
12722 out_not_found:
12723 kfree(vpd_data);
12724 if (tp->board_part_number[0])
12725 return;
12726
12727 out_no_vpd:
12728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12729 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12730 strcpy(tp->board_part_number, "BCM5717");
12731 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12732 strcpy(tp->board_part_number, "BCM5718");
12733 else
12734 goto nomatch;
12735 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12736 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12737 strcpy(tp->board_part_number, "BCM57780");
12738 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12739 strcpy(tp->board_part_number, "BCM57760");
12740 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12741 strcpy(tp->board_part_number, "BCM57790");
12742 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12743 strcpy(tp->board_part_number, "BCM57788");
12744 else
12745 goto nomatch;
12746 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12747 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12748 strcpy(tp->board_part_number, "BCM57761");
12749 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12750 strcpy(tp->board_part_number, "BCM57765");
12751 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12752 strcpy(tp->board_part_number, "BCM57781");
12753 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12754 strcpy(tp->board_part_number, "BCM57785");
12755 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12756 strcpy(tp->board_part_number, "BCM57791");
12757 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12758 strcpy(tp->board_part_number, "BCM57795");
12759 else
12760 goto nomatch;
12761 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12762 strcpy(tp->board_part_number, "BCM95906");
12763 } else {
12764 nomatch:
12765 strcpy(tp->board_part_number, "none");
12766 }
12767 }
12768
12769 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12770 {
12771 u32 val;
12772
12773 if (tg3_nvram_read(tp, offset, &val) ||
12774 (val & 0xfc000000) != 0x0c000000 ||
12775 tg3_nvram_read(tp, offset + 4, &val) ||
12776 val != 0)
12777 return 0;
12778
12779 return 1;
12780 }
12781
12782 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12783 {
12784 u32 val, offset, start, ver_offset;
12785 int i, dst_off;
12786 bool newver = false;
12787
12788 if (tg3_nvram_read(tp, 0xc, &offset) ||
12789 tg3_nvram_read(tp, 0x4, &start))
12790 return;
12791
12792 offset = tg3_nvram_logical_addr(tp, offset);
12793
12794 if (tg3_nvram_read(tp, offset, &val))
12795 return;
12796
12797 if ((val & 0xfc000000) == 0x0c000000) {
12798 if (tg3_nvram_read(tp, offset + 4, &val))
12799 return;
12800
12801 if (val == 0)
12802 newver = true;
12803 }
12804
12805 dst_off = strlen(tp->fw_ver);
12806
12807 if (newver) {
12808 if (TG3_VER_SIZE - dst_off < 16 ||
12809 tg3_nvram_read(tp, offset + 8, &ver_offset))
12810 return;
12811
12812 offset = offset + ver_offset - start;
12813 for (i = 0; i < 16; i += 4) {
12814 __be32 v;
12815 if (tg3_nvram_read_be32(tp, offset + i, &v))
12816 return;
12817
12818 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12819 }
12820 } else {
12821 u32 major, minor;
12822
12823 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12824 return;
12825
12826 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12827 TG3_NVM_BCVER_MAJSFT;
12828 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12829 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12830 "v%d.%02d", major, minor);
12831 }
12832 }
12833
12834 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12835 {
12836 u32 val, major, minor;
12837
12838 /* Use native endian representation */
12839 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12840 return;
12841
12842 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12843 TG3_NVM_HWSB_CFG1_MAJSFT;
12844 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12845 TG3_NVM_HWSB_CFG1_MINSFT;
12846
12847 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12848 }
12849
12850 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12851 {
12852 u32 offset, major, minor, build;
12853
12854 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12855
12856 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12857 return;
12858
12859 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12860 case TG3_EEPROM_SB_REVISION_0:
12861 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12862 break;
12863 case TG3_EEPROM_SB_REVISION_2:
12864 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12865 break;
12866 case TG3_EEPROM_SB_REVISION_3:
12867 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12868 break;
12869 case TG3_EEPROM_SB_REVISION_4:
12870 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12871 break;
12872 case TG3_EEPROM_SB_REVISION_5:
12873 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12874 break;
12875 case TG3_EEPROM_SB_REVISION_6:
12876 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12877 break;
12878 default:
12879 return;
12880 }
12881
12882 if (tg3_nvram_read(tp, offset, &val))
12883 return;
12884
12885 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12886 TG3_EEPROM_SB_EDH_BLD_SHFT;
12887 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12888 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12889 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12890
12891 if (minor > 99 || build > 26)
12892 return;
12893
12894 offset = strlen(tp->fw_ver);
12895 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12896 " v%d.%02d", major, minor);
12897
12898 if (build > 0) {
12899 offset = strlen(tp->fw_ver);
12900 if (offset < TG3_VER_SIZE - 1)
12901 tp->fw_ver[offset] = 'a' + build - 1;
12902 }
12903 }
12904
12905 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12906 {
12907 u32 val, offset, start;
12908 int i, vlen;
12909
12910 for (offset = TG3_NVM_DIR_START;
12911 offset < TG3_NVM_DIR_END;
12912 offset += TG3_NVM_DIRENT_SIZE) {
12913 if (tg3_nvram_read(tp, offset, &val))
12914 return;
12915
12916 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12917 break;
12918 }
12919
12920 if (offset == TG3_NVM_DIR_END)
12921 return;
12922
12923 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12924 start = 0x08000000;
12925 else if (tg3_nvram_read(tp, offset - 4, &start))
12926 return;
12927
12928 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12929 !tg3_fw_img_is_valid(tp, offset) ||
12930 tg3_nvram_read(tp, offset + 8, &val))
12931 return;
12932
12933 offset += val - start;
12934
12935 vlen = strlen(tp->fw_ver);
12936
12937 tp->fw_ver[vlen++] = ',';
12938 tp->fw_ver[vlen++] = ' ';
12939
12940 for (i = 0; i < 4; i++) {
12941 __be32 v;
12942 if (tg3_nvram_read_be32(tp, offset, &v))
12943 return;
12944
12945 offset += sizeof(v);
12946
12947 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12948 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12949 break;
12950 }
12951
12952 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12953 vlen += sizeof(v);
12954 }
12955 }
12956
12957 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12958 {
12959 int vlen;
12960 u32 apedata;
12961 char *fwtype;
12962
12963 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12964 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12965 return;
12966
12967 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12968 if (apedata != APE_SEG_SIG_MAGIC)
12969 return;
12970
12971 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12972 if (!(apedata & APE_FW_STATUS_READY))
12973 return;
12974
12975 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12976
12977 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12978 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12979 fwtype = "NCSI";
12980 } else {
12981 fwtype = "DASH";
12982 }
12983
12984 vlen = strlen(tp->fw_ver);
12985
12986 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12987 fwtype,
12988 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12989 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12990 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12991 (apedata & APE_FW_VERSION_BLDMSK));
12992 }
12993
12994 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12995 {
12996 u32 val;
12997 bool vpd_vers = false;
12998
12999 if (tp->fw_ver[0] != 0)
13000 vpd_vers = true;
13001
13002 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13003 strcat(tp->fw_ver, "sb");
13004 return;
13005 }
13006
13007 if (tg3_nvram_read(tp, 0, &val))
13008 return;
13009
13010 if (val == TG3_EEPROM_MAGIC)
13011 tg3_read_bc_ver(tp);
13012 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13013 tg3_read_sb_ver(tp, val);
13014 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13015 tg3_read_hwsb_ver(tp);
13016 else
13017 return;
13018
13019 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13020 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13021 goto done;
13022
13023 tg3_read_mgmtfw_ver(tp);
13024
13025 done:
13026 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13027 }
13028
13029 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13030
13031 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
13032 {
13033 #if TG3_VLAN_TAG_USED
13034 dev->vlan_features |= flags;
13035 #endif
13036 }
13037
13038 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13039 {
13040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13041 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13042 return 4096;
13043 else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13044 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13045 return 1024;
13046 else
13047 return 512;
13048 }
13049
13050 static int __devinit tg3_get_invariants(struct tg3 *tp)
13051 {
13052 static struct pci_device_id write_reorder_chipsets[] = {
13053 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13054 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13055 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13056 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13057 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
13058 PCI_DEVICE_ID_VIA_8385_0) },
13059 { },
13060 };
13061 u32 misc_ctrl_reg;
13062 u32 pci_state_reg, grc_misc_cfg;
13063 u32 val;
13064 u16 pci_cmd;
13065 int err;
13066
13067 /* Force memory write invalidate off. If we leave it on,
13068 * then on 5700_BX chips we have to enable a workaround.
13069 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13070 * to match the cacheline size. The Broadcom driver have this
13071 * workaround but turns MWI off all the times so never uses
13072 * it. This seems to suggest that the workaround is insufficient.
13073 */
13074 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13075 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13076 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13077
13078 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13079 * has the register indirect write enable bit set before
13080 * we try to access any of the MMIO registers. It is also
13081 * critical that the PCI-X hw workaround situation is decided
13082 * before that as well.
13083 */
13084 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13085 &misc_ctrl_reg);
13086
13087 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13088 MISC_HOST_CTRL_CHIPREV_SHIFT);
13089 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13090 u32 prod_id_asic_rev;
13091
13092 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13093 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13094 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
13095 pci_read_config_dword(tp->pdev,
13096 TG3PCI_GEN2_PRODID_ASICREV,
13097 &prod_id_asic_rev);
13098 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13099 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13100 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13101 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13102 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13103 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13104 pci_read_config_dword(tp->pdev,
13105 TG3PCI_GEN15_PRODID_ASICREV,
13106 &prod_id_asic_rev);
13107 else
13108 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13109 &prod_id_asic_rev);
13110
13111 tp->pci_chip_rev_id = prod_id_asic_rev;
13112 }
13113
13114 /* Wrong chip ID in 5752 A0. This code can be removed later
13115 * as A0 is not in production.
13116 */
13117 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13118 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13119
13120 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13121 * we need to disable memory and use config. cycles
13122 * only to access all registers. The 5702/03 chips
13123 * can mistakenly decode the special cycles from the
13124 * ICH chipsets as memory write cycles, causing corruption
13125 * of register and memory space. Only certain ICH bridges
13126 * will drive special cycles with non-zero data during the
13127 * address phase which can fall within the 5703's address
13128 * range. This is not an ICH bug as the PCI spec allows
13129 * non-zero address during special cycles. However, only
13130 * these ICH bridges are known to drive non-zero addresses
13131 * during special cycles.
13132 *
13133 * Since special cycles do not cross PCI bridges, we only
13134 * enable this workaround if the 5703 is on the secondary
13135 * bus of these ICH bridges.
13136 */
13137 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13138 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13139 static struct tg3_dev_id {
13140 u32 vendor;
13141 u32 device;
13142 u32 rev;
13143 } ich_chipsets[] = {
13144 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13145 PCI_ANY_ID },
13146 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13147 PCI_ANY_ID },
13148 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13149 0xa },
13150 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13151 PCI_ANY_ID },
13152 { },
13153 };
13154 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13155 struct pci_dev *bridge = NULL;
13156
13157 while (pci_id->vendor != 0) {
13158 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13159 bridge);
13160 if (!bridge) {
13161 pci_id++;
13162 continue;
13163 }
13164 if (pci_id->rev != PCI_ANY_ID) {
13165 if (bridge->revision > pci_id->rev)
13166 continue;
13167 }
13168 if (bridge->subordinate &&
13169 (bridge->subordinate->number ==
13170 tp->pdev->bus->number)) {
13171
13172 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13173 pci_dev_put(bridge);
13174 break;
13175 }
13176 }
13177 }
13178
13179 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13180 static struct tg3_dev_id {
13181 u32 vendor;
13182 u32 device;
13183 } bridge_chipsets[] = {
13184 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13185 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13186 { },
13187 };
13188 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13189 struct pci_dev *bridge = NULL;
13190
13191 while (pci_id->vendor != 0) {
13192 bridge = pci_get_device(pci_id->vendor,
13193 pci_id->device,
13194 bridge);
13195 if (!bridge) {
13196 pci_id++;
13197 continue;
13198 }
13199 if (bridge->subordinate &&
13200 (bridge->subordinate->number <=
13201 tp->pdev->bus->number) &&
13202 (bridge->subordinate->subordinate >=
13203 tp->pdev->bus->number)) {
13204 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13205 pci_dev_put(bridge);
13206 break;
13207 }
13208 }
13209 }
13210
13211 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13212 * DMA addresses > 40-bit. This bridge may have other additional
13213 * 57xx devices behind it in some 4-port NIC designs for example.
13214 * Any tg3 device found behind the bridge will also need the 40-bit
13215 * DMA workaround.
13216 */
13217 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13218 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13219 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13220 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13221 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13222 } else {
13223 struct pci_dev *bridge = NULL;
13224
13225 do {
13226 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13227 PCI_DEVICE_ID_SERVERWORKS_EPB,
13228 bridge);
13229 if (bridge && bridge->subordinate &&
13230 (bridge->subordinate->number <=
13231 tp->pdev->bus->number) &&
13232 (bridge->subordinate->subordinate >=
13233 tp->pdev->bus->number)) {
13234 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13235 pci_dev_put(bridge);
13236 break;
13237 }
13238 } while (bridge);
13239 }
13240
13241 /* Initialize misc host control in PCI block. */
13242 tp->misc_host_ctrl |= (misc_ctrl_reg &
13243 MISC_HOST_CTRL_CHIPREV);
13244 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13245 tp->misc_host_ctrl);
13246
13247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13249 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13250 tp->pdev_peer = tg3_find_peer(tp);
13251
13252 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13253 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13254 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13255 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13256
13257 /* Intentionally exclude ASIC_REV_5906 */
13258 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13259 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13260 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13261 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13262 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13263 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13264 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13265 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13266
13267 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13268 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13269 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13270 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13271 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13272 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13273
13274 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13275 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13276 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13277
13278 /* 5700 B0 chips do not support checksumming correctly due
13279 * to hardware bugs.
13280 */
13281 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13282 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13283 else {
13284 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13285
13286 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13287 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13288 features |= NETIF_F_IPV6_CSUM;
13289 tp->dev->features |= features;
13290 vlan_features_add(tp->dev, features);
13291 }
13292
13293 /* Determine TSO capabilities */
13294 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13295 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13296 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13297 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13298 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13299 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13300 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13301 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13302 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13303 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13304 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13305 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13306 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13307 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13308 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13309 tp->fw_needed = FIRMWARE_TG3TSO5;
13310 else
13311 tp->fw_needed = FIRMWARE_TG3TSO;
13312 }
13313
13314 tp->irq_max = 1;
13315
13316 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13317 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13318 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13319 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13320 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13321 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13322 tp->pdev_peer == tp->pdev))
13323 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13324
13325 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13326 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13327 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13328 }
13329
13330 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13331 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13332 tp->irq_max = TG3_IRQ_MAX_VECS;
13333 }
13334 }
13335
13336 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13337 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13338 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13339 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13340 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13341 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13342 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13343 }
13344
13345 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13346 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13347
13348 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13349 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13350 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13351 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13352
13353 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13354 &pci_state_reg);
13355
13356 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13357 if (tp->pcie_cap != 0) {
13358 u16 lnkctl;
13359
13360 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13361
13362 pcie_set_readrq(tp->pdev, 4096);
13363
13364 pci_read_config_word(tp->pdev,
13365 tp->pcie_cap + PCI_EXP_LNKCTL,
13366 &lnkctl);
13367 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13368 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13369 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13370 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13371 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13372 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13373 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13374 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13375 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13376 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13377 }
13378 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13379 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13380 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13381 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13382 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13383 if (!tp->pcix_cap) {
13384 dev_err(&tp->pdev->dev,
13385 "Cannot find PCI-X capability, aborting\n");
13386 return -EIO;
13387 }
13388
13389 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13390 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13391 }
13392
13393 /* If we have an AMD 762 or VIA K8T800 chipset, write
13394 * reordering to the mailbox registers done by the host
13395 * controller can cause major troubles. We read back from
13396 * every mailbox register write to force the writes to be
13397 * posted to the chip in order.
13398 */
13399 if (pci_dev_present(write_reorder_chipsets) &&
13400 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13401 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13402
13403 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13404 &tp->pci_cacheline_sz);
13405 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13406 &tp->pci_lat_timer);
13407 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13408 tp->pci_lat_timer < 64) {
13409 tp->pci_lat_timer = 64;
13410 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13411 tp->pci_lat_timer);
13412 }
13413
13414 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13415 /* 5700 BX chips need to have their TX producer index
13416 * mailboxes written twice to workaround a bug.
13417 */
13418 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13419
13420 /* If we are in PCI-X mode, enable register write workaround.
13421 *
13422 * The workaround is to use indirect register accesses
13423 * for all chip writes not to mailbox registers.
13424 */
13425 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13426 u32 pm_reg;
13427
13428 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13429
13430 /* The chip can have it's power management PCI config
13431 * space registers clobbered due to this bug.
13432 * So explicitly force the chip into D0 here.
13433 */
13434 pci_read_config_dword(tp->pdev,
13435 tp->pm_cap + PCI_PM_CTRL,
13436 &pm_reg);
13437 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13438 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13439 pci_write_config_dword(tp->pdev,
13440 tp->pm_cap + PCI_PM_CTRL,
13441 pm_reg);
13442
13443 /* Also, force SERR#/PERR# in PCI command. */
13444 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13445 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13446 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13447 }
13448 }
13449
13450 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13451 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13452 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13453 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13454
13455 /* Chip-specific fixup from Broadcom driver */
13456 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13457 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13458 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13459 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13460 }
13461
13462 /* Default fast path register access methods */
13463 tp->read32 = tg3_read32;
13464 tp->write32 = tg3_write32;
13465 tp->read32_mbox = tg3_read32;
13466 tp->write32_mbox = tg3_write32;
13467 tp->write32_tx_mbox = tg3_write32;
13468 tp->write32_rx_mbox = tg3_write32;
13469
13470 /* Various workaround register access methods */
13471 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13472 tp->write32 = tg3_write_indirect_reg32;
13473 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13474 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13475 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13476 /*
13477 * Back to back register writes can cause problems on these
13478 * chips, the workaround is to read back all reg writes
13479 * except those to mailbox regs.
13480 *
13481 * See tg3_write_indirect_reg32().
13482 */
13483 tp->write32 = tg3_write_flush_reg32;
13484 }
13485
13486 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13487 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13488 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13489 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13490 tp->write32_rx_mbox = tg3_write_flush_reg32;
13491 }
13492
13493 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13494 tp->read32 = tg3_read_indirect_reg32;
13495 tp->write32 = tg3_write_indirect_reg32;
13496 tp->read32_mbox = tg3_read_indirect_mbox;
13497 tp->write32_mbox = tg3_write_indirect_mbox;
13498 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13499 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13500
13501 iounmap(tp->regs);
13502 tp->regs = NULL;
13503
13504 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13505 pci_cmd &= ~PCI_COMMAND_MEMORY;
13506 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13507 }
13508 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13509 tp->read32_mbox = tg3_read32_mbox_5906;
13510 tp->write32_mbox = tg3_write32_mbox_5906;
13511 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13512 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13513 }
13514
13515 if (tp->write32 == tg3_write_indirect_reg32 ||
13516 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13517 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13518 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13519 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13520
13521 /* Get eeprom hw config before calling tg3_set_power_state().
13522 * In particular, the TG3_FLG2_IS_NIC flag must be
13523 * determined before calling tg3_set_power_state() so that
13524 * we know whether or not to switch out of Vaux power.
13525 * When the flag is set, it means that GPIO1 is used for eeprom
13526 * write protect and also implies that it is a LOM where GPIOs
13527 * are not used to switch power.
13528 */
13529 tg3_get_eeprom_hw_cfg(tp);
13530
13531 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13532 /* Allow reads and writes to the
13533 * APE register and memory space.
13534 */
13535 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13536 PCISTATE_ALLOW_APE_SHMEM_WR |
13537 PCISTATE_ALLOW_APE_PSPACE_WR;
13538 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13539 pci_state_reg);
13540 }
13541
13542 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13543 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13544 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13546 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13547 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13548
13549 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13550 * GPIO1 driven high will bring 5700's external PHY out of reset.
13551 * It is also used as eeprom write protect on LOMs.
13552 */
13553 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13554 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13555 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13556 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13557 GRC_LCLCTRL_GPIO_OUTPUT1);
13558 /* Unused GPIO3 must be driven as output on 5752 because there
13559 * are no pull-up resistors on unused GPIO pins.
13560 */
13561 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13562 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13563
13564 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13565 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13566 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13567 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13568
13569 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13570 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13571 /* Turn off the debug UART. */
13572 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13573 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13574 /* Keep VMain power. */
13575 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13576 GRC_LCLCTRL_GPIO_OUTPUT0;
13577 }
13578
13579 /* Force the chip into D0. */
13580 err = tg3_set_power_state(tp, PCI_D0);
13581 if (err) {
13582 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13583 return err;
13584 }
13585
13586 /* Derive initial jumbo mode from MTU assigned in
13587 * ether_setup() via the alloc_etherdev() call
13588 */
13589 if (tp->dev->mtu > ETH_DATA_LEN &&
13590 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13591 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13592
13593 /* Determine WakeOnLan speed to use. */
13594 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13595 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13596 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13597 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13598 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13599 } else {
13600 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13601 }
13602
13603 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13604 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13605
13606 /* A few boards don't want Ethernet@WireSpeed phy feature */
13607 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13608 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13609 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13610 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13611 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13612 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13613 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13614
13615 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13616 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13617 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13618 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13619 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13620
13621 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13622 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13623 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13624 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13625 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13626 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13627 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13628 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13629 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13630 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13631 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13632 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13633 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13634 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13635 } else
13636 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13637 }
13638
13639 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13640 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13641 tp->phy_otp = tg3_read_otp_phycfg(tp);
13642 if (tp->phy_otp == 0)
13643 tp->phy_otp = TG3_OTP_DEFAULT;
13644 }
13645
13646 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13647 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13648 else
13649 tp->mi_mode = MAC_MI_MODE_BASE;
13650
13651 tp->coalesce_mode = 0;
13652 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13653 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13654 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13655
13656 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13657 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13658 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13659
13660 err = tg3_mdio_init(tp);
13661 if (err)
13662 return err;
13663
13664 /* Initialize data/descriptor byte/word swapping. */
13665 val = tr32(GRC_MODE);
13666 val &= GRC_MODE_HOST_STACKUP;
13667 tw32(GRC_MODE, val | tp->grc_mode);
13668
13669 tg3_switch_clocks(tp);
13670
13671 /* Clear this out for sanity. */
13672 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13673
13674 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13675 &pci_state_reg);
13676 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13677 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13678 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13679
13680 if (chiprevid == CHIPREV_ID_5701_A0 ||
13681 chiprevid == CHIPREV_ID_5701_B0 ||
13682 chiprevid == CHIPREV_ID_5701_B2 ||
13683 chiprevid == CHIPREV_ID_5701_B5) {
13684 void __iomem *sram_base;
13685
13686 /* Write some dummy words into the SRAM status block
13687 * area, see if it reads back correctly. If the return
13688 * value is bad, force enable the PCIX workaround.
13689 */
13690 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13691
13692 writel(0x00000000, sram_base);
13693 writel(0x00000000, sram_base + 4);
13694 writel(0xffffffff, sram_base + 4);
13695 if (readl(sram_base) != 0x00000000)
13696 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13697 }
13698 }
13699
13700 udelay(50);
13701 tg3_nvram_init(tp);
13702
13703 grc_misc_cfg = tr32(GRC_MISC_CFG);
13704 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13705
13706 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13707 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13708 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13709 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13710
13711 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13712 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13713 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13714 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13715 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13716 HOSTCC_MODE_CLRTICK_TXBD);
13717
13718 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13719 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13720 tp->misc_host_ctrl);
13721 }
13722
13723 /* Preserve the APE MAC_MODE bits */
13724 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13725 tp->mac_mode = tr32(MAC_MODE) |
13726 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13727 else
13728 tp->mac_mode = TG3_DEF_MAC_MODE;
13729
13730 /* these are limited to 10/100 only */
13731 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13732 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13733 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13734 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13735 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13736 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13737 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13738 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13739 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13740 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13741 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13742 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13743 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13744 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13745 (tp->phy_flags & TG3_PHYFLG_IS_FET))
13746 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13747
13748 err = tg3_phy_probe(tp);
13749 if (err) {
13750 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13751 /* ... but do not return immediately ... */
13752 tg3_mdio_fini(tp);
13753 }
13754
13755 tg3_read_vpd(tp);
13756 tg3_read_fw_ver(tp);
13757
13758 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13759 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13760 } else {
13761 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13762 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13763 else
13764 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13765 }
13766
13767 /* 5700 {AX,BX} chips have a broken status block link
13768 * change bit implementation, so we must use the
13769 * status register in those cases.
13770 */
13771 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13772 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13773 else
13774 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13775
13776 /* The led_ctrl is set during tg3_phy_probe, here we might
13777 * have to force the link status polling mechanism based
13778 * upon subsystem IDs.
13779 */
13780 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13781 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13782 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13783 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13784 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13785 }
13786
13787 /* For all SERDES we poll the MAC status register. */
13788 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13789 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13790 else
13791 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13792
13793 tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13794 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13795 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13796 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13797 tp->rx_offset -= NET_IP_ALIGN;
13798 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13799 tp->rx_copy_thresh = ~(u16)0;
13800 #endif
13801 }
13802
13803 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13804 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13805 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13806
13807 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13808
13809 /* Increment the rx prod index on the rx std ring by at most
13810 * 8 for these chips to workaround hw errata.
13811 */
13812 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13813 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13814 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13815 tp->rx_std_max_post = 8;
13816
13817 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13818 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13819 PCIE_PWR_MGMT_L1_THRESH_MSK;
13820
13821 return err;
13822 }
13823
13824 #ifdef CONFIG_SPARC
13825 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13826 {
13827 struct net_device *dev = tp->dev;
13828 struct pci_dev *pdev = tp->pdev;
13829 struct device_node *dp = pci_device_to_OF_node(pdev);
13830 const unsigned char *addr;
13831 int len;
13832
13833 addr = of_get_property(dp, "local-mac-address", &len);
13834 if (addr && len == 6) {
13835 memcpy(dev->dev_addr, addr, 6);
13836 memcpy(dev->perm_addr, dev->dev_addr, 6);
13837 return 0;
13838 }
13839 return -ENODEV;
13840 }
13841
13842 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13843 {
13844 struct net_device *dev = tp->dev;
13845
13846 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13847 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13848 return 0;
13849 }
13850 #endif
13851
13852 static int __devinit tg3_get_device_address(struct tg3 *tp)
13853 {
13854 struct net_device *dev = tp->dev;
13855 u32 hi, lo, mac_offset;
13856 int addr_ok = 0;
13857
13858 #ifdef CONFIG_SPARC
13859 if (!tg3_get_macaddr_sparc(tp))
13860 return 0;
13861 #endif
13862
13863 mac_offset = 0x7c;
13864 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13865 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13866 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13867 mac_offset = 0xcc;
13868 if (tg3_nvram_lock(tp))
13869 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13870 else
13871 tg3_nvram_unlock(tp);
13872 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13873 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13874 if (PCI_FUNC(tp->pdev->devfn) & 1)
13875 mac_offset = 0xcc;
13876 if (PCI_FUNC(tp->pdev->devfn) > 1)
13877 mac_offset += 0x18c;
13878 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13879 mac_offset = 0x10;
13880
13881 /* First try to get it from MAC address mailbox. */
13882 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13883 if ((hi >> 16) == 0x484b) {
13884 dev->dev_addr[0] = (hi >> 8) & 0xff;
13885 dev->dev_addr[1] = (hi >> 0) & 0xff;
13886
13887 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13888 dev->dev_addr[2] = (lo >> 24) & 0xff;
13889 dev->dev_addr[3] = (lo >> 16) & 0xff;
13890 dev->dev_addr[4] = (lo >> 8) & 0xff;
13891 dev->dev_addr[5] = (lo >> 0) & 0xff;
13892
13893 /* Some old bootcode may report a 0 MAC address in SRAM */
13894 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13895 }
13896 if (!addr_ok) {
13897 /* Next, try NVRAM. */
13898 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13899 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13900 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13901 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13902 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13903 }
13904 /* Finally just fetch it out of the MAC control regs. */
13905 else {
13906 hi = tr32(MAC_ADDR_0_HIGH);
13907 lo = tr32(MAC_ADDR_0_LOW);
13908
13909 dev->dev_addr[5] = lo & 0xff;
13910 dev->dev_addr[4] = (lo >> 8) & 0xff;
13911 dev->dev_addr[3] = (lo >> 16) & 0xff;
13912 dev->dev_addr[2] = (lo >> 24) & 0xff;
13913 dev->dev_addr[1] = hi & 0xff;
13914 dev->dev_addr[0] = (hi >> 8) & 0xff;
13915 }
13916 }
13917
13918 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13919 #ifdef CONFIG_SPARC
13920 if (!tg3_get_default_macaddr_sparc(tp))
13921 return 0;
13922 #endif
13923 return -EINVAL;
13924 }
13925 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13926 return 0;
13927 }
13928
13929 #define BOUNDARY_SINGLE_CACHELINE 1
13930 #define BOUNDARY_MULTI_CACHELINE 2
13931
13932 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13933 {
13934 int cacheline_size;
13935 u8 byte;
13936 int goal;
13937
13938 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13939 if (byte == 0)
13940 cacheline_size = 1024;
13941 else
13942 cacheline_size = (int) byte * 4;
13943
13944 /* On 5703 and later chips, the boundary bits have no
13945 * effect.
13946 */
13947 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13948 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13949 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13950 goto out;
13951
13952 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13953 goal = BOUNDARY_MULTI_CACHELINE;
13954 #else
13955 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13956 goal = BOUNDARY_SINGLE_CACHELINE;
13957 #else
13958 goal = 0;
13959 #endif
13960 #endif
13961
13962 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13963 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13964 goto out;
13965 }
13966
13967 if (!goal)
13968 goto out;
13969
13970 /* PCI controllers on most RISC systems tend to disconnect
13971 * when a device tries to burst across a cache-line boundary.
13972 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13973 *
13974 * Unfortunately, for PCI-E there are only limited
13975 * write-side controls for this, and thus for reads
13976 * we will still get the disconnects. We'll also waste
13977 * these PCI cycles for both read and write for chips
13978 * other than 5700 and 5701 which do not implement the
13979 * boundary bits.
13980 */
13981 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13982 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13983 switch (cacheline_size) {
13984 case 16:
13985 case 32:
13986 case 64:
13987 case 128:
13988 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13989 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13990 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13991 } else {
13992 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13993 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13994 }
13995 break;
13996
13997 case 256:
13998 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13999 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14000 break;
14001
14002 default:
14003 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14004 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14005 break;
14006 }
14007 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14008 switch (cacheline_size) {
14009 case 16:
14010 case 32:
14011 case 64:
14012 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14013 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14014 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14015 break;
14016 }
14017 /* fallthrough */
14018 case 128:
14019 default:
14020 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14021 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14022 break;
14023 }
14024 } else {
14025 switch (cacheline_size) {
14026 case 16:
14027 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14028 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14029 DMA_RWCTRL_WRITE_BNDRY_16);
14030 break;
14031 }
14032 /* fallthrough */
14033 case 32:
14034 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14035 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14036 DMA_RWCTRL_WRITE_BNDRY_32);
14037 break;
14038 }
14039 /* fallthrough */
14040 case 64:
14041 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14042 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14043 DMA_RWCTRL_WRITE_BNDRY_64);
14044 break;
14045 }
14046 /* fallthrough */
14047 case 128:
14048 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14049 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14050 DMA_RWCTRL_WRITE_BNDRY_128);
14051 break;
14052 }
14053 /* fallthrough */
14054 case 256:
14055 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14056 DMA_RWCTRL_WRITE_BNDRY_256);
14057 break;
14058 case 512:
14059 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14060 DMA_RWCTRL_WRITE_BNDRY_512);
14061 break;
14062 case 1024:
14063 default:
14064 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14065 DMA_RWCTRL_WRITE_BNDRY_1024);
14066 break;
14067 }
14068 }
14069
14070 out:
14071 return val;
14072 }
14073
14074 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14075 {
14076 struct tg3_internal_buffer_desc test_desc;
14077 u32 sram_dma_descs;
14078 int i, ret;
14079
14080 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14081
14082 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14083 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14084 tw32(RDMAC_STATUS, 0);
14085 tw32(WDMAC_STATUS, 0);
14086
14087 tw32(BUFMGR_MODE, 0);
14088 tw32(FTQ_RESET, 0);
14089
14090 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14091 test_desc.addr_lo = buf_dma & 0xffffffff;
14092 test_desc.nic_mbuf = 0x00002100;
14093 test_desc.len = size;
14094
14095 /*
14096 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14097 * the *second* time the tg3 driver was getting loaded after an
14098 * initial scan.
14099 *
14100 * Broadcom tells me:
14101 * ...the DMA engine is connected to the GRC block and a DMA
14102 * reset may affect the GRC block in some unpredictable way...
14103 * The behavior of resets to individual blocks has not been tested.
14104 *
14105 * Broadcom noted the GRC reset will also reset all sub-components.
14106 */
14107 if (to_device) {
14108 test_desc.cqid_sqid = (13 << 8) | 2;
14109
14110 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14111 udelay(40);
14112 } else {
14113 test_desc.cqid_sqid = (16 << 8) | 7;
14114
14115 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14116 udelay(40);
14117 }
14118 test_desc.flags = 0x00000005;
14119
14120 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14121 u32 val;
14122
14123 val = *(((u32 *)&test_desc) + i);
14124 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14125 sram_dma_descs + (i * sizeof(u32)));
14126 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14127 }
14128 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14129
14130 if (to_device)
14131 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14132 else
14133 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14134
14135 ret = -ENODEV;
14136 for (i = 0; i < 40; i++) {
14137 u32 val;
14138
14139 if (to_device)
14140 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14141 else
14142 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14143 if ((val & 0xffff) == sram_dma_descs) {
14144 ret = 0;
14145 break;
14146 }
14147
14148 udelay(100);
14149 }
14150
14151 return ret;
14152 }
14153
14154 #define TEST_BUFFER_SIZE 0x2000
14155
14156 static int __devinit tg3_test_dma(struct tg3 *tp)
14157 {
14158 dma_addr_t buf_dma;
14159 u32 *buf, saved_dma_rwctrl;
14160 int ret = 0;
14161
14162 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14163 if (!buf) {
14164 ret = -ENOMEM;
14165 goto out_nofree;
14166 }
14167
14168 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14169 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14170
14171 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14172
14173 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14174 goto out;
14175
14176 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14177 /* DMA read watermark not used on PCIE */
14178 tp->dma_rwctrl |= 0x00180000;
14179 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14180 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14181 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14182 tp->dma_rwctrl |= 0x003f0000;
14183 else
14184 tp->dma_rwctrl |= 0x003f000f;
14185 } else {
14186 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14187 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14188 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14189 u32 read_water = 0x7;
14190
14191 /* If the 5704 is behind the EPB bridge, we can
14192 * do the less restrictive ONE_DMA workaround for
14193 * better performance.
14194 */
14195 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14196 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14197 tp->dma_rwctrl |= 0x8000;
14198 else if (ccval == 0x6 || ccval == 0x7)
14199 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14200
14201 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14202 read_water = 4;
14203 /* Set bit 23 to enable PCIX hw bug fix */
14204 tp->dma_rwctrl |=
14205 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14206 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14207 (1 << 23);
14208 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14209 /* 5780 always in PCIX mode */
14210 tp->dma_rwctrl |= 0x00144000;
14211 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14212 /* 5714 always in PCIX mode */
14213 tp->dma_rwctrl |= 0x00148000;
14214 } else {
14215 tp->dma_rwctrl |= 0x001b000f;
14216 }
14217 }
14218
14219 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14220 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14221 tp->dma_rwctrl &= 0xfffffff0;
14222
14223 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14224 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14225 /* Remove this if it causes problems for some boards. */
14226 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14227
14228 /* On 5700/5701 chips, we need to set this bit.
14229 * Otherwise the chip will issue cacheline transactions
14230 * to streamable DMA memory with not all the byte
14231 * enables turned on. This is an error on several
14232 * RISC PCI controllers, in particular sparc64.
14233 *
14234 * On 5703/5704 chips, this bit has been reassigned
14235 * a different meaning. In particular, it is used
14236 * on those chips to enable a PCI-X workaround.
14237 */
14238 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14239 }
14240
14241 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14242
14243 #if 0
14244 /* Unneeded, already done by tg3_get_invariants. */
14245 tg3_switch_clocks(tp);
14246 #endif
14247
14248 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14249 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14250 goto out;
14251
14252 /* It is best to perform DMA test with maximum write burst size
14253 * to expose the 5700/5701 write DMA bug.
14254 */
14255 saved_dma_rwctrl = tp->dma_rwctrl;
14256 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14257 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14258
14259 while (1) {
14260 u32 *p = buf, i;
14261
14262 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14263 p[i] = i;
14264
14265 /* Send the buffer to the chip. */
14266 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14267 if (ret) {
14268 dev_err(&tp->pdev->dev,
14269 "%s: Buffer write failed. err = %d\n",
14270 __func__, ret);
14271 break;
14272 }
14273
14274 #if 0
14275 /* validate data reached card RAM correctly. */
14276 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14277 u32 val;
14278 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14279 if (le32_to_cpu(val) != p[i]) {
14280 dev_err(&tp->pdev->dev,
14281 "%s: Buffer corrupted on device! "
14282 "(%d != %d)\n", __func__, val, i);
14283 /* ret = -ENODEV here? */
14284 }
14285 p[i] = 0;
14286 }
14287 #endif
14288 /* Now read it back. */
14289 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14290 if (ret) {
14291 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14292 "err = %d\n", __func__, ret);
14293 break;
14294 }
14295
14296 /* Verify it. */
14297 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14298 if (p[i] == i)
14299 continue;
14300
14301 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14302 DMA_RWCTRL_WRITE_BNDRY_16) {
14303 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14304 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14305 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14306 break;
14307 } else {
14308 dev_err(&tp->pdev->dev,
14309 "%s: Buffer corrupted on read back! "
14310 "(%d != %d)\n", __func__, p[i], i);
14311 ret = -ENODEV;
14312 goto out;
14313 }
14314 }
14315
14316 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14317 /* Success. */
14318 ret = 0;
14319 break;
14320 }
14321 }
14322 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14323 DMA_RWCTRL_WRITE_BNDRY_16) {
14324 static struct pci_device_id dma_wait_state_chipsets[] = {
14325 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14326 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14327 { },
14328 };
14329
14330 /* DMA test passed without adjusting DMA boundary,
14331 * now look for chipsets that are known to expose the
14332 * DMA bug without failing the test.
14333 */
14334 if (pci_dev_present(dma_wait_state_chipsets)) {
14335 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14336 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14337 } else {
14338 /* Safe to use the calculated DMA boundary. */
14339 tp->dma_rwctrl = saved_dma_rwctrl;
14340 }
14341
14342 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14343 }
14344
14345 out:
14346 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14347 out_nofree:
14348 return ret;
14349 }
14350
14351 static void __devinit tg3_init_link_config(struct tg3 *tp)
14352 {
14353 tp->link_config.advertising =
14354 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14355 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14356 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14357 ADVERTISED_Autoneg | ADVERTISED_MII);
14358 tp->link_config.speed = SPEED_INVALID;
14359 tp->link_config.duplex = DUPLEX_INVALID;
14360 tp->link_config.autoneg = AUTONEG_ENABLE;
14361 tp->link_config.active_speed = SPEED_INVALID;
14362 tp->link_config.active_duplex = DUPLEX_INVALID;
14363 tp->link_config.orig_speed = SPEED_INVALID;
14364 tp->link_config.orig_duplex = DUPLEX_INVALID;
14365 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14366 }
14367
14368 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14369 {
14370 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14371 tp->bufmgr_config.mbuf_read_dma_low_water =
14372 DEFAULT_MB_RDMA_LOW_WATER_5705;
14373 tp->bufmgr_config.mbuf_mac_rx_low_water =
14374 DEFAULT_MB_MACRX_LOW_WATER_57765;
14375 tp->bufmgr_config.mbuf_high_water =
14376 DEFAULT_MB_HIGH_WATER_57765;
14377
14378 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14379 DEFAULT_MB_RDMA_LOW_WATER_5705;
14380 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14381 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14382 tp->bufmgr_config.mbuf_high_water_jumbo =
14383 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14384 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14385 tp->bufmgr_config.mbuf_read_dma_low_water =
14386 DEFAULT_MB_RDMA_LOW_WATER_5705;
14387 tp->bufmgr_config.mbuf_mac_rx_low_water =
14388 DEFAULT_MB_MACRX_LOW_WATER_5705;
14389 tp->bufmgr_config.mbuf_high_water =
14390 DEFAULT_MB_HIGH_WATER_5705;
14391 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14392 tp->bufmgr_config.mbuf_mac_rx_low_water =
14393 DEFAULT_MB_MACRX_LOW_WATER_5906;
14394 tp->bufmgr_config.mbuf_high_water =
14395 DEFAULT_MB_HIGH_WATER_5906;
14396 }
14397
14398 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14399 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14400 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14401 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14402 tp->bufmgr_config.mbuf_high_water_jumbo =
14403 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14404 } else {
14405 tp->bufmgr_config.mbuf_read_dma_low_water =
14406 DEFAULT_MB_RDMA_LOW_WATER;
14407 tp->bufmgr_config.mbuf_mac_rx_low_water =
14408 DEFAULT_MB_MACRX_LOW_WATER;
14409 tp->bufmgr_config.mbuf_high_water =
14410 DEFAULT_MB_HIGH_WATER;
14411
14412 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14413 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14414 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14415 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14416 tp->bufmgr_config.mbuf_high_water_jumbo =
14417 DEFAULT_MB_HIGH_WATER_JUMBO;
14418 }
14419
14420 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14421 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14422 }
14423
14424 static char * __devinit tg3_phy_string(struct tg3 *tp)
14425 {
14426 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14427 case TG3_PHY_ID_BCM5400: return "5400";
14428 case TG3_PHY_ID_BCM5401: return "5401";
14429 case TG3_PHY_ID_BCM5411: return "5411";
14430 case TG3_PHY_ID_BCM5701: return "5701";
14431 case TG3_PHY_ID_BCM5703: return "5703";
14432 case TG3_PHY_ID_BCM5704: return "5704";
14433 case TG3_PHY_ID_BCM5705: return "5705";
14434 case TG3_PHY_ID_BCM5750: return "5750";
14435 case TG3_PHY_ID_BCM5752: return "5752";
14436 case TG3_PHY_ID_BCM5714: return "5714";
14437 case TG3_PHY_ID_BCM5780: return "5780";
14438 case TG3_PHY_ID_BCM5755: return "5755";
14439 case TG3_PHY_ID_BCM5787: return "5787";
14440 case TG3_PHY_ID_BCM5784: return "5784";
14441 case TG3_PHY_ID_BCM5756: return "5722/5756";
14442 case TG3_PHY_ID_BCM5906: return "5906";
14443 case TG3_PHY_ID_BCM5761: return "5761";
14444 case TG3_PHY_ID_BCM5718C: return "5718C";
14445 case TG3_PHY_ID_BCM5718S: return "5718S";
14446 case TG3_PHY_ID_BCM57765: return "57765";
14447 case TG3_PHY_ID_BCM5719C: return "5719C";
14448 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14449 case 0: return "serdes";
14450 default: return "unknown";
14451 }
14452 }
14453
14454 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14455 {
14456 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14457 strcpy(str, "PCI Express");
14458 return str;
14459 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14460 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14461
14462 strcpy(str, "PCIX:");
14463
14464 if ((clock_ctrl == 7) ||
14465 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14466 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14467 strcat(str, "133MHz");
14468 else if (clock_ctrl == 0)
14469 strcat(str, "33MHz");
14470 else if (clock_ctrl == 2)
14471 strcat(str, "50MHz");
14472 else if (clock_ctrl == 4)
14473 strcat(str, "66MHz");
14474 else if (clock_ctrl == 6)
14475 strcat(str, "100MHz");
14476 } else {
14477 strcpy(str, "PCI:");
14478 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14479 strcat(str, "66MHz");
14480 else
14481 strcat(str, "33MHz");
14482 }
14483 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14484 strcat(str, ":32-bit");
14485 else
14486 strcat(str, ":64-bit");
14487 return str;
14488 }
14489
14490 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14491 {
14492 struct pci_dev *peer;
14493 unsigned int func, devnr = tp->pdev->devfn & ~7;
14494
14495 for (func = 0; func < 8; func++) {
14496 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14497 if (peer && peer != tp->pdev)
14498 break;
14499 pci_dev_put(peer);
14500 }
14501 /* 5704 can be configured in single-port mode, set peer to
14502 * tp->pdev in that case.
14503 */
14504 if (!peer) {
14505 peer = tp->pdev;
14506 return peer;
14507 }
14508
14509 /*
14510 * We don't need to keep the refcount elevated; there's no way
14511 * to remove one half of this device without removing the other
14512 */
14513 pci_dev_put(peer);
14514
14515 return peer;
14516 }
14517
14518 static void __devinit tg3_init_coal(struct tg3 *tp)
14519 {
14520 struct ethtool_coalesce *ec = &tp->coal;
14521
14522 memset(ec, 0, sizeof(*ec));
14523 ec->cmd = ETHTOOL_GCOALESCE;
14524 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14525 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14526 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14527 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14528 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14529 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14530 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14531 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14532 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14533
14534 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14535 HOSTCC_MODE_CLRTICK_TXBD)) {
14536 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14537 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14538 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14539 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14540 }
14541
14542 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14543 ec->rx_coalesce_usecs_irq = 0;
14544 ec->tx_coalesce_usecs_irq = 0;
14545 ec->stats_block_coalesce_usecs = 0;
14546 }
14547 }
14548
14549 static const struct net_device_ops tg3_netdev_ops = {
14550 .ndo_open = tg3_open,
14551 .ndo_stop = tg3_close,
14552 .ndo_start_xmit = tg3_start_xmit,
14553 .ndo_get_stats64 = tg3_get_stats64,
14554 .ndo_validate_addr = eth_validate_addr,
14555 .ndo_set_multicast_list = tg3_set_rx_mode,
14556 .ndo_set_mac_address = tg3_set_mac_addr,
14557 .ndo_do_ioctl = tg3_ioctl,
14558 .ndo_tx_timeout = tg3_tx_timeout,
14559 .ndo_change_mtu = tg3_change_mtu,
14560 #if TG3_VLAN_TAG_USED
14561 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14562 #endif
14563 #ifdef CONFIG_NET_POLL_CONTROLLER
14564 .ndo_poll_controller = tg3_poll_controller,
14565 #endif
14566 };
14567
14568 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14569 .ndo_open = tg3_open,
14570 .ndo_stop = tg3_close,
14571 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14572 .ndo_get_stats64 = tg3_get_stats64,
14573 .ndo_validate_addr = eth_validate_addr,
14574 .ndo_set_multicast_list = tg3_set_rx_mode,
14575 .ndo_set_mac_address = tg3_set_mac_addr,
14576 .ndo_do_ioctl = tg3_ioctl,
14577 .ndo_tx_timeout = tg3_tx_timeout,
14578 .ndo_change_mtu = tg3_change_mtu,
14579 #if TG3_VLAN_TAG_USED
14580 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14581 #endif
14582 #ifdef CONFIG_NET_POLL_CONTROLLER
14583 .ndo_poll_controller = tg3_poll_controller,
14584 #endif
14585 };
14586
14587 static int __devinit tg3_init_one(struct pci_dev *pdev,
14588 const struct pci_device_id *ent)
14589 {
14590 struct net_device *dev;
14591 struct tg3 *tp;
14592 int i, err, pm_cap;
14593 u32 sndmbx, rcvmbx, intmbx;
14594 char str[40];
14595 u64 dma_mask, persist_dma_mask;
14596
14597 printk_once(KERN_INFO "%s\n", version);
14598
14599 err = pci_enable_device(pdev);
14600 if (err) {
14601 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14602 return err;
14603 }
14604
14605 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14606 if (err) {
14607 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14608 goto err_out_disable_pdev;
14609 }
14610
14611 pci_set_master(pdev);
14612
14613 /* Find power-management capability. */
14614 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14615 if (pm_cap == 0) {
14616 dev_err(&pdev->dev,
14617 "Cannot find Power Management capability, aborting\n");
14618 err = -EIO;
14619 goto err_out_free_res;
14620 }
14621
14622 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14623 if (!dev) {
14624 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14625 err = -ENOMEM;
14626 goto err_out_free_res;
14627 }
14628
14629 SET_NETDEV_DEV(dev, &pdev->dev);
14630
14631 #if TG3_VLAN_TAG_USED
14632 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14633 #endif
14634
14635 tp = netdev_priv(dev);
14636 tp->pdev = pdev;
14637 tp->dev = dev;
14638 tp->pm_cap = pm_cap;
14639 tp->rx_mode = TG3_DEF_RX_MODE;
14640 tp->tx_mode = TG3_DEF_TX_MODE;
14641
14642 if (tg3_debug > 0)
14643 tp->msg_enable = tg3_debug;
14644 else
14645 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14646
14647 /* The word/byte swap controls here control register access byte
14648 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14649 * setting below.
14650 */
14651 tp->misc_host_ctrl =
14652 MISC_HOST_CTRL_MASK_PCI_INT |
14653 MISC_HOST_CTRL_WORD_SWAP |
14654 MISC_HOST_CTRL_INDIR_ACCESS |
14655 MISC_HOST_CTRL_PCISTATE_RW;
14656
14657 /* The NONFRM (non-frame) byte/word swap controls take effect
14658 * on descriptor entries, anything which isn't packet data.
14659 *
14660 * The StrongARM chips on the board (one for tx, one for rx)
14661 * are running in big-endian mode.
14662 */
14663 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14664 GRC_MODE_WSWAP_NONFRM_DATA);
14665 #ifdef __BIG_ENDIAN
14666 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14667 #endif
14668 spin_lock_init(&tp->lock);
14669 spin_lock_init(&tp->indirect_lock);
14670 INIT_WORK(&tp->reset_task, tg3_reset_task);
14671
14672 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14673 if (!tp->regs) {
14674 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14675 err = -ENOMEM;
14676 goto err_out_free_dev;
14677 }
14678
14679 tg3_init_link_config(tp);
14680
14681 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14682 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14683
14684 dev->ethtool_ops = &tg3_ethtool_ops;
14685 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14686 dev->irq = pdev->irq;
14687
14688 err = tg3_get_invariants(tp);
14689 if (err) {
14690 dev_err(&pdev->dev,
14691 "Problem fetching invariants of chip, aborting\n");
14692 goto err_out_iounmap;
14693 }
14694
14695 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14696 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14697 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14698 dev->netdev_ops = &tg3_netdev_ops;
14699 else
14700 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14701
14702
14703 /* The EPB bridge inside 5714, 5715, and 5780 and any
14704 * device behind the EPB cannot support DMA addresses > 40-bit.
14705 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14706 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14707 * do DMA address check in tg3_start_xmit().
14708 */
14709 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14710 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14711 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14712 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14713 #ifdef CONFIG_HIGHMEM
14714 dma_mask = DMA_BIT_MASK(64);
14715 #endif
14716 } else
14717 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14718
14719 /* Configure DMA attributes. */
14720 if (dma_mask > DMA_BIT_MASK(32)) {
14721 err = pci_set_dma_mask(pdev, dma_mask);
14722 if (!err) {
14723 dev->features |= NETIF_F_HIGHDMA;
14724 err = pci_set_consistent_dma_mask(pdev,
14725 persist_dma_mask);
14726 if (err < 0) {
14727 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14728 "DMA for consistent allocations\n");
14729 goto err_out_iounmap;
14730 }
14731 }
14732 }
14733 if (err || dma_mask == DMA_BIT_MASK(32)) {
14734 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14735 if (err) {
14736 dev_err(&pdev->dev,
14737 "No usable DMA configuration, aborting\n");
14738 goto err_out_iounmap;
14739 }
14740 }
14741
14742 tg3_init_bufmgr_config(tp);
14743
14744 /* Selectively allow TSO based on operating conditions */
14745 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14746 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14747 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14748 else {
14749 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14750 tp->fw_needed = NULL;
14751 }
14752
14753 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14754 tp->fw_needed = FIRMWARE_TG3;
14755
14756 /* TSO is on by default on chips that support hardware TSO.
14757 * Firmware TSO on older chips gives lower performance, so it
14758 * is off by default, but can be enabled using ethtool.
14759 */
14760 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14761 (dev->features & NETIF_F_IP_CSUM)) {
14762 dev->features |= NETIF_F_TSO;
14763 vlan_features_add(dev, NETIF_F_TSO);
14764 }
14765 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14766 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14767 if (dev->features & NETIF_F_IPV6_CSUM) {
14768 dev->features |= NETIF_F_TSO6;
14769 vlan_features_add(dev, NETIF_F_TSO6);
14770 }
14771 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14772 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14773 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14774 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14775 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14776 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14777 dev->features |= NETIF_F_TSO_ECN;
14778 vlan_features_add(dev, NETIF_F_TSO_ECN);
14779 }
14780 }
14781
14782 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14783 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14784 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14785 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14786 tp->rx_pending = 63;
14787 }
14788
14789 err = tg3_get_device_address(tp);
14790 if (err) {
14791 dev_err(&pdev->dev,
14792 "Could not obtain valid ethernet address, aborting\n");
14793 goto err_out_iounmap;
14794 }
14795
14796 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14797 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14798 if (!tp->aperegs) {
14799 dev_err(&pdev->dev,
14800 "Cannot map APE registers, aborting\n");
14801 err = -ENOMEM;
14802 goto err_out_iounmap;
14803 }
14804
14805 tg3_ape_lock_init(tp);
14806
14807 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14808 tg3_read_dash_ver(tp);
14809 }
14810
14811 /*
14812 * Reset chip in case UNDI or EFI driver did not shutdown
14813 * DMA self test will enable WDMAC and we'll see (spurious)
14814 * pending DMA on the PCI bus at that point.
14815 */
14816 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14817 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14818 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14819 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14820 }
14821
14822 err = tg3_test_dma(tp);
14823 if (err) {
14824 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14825 goto err_out_apeunmap;
14826 }
14827
14828 /* flow control autonegotiation is default behavior */
14829 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14830 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14831
14832 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14833 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14834 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14835 for (i = 0; i < tp->irq_max; i++) {
14836 struct tg3_napi *tnapi = &tp->napi[i];
14837
14838 tnapi->tp = tp;
14839 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14840
14841 tnapi->int_mbox = intmbx;
14842 if (i < 4)
14843 intmbx += 0x8;
14844 else
14845 intmbx += 0x4;
14846
14847 tnapi->consmbox = rcvmbx;
14848 tnapi->prodmbox = sndmbx;
14849
14850 if (i)
14851 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14852 else
14853 tnapi->coal_now = HOSTCC_MODE_NOW;
14854
14855 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14856 break;
14857
14858 /*
14859 * If we support MSIX, we'll be using RSS. If we're using
14860 * RSS, the first vector only handles link interrupts and the
14861 * remaining vectors handle rx and tx interrupts. Reuse the
14862 * mailbox values for the next iteration. The values we setup
14863 * above are still useful for the single vectored mode.
14864 */
14865 if (!i)
14866 continue;
14867
14868 rcvmbx += 0x8;
14869
14870 if (sndmbx & 0x4)
14871 sndmbx -= 0x4;
14872 else
14873 sndmbx += 0xc;
14874 }
14875
14876 tg3_init_coal(tp);
14877
14878 pci_set_drvdata(pdev, dev);
14879
14880 err = register_netdev(dev);
14881 if (err) {
14882 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14883 goto err_out_apeunmap;
14884 }
14885
14886 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14887 tp->board_part_number,
14888 tp->pci_chip_rev_id,
14889 tg3_bus_string(tp, str),
14890 dev->dev_addr);
14891
14892 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14893 struct phy_device *phydev;
14894 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14895 netdev_info(dev,
14896 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14897 phydev->drv->name, dev_name(&phydev->dev));
14898 } else {
14899 char *ethtype;
14900
14901 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14902 ethtype = "10/100Base-TX";
14903 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14904 ethtype = "1000Base-SX";
14905 else
14906 ethtype = "10/100/1000Base-T";
14907
14908 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14909 "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14910 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14911 }
14912
14913 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14914 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14915 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14916 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14917 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14918 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14919 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14920 tp->dma_rwctrl,
14921 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14922 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14923
14924 return 0;
14925
14926 err_out_apeunmap:
14927 if (tp->aperegs) {
14928 iounmap(tp->aperegs);
14929 tp->aperegs = NULL;
14930 }
14931
14932 err_out_iounmap:
14933 if (tp->regs) {
14934 iounmap(tp->regs);
14935 tp->regs = NULL;
14936 }
14937
14938 err_out_free_dev:
14939 free_netdev(dev);
14940
14941 err_out_free_res:
14942 pci_release_regions(pdev);
14943
14944 err_out_disable_pdev:
14945 pci_disable_device(pdev);
14946 pci_set_drvdata(pdev, NULL);
14947 return err;
14948 }
14949
14950 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14951 {
14952 struct net_device *dev = pci_get_drvdata(pdev);
14953
14954 if (dev) {
14955 struct tg3 *tp = netdev_priv(dev);
14956
14957 if (tp->fw)
14958 release_firmware(tp->fw);
14959
14960 flush_scheduled_work();
14961
14962 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14963 tg3_phy_fini(tp);
14964 tg3_mdio_fini(tp);
14965 }
14966
14967 unregister_netdev(dev);
14968 if (tp->aperegs) {
14969 iounmap(tp->aperegs);
14970 tp->aperegs = NULL;
14971 }
14972 if (tp->regs) {
14973 iounmap(tp->regs);
14974 tp->regs = NULL;
14975 }
14976 free_netdev(dev);
14977 pci_release_regions(pdev);
14978 pci_disable_device(pdev);
14979 pci_set_drvdata(pdev, NULL);
14980 }
14981 }
14982
14983 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14984 {
14985 struct net_device *dev = pci_get_drvdata(pdev);
14986 struct tg3 *tp = netdev_priv(dev);
14987 pci_power_t target_state;
14988 int err;
14989
14990 /* PCI register 4 needs to be saved whether netif_running() or not.
14991 * MSI address and data need to be saved if using MSI and
14992 * netif_running().
14993 */
14994 pci_save_state(pdev);
14995
14996 if (!netif_running(dev))
14997 return 0;
14998
14999 flush_scheduled_work();
15000 tg3_phy_stop(tp);
15001 tg3_netif_stop(tp);
15002
15003 del_timer_sync(&tp->timer);
15004
15005 tg3_full_lock(tp, 1);
15006 tg3_disable_ints(tp);
15007 tg3_full_unlock(tp);
15008
15009 netif_device_detach(dev);
15010
15011 tg3_full_lock(tp, 0);
15012 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15013 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15014 tg3_full_unlock(tp);
15015
15016 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
15017
15018 err = tg3_set_power_state(tp, target_state);
15019 if (err) {
15020 int err2;
15021
15022 tg3_full_lock(tp, 0);
15023
15024 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15025 err2 = tg3_restart_hw(tp, 1);
15026 if (err2)
15027 goto out;
15028
15029 tp->timer.expires = jiffies + tp->timer_offset;
15030 add_timer(&tp->timer);
15031
15032 netif_device_attach(dev);
15033 tg3_netif_start(tp);
15034
15035 out:
15036 tg3_full_unlock(tp);
15037
15038 if (!err2)
15039 tg3_phy_start(tp);
15040 }
15041
15042 return err;
15043 }
15044
15045 static int tg3_resume(struct pci_dev *pdev)
15046 {
15047 struct net_device *dev = pci_get_drvdata(pdev);
15048 struct tg3 *tp = netdev_priv(dev);
15049 int err;
15050
15051 pci_restore_state(tp->pdev);
15052
15053 if (!netif_running(dev))
15054 return 0;
15055
15056 err = tg3_set_power_state(tp, PCI_D0);
15057 if (err)
15058 return err;
15059
15060 netif_device_attach(dev);
15061
15062 tg3_full_lock(tp, 0);
15063
15064 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15065 err = tg3_restart_hw(tp, 1);
15066 if (err)
15067 goto out;
15068
15069 tp->timer.expires = jiffies + tp->timer_offset;
15070 add_timer(&tp->timer);
15071
15072 tg3_netif_start(tp);
15073
15074 out:
15075 tg3_full_unlock(tp);
15076
15077 if (!err)
15078 tg3_phy_start(tp);
15079
15080 return err;
15081 }
15082
15083 static struct pci_driver tg3_driver = {
15084 .name = DRV_MODULE_NAME,
15085 .id_table = tg3_pci_tbl,
15086 .probe = tg3_init_one,
15087 .remove = __devexit_p(tg3_remove_one),
15088 .suspend = tg3_suspend,
15089 .resume = tg3_resume
15090 };
15091
15092 static int __init tg3_init(void)
15093 {
15094 return pci_register_driver(&tg3_driver);
15095 }
15096
15097 static void __exit tg3_cleanup(void)
15098 {
15099 pci_unregister_driver(&tg3_driver);
15100 }
15101
15102 module_init(tg3_init);
15103 module_exit(tg3_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree