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ARM: PL08x: ensure loops use cpu_relax()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / r6040.c
blob0b014c894686b06921d4fa4fa31321fdb0d1412e
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/interrupt.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/mii.h>
40 #include <linux/ethtool.h>
41 #include <linux/crc32.h>
42 #include <linux/spinlock.h>
43 #include <linux/bitops.h>
44 #include <linux/io.h>
45 #include <linux/irq.h>
46 #include <linux/uaccess.h>
47 #include <linux/phy.h>
48
49 #include <asm/processor.h>
50
51 #define DRV_NAME "r6040"
52 #define DRV_VERSION "0.26"
53 #define DRV_RELDATE "30May2010"
54
55 /* PHY CHIP Address */
56 #define PHY1_ADDR 1 /* For MAC1 */
57 #define PHY2_ADDR 3 /* For MAC2 */
58 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
59 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
60
61 /* Time in jiffies before concluding the transmitter is hung. */
62 #define TX_TIMEOUT (6000 * HZ / 1000)
63
64 /* RDC MAC I/O Size */
65 #define R6040_IO_SIZE 256
66
67 /* MAX RDC MAC */
68 #define MAX_MAC 2
69
70 /* MAC registers */
71 #define MCR0 0x00 /* Control register 0 */
72 #define MCR1 0x04 /* Control register 1 */
73 #define MAC_RST 0x0001 /* Reset the MAC */
74 #define MBCR 0x08 /* Bus control */
75 #define MT_ICR 0x0C /* TX interrupt control */
76 #define MR_ICR 0x10 /* RX interrupt control */
77 #define MTPR 0x14 /* TX poll command register */
78 #define MR_BSR 0x18 /* RX buffer size */
79 #define MR_DCR 0x1A /* RX descriptor control */
80 #define MLSR 0x1C /* Last status */
81 #define MMDIO 0x20 /* MDIO control register */
82 #define MDIO_WRITE 0x4000 /* MDIO write */
83 #define MDIO_READ 0x2000 /* MDIO read */
84 #define MMRD 0x24 /* MDIO read data register */
85 #define MMWD 0x28 /* MDIO write data register */
86 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
87 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
88 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
89 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
90 #define MISR 0x3C /* Status register */
91 #define MIER 0x40 /* INT enable register */
92 #define MSK_INT 0x0000 /* Mask off interrupts */
93 #define RX_FINISH 0x0001 /* RX finished */
94 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
95 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
96 #define RX_EARLY 0x0008 /* RX early */
97 #define TX_FINISH 0x0010 /* TX finished */
98 #define TX_EARLY 0x0080 /* TX early */
99 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
100 #define LINK_CHANGED 0x0200 /* PHY link changed */
101 #define ME_CISR 0x44 /* Event counter INT status */
102 #define ME_CIER 0x48 /* Event counter INT enable */
103 #define MR_CNT 0x50 /* Successfully received packet counter */
104 #define ME_CNT0 0x52 /* Event counter 0 */
105 #define ME_CNT1 0x54 /* Event counter 1 */
106 #define ME_CNT2 0x56 /* Event counter 2 */
107 #define ME_CNT3 0x58 /* Event counter 3 */
108 #define MT_CNT 0x5A /* Successfully transmit packet counter */
109 #define ME_CNT4 0x5C /* Event counter 4 */
110 #define MP_CNT 0x5E /* Pause frame counter register */
111 #define MAR0 0x60 /* Hash table 0 */
112 #define MAR1 0x62 /* Hash table 1 */
113 #define MAR2 0x64 /* Hash table 2 */
114 #define MAR3 0x66 /* Hash table 3 */
115 #define MID_0L 0x68 /* Multicast address MID0 Low */
116 #define MID_0M 0x6A /* Multicast address MID0 Medium */
117 #define MID_0H 0x6C /* Multicast address MID0 High */
118 #define MID_1L 0x70 /* MID1 Low */
119 #define MID_1M 0x72 /* MID1 Medium */
120 #define MID_1H 0x74 /* MID1 High */
121 #define MID_2L 0x78 /* MID2 Low */
122 #define MID_2M 0x7A /* MID2 Medium */
123 #define MID_2H 0x7C /* MID2 High */
124 #define MID_3L 0x80 /* MID3 Low */
125 #define MID_3M 0x82 /* MID3 Medium */
126 #define MID_3H 0x84 /* MID3 High */
127 #define PHY_CC 0x88 /* PHY status change configuration register */
128 #define PHY_ST 0x8A /* PHY status register */
129 #define MAC_SM 0xAC /* MAC status machine */
130 #define MAC_ID 0xBE /* Identifier register */
131
132 #define TX_DCNT 0x80 /* TX descriptor count */
133 #define RX_DCNT 0x80 /* RX descriptor count */
134 #define MAX_BUF_SIZE 0x600
135 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
136 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
137 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
138 #define MCAST_MAX 3 /* Max number multicast addresses to filter */
139
140 /* Descriptor status */
141 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
142 #define DSC_RX_OK 0x4000 /* RX was successful */
143 #define DSC_RX_ERR 0x0800 /* RX PHY error */
144 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
145 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
146 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
147 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
148 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
149 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
150 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
151 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
152 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
153 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
154
155 /* PHY settings */
156 #define ICPLUS_PHY_ID 0x0243
157
158 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
159 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
160 "Florian Fainelli <florian@openwrt.org>");
161 MODULE_LICENSE("GPL");
162 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
163 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
164
165 /* RX and TX interrupts that we handle */
166 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
167 #define TX_INTS (TX_FINISH)
168 #define INT_MASK (RX_INTS | TX_INTS)
169
170 struct r6040_descriptor {
171 u16 status, len; /* 0-3 */
172 __le32 buf; /* 4-7 */
173 __le32 ndesc; /* 8-B */
174 u32 rev1; /* C-F */
175 char *vbufp; /* 10-13 */
176 struct r6040_descriptor *vndescp; /* 14-17 */
177 struct sk_buff *skb_ptr; /* 18-1B */
178 u32 rev2; /* 1C-1F */
179 } __attribute__((aligned(32)));
180
181 struct r6040_private {
182 spinlock_t lock; /* driver lock */
183 struct pci_dev *pdev;
184 struct r6040_descriptor *rx_insert_ptr;
185 struct r6040_descriptor *rx_remove_ptr;
186 struct r6040_descriptor *tx_insert_ptr;
187 struct r6040_descriptor *tx_remove_ptr;
188 struct r6040_descriptor *rx_ring;
189 struct r6040_descriptor *tx_ring;
190 dma_addr_t rx_ring_dma;
191 dma_addr_t tx_ring_dma;
192 u16 tx_free_desc, phy_addr;
193 u16 mcr0, mcr1;
194 struct net_device *dev;
195 struct mii_bus *mii_bus;
196 struct napi_struct napi;
197 void __iomem *base;
198 struct phy_device *phydev;
199 int old_link;
200 int old_duplex;
201 };
202
203 static char version[] __devinitdata = DRV_NAME
204 ": RDC R6040 NAPI net driver,"
205 "version "DRV_VERSION " (" DRV_RELDATE ")";
206
207 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
208
209 /* Read a word data from PHY Chip */
210 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
211 {
212 int limit = 2048;
213 u16 cmd;
214
215 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
216 /* Wait for the read bit to be cleared */
217 while (limit--) {
218 cmd = ioread16(ioaddr + MMDIO);
219 if (!(cmd & MDIO_READ))
220 break;
221 }
222
223 return ioread16(ioaddr + MMRD);
224 }
225
226 /* Write a word data from PHY Chip */
227 static void r6040_phy_write(void __iomem *ioaddr,
228 int phy_addr, int reg, u16 val)
229 {
230 int limit = 2048;
231 u16 cmd;
232
233 iowrite16(val, ioaddr + MMWD);
234 /* Write the command to the MDIO bus */
235 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
236 /* Wait for the write bit to be cleared */
237 while (limit--) {
238 cmd = ioread16(ioaddr + MMDIO);
239 if (!(cmd & MDIO_WRITE))
240 break;
241 }
242 }
243
244 static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
245 {
246 struct net_device *dev = bus->priv;
247 struct r6040_private *lp = netdev_priv(dev);
248 void __iomem *ioaddr = lp->base;
249
250 return r6040_phy_read(ioaddr, phy_addr, reg);
251 }
252
253 static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
254 int reg, u16 value)
255 {
256 struct net_device *dev = bus->priv;
257 struct r6040_private *lp = netdev_priv(dev);
258 void __iomem *ioaddr = lp->base;
259
260 r6040_phy_write(ioaddr, phy_addr, reg, value);
261
262 return 0;
263 }
264
265 static int r6040_mdiobus_reset(struct mii_bus *bus)
266 {
267 return 0;
268 }
269
270 static void r6040_free_txbufs(struct net_device *dev)
271 {
272 struct r6040_private *lp = netdev_priv(dev);
273 int i;
274
275 for (i = 0; i < TX_DCNT; i++) {
276 if (lp->tx_insert_ptr->skb_ptr) {
277 pci_unmap_single(lp->pdev,
278 le32_to_cpu(lp->tx_insert_ptr->buf),
279 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
280 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
281 lp->tx_insert_ptr->skb_ptr = NULL;
282 }
283 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
284 }
285 }
286
287 static void r6040_free_rxbufs(struct net_device *dev)
288 {
289 struct r6040_private *lp = netdev_priv(dev);
290 int i;
291
292 for (i = 0; i < RX_DCNT; i++) {
293 if (lp->rx_insert_ptr->skb_ptr) {
294 pci_unmap_single(lp->pdev,
295 le32_to_cpu(lp->rx_insert_ptr->buf),
296 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
297 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
298 lp->rx_insert_ptr->skb_ptr = NULL;
299 }
300 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
301 }
302 }
303
304 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
305 dma_addr_t desc_dma, int size)
306 {
307 struct r6040_descriptor *desc = desc_ring;
308 dma_addr_t mapping = desc_dma;
309
310 while (size-- > 0) {
311 mapping += sizeof(*desc);
312 desc->ndesc = cpu_to_le32(mapping);
313 desc->vndescp = desc + 1;
314 desc++;
315 }
316 desc--;
317 desc->ndesc = cpu_to_le32(desc_dma);
318 desc->vndescp = desc_ring;
319 }
320
321 static void r6040_init_txbufs(struct net_device *dev)
322 {
323 struct r6040_private *lp = netdev_priv(dev);
324
325 lp->tx_free_desc = TX_DCNT;
326
327 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
328 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
329 }
330
331 static int r6040_alloc_rxbufs(struct net_device *dev)
332 {
333 struct r6040_private *lp = netdev_priv(dev);
334 struct r6040_descriptor *desc;
335 struct sk_buff *skb;
336 int rc;
337
338 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
339 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
340
341 /* Allocate skbs for the rx descriptors */
342 desc = lp->rx_ring;
343 do {
344 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
345 if (!skb) {
346 netdev_err(dev, "failed to alloc skb for rx\n");
347 rc = -ENOMEM;
348 goto err_exit;
349 }
350 desc->skb_ptr = skb;
351 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
352 desc->skb_ptr->data,
353 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
354 desc->status = DSC_OWNER_MAC;
355 desc = desc->vndescp;
356 } while (desc != lp->rx_ring);
357
358 return 0;
359
360 err_exit:
361 /* Deallocate all previously allocated skbs */
362 r6040_free_rxbufs(dev);
363 return rc;
364 }
365
366 static void r6040_init_mac_regs(struct net_device *dev)
367 {
368 struct r6040_private *lp = netdev_priv(dev);
369 void __iomem *ioaddr = lp->base;
370 int limit = 2048;
371 u16 cmd;
372
373 /* Mask Off Interrupt */
374 iowrite16(MSK_INT, ioaddr + MIER);
375
376 /* Reset RDC MAC */
377 iowrite16(MAC_RST, ioaddr + MCR1);
378 while (limit--) {
379 cmd = ioread16(ioaddr + MCR1);
380 if (cmd & 0x1)
381 break;
382 }
383 /* Reset internal state machine */
384 iowrite16(2, ioaddr + MAC_SM);
385 iowrite16(0, ioaddr + MAC_SM);
386 mdelay(5);
387
388 /* MAC Bus Control Register */
389 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
390
391 /* Buffer Size Register */
392 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
393
394 /* Write TX ring start address */
395 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
396 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
397
398 /* Write RX ring start address */
399 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
400 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
401
402 /* Set interrupt waiting time and packet numbers */
403 iowrite16(0, ioaddr + MT_ICR);
404 iowrite16(0, ioaddr + MR_ICR);
405
406 /* Enable interrupts */
407 iowrite16(INT_MASK, ioaddr + MIER);
408
409 /* Enable TX and RX */
410 iowrite16(lp->mcr0 | 0x0002, ioaddr);
411
412 /* Let TX poll the descriptors
413 * we may got called by r6040_tx_timeout which has left
414 * some unsent tx buffers */
415 iowrite16(0x01, ioaddr + MTPR);
416 }
417
418 static void r6040_tx_timeout(struct net_device *dev)
419 {
420 struct r6040_private *priv = netdev_priv(dev);
421 void __iomem *ioaddr = priv->base;
422
423 netdev_warn(dev, "transmit timed out, int enable %4.4x "
424 "status %4.4x\n",
425 ioread16(ioaddr + MIER),
426 ioread16(ioaddr + MISR));
427
428 dev->stats.tx_errors++;
429
430 /* Reset MAC and re-init all registers */
431 r6040_init_mac_regs(dev);
432 }
433
434 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
435 {
436 struct r6040_private *priv = netdev_priv(dev);
437 void __iomem *ioaddr = priv->base;
438 unsigned long flags;
439
440 spin_lock_irqsave(&priv->lock, flags);
441 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
442 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
443 spin_unlock_irqrestore(&priv->lock, flags);
444
445 return &dev->stats;
446 }
447
448 /* Stop RDC MAC and Free the allocated resource */
449 static void r6040_down(struct net_device *dev)
450 {
451 struct r6040_private *lp = netdev_priv(dev);
452 void __iomem *ioaddr = lp->base;
453 int limit = 2048;
454 u16 *adrp;
455 u16 cmd;
456
457 /* Stop MAC */
458 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
459 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
460 while (limit--) {
461 cmd = ioread16(ioaddr + MCR1);
462 if (cmd & 0x1)
463 break;
464 }
465
466 /* Restore MAC Address to MIDx */
467 adrp = (u16 *) dev->dev_addr;
468 iowrite16(adrp[0], ioaddr + MID_0L);
469 iowrite16(adrp[1], ioaddr + MID_0M);
470 iowrite16(adrp[2], ioaddr + MID_0H);
471 }
472
473 static int r6040_close(struct net_device *dev)
474 {
475 struct r6040_private *lp = netdev_priv(dev);
476 struct pci_dev *pdev = lp->pdev;
477
478 spin_lock_irq(&lp->lock);
479 napi_disable(&lp->napi);
480 netif_stop_queue(dev);
481 r6040_down(dev);
482
483 free_irq(dev->irq, dev);
484
485 /* Free RX buffer */
486 r6040_free_rxbufs(dev);
487
488 /* Free TX buffer */
489 r6040_free_txbufs(dev);
490
491 spin_unlock_irq(&lp->lock);
492
493 /* Free Descriptor memory */
494 if (lp->rx_ring) {
495 pci_free_consistent(pdev,
496 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
497 lp->rx_ring = NULL;
498 }
499
500 if (lp->tx_ring) {
501 pci_free_consistent(pdev,
502 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
503 lp->tx_ring = NULL;
504 }
505
506 return 0;
507 }
508
509 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
510 {
511 struct r6040_private *lp = netdev_priv(dev);
512
513 if (!lp->phydev)
514 return -EINVAL;
515
516 return phy_mii_ioctl(lp->phydev, rq, cmd);
517 }
518
519 static int r6040_rx(struct net_device *dev, int limit)
520 {
521 struct r6040_private *priv = netdev_priv(dev);
522 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
523 struct sk_buff *skb_ptr, *new_skb;
524 int count = 0;
525 u16 err;
526
527 /* Limit not reached and the descriptor belongs to the CPU */
528 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
529 /* Read the descriptor status */
530 err = descptr->status;
531 /* Global error status set */
532 if (err & DSC_RX_ERR) {
533 /* RX dribble */
534 if (err & DSC_RX_ERR_DRI)
535 dev->stats.rx_frame_errors++;
536 /* Buffer lenght exceeded */
537 if (err & DSC_RX_ERR_BUF)
538 dev->stats.rx_length_errors++;
539 /* Packet too long */
540 if (err & DSC_RX_ERR_LONG)
541 dev->stats.rx_length_errors++;
542 /* Packet < 64 bytes */
543 if (err & DSC_RX_ERR_RUNT)
544 dev->stats.rx_length_errors++;
545 /* CRC error */
546 if (err & DSC_RX_ERR_CRC) {
547 spin_lock(&priv->lock);
548 dev->stats.rx_crc_errors++;
549 spin_unlock(&priv->lock);
550 }
551 goto next_descr;
552 }
553
554 /* Packet successfully received */
555 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
556 if (!new_skb) {
557 dev->stats.rx_dropped++;
558 goto next_descr;
559 }
560 skb_ptr = descptr->skb_ptr;
561 skb_ptr->dev = priv->dev;
562
563 /* Do not count the CRC */
564 skb_put(skb_ptr, descptr->len - 4);
565 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
566 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
567 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
568
569 /* Send to upper layer */
570 netif_receive_skb(skb_ptr);
571 dev->stats.rx_packets++;
572 dev->stats.rx_bytes += descptr->len - 4;
573
574 /* put new skb into descriptor */
575 descptr->skb_ptr = new_skb;
576 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
577 descptr->skb_ptr->data,
578 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
579
580 next_descr:
581 /* put the descriptor back to the MAC */
582 descptr->status = DSC_OWNER_MAC;
583 descptr = descptr->vndescp;
584 count++;
585 }
586 priv->rx_remove_ptr = descptr;
587
588 return count;
589 }
590
591 static void r6040_tx(struct net_device *dev)
592 {
593 struct r6040_private *priv = netdev_priv(dev);
594 struct r6040_descriptor *descptr;
595 void __iomem *ioaddr = priv->base;
596 struct sk_buff *skb_ptr;
597 u16 err;
598
599 spin_lock(&priv->lock);
600 descptr = priv->tx_remove_ptr;
601 while (priv->tx_free_desc < TX_DCNT) {
602 /* Check for errors */
603 err = ioread16(ioaddr + MLSR);
604
605 if (err & 0x0200)
606 dev->stats.rx_fifo_errors++;
607 if (err & (0x2000 | 0x4000))
608 dev->stats.tx_carrier_errors++;
609
610 if (descptr->status & DSC_OWNER_MAC)
611 break; /* Not complete */
612 skb_ptr = descptr->skb_ptr;
613 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
614 skb_ptr->len, PCI_DMA_TODEVICE);
615 /* Free buffer */
616 dev_kfree_skb_irq(skb_ptr);
617 descptr->skb_ptr = NULL;
618 /* To next descriptor */
619 descptr = descptr->vndescp;
620 priv->tx_free_desc++;
621 }
622 priv->tx_remove_ptr = descptr;
623
624 if (priv->tx_free_desc)
625 netif_wake_queue(dev);
626 spin_unlock(&priv->lock);
627 }
628
629 static int r6040_poll(struct napi_struct *napi, int budget)
630 {
631 struct r6040_private *priv =
632 container_of(napi, struct r6040_private, napi);
633 struct net_device *dev = priv->dev;
634 void __iomem *ioaddr = priv->base;
635 int work_done;
636
637 work_done = r6040_rx(dev, budget);
638
639 if (work_done < budget) {
640 napi_complete(napi);
641 /* Enable RX interrupt */
642 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
643 }
644 return work_done;
645 }
646
647 /* The RDC interrupt handler. */
648 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
649 {
650 struct net_device *dev = dev_id;
651 struct r6040_private *lp = netdev_priv(dev);
652 void __iomem *ioaddr = lp->base;
653 u16 misr, status;
654
655 /* Save MIER */
656 misr = ioread16(ioaddr + MIER);
657 /* Mask off RDC MAC interrupt */
658 iowrite16(MSK_INT, ioaddr + MIER);
659 /* Read MISR status and clear */
660 status = ioread16(ioaddr + MISR);
661
662 if (status == 0x0000 || status == 0xffff) {
663 /* Restore RDC MAC interrupt */
664 iowrite16(misr, ioaddr + MIER);
665 return IRQ_NONE;
666 }
667
668 /* RX interrupt request */
669 if (status & RX_INTS) {
670 if (status & RX_NO_DESC) {
671 /* RX descriptor unavailable */
672 dev->stats.rx_dropped++;
673 dev->stats.rx_missed_errors++;
674 }
675 if (status & RX_FIFO_FULL)
676 dev->stats.rx_fifo_errors++;
677
678 /* Mask off RX interrupt */
679 misr &= ~RX_INTS;
680 napi_schedule(&lp->napi);
681 }
682
683 /* TX interrupt request */
684 if (status & TX_INTS)
685 r6040_tx(dev);
686
687 /* Restore RDC MAC interrupt */
688 iowrite16(misr, ioaddr + MIER);
689
690 return IRQ_HANDLED;
691 }
692
693 #ifdef CONFIG_NET_POLL_CONTROLLER
694 static void r6040_poll_controller(struct net_device *dev)
695 {
696 disable_irq(dev->irq);
697 r6040_interrupt(dev->irq, dev);
698 enable_irq(dev->irq);
699 }
700 #endif
701
702 /* Init RDC MAC */
703 static int r6040_up(struct net_device *dev)
704 {
705 struct r6040_private *lp = netdev_priv(dev);
706 void __iomem *ioaddr = lp->base;
707 int ret;
708
709 /* Initialise and alloc RX/TX buffers */
710 r6040_init_txbufs(dev);
711 ret = r6040_alloc_rxbufs(dev);
712 if (ret)
713 return ret;
714
715 /* improve performance (by RDC guys) */
716 r6040_phy_write(ioaddr, 30, 17,
717 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
718 r6040_phy_write(ioaddr, 30, 17,
719 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
720 r6040_phy_write(ioaddr, 0, 19, 0x0000);
721 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
722
723 /* Initialize all MAC registers */
724 r6040_init_mac_regs(dev);
725
726 return 0;
727 }
728
729
730 /* Read/set MAC address routines */
731 static void r6040_mac_address(struct net_device *dev)
732 {
733 struct r6040_private *lp = netdev_priv(dev);
734 void __iomem *ioaddr = lp->base;
735 u16 *adrp;
736
737 /* MAC operation register */
738 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
739 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
740 iowrite16(0, ioaddr + MAC_SM);
741 mdelay(5);
742
743 /* Restore MAC Address */
744 adrp = (u16 *) dev->dev_addr;
745 iowrite16(adrp[0], ioaddr + MID_0L);
746 iowrite16(adrp[1], ioaddr + MID_0M);
747 iowrite16(adrp[2], ioaddr + MID_0H);
748
749 /* Store MAC Address in perm_addr */
750 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
751 }
752
753 static int r6040_open(struct net_device *dev)
754 {
755 struct r6040_private *lp = netdev_priv(dev);
756 int ret;
757
758 /* Request IRQ and Register interrupt handler */
759 ret = request_irq(dev->irq, r6040_interrupt,
760 IRQF_SHARED, dev->name, dev);
761 if (ret)
762 goto out;
763
764 /* Set MAC address */
765 r6040_mac_address(dev);
766
767 /* Allocate Descriptor memory */
768 lp->rx_ring =
769 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
770 if (!lp->rx_ring) {
771 ret = -ENOMEM;
772 goto err_free_irq;
773 }
774
775 lp->tx_ring =
776 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
777 if (!lp->tx_ring) {
778 ret = -ENOMEM;
779 goto err_free_rx_ring;
780 }
781
782 ret = r6040_up(dev);
783 if (ret)
784 goto err_free_tx_ring;
785
786 napi_enable(&lp->napi);
787 netif_start_queue(dev);
788
789 return 0;
790
791 err_free_tx_ring:
792 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
793 lp->tx_ring_dma);
794 err_free_rx_ring:
795 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
796 lp->rx_ring_dma);
797 err_free_irq:
798 free_irq(dev->irq, dev);
799 out:
800 return ret;
801 }
802
803 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
804 struct net_device *dev)
805 {
806 struct r6040_private *lp = netdev_priv(dev);
807 struct r6040_descriptor *descptr;
808 void __iomem *ioaddr = lp->base;
809 unsigned long flags;
810
811 /* Critical Section */
812 spin_lock_irqsave(&lp->lock, flags);
813
814 /* TX resource check */
815 if (!lp->tx_free_desc) {
816 spin_unlock_irqrestore(&lp->lock, flags);
817 netif_stop_queue(dev);
818 netdev_err(dev, ": no tx descriptor\n");
819 return NETDEV_TX_BUSY;
820 }
821
822 /* Statistic Counter */
823 dev->stats.tx_packets++;
824 dev->stats.tx_bytes += skb->len;
825 /* Set TX descriptor & Transmit it */
826 lp->tx_free_desc--;
827 descptr = lp->tx_insert_ptr;
828 if (skb->len < MISR)
829 descptr->len = MISR;
830 else
831 descptr->len = skb->len;
832
833 descptr->skb_ptr = skb;
834 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
835 skb->data, skb->len, PCI_DMA_TODEVICE));
836 descptr->status = DSC_OWNER_MAC;
837 /* Trigger the MAC to check the TX descriptor */
838 iowrite16(0x01, ioaddr + MTPR);
839 lp->tx_insert_ptr = descptr->vndescp;
840
841 /* If no tx resource, stop */
842 if (!lp->tx_free_desc)
843 netif_stop_queue(dev);
844
845 spin_unlock_irqrestore(&lp->lock, flags);
846
847 return NETDEV_TX_OK;
848 }
849
850 static void r6040_multicast_list(struct net_device *dev)
851 {
852 struct r6040_private *lp = netdev_priv(dev);
853 void __iomem *ioaddr = lp->base;
854 u16 *adrp;
855 u16 reg;
856 unsigned long flags;
857 struct netdev_hw_addr *ha;
858 int i;
859
860 /* MAC Address */
861 adrp = (u16 *)dev->dev_addr;
862 iowrite16(adrp[0], ioaddr + MID_0L);
863 iowrite16(adrp[1], ioaddr + MID_0M);
864 iowrite16(adrp[2], ioaddr + MID_0H);
865
866 /* Promiscous Mode */
867 spin_lock_irqsave(&lp->lock, flags);
868
869 /* Clear AMCP & PROM bits */
870 reg = ioread16(ioaddr) & ~0x0120;
871 if (dev->flags & IFF_PROMISC) {
872 reg |= 0x0020;
873 lp->mcr0 |= 0x0020;
874 }
875 /* Too many multicast addresses
876 * accept all traffic */
877 else if ((netdev_mc_count(dev) > MCAST_MAX) ||
878 (dev->flags & IFF_ALLMULTI))
879 reg |= 0x0020;
880
881 iowrite16(reg, ioaddr);
882 spin_unlock_irqrestore(&lp->lock, flags);
883
884 /* Build the hash table */
885 if (netdev_mc_count(dev) > MCAST_MAX) {
886 u16 hash_table[4];
887 u32 crc;
888
889 for (i = 0; i < 4; i++)
890 hash_table[i] = 0;
891
892 netdev_for_each_mc_addr(ha, dev) {
893 char *addrs = ha->addr;
894
895 if (!(*addrs & 1))
896 continue;
897
898 crc = ether_crc_le(6, addrs);
899 crc >>= 26;
900 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
901 }
902 /* Fill the MAC hash tables with their values */
903 iowrite16(hash_table[0], ioaddr + MAR0);
904 iowrite16(hash_table[1], ioaddr + MAR1);
905 iowrite16(hash_table[2], ioaddr + MAR2);
906 iowrite16(hash_table[3], ioaddr + MAR3);
907 }
908 /* Multicast Address 1~4 case */
909 i = 0;
910 netdev_for_each_mc_addr(ha, dev) {
911 if (i >= MCAST_MAX)
912 break;
913 adrp = (u16 *) ha->addr;
914 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
915 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
916 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
917 i++;
918 }
919 while (i < MCAST_MAX) {
920 iowrite16(0xffff, ioaddr + MID_1L + 8 * i);
921 iowrite16(0xffff, ioaddr + MID_1M + 8 * i);
922 iowrite16(0xffff, ioaddr + MID_1H + 8 * i);
923 i++;
924 }
925 }
926
927 static void netdev_get_drvinfo(struct net_device *dev,
928 struct ethtool_drvinfo *info)
929 {
930 struct r6040_private *rp = netdev_priv(dev);
931
932 strcpy(info->driver, DRV_NAME);
933 strcpy(info->version, DRV_VERSION);
934 strcpy(info->bus_info, pci_name(rp->pdev));
935 }
936
937 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
938 {
939 struct r6040_private *rp = netdev_priv(dev);
940
941 return phy_ethtool_gset(rp->phydev, cmd);
942 }
943
944 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
945 {
946 struct r6040_private *rp = netdev_priv(dev);
947
948 return phy_ethtool_sset(rp->phydev, cmd);
949 }
950
951 static const struct ethtool_ops netdev_ethtool_ops = {
952 .get_drvinfo = netdev_get_drvinfo,
953 .get_settings = netdev_get_settings,
954 .set_settings = netdev_set_settings,
955 .get_link = ethtool_op_get_link,
956 };
957
958 static const struct net_device_ops r6040_netdev_ops = {
959 .ndo_open = r6040_open,
960 .ndo_stop = r6040_close,
961 .ndo_start_xmit = r6040_start_xmit,
962 .ndo_get_stats = r6040_get_stats,
963 .ndo_set_multicast_list = r6040_multicast_list,
964 .ndo_change_mtu = eth_change_mtu,
965 .ndo_validate_addr = eth_validate_addr,
966 .ndo_set_mac_address = eth_mac_addr,
967 .ndo_do_ioctl = r6040_ioctl,
968 .ndo_tx_timeout = r6040_tx_timeout,
969 #ifdef CONFIG_NET_POLL_CONTROLLER
970 .ndo_poll_controller = r6040_poll_controller,
971 #endif
972 };
973
974 static void r6040_adjust_link(struct net_device *dev)
975 {
976 struct r6040_private *lp = netdev_priv(dev);
977 struct phy_device *phydev = lp->phydev;
978 int status_changed = 0;
979 void __iomem *ioaddr = lp->base;
980
981 BUG_ON(!phydev);
982
983 if (lp->old_link != phydev->link) {
984 status_changed = 1;
985 lp->old_link = phydev->link;
986 }
987
988 /* reflect duplex change */
989 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
990 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? 0x8000 : 0);
991 iowrite16(lp->mcr0, ioaddr);
992
993 status_changed = 1;
994 lp->old_duplex = phydev->duplex;
995 }
996
997 if (status_changed) {
998 pr_info("%s: link %s", dev->name, phydev->link ?
999 "UP" : "DOWN");
1000 if (phydev->link)
1001 pr_cont(" - %d/%s", phydev->speed,
1002 DUPLEX_FULL == phydev->duplex ? "full" : "half");
1003 pr_cont("\n");
1004 }
1005 }
1006
1007 static int r6040_mii_probe(struct net_device *dev)
1008 {
1009 struct r6040_private *lp = netdev_priv(dev);
1010 struct phy_device *phydev = NULL;
1011
1012 phydev = phy_find_first(lp->mii_bus);
1013 if (!phydev) {
1014 dev_err(&lp->pdev->dev, "no PHY found\n");
1015 return -ENODEV;
1016 }
1017
1018 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
1019 0, PHY_INTERFACE_MODE_MII);
1020
1021 if (IS_ERR(phydev)) {
1022 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1023 return PTR_ERR(phydev);
1024 }
1025
1026 /* mask with MAC supported features */
1027 phydev->supported &= (SUPPORTED_10baseT_Half
1028 | SUPPORTED_10baseT_Full
1029 | SUPPORTED_100baseT_Half
1030 | SUPPORTED_100baseT_Full
1031 | SUPPORTED_Autoneg
1032 | SUPPORTED_MII
1033 | SUPPORTED_TP);
1034
1035 phydev->advertising = phydev->supported;
1036 lp->phydev = phydev;
1037 lp->old_link = 0;
1038 lp->old_duplex = -1;
1039
1040 dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1041 "(mii_bus:phy_addr=%s)\n",
1042 phydev->drv->name, dev_name(&phydev->dev));
1043
1044 return 0;
1045 }
1046
1047 static int __devinit r6040_init_one(struct pci_dev *pdev,
1048 const struct pci_device_id *ent)
1049 {
1050 struct net_device *dev;
1051 struct r6040_private *lp;
1052 void __iomem *ioaddr;
1053 int err, io_size = R6040_IO_SIZE;
1054 static int card_idx = -1;
1055 int bar = 0;
1056 u16 *adrp;
1057 int i;
1058
1059 pr_info("%s\n", version);
1060
1061 err = pci_enable_device(pdev);
1062 if (err)
1063 goto err_out;
1064
1065 /* this should always be supported */
1066 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1067 if (err) {
1068 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1069 "not supported by the card\n");
1070 goto err_out;
1071 }
1072 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1073 if (err) {
1074 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1075 "not supported by the card\n");
1076 goto err_out;
1077 }
1078
1079 /* IO Size check */
1080 if (pci_resource_len(pdev, bar) < io_size) {
1081 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1082 err = -EIO;
1083 goto err_out;
1084 }
1085
1086 pci_set_master(pdev);
1087
1088 dev = alloc_etherdev(sizeof(struct r6040_private));
1089 if (!dev) {
1090 dev_err(&pdev->dev, "Failed to allocate etherdev\n");
1091 err = -ENOMEM;
1092 goto err_out;
1093 }
1094 SET_NETDEV_DEV(dev, &pdev->dev);
1095 lp = netdev_priv(dev);
1096
1097 err = pci_request_regions(pdev, DRV_NAME);
1098
1099 if (err) {
1100 dev_err(&pdev->dev, "Failed to request PCI regions\n");
1101 goto err_out_free_dev;
1102 }
1103
1104 ioaddr = pci_iomap(pdev, bar, io_size);
1105 if (!ioaddr) {
1106 dev_err(&pdev->dev, "ioremap failed for device\n");
1107 err = -EIO;
1108 goto err_out_free_res;
1109 }
1110 /* If PHY status change register is still set to zero it means the
1111 * bootloader didn't initialize it */
1112 if (ioread16(ioaddr + PHY_CC) == 0)
1113 iowrite16(0x9f07, ioaddr + PHY_CC);
1114
1115 /* Init system & device */
1116 lp->base = ioaddr;
1117 dev->irq = pdev->irq;
1118
1119 spin_lock_init(&lp->lock);
1120 pci_set_drvdata(pdev, dev);
1121
1122 /* Set MAC address */
1123 card_idx++;
1124
1125 adrp = (u16 *)dev->dev_addr;
1126 adrp[0] = ioread16(ioaddr + MID_0L);
1127 adrp[1] = ioread16(ioaddr + MID_0M);
1128 adrp[2] = ioread16(ioaddr + MID_0H);
1129
1130 /* Some bootloader/BIOSes do not initialize
1131 * MAC address, warn about that */
1132 if (!(adrp[0] || adrp[1] || adrp[2])) {
1133 netdev_warn(dev, "MAC address not initialized, "
1134 "generating random\n");
1135 random_ether_addr(dev->dev_addr);
1136 }
1137
1138 /* Link new device into r6040_root_dev */
1139 lp->pdev = pdev;
1140 lp->dev = dev;
1141
1142 /* Init RDC private data */
1143 lp->mcr0 = 0x1002;
1144 lp->phy_addr = phy_table[card_idx];
1145
1146 /* The RDC-specific entries in the device structure. */
1147 dev->netdev_ops = &r6040_netdev_ops;
1148 dev->ethtool_ops = &netdev_ethtool_ops;
1149 dev->watchdog_timeo = TX_TIMEOUT;
1150
1151 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1152
1153 lp->mii_bus = mdiobus_alloc();
1154 if (!lp->mii_bus) {
1155 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1156 goto err_out_unmap;
1157 }
1158
1159 lp->mii_bus->priv = dev;
1160 lp->mii_bus->read = r6040_mdiobus_read;
1161 lp->mii_bus->write = r6040_mdiobus_write;
1162 lp->mii_bus->reset = r6040_mdiobus_reset;
1163 lp->mii_bus->name = "r6040_eth_mii";
1164 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x", card_idx);
1165 lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1166 if (!lp->mii_bus->irq) {
1167 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
1168 goto err_out_mdio;
1169 }
1170
1171 for (i = 0; i < PHY_MAX_ADDR; i++)
1172 lp->mii_bus->irq[i] = PHY_POLL;
1173
1174 err = mdiobus_register(lp->mii_bus);
1175 if (err) {
1176 dev_err(&pdev->dev, "failed to register MII bus\n");
1177 goto err_out_mdio_irq;
1178 }
1179
1180 err = r6040_mii_probe(dev);
1181 if (err) {
1182 dev_err(&pdev->dev, "failed to probe MII bus\n");
1183 goto err_out_mdio_unregister;
1184 }
1185
1186 /* Register net device. After this dev->name assign */
1187 err = register_netdev(dev);
1188 if (err) {
1189 dev_err(&pdev->dev, "Failed to register net device\n");
1190 goto err_out_mdio_unregister;
1191 }
1192 return 0;
1193
1194 err_out_mdio_unregister:
1195 mdiobus_unregister(lp->mii_bus);
1196 err_out_mdio_irq:
1197 kfree(lp->mii_bus->irq);
1198 err_out_mdio:
1199 mdiobus_free(lp->mii_bus);
1200 err_out_unmap:
1201 pci_iounmap(pdev, ioaddr);
1202 err_out_free_res:
1203 pci_release_regions(pdev);
1204 err_out_free_dev:
1205 free_netdev(dev);
1206 err_out:
1207 return err;
1208 }
1209
1210 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1211 {
1212 struct net_device *dev = pci_get_drvdata(pdev);
1213 struct r6040_private *lp = netdev_priv(dev);
1214
1215 unregister_netdev(dev);
1216 mdiobus_unregister(lp->mii_bus);
1217 kfree(lp->mii_bus->irq);
1218 mdiobus_free(lp->mii_bus);
1219 pci_release_regions(pdev);
1220 free_netdev(dev);
1221 pci_disable_device(pdev);
1222 pci_set_drvdata(pdev, NULL);
1223 }
1224
1225
1226 static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
1227 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1228 { 0 }
1229 };
1230 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1231
1232 static struct pci_driver r6040_driver = {
1233 .name = DRV_NAME,
1234 .id_table = r6040_pci_tbl,
1235 .probe = r6040_init_one,
1236 .remove = __devexit_p(r6040_remove_one),
1237 };
1238
1239
1240 static int __init r6040_init(void)
1241 {
1242 return pci_register_driver(&r6040_driver);
1243 }
1244
1245
1246 static void __exit r6040_cleanup(void)
1247 {
1248 pci_unregister_driver(&r6040_driver);
1249 }
1250
1251 module_init(r6040_init);
1252 module_exit(r6040_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree