2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 #include <arch/chip.h>
17 #include <linux/types.h>
18 #include <linux/string.h>
19 #include <linux/module.h>
22 void *memset(void *s
, int c
, size_t n
)
34 /* Experimentation shows that a trivial tight loop is a win up until
35 * around a size of 20, where writing a word at a time starts to win.
37 #define BYTE_CUTOFF 20
40 /* This must be at least at least this big, or some code later
43 #error "BYTE_CUTOFF is too small"
46 if (n
< BYTE_CUTOFF
) {
47 /* Strangely, this turns out to be the tightest way to
52 /* Strangely, combining these into one line
64 /* Use a spare issue slot to start prefetching the first cache
65 * line early. This instruction is free as the store can be buried
66 * in otherwise idle issue slots doing ALU ops.
68 __insn_prefetch(out8
);
70 /* We prefetch the end so that a short memset that spans two cache
71 * lines gets some prefetching benefit. Again we believe this is free
74 __insn_prefetch(&out8
[n
- 1]);
75 #endif /* !CHIP_HAS_WH64() */
78 /* Align 'out8'. We know n >= 3 so this won't write past the end. */
79 while (((uintptr_t) out8
& 3) != 0) {
88 out32
= (uint32_t *) out8
;
91 /* Tile input byte out to 32 bits. */
92 v16
= __insn_intlb(c
, c
);
93 v32
= __insn_intlh(v16
, v16
);
95 /* This must be at least 8 or the following loop doesn't work. */
96 #define CACHE_LINE_SIZE_IN_WORDS (CHIP_L2_LINE_SIZE() / 4)
100 ahead32
= CACHE_LINE_SIZE_IN_WORDS
;
102 /* We already prefetched the first and last cache lines, so
103 * we only need to do more prefetching if we are storing
104 * to more than two cache lines.
106 if (n32
> CACHE_LINE_SIZE_IN_WORDS
* 2) {
109 /* Prefetch the next several cache lines.
110 * This is the setup code for the software-pipelined
113 #define MAX_PREFETCH 5
114 ahead32
= n32
& -CACHE_LINE_SIZE_IN_WORDS
;
115 if (ahead32
> MAX_PREFETCH
* CACHE_LINE_SIZE_IN_WORDS
)
116 ahead32
= MAX_PREFETCH
* CACHE_LINE_SIZE_IN_WORDS
;
118 for (i
= CACHE_LINE_SIZE_IN_WORDS
;
119 i
< ahead32
; i
+= CACHE_LINE_SIZE_IN_WORDS
)
120 __insn_prefetch(&out32
[i
]);
127 /* Prefetch by reading one word several cache lines
128 * ahead. Since loads are non-blocking this will
129 * cause the full cache line to be read while we are
130 * finishing earlier cache lines. Using a store
131 * here causes microarchitectural performance
132 * problems where a victimizing store miss goes to
133 * the head of the retry FIFO and locks the pipe for
134 * a few cycles. So a few subsequent stores in this
135 * loop go into the retry FIFO, and then later
136 * stores see other stores to the same cache line
137 * are already in the retry FIFO and themselves go
138 * into the retry FIFO, filling it up and grinding
139 * to a halt waiting for the original miss to be
142 __insn_prefetch(&out32
[ahead32
]);
144 #if CACHE_LINE_SIZE_IN_WORDS % 4 != 0
145 #error "Unhandled CACHE_LINE_SIZE_IN_WORDS"
148 n32
-= CACHE_LINE_SIZE_IN_WORDS
;
150 /* Save icache space by only partially unrolling
153 for (j
= CACHE_LINE_SIZE_IN_WORDS
/ 4; j
> 0; j
--) {
160 /* To save compiled code size, reuse this loop even
161 * when we run out of prefetching to do by dropping
164 if (n32
<= ahead32
) {
165 /* Not even a full cache line left,
168 if (n32
< CACHE_LINE_SIZE_IN_WORDS
)
171 /* Choose a small enough value that we don't
172 * prefetch past the end. There's no sense
173 * in touching cache lines we don't have to.
175 ahead32
= CACHE_LINE_SIZE_IN_WORDS
- 1;
180 #else /* CHIP_HAS_WH64() */
182 /* Determine how many words we need to emit before the 'out32'
183 * pointer becomes aligned modulo the cache line size.
186 (-((uintptr_t)out32
>> 2)) & (CACHE_LINE_SIZE_IN_WORDS
- 1);
188 /* Only bother aligning and using wh64 if there is at least
189 * one full cache line to process. This check also prevents
190 * overrunning the end of the buffer with alignment words.
192 if (to_align32
<= n32
- CACHE_LINE_SIZE_IN_WORDS
) {
195 /* Align out32 mod the cache line size so we can use wh64. */
197 for (; to_align32
!= 0; to_align32
--) {
202 /* Use unsigned divide to turn this into a right shift. */
203 lines_left
= (unsigned)n32
/ CACHE_LINE_SIZE_IN_WORDS
;
206 /* Only wh64 a few lines at a time, so we don't
207 * exceed the maximum number of victim lines.
209 int x
= ((lines_left
< CHIP_MAX_OUTSTANDING_VICTIMS())
211 : CHIP_MAX_OUTSTANDING_VICTIMS());
212 uint32_t *wh
= out32
;
220 wh
+= CACHE_LINE_SIZE_IN_WORDS
;
223 for (j
= x
* (CACHE_LINE_SIZE_IN_WORDS
/ 4);
230 } while (lines_left
!= 0);
232 /* We processed all full lines above, so only this many
233 * words remain to be processed.
235 n32
&= CACHE_LINE_SIZE_IN_WORDS
- 1;
238 #endif /* CHIP_HAS_WH64() */
240 /* Now handle any leftover values. */
245 } while (--n32
!= 0);
250 EXPORT_SYMBOL(memset
);