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ACPI: ibm-acpi: cleanup fan_write
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / sky2.c
blob67ecd66f26d6cee6c265fa148df05023eeaaa7f9
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.10"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66 #define RX_SKB_ALIGN 8
67 #define RX_BUF_WRITE 16
68
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
79
80 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
82 static const u32 default_msg =
83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
86
87 static int debug = -1; /* defaults above */
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
91 static int copybreak __read_mostly = 128;
92 module_param(copybreak, int, 0);
93 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
95 static int disable_msi = 0;
96 module_param(disable_msi, int, 0);
97 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
99 static int idle_timeout = 0;
100 module_param(idle_timeout, int, 0);
101 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
102
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
130 { 0 }
131 };
132
133 MODULE_DEVICE_TABLE(pci, sky2_id_table);
134
135 /* Avoid conditionals by using array */
136 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
137 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
138 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
139
140 /* This driver supports yukon2 chipset only */
141 static const char *yukon2_name[] = {
142 "XL", /* 0xb3 */
143 "EC Ultra", /* 0xb4 */
144 "UNKNOWN", /* 0xb5 */
145 "EC", /* 0xb6 */
146 "FE", /* 0xb7 */
147 };
148
149 /* Access to external PHY */
150 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
151 {
152 int i;
153
154 gma_write16(hw, port, GM_SMI_DATA, val);
155 gma_write16(hw, port, GM_SMI_CTRL,
156 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
157
158 for (i = 0; i < PHY_RETRIES; i++) {
159 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
160 return 0;
161 udelay(1);
162 }
163
164 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
165 return -ETIMEDOUT;
166 }
167
168 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
169 {
170 int i;
171
172 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
173 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
174
175 for (i = 0; i < PHY_RETRIES; i++) {
176 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
177 *val = gma_read16(hw, port, GM_SMI_DATA);
178 return 0;
179 }
180
181 udelay(1);
182 }
183
184 return -ETIMEDOUT;
185 }
186
187 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
188 {
189 u16 v;
190
191 if (__gm_phy_read(hw, port, reg, &v) != 0)
192 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
193 return v;
194 }
195
196 static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
197 {
198 u16 power_control;
199 int vaux;
200
201 pr_debug("sky2_set_power_state %d\n", state);
202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
203
204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
205 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
206 (power_control & PCI_PM_CAP_PME_D3cold);
207
208 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
209
210 power_control |= PCI_PM_CTRL_PME_STATUS;
211 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
212
213 switch (state) {
214 case PCI_D0:
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, B0_POWER_CTRL,
217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
218
219 /* disable Core Clock Division, */
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
221
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
223 /* enable bits are inverted */
224 sky2_write8(hw, B2_Y2_CLK_GATE,
225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
228 else
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
230
231 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
232 u32 reg1;
233
234 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
235 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
236 reg1 &= P_ASPM_CONTROL_MSK;
237 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
238 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
239 }
240
241 break;
242
243 case PCI_D3hot:
244 case PCI_D3cold:
245 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
246 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
247 else
248 /* enable bits are inverted */
249 sky2_write8(hw, B2_Y2_CLK_GATE,
250 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
251 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
252 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
253
254 /* switch power to VAUX */
255 if (vaux && state != PCI_D3cold)
256 sky2_write8(hw, B0_POWER_CTRL,
257 (PC_VAUX_ENA | PC_VCC_ENA |
258 PC_VAUX_ON | PC_VCC_OFF));
259 break;
260 default:
261 printk(KERN_ERR PFX "Unknown power state %d\n", state);
262 }
263
264 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
265 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
266 }
267
268 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
269 {
270 u16 reg;
271
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
276
277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
281
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
285 }
286
287 /* flow control to advertise bits */
288 static const u16 copper_fc_adv[] = {
289 [FC_NONE] = 0,
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
293 };
294
295 /* flow control to advertise bits when using 1000BaseX */
296 static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
301 };
302
303 /* flow control to GMA disable bits */
304 static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
308 [FC_BOTH] = 0,
309 };
310
311
312 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
313 {
314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
315 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
316
317 if (sky2->autoneg == AUTONEG_ENABLE &&
318 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
319 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
320
321 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
322 PHY_M_EC_MAC_S_MSK);
323 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
324
325 if (hw->chip_id == CHIP_ID_YUKON_EC)
326 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
327 else
328 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
329
330 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
331 }
332
333 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
334 if (sky2_is_copper(hw)) {
335 if (hw->chip_id == CHIP_ID_YUKON_FE) {
336 /* enable automatic crossover */
337 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
338 } else {
339 /* disable energy detect */
340 ctrl &= ~PHY_M_PC_EN_DET_MSK;
341
342 /* enable automatic crossover */
343 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
344
345 if (sky2->autoneg == AUTONEG_ENABLE &&
346 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
347 ctrl &= ~PHY_M_PC_DSC_MSK;
348 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
349 }
350 }
351 } else {
352 /* workaround for deviation #4.88 (CRC errors) */
353 /* disable Automatic Crossover */
354
355 ctrl &= ~PHY_M_PC_MDIX_MSK;
356 }
357
358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 /* special setup for PHY 88E1112 Fiber */
361 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
362 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
363
364 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
366 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
367 ctrl &= ~PHY_M_MAC_MD_MSK;
368 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
369 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
370
371 if (hw->pmd_type == 'P') {
372 /* select page 1 to access Fiber registers */
373 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
374
375 /* for SFP-module set SIGDET polarity to low */
376 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
377 ctrl |= PHY_M_FIB_SIGD_POL;
378 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
379 }
380
381 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
382 }
383
384 ctrl = PHY_CT_RESET;
385 ct1000 = 0;
386 adv = PHY_AN_CSMA;
387 reg = 0;
388
389 if (sky2->autoneg == AUTONEG_ENABLE) {
390 if (sky2_is_copper(hw)) {
391 if (sky2->advertising & ADVERTISED_1000baseT_Full)
392 ct1000 |= PHY_M_1000C_AFD;
393 if (sky2->advertising & ADVERTISED_1000baseT_Half)
394 ct1000 |= PHY_M_1000C_AHD;
395 if (sky2->advertising & ADVERTISED_100baseT_Full)
396 adv |= PHY_M_AN_100_FD;
397 if (sky2->advertising & ADVERTISED_100baseT_Half)
398 adv |= PHY_M_AN_100_HD;
399 if (sky2->advertising & ADVERTISED_10baseT_Full)
400 adv |= PHY_M_AN_10_FD;
401 if (sky2->advertising & ADVERTISED_10baseT_Half)
402 adv |= PHY_M_AN_10_HD;
403
404 adv |= copper_fc_adv[sky2->flow_mode];
405 } else { /* special defines for FIBER (88E1040S only) */
406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
407 adv |= PHY_M_AN_1000X_AFD;
408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
409 adv |= PHY_M_AN_1000X_AHD;
410
411 adv |= fiber_fc_adv[sky2->flow_mode];
412 }
413
414 /* Restart Auto-negotiation */
415 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
416 } else {
417 /* forced speed/duplex settings */
418 ct1000 = PHY_M_1000C_MSE;
419
420 /* Disable auto update for duplex flow control and speed */
421 reg |= GM_GPCR_AU_ALL_DIS;
422
423 switch (sky2->speed) {
424 case SPEED_1000:
425 ctrl |= PHY_CT_SP1000;
426 reg |= GM_GPCR_SPEED_1000;
427 break;
428 case SPEED_100:
429 ctrl |= PHY_CT_SP100;
430 reg |= GM_GPCR_SPEED_100;
431 break;
432 }
433
434 if (sky2->duplex == DUPLEX_FULL) {
435 reg |= GM_GPCR_DUP_FULL;
436 ctrl |= PHY_CT_DUP_MD;
437 } else if (sky2->speed < SPEED_1000)
438 sky2->flow_mode = FC_NONE;
439
440
441 reg |= gm_fc_disable[sky2->flow_mode];
442
443 /* Forward pause packets to GMAC? */
444 if (sky2->flow_mode & FC_RX)
445 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
446 else
447 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
448 }
449
450 gma_write16(hw, port, GM_GP_CTRL, reg);
451
452 if (hw->chip_id != CHIP_ID_YUKON_FE)
453 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
454
455 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
456 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
457
458 /* Setup Phy LED's */
459 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
460 ledover = 0;
461
462 switch (hw->chip_id) {
463 case CHIP_ID_YUKON_FE:
464 /* on 88E3082 these bits are at 11..9 (shifted left) */
465 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
466
467 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
468
469 /* delete ACT LED control bits */
470 ctrl &= ~PHY_M_FELP_LED1_MSK;
471 /* change ACT LED control to blink mode */
472 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
473 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
474 break;
475
476 case CHIP_ID_YUKON_XL:
477 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
478
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
481
482 /* set LED Function Control register */
483 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
488
489 /* set Polarity Control register */
490 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
491 (PHY_M_POLC_LS1_P_MIX(4) |
492 PHY_M_POLC_IS0_P_MIX(4) |
493 PHY_M_POLC_LOS_CTRL(2) |
494 PHY_M_POLC_INIT_CTRL(2) |
495 PHY_M_POLC_STA1_CTRL(2) |
496 PHY_M_POLC_STA0_CTRL(2)));
497
498 /* restore page register */
499 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
500 break;
501 case CHIP_ID_YUKON_EC_U:
502 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
503
504 /* select page 3 to access LED control register */
505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
506
507 /* set LED Function Control register */
508 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
509 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
510 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
511 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
512 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
513
514 /* set Blink Rate in LED Timer Control Register */
515 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
516 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
517 /* restore page register */
518 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
519 break;
520
521 default:
522 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
523 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
524 /* turn off the Rx LED (LED_RX) */
525 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
526 }
527
528 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
529 /* apply fixes in PHY AFE */
530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
532
533 /* increase differential signal amplitude in 10BASE-T */
534 gm_phy_write(hw, port, 0x18, 0xaa99);
535 gm_phy_write(hw, port, 0x17, 0x2011);
536
537 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
538 gm_phy_write(hw, port, 0x18, 0xa204);
539 gm_phy_write(hw, port, 0x17, 0x2002);
540
541 /* set page register to 0 */
542 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
543 } else {
544 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
545
546 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
547 /* turn on 100 Mbps LED (LED_LINK100) */
548 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
549 }
550
551 if (ledover)
552 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
553
554 }
555
556 /* Enable phy interrupt on auto-negotiation complete (or link up) */
557 if (sky2->autoneg == AUTONEG_ENABLE)
558 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
559 else
560 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
561 }
562
563 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
564 {
565 u32 reg1;
566 static const u32 phy_power[]
567 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
568
569 /* looks like this XL is back asswards .. */
570 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
571 onoff = !onoff;
572
573 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
574
575 if (onoff)
576 /* Turn off phy power saving */
577 reg1 &= ~phy_power[port];
578 else
579 reg1 |= phy_power[port];
580
581 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
582 sky2_pci_read32(hw, PCI_DEV_REG1);
583 udelay(100);
584 }
585
586 /* Force a renegotiation */
587 static void sky2_phy_reinit(struct sky2_port *sky2)
588 {
589 spin_lock_bh(&sky2->phy_lock);
590 sky2_phy_init(sky2->hw, sky2->port);
591 spin_unlock_bh(&sky2->phy_lock);
592 }
593
594 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
595 {
596 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
597 u16 reg;
598 int i;
599 const u8 *addr = hw->dev[port]->dev_addr;
600
601 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
602 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
603
604 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
605
606 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
607 /* WA DEV_472 -- looks like crossed wires on port 2 */
608 /* clear GMAC 1 Control reset */
609 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
610 do {
611 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
612 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
613 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
614 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
615 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
616 }
617
618 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
619
620 /* Enable Transmit FIFO Underrun */
621 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
622
623 spin_lock_bh(&sky2->phy_lock);
624 sky2_phy_init(hw, port);
625 spin_unlock_bh(&sky2->phy_lock);
626
627 /* MIB clear */
628 reg = gma_read16(hw, port, GM_PHY_ADDR);
629 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
630
631 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
632 gma_read16(hw, port, i);
633 gma_write16(hw, port, GM_PHY_ADDR, reg);
634
635 /* transmit control */
636 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
637
638 /* receive control reg: unicast + multicast + no FCS */
639 gma_write16(hw, port, GM_RX_CTRL,
640 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
641
642 /* transmit flow control */
643 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
644
645 /* transmit parameter */
646 gma_write16(hw, port, GM_TX_PARAM,
647 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
648 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
649 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
650 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
651
652 /* serial mode register */
653 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
654 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
655
656 if (hw->dev[port]->mtu > ETH_DATA_LEN)
657 reg |= GM_SMOD_JUMBO_ENA;
658
659 gma_write16(hw, port, GM_SERIAL_MODE, reg);
660
661 /* virtual address for data */
662 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
663
664 /* physical address: used for pause frames */
665 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
666
667 /* ignore counter overflows */
668 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
669 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
670 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
671
672 /* Configure Rx MAC FIFO */
673 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
674 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
675 GMF_OPER_ON | GMF_RX_F_FL_ON);
676
677 /* Flush Rx MAC FIFO on any flow control or error */
678 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
679
680 /* Set threshold to 0xa (64 bytes)
681 * ASF disabled so no need to do WA dev #4.30
682 */
683 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
684
685 /* Configure Tx MAC FIFO */
686 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
687 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
688
689 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
690 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8);
691 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
692 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
693 /* set Tx GMAC FIFO Almost Empty Threshold */
694 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
695 /* Disable Store & Forward mode for TX */
696 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
697 }
698 }
699
700 }
701
702 /* Assign Ram Buffer allocation.
703 * start and end are in units of 4k bytes
704 * ram registers are in units of 64bit words
705 */
706 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
707 {
708 u32 start, end;
709
710 start = startk * 4096/8;
711 end = (endk * 4096/8) - 1;
712
713 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
714 sky2_write32(hw, RB_ADDR(q, RB_START), start);
715 sky2_write32(hw, RB_ADDR(q, RB_END), end);
716 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
717 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
718
719 if (q == Q_R1 || q == Q_R2) {
720 u32 space = (endk - startk) * 4096/8;
721 u32 tp = space - space/4;
722
723 /* On receive queue's set the thresholds
724 * give receiver priority when > 3/4 full
725 * send pause when down to 2K
726 */
727 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
728 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
729
730 tp = space - 2048/8;
731 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
732 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
733 } else {
734 /* Enable store & forward on Tx queue's because
735 * Tx FIFO is only 1K on Yukon
736 */
737 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
738 }
739
740 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
741 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
742 }
743
744 /* Setup Bus Memory Interface */
745 static void sky2_qset(struct sky2_hw *hw, u16 q)
746 {
747 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
748 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
749 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
750 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
751 }
752
753 /* Setup prefetch unit registers. This is the interface between
754 * hardware and driver list elements
755 */
756 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
757 u64 addr, u32 last)
758 {
759 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
760 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
761 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
762 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
763 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
764 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
765
766 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
767 }
768
769 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
770 {
771 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
772
773 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
774 le->ctrl = 0;
775 return le;
776 }
777
778 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
779 struct sky2_tx_le *le)
780 {
781 return sky2->tx_ring + (le - sky2->tx_le);
782 }
783
784 /* Update chip's next pointer */
785 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
786 {
787 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
788 wmb();
789 sky2_write16(hw, q, idx);
790 sky2_read16(hw, q);
791 }
792
793
794 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
795 {
796 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
797 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
798 le->ctrl = 0;
799 return le;
800 }
801
802 /* Return high part of DMA address (could be 32 or 64 bit) */
803 static inline u32 high32(dma_addr_t a)
804 {
805 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
806 }
807
808 /* Build description to hardware for one receive segment */
809 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
810 dma_addr_t map, unsigned len)
811 {
812 struct sky2_rx_le *le;
813 u32 hi = high32(map);
814
815 if (sky2->rx_addr64 != hi) {
816 le = sky2_next_rx(sky2);
817 le->addr = cpu_to_le32(hi);
818 le->opcode = OP_ADDR64 | HW_OWNER;
819 sky2->rx_addr64 = high32(map + len);
820 }
821
822 le = sky2_next_rx(sky2);
823 le->addr = cpu_to_le32((u32) map);
824 le->length = cpu_to_le16(len);
825 le->opcode = op | HW_OWNER;
826 }
827
828 /* Build description to hardware for one possibly fragmented skb */
829 static void sky2_rx_submit(struct sky2_port *sky2,
830 const struct rx_ring_info *re)
831 {
832 int i;
833
834 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
835
836 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
837 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
838 }
839
840
841 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
842 unsigned size)
843 {
844 struct sk_buff *skb = re->skb;
845 int i;
846
847 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
848 pci_unmap_len_set(re, data_size, size);
849
850 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
851 re->frag_addr[i] = pci_map_page(pdev,
852 skb_shinfo(skb)->frags[i].page,
853 skb_shinfo(skb)->frags[i].page_offset,
854 skb_shinfo(skb)->frags[i].size,
855 PCI_DMA_FROMDEVICE);
856 }
857
858 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
859 {
860 struct sk_buff *skb = re->skb;
861 int i;
862
863 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
864 PCI_DMA_FROMDEVICE);
865
866 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
867 pci_unmap_page(pdev, re->frag_addr[i],
868 skb_shinfo(skb)->frags[i].size,
869 PCI_DMA_FROMDEVICE);
870 }
871
872 /* Tell chip where to start receive checksum.
873 * Actually has two checksums, but set both same to avoid possible byte
874 * order problems.
875 */
876 static void rx_set_checksum(struct sky2_port *sky2)
877 {
878 struct sky2_rx_le *le;
879
880 le = sky2_next_rx(sky2);
881 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
882 le->ctrl = 0;
883 le->opcode = OP_TCPSTART | HW_OWNER;
884
885 sky2_write32(sky2->hw,
886 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
887 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
888
889 }
890
891 /*
892 * The RX Stop command will not work for Yukon-2 if the BMU does not
893 * reach the end of packet and since we can't make sure that we have
894 * incoming data, we must reset the BMU while it is not doing a DMA
895 * transfer. Since it is possible that the RX path is still active,
896 * the RX RAM buffer will be stopped first, so any possible incoming
897 * data will not trigger a DMA. After the RAM buffer is stopped, the
898 * BMU is polled until any DMA in progress is ended and only then it
899 * will be reset.
900 */
901 static void sky2_rx_stop(struct sky2_port *sky2)
902 {
903 struct sky2_hw *hw = sky2->hw;
904 unsigned rxq = rxqaddr[sky2->port];
905 int i;
906
907 /* disable the RAM Buffer receive queue */
908 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
909
910 for (i = 0; i < 0xffff; i++)
911 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
912 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
913 goto stopped;
914
915 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
916 sky2->netdev->name);
917 stopped:
918 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
919
920 /* reset the Rx prefetch unit */
921 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
922 }
923
924 /* Clean out receive buffer area, assumes receiver hardware stopped */
925 static void sky2_rx_clean(struct sky2_port *sky2)
926 {
927 unsigned i;
928
929 memset(sky2->rx_le, 0, RX_LE_BYTES);
930 for (i = 0; i < sky2->rx_pending; i++) {
931 struct rx_ring_info *re = sky2->rx_ring + i;
932
933 if (re->skb) {
934 sky2_rx_unmap_skb(sky2->hw->pdev, re);
935 kfree_skb(re->skb);
936 re->skb = NULL;
937 }
938 }
939 }
940
941 /* Basic MII support */
942 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
943 {
944 struct mii_ioctl_data *data = if_mii(ifr);
945 struct sky2_port *sky2 = netdev_priv(dev);
946 struct sky2_hw *hw = sky2->hw;
947 int err = -EOPNOTSUPP;
948
949 if (!netif_running(dev))
950 return -ENODEV; /* Phy still in reset */
951
952 switch (cmd) {
953 case SIOCGMIIPHY:
954 data->phy_id = PHY_ADDR_MARV;
955
956 /* fallthru */
957 case SIOCGMIIREG: {
958 u16 val = 0;
959
960 spin_lock_bh(&sky2->phy_lock);
961 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
962 spin_unlock_bh(&sky2->phy_lock);
963
964 data->val_out = val;
965 break;
966 }
967
968 case SIOCSMIIREG:
969 if (!capable(CAP_NET_ADMIN))
970 return -EPERM;
971
972 spin_lock_bh(&sky2->phy_lock);
973 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
974 data->val_in);
975 spin_unlock_bh(&sky2->phy_lock);
976 break;
977 }
978 return err;
979 }
980
981 #ifdef SKY2_VLAN_TAG_USED
982 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
983 {
984 struct sky2_port *sky2 = netdev_priv(dev);
985 struct sky2_hw *hw = sky2->hw;
986 u16 port = sky2->port;
987
988 netif_tx_lock_bh(dev);
989
990 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
991 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
992 sky2->vlgrp = grp;
993
994 netif_tx_unlock_bh(dev);
995 }
996
997 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
998 {
999 struct sky2_port *sky2 = netdev_priv(dev);
1000 struct sky2_hw *hw = sky2->hw;
1001 u16 port = sky2->port;
1002
1003 netif_tx_lock_bh(dev);
1004
1005 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1006 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1007 if (sky2->vlgrp)
1008 sky2->vlgrp->vlan_devices[vid] = NULL;
1009
1010 netif_tx_unlock_bh(dev);
1011 }
1012 #endif
1013
1014 /*
1015 * Allocate an skb for receiving. If the MTU is large enough
1016 * make the skb non-linear with a fragment list of pages.
1017 *
1018 * It appears the hardware has a bug in the FIFO logic that
1019 * cause it to hang if the FIFO gets overrun and the receive buffer
1020 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1021 * aligned except if slab debugging is enabled.
1022 */
1023 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1024 {
1025 struct sk_buff *skb;
1026 unsigned long p;
1027 int i;
1028
1029 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1030 if (!skb)
1031 goto nomem;
1032
1033 p = (unsigned long) skb->data;
1034 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1035
1036 for (i = 0; i < sky2->rx_nfrags; i++) {
1037 struct page *page = alloc_page(GFP_ATOMIC);
1038
1039 if (!page)
1040 goto free_partial;
1041 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1042 }
1043
1044 return skb;
1045 free_partial:
1046 kfree_skb(skb);
1047 nomem:
1048 return NULL;
1049 }
1050
1051 /*
1052 * Allocate and setup receiver buffer pool.
1053 * Normal case this ends up creating one list element for skb
1054 * in the receive ring. Worst case if using large MTU and each
1055 * allocation falls on a different 64 bit region, that results
1056 * in 6 list elements per ring entry.
1057 * One element is used for checksum enable/disable, and one
1058 * extra to avoid wrap.
1059 */
1060 static int sky2_rx_start(struct sky2_port *sky2)
1061 {
1062 struct sky2_hw *hw = sky2->hw;
1063 struct rx_ring_info *re;
1064 unsigned rxq = rxqaddr[sky2->port];
1065 unsigned i, size, space, thresh;
1066
1067 sky2->rx_put = sky2->rx_next = 0;
1068 sky2_qset(hw, rxq);
1069
1070 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
1071 /* MAC Rx RAM Read is controlled by hardware */
1072 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1073 }
1074
1075 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1076
1077 rx_set_checksum(sky2);
1078
1079 /* Space needed for frame data + headers rounded up */
1080 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1081 + 8;
1082
1083 /* Stopping point for hardware truncation */
1084 thresh = (size - 8) / sizeof(u32);
1085
1086 /* Account for overhead of skb - to avoid order > 0 allocation */
1087 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1088 + sizeof(struct skb_shared_info);
1089
1090 sky2->rx_nfrags = space >> PAGE_SHIFT;
1091 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1092
1093 if (sky2->rx_nfrags != 0) {
1094 /* Compute residue after pages */
1095 space = sky2->rx_nfrags << PAGE_SHIFT;
1096
1097 if (space < size)
1098 size -= space;
1099 else
1100 size = 0;
1101
1102 /* Optimize to handle small packets and headers */
1103 if (size < copybreak)
1104 size = copybreak;
1105 if (size < ETH_HLEN)
1106 size = ETH_HLEN;
1107 }
1108 sky2->rx_data_size = size;
1109
1110 /* Fill Rx ring */
1111 for (i = 0; i < sky2->rx_pending; i++) {
1112 re = sky2->rx_ring + i;
1113
1114 re->skb = sky2_rx_alloc(sky2);
1115 if (!re->skb)
1116 goto nomem;
1117
1118 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1119 sky2_rx_submit(sky2, re);
1120 }
1121
1122 /*
1123 * The receiver hangs if it receives frames larger than the
1124 * packet buffer. As a workaround, truncate oversize frames, but
1125 * the register is limited to 9 bits, so if you do frames > 2052
1126 * you better get the MTU right!
1127 */
1128 if (thresh > 0x1ff)
1129 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1130 else {
1131 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1132 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1133 }
1134
1135 /* Tell chip about available buffers */
1136 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1137 return 0;
1138 nomem:
1139 sky2_rx_clean(sky2);
1140 return -ENOMEM;
1141 }
1142
1143 /* Bring up network interface. */
1144 static int sky2_up(struct net_device *dev)
1145 {
1146 struct sky2_port *sky2 = netdev_priv(dev);
1147 struct sky2_hw *hw = sky2->hw;
1148 unsigned port = sky2->port;
1149 u32 ramsize, rxspace, imask;
1150 int cap, err = -ENOMEM;
1151 struct net_device *otherdev = hw->dev[sky2->port^1];
1152
1153 /*
1154 * On dual port PCI-X card, there is an problem where status
1155 * can be received out of order due to split transactions
1156 */
1157 if (otherdev && netif_running(otherdev) &&
1158 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1159 struct sky2_port *osky2 = netdev_priv(otherdev);
1160 u16 cmd;
1161
1162 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1163 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1164 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1165
1166 sky2->rx_csum = 0;
1167 osky2->rx_csum = 0;
1168 }
1169
1170 if (netif_msg_ifup(sky2))
1171 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1172
1173 /* must be power of 2 */
1174 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1175 TX_RING_SIZE *
1176 sizeof(struct sky2_tx_le),
1177 &sky2->tx_le_map);
1178 if (!sky2->tx_le)
1179 goto err_out;
1180
1181 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1182 GFP_KERNEL);
1183 if (!sky2->tx_ring)
1184 goto err_out;
1185 sky2->tx_prod = sky2->tx_cons = 0;
1186
1187 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1188 &sky2->rx_le_map);
1189 if (!sky2->rx_le)
1190 goto err_out;
1191 memset(sky2->rx_le, 0, RX_LE_BYTES);
1192
1193 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1194 GFP_KERNEL);
1195 if (!sky2->rx_ring)
1196 goto err_out;
1197
1198 sky2_phy_power(hw, port, 1);
1199
1200 sky2_mac_init(hw, port);
1201
1202 /* Determine available ram buffer space (in 4K blocks).
1203 * Note: not sure about the FE setting below yet
1204 */
1205 if (hw->chip_id == CHIP_ID_YUKON_FE)
1206 ramsize = 4;
1207 else
1208 ramsize = sky2_read8(hw, B2_E_0);
1209
1210 /* Give transmitter one third (rounded up) */
1211 rxspace = ramsize - (ramsize + 2) / 3;
1212
1213 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1214 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1215
1216 /* Make sure SyncQ is disabled */
1217 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1218 RB_RST_SET);
1219
1220 sky2_qset(hw, txqaddr[port]);
1221
1222 /* Set almost empty threshold */
1223 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1224 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1225 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1226
1227 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1228 TX_RING_SIZE - 1);
1229
1230 err = sky2_rx_start(sky2);
1231 if (err)
1232 goto err_out;
1233
1234 /* Enable interrupts from phy/mac for port */
1235 imask = sky2_read32(hw, B0_IMSK);
1236 imask |= portirq_msk[port];
1237 sky2_write32(hw, B0_IMSK, imask);
1238
1239 return 0;
1240
1241 err_out:
1242 if (sky2->rx_le) {
1243 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1244 sky2->rx_le, sky2->rx_le_map);
1245 sky2->rx_le = NULL;
1246 }
1247 if (sky2->tx_le) {
1248 pci_free_consistent(hw->pdev,
1249 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1250 sky2->tx_le, sky2->tx_le_map);
1251 sky2->tx_le = NULL;
1252 }
1253 kfree(sky2->tx_ring);
1254 kfree(sky2->rx_ring);
1255
1256 sky2->tx_ring = NULL;
1257 sky2->rx_ring = NULL;
1258 return err;
1259 }
1260
1261 /* Modular subtraction in ring */
1262 static inline int tx_dist(unsigned tail, unsigned head)
1263 {
1264 return (head - tail) & (TX_RING_SIZE - 1);
1265 }
1266
1267 /* Number of list elements available for next tx */
1268 static inline int tx_avail(const struct sky2_port *sky2)
1269 {
1270 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1271 }
1272
1273 /* Estimate of number of transmit list elements required */
1274 static unsigned tx_le_req(const struct sk_buff *skb)
1275 {
1276 unsigned count;
1277
1278 count = sizeof(dma_addr_t) / sizeof(u32);
1279 count += skb_shinfo(skb)->nr_frags * count;
1280
1281 if (skb_is_gso(skb))
1282 ++count;
1283
1284 if (skb->ip_summed == CHECKSUM_PARTIAL)
1285 ++count;
1286
1287 return count;
1288 }
1289
1290 /*
1291 * Put one packet in ring for transmit.
1292 * A single packet can generate multiple list elements, and
1293 * the number of ring elements will probably be less than the number
1294 * of list elements used.
1295 */
1296 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1297 {
1298 struct sky2_port *sky2 = netdev_priv(dev);
1299 struct sky2_hw *hw = sky2->hw;
1300 struct sky2_tx_le *le = NULL;
1301 struct tx_ring_info *re;
1302 unsigned i, len;
1303 dma_addr_t mapping;
1304 u32 addr64;
1305 u16 mss;
1306 u8 ctrl;
1307
1308 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1309 return NETDEV_TX_BUSY;
1310
1311 if (unlikely(netif_msg_tx_queued(sky2)))
1312 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1313 dev->name, sky2->tx_prod, skb->len);
1314
1315 len = skb_headlen(skb);
1316 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1317 addr64 = high32(mapping);
1318
1319 /* Send high bits if changed or crosses boundary */
1320 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1321 le = get_tx_le(sky2);
1322 le->addr = cpu_to_le32(addr64);
1323 le->opcode = OP_ADDR64 | HW_OWNER;
1324 sky2->tx_addr64 = high32(mapping + len);
1325 }
1326
1327 /* Check for TCP Segmentation Offload */
1328 mss = skb_shinfo(skb)->gso_size;
1329 if (mss != 0) {
1330 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1331 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1332 mss += ETH_HLEN;
1333
1334 if (mss != sky2->tx_last_mss) {
1335 le = get_tx_le(sky2);
1336 le->addr = cpu_to_le32(mss);
1337 le->opcode = OP_LRGLEN | HW_OWNER;
1338 sky2->tx_last_mss = mss;
1339 }
1340 }
1341
1342 ctrl = 0;
1343 #ifdef SKY2_VLAN_TAG_USED
1344 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1345 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1346 if (!le) {
1347 le = get_tx_le(sky2);
1348 le->addr = 0;
1349 le->opcode = OP_VLAN|HW_OWNER;
1350 } else
1351 le->opcode |= OP_VLAN;
1352 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1353 ctrl |= INS_VLAN;
1354 }
1355 #endif
1356
1357 /* Handle TCP checksum offload */
1358 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1359 unsigned offset = skb->h.raw - skb->data;
1360 u32 tcpsum;
1361
1362 tcpsum = offset << 16; /* sum start */
1363 tcpsum |= offset + skb->csum; /* sum write */
1364
1365 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1366 if (skb->nh.iph->protocol == IPPROTO_UDP)
1367 ctrl |= UDPTCP;
1368
1369 if (tcpsum != sky2->tx_tcpsum) {
1370 sky2->tx_tcpsum = tcpsum;
1371
1372 le = get_tx_le(sky2);
1373 le->addr = cpu_to_le32(tcpsum);
1374 le->length = 0; /* initial checksum value */
1375 le->ctrl = 1; /* one packet */
1376 le->opcode = OP_TCPLISW | HW_OWNER;
1377 }
1378 }
1379
1380 le = get_tx_le(sky2);
1381 le->addr = cpu_to_le32((u32) mapping);
1382 le->length = cpu_to_le16(len);
1383 le->ctrl = ctrl;
1384 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1385
1386 re = tx_le_re(sky2, le);
1387 re->skb = skb;
1388 pci_unmap_addr_set(re, mapaddr, mapping);
1389 pci_unmap_len_set(re, maplen, len);
1390
1391 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1392 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1393
1394 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1395 frag->size, PCI_DMA_TODEVICE);
1396 addr64 = high32(mapping);
1397 if (addr64 != sky2->tx_addr64) {
1398 le = get_tx_le(sky2);
1399 le->addr = cpu_to_le32(addr64);
1400 le->ctrl = 0;
1401 le->opcode = OP_ADDR64 | HW_OWNER;
1402 sky2->tx_addr64 = addr64;
1403 }
1404
1405 le = get_tx_le(sky2);
1406 le->addr = cpu_to_le32((u32) mapping);
1407 le->length = cpu_to_le16(frag->size);
1408 le->ctrl = ctrl;
1409 le->opcode = OP_BUFFER | HW_OWNER;
1410
1411 re = tx_le_re(sky2, le);
1412 re->skb = skb;
1413 pci_unmap_addr_set(re, mapaddr, mapping);
1414 pci_unmap_len_set(re, maplen, frag->size);
1415 }
1416
1417 le->ctrl |= EOP;
1418
1419 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1420 netif_stop_queue(dev);
1421
1422 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1423
1424 dev->trans_start = jiffies;
1425 return NETDEV_TX_OK;
1426 }
1427
1428 /*
1429 * Free ring elements from starting at tx_cons until "done"
1430 *
1431 * NB: the hardware will tell us about partial completion of multi-part
1432 * buffers so make sure not to free skb to early.
1433 */
1434 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1435 {
1436 struct net_device *dev = sky2->netdev;
1437 struct pci_dev *pdev = sky2->hw->pdev;
1438 unsigned idx;
1439
1440 BUG_ON(done >= TX_RING_SIZE);
1441
1442 for (idx = sky2->tx_cons; idx != done;
1443 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1444 struct sky2_tx_le *le = sky2->tx_le + idx;
1445 struct tx_ring_info *re = sky2->tx_ring + idx;
1446
1447 switch(le->opcode & ~HW_OWNER) {
1448 case OP_LARGESEND:
1449 case OP_PACKET:
1450 pci_unmap_single(pdev,
1451 pci_unmap_addr(re, mapaddr),
1452 pci_unmap_len(re, maplen),
1453 PCI_DMA_TODEVICE);
1454 break;
1455 case OP_BUFFER:
1456 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1457 pci_unmap_len(re, maplen),
1458 PCI_DMA_TODEVICE);
1459 break;
1460 }
1461
1462 if (le->ctrl & EOP) {
1463 if (unlikely(netif_msg_tx_done(sky2)))
1464 printk(KERN_DEBUG "%s: tx done %u\n",
1465 dev->name, idx);
1466 dev_kfree_skb(re->skb);
1467 }
1468
1469 le->opcode = 0; /* paranoia */
1470 }
1471
1472 sky2->tx_cons = idx;
1473 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1474 netif_wake_queue(dev);
1475 }
1476
1477 /* Cleanup all untransmitted buffers, assume transmitter not running */
1478 static void sky2_tx_clean(struct net_device *dev)
1479 {
1480 struct sky2_port *sky2 = netdev_priv(dev);
1481
1482 netif_tx_lock_bh(dev);
1483 sky2_tx_complete(sky2, sky2->tx_prod);
1484 netif_tx_unlock_bh(dev);
1485 }
1486
1487 /* Network shutdown */
1488 static int sky2_down(struct net_device *dev)
1489 {
1490 struct sky2_port *sky2 = netdev_priv(dev);
1491 struct sky2_hw *hw = sky2->hw;
1492 unsigned port = sky2->port;
1493 u16 ctrl;
1494 u32 imask;
1495
1496 /* Never really got started! */
1497 if (!sky2->tx_le)
1498 return 0;
1499
1500 if (netif_msg_ifdown(sky2))
1501 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1502
1503 /* Stop more packets from being queued */
1504 netif_stop_queue(dev);
1505
1506 /* Disable port IRQ */
1507 imask = sky2_read32(hw, B0_IMSK);
1508 imask &= ~portirq_msk[port];
1509 sky2_write32(hw, B0_IMSK, imask);
1510
1511 sky2_gmac_reset(hw, port);
1512
1513 /* Stop transmitter */
1514 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1515 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1516
1517 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1518 RB_RST_SET | RB_DIS_OP_MD);
1519
1520 /* WA for dev. #4.209 */
1521 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1522 && hw->chip_rev == CHIP_REV_YU_EC_U_A1)
1523 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1524 sky2->speed != SPEED_1000 ?
1525 TX_STFW_ENA : TX_STFW_DIS);
1526
1527 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1528 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1529 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1530
1531 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1532
1533 /* Workaround shared GMAC reset */
1534 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1535 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1536 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1537
1538 /* Disable Force Sync bit and Enable Alloc bit */
1539 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1540 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1541
1542 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1543 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1544 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1545
1546 /* Reset the PCI FIFO of the async Tx queue */
1547 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1548 BMU_RST_SET | BMU_FIFO_RST);
1549
1550 /* Reset the Tx prefetch units */
1551 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1552 PREF_UNIT_RST_SET);
1553
1554 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1555
1556 sky2_rx_stop(sky2);
1557
1558 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1559 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1560
1561 sky2_phy_power(hw, port, 0);
1562
1563 /* turn off LED's */
1564 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1565
1566 synchronize_irq(hw->pdev->irq);
1567
1568 sky2_tx_clean(dev);
1569 sky2_rx_clean(sky2);
1570
1571 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1572 sky2->rx_le, sky2->rx_le_map);
1573 kfree(sky2->rx_ring);
1574
1575 pci_free_consistent(hw->pdev,
1576 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1577 sky2->tx_le, sky2->tx_le_map);
1578 kfree(sky2->tx_ring);
1579
1580 sky2->tx_le = NULL;
1581 sky2->rx_le = NULL;
1582
1583 sky2->rx_ring = NULL;
1584 sky2->tx_ring = NULL;
1585
1586 return 0;
1587 }
1588
1589 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1590 {
1591 if (!sky2_is_copper(hw))
1592 return SPEED_1000;
1593
1594 if (hw->chip_id == CHIP_ID_YUKON_FE)
1595 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1596
1597 switch (aux & PHY_M_PS_SPEED_MSK) {
1598 case PHY_M_PS_SPEED_1000:
1599 return SPEED_1000;
1600 case PHY_M_PS_SPEED_100:
1601 return SPEED_100;
1602 default:
1603 return SPEED_10;
1604 }
1605 }
1606
1607 static void sky2_link_up(struct sky2_port *sky2)
1608 {
1609 struct sky2_hw *hw = sky2->hw;
1610 unsigned port = sky2->port;
1611 u16 reg;
1612 static const char *fc_name[] = {
1613 [FC_NONE] = "none",
1614 [FC_TX] = "tx",
1615 [FC_RX] = "rx",
1616 [FC_BOTH] = "both",
1617 };
1618
1619 /* enable Rx/Tx */
1620 reg = gma_read16(hw, port, GM_GP_CTRL);
1621 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1622 gma_write16(hw, port, GM_GP_CTRL, reg);
1623
1624 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1625
1626 netif_carrier_on(sky2->netdev);
1627 netif_wake_queue(sky2->netdev);
1628
1629 /* Turn on link LED */
1630 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1631 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1632
1633 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
1634 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1635 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1636
1637 switch(sky2->speed) {
1638 case SPEED_10:
1639 led |= PHY_M_LEDC_INIT_CTRL(7);
1640 break;
1641
1642 case SPEED_100:
1643 led |= PHY_M_LEDC_STA1_CTRL(7);
1644 break;
1645
1646 case SPEED_1000:
1647 led |= PHY_M_LEDC_STA0_CTRL(7);
1648 break;
1649 }
1650
1651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1652 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1653 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1654 }
1655
1656 if (netif_msg_link(sky2))
1657 printk(KERN_INFO PFX
1658 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1659 sky2->netdev->name, sky2->speed,
1660 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1661 fc_name[sky2->flow_status]);
1662 }
1663
1664 static void sky2_link_down(struct sky2_port *sky2)
1665 {
1666 struct sky2_hw *hw = sky2->hw;
1667 unsigned port = sky2->port;
1668 u16 reg;
1669
1670 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1671
1672 reg = gma_read16(hw, port, GM_GP_CTRL);
1673 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1674 gma_write16(hw, port, GM_GP_CTRL, reg);
1675
1676 if (sky2->flow_status == FC_RX) {
1677 /* restore Asymmetric Pause bit */
1678 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1679 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1680 | PHY_M_AN_ASP);
1681 }
1682
1683 netif_carrier_off(sky2->netdev);
1684 netif_stop_queue(sky2->netdev);
1685
1686 /* Turn on link LED */
1687 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1688
1689 if (netif_msg_link(sky2))
1690 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1691
1692 sky2_phy_init(hw, port);
1693 }
1694
1695 static enum flow_control sky2_flow(int rx, int tx)
1696 {
1697 if (rx)
1698 return tx ? FC_BOTH : FC_RX;
1699 else
1700 return tx ? FC_TX : FC_NONE;
1701 }
1702
1703 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1704 {
1705 struct sky2_hw *hw = sky2->hw;
1706 unsigned port = sky2->port;
1707 u16 lpa;
1708
1709 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1710
1711 if (lpa & PHY_M_AN_RF) {
1712 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1713 return -1;
1714 }
1715
1716 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1717 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1718 sky2->netdev->name);
1719 return -1;
1720 }
1721
1722 sky2->speed = sky2_phy_speed(hw, aux);
1723 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1724
1725 /* Pause bits are offset (9..8) */
1726 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1727 aux >>= 6;
1728
1729 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1730 aux & PHY_M_PS_TX_P_EN);
1731
1732 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1733 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1734 sky2->flow_status = FC_NONE;
1735
1736 if (aux & PHY_M_PS_RX_P_EN)
1737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1738 else
1739 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1740
1741 return 0;
1742 }
1743
1744 /* Interrupt from PHY */
1745 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1746 {
1747 struct net_device *dev = hw->dev[port];
1748 struct sky2_port *sky2 = netdev_priv(dev);
1749 u16 istatus, phystat;
1750
1751 if (!netif_running(dev))
1752 return;
1753
1754 spin_lock(&sky2->phy_lock);
1755 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1756 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1757
1758 if (netif_msg_intr(sky2))
1759 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1760 sky2->netdev->name, istatus, phystat);
1761
1762 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1763 if (sky2_autoneg_done(sky2, phystat) == 0)
1764 sky2_link_up(sky2);
1765 goto out;
1766 }
1767
1768 if (istatus & PHY_M_IS_LSP_CHANGE)
1769 sky2->speed = sky2_phy_speed(hw, phystat);
1770
1771 if (istatus & PHY_M_IS_DUP_CHANGE)
1772 sky2->duplex =
1773 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1774
1775 if (istatus & PHY_M_IS_LST_CHANGE) {
1776 if (phystat & PHY_M_PS_LINK_UP)
1777 sky2_link_up(sky2);
1778 else
1779 sky2_link_down(sky2);
1780 }
1781 out:
1782 spin_unlock(&sky2->phy_lock);
1783 }
1784
1785
1786 /* Transmit timeout is only called if we are running, carries is up
1787 * and tx queue is full (stopped).
1788 */
1789 static void sky2_tx_timeout(struct net_device *dev)
1790 {
1791 struct sky2_port *sky2 = netdev_priv(dev);
1792 struct sky2_hw *hw = sky2->hw;
1793 unsigned txq = txqaddr[sky2->port];
1794 u16 report, done;
1795
1796 if (netif_msg_timer(sky2))
1797 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1798
1799 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1800 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1801
1802 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1803 dev->name,
1804 sky2->tx_cons, sky2->tx_prod, report, done);
1805
1806 if (report != done) {
1807 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1808
1809 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1810 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1811 } else if (report != sky2->tx_cons) {
1812 printk(KERN_INFO PFX "status report lost?\n");
1813
1814 netif_tx_lock_bh(dev);
1815 sky2_tx_complete(sky2, report);
1816 netif_tx_unlock_bh(dev);
1817 } else {
1818 printk(KERN_INFO PFX "hardware hung? flushing\n");
1819
1820 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1821 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1822
1823 sky2_tx_clean(dev);
1824
1825 sky2_qset(hw, txq);
1826 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1827 }
1828 }
1829
1830 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1831 {
1832 struct sky2_port *sky2 = netdev_priv(dev);
1833 struct sky2_hw *hw = sky2->hw;
1834 int err;
1835 u16 ctl, mode;
1836 u32 imask;
1837
1838 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1839 return -EINVAL;
1840
1841 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1842 return -EINVAL;
1843
1844 if (!netif_running(dev)) {
1845 dev->mtu = new_mtu;
1846 return 0;
1847 }
1848
1849 imask = sky2_read32(hw, B0_IMSK);
1850 sky2_write32(hw, B0_IMSK, 0);
1851
1852 dev->trans_start = jiffies; /* prevent tx timeout */
1853 netif_stop_queue(dev);
1854 netif_poll_disable(hw->dev[0]);
1855
1856 synchronize_irq(hw->pdev->irq);
1857
1858 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1859 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1860 sky2_rx_stop(sky2);
1861 sky2_rx_clean(sky2);
1862
1863 dev->mtu = new_mtu;
1864
1865 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1866 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1867
1868 if (dev->mtu > ETH_DATA_LEN)
1869 mode |= GM_SMOD_JUMBO_ENA;
1870
1871 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1872
1873 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1874
1875 err = sky2_rx_start(sky2);
1876 sky2_write32(hw, B0_IMSK, imask);
1877
1878 if (err)
1879 dev_close(dev);
1880 else {
1881 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1882
1883 netif_poll_enable(hw->dev[0]);
1884 netif_wake_queue(dev);
1885 }
1886
1887 return err;
1888 }
1889
1890 /* For small just reuse existing skb for next receive */
1891 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1892 const struct rx_ring_info *re,
1893 unsigned length)
1894 {
1895 struct sk_buff *skb;
1896
1897 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1898 if (likely(skb)) {
1899 skb_reserve(skb, 2);
1900 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1901 length, PCI_DMA_FROMDEVICE);
1902 memcpy(skb->data, re->skb->data, length);
1903 skb->ip_summed = re->skb->ip_summed;
1904 skb->csum = re->skb->csum;
1905 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1906 length, PCI_DMA_FROMDEVICE);
1907 re->skb->ip_summed = CHECKSUM_NONE;
1908 skb_put(skb, length);
1909 }
1910 return skb;
1911 }
1912
1913 /* Adjust length of skb with fragments to match received data */
1914 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1915 unsigned int length)
1916 {
1917 int i, num_frags;
1918 unsigned int size;
1919
1920 /* put header into skb */
1921 size = min(length, hdr_space);
1922 skb->tail += size;
1923 skb->len += size;
1924 length -= size;
1925
1926 num_frags = skb_shinfo(skb)->nr_frags;
1927 for (i = 0; i < num_frags; i++) {
1928 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1929
1930 if (length == 0) {
1931 /* don't need this page */
1932 __free_page(frag->page);
1933 --skb_shinfo(skb)->nr_frags;
1934 } else {
1935 size = min(length, (unsigned) PAGE_SIZE);
1936
1937 frag->size = size;
1938 skb->data_len += size;
1939 skb->truesize += size;
1940 skb->len += size;
1941 length -= size;
1942 }
1943 }
1944 }
1945
1946 /* Normal packet - take skb from ring element and put in a new one */
1947 static struct sk_buff *receive_new(struct sky2_port *sky2,
1948 struct rx_ring_info *re,
1949 unsigned int length)
1950 {
1951 struct sk_buff *skb, *nskb;
1952 unsigned hdr_space = sky2->rx_data_size;
1953
1954 pr_debug(PFX "receive new length=%d\n", length);
1955
1956 /* Don't be tricky about reusing pages (yet) */
1957 nskb = sky2_rx_alloc(sky2);
1958 if (unlikely(!nskb))
1959 return NULL;
1960
1961 skb = re->skb;
1962 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1963
1964 prefetch(skb->data);
1965 re->skb = nskb;
1966 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1967
1968 if (skb_shinfo(skb)->nr_frags)
1969 skb_put_frags(skb, hdr_space, length);
1970 else
1971 skb_put(skb, length);
1972 return skb;
1973 }
1974
1975 /*
1976 * Receive one packet.
1977 * For larger packets, get new buffer.
1978 */
1979 static struct sk_buff *sky2_receive(struct net_device *dev,
1980 u16 length, u32 status)
1981 {
1982 struct sky2_port *sky2 = netdev_priv(dev);
1983 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
1984 struct sk_buff *skb = NULL;
1985
1986 if (unlikely(netif_msg_rx_status(sky2)))
1987 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1988 dev->name, sky2->rx_next, status, length);
1989
1990 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1991 prefetch(sky2->rx_ring + sky2->rx_next);
1992
1993 if (status & GMR_FS_ANY_ERR)
1994 goto error;
1995
1996 if (!(status & GMR_FS_RX_OK))
1997 goto resubmit;
1998
1999 if (length > dev->mtu + ETH_HLEN)
2000 goto oversize;
2001
2002 if (length < copybreak)
2003 skb = receive_copy(sky2, re, length);
2004 else
2005 skb = receive_new(sky2, re, length);
2006 resubmit:
2007 sky2_rx_submit(sky2, re);
2008
2009 return skb;
2010
2011 oversize:
2012 ++sky2->net_stats.rx_over_errors;
2013 goto resubmit;
2014
2015 error:
2016 ++sky2->net_stats.rx_errors;
2017 if (status & GMR_FS_RX_FF_OV) {
2018 sky2->net_stats.rx_fifo_errors++;
2019 goto resubmit;
2020 }
2021
2022 if (netif_msg_rx_err(sky2) && net_ratelimit())
2023 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2024 dev->name, status, length);
2025
2026 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2027 sky2->net_stats.rx_length_errors++;
2028 if (status & GMR_FS_FRAGMENT)
2029 sky2->net_stats.rx_frame_errors++;
2030 if (status & GMR_FS_CRC_ERR)
2031 sky2->net_stats.rx_crc_errors++;
2032
2033 goto resubmit;
2034 }
2035
2036 /* Transmit complete */
2037 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2038 {
2039 struct sky2_port *sky2 = netdev_priv(dev);
2040
2041 if (netif_running(dev)) {
2042 netif_tx_lock(dev);
2043 sky2_tx_complete(sky2, last);
2044 netif_tx_unlock(dev);
2045 }
2046 }
2047
2048 /* Process status response ring */
2049 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2050 {
2051 struct sky2_port *sky2;
2052 int work_done = 0;
2053 unsigned buf_write[2] = { 0, 0 };
2054 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2055
2056 rmb();
2057
2058 while (hw->st_idx != hwidx) {
2059 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2060 struct net_device *dev;
2061 struct sk_buff *skb;
2062 u32 status;
2063 u16 length;
2064
2065 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2066
2067 BUG_ON(le->link >= 2);
2068 dev = hw->dev[le->link];
2069
2070 sky2 = netdev_priv(dev);
2071 length = le16_to_cpu(le->length);
2072 status = le32_to_cpu(le->status);
2073
2074 switch (le->opcode & ~HW_OWNER) {
2075 case OP_RXSTAT:
2076 skb = sky2_receive(dev, length, status);
2077 if (!skb)
2078 break;
2079
2080 skb->protocol = eth_type_trans(skb, dev);
2081 dev->last_rx = jiffies;
2082
2083 #ifdef SKY2_VLAN_TAG_USED
2084 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2085 vlan_hwaccel_receive_skb(skb,
2086 sky2->vlgrp,
2087 be16_to_cpu(sky2->rx_tag));
2088 } else
2089 #endif
2090 netif_receive_skb(skb);
2091
2092 /* Update receiver after 16 frames */
2093 if (++buf_write[le->link] == RX_BUF_WRITE) {
2094 sky2_put_idx(hw, rxqaddr[le->link],
2095 sky2->rx_put);
2096 buf_write[le->link] = 0;
2097 }
2098
2099 /* Stop after net poll weight */
2100 if (++work_done >= to_do)
2101 goto exit_loop;
2102 break;
2103
2104 #ifdef SKY2_VLAN_TAG_USED
2105 case OP_RXVLAN:
2106 sky2->rx_tag = length;
2107 break;
2108
2109 case OP_RXCHKSVLAN:
2110 sky2->rx_tag = length;
2111 /* fall through */
2112 #endif
2113 case OP_RXCHKS:
2114 skb = sky2->rx_ring[sky2->rx_next].skb;
2115 skb->ip_summed = CHECKSUM_COMPLETE;
2116 skb->csum = status & 0xffff;
2117 break;
2118
2119 case OP_TXINDEXLE:
2120 /* TX index reports status for both ports */
2121 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2122 sky2_tx_done(hw->dev[0], status & 0xfff);
2123 if (hw->dev[1])
2124 sky2_tx_done(hw->dev[1],
2125 ((status >> 24) & 0xff)
2126 | (u16)(length & 0xf) << 8);
2127 break;
2128
2129 default:
2130 if (net_ratelimit())
2131 printk(KERN_WARNING PFX
2132 "unknown status opcode 0x%x\n", le->opcode);
2133 goto exit_loop;
2134 }
2135 }
2136
2137 /* Fully processed status ring so clear irq */
2138 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2139
2140 exit_loop:
2141 if (buf_write[0]) {
2142 sky2 = netdev_priv(hw->dev[0]);
2143 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2144 }
2145
2146 if (buf_write[1]) {
2147 sky2 = netdev_priv(hw->dev[1]);
2148 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2149 }
2150
2151 return work_done;
2152 }
2153
2154 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2155 {
2156 struct net_device *dev = hw->dev[port];
2157
2158 if (net_ratelimit())
2159 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2160 dev->name, status);
2161
2162 if (status & Y2_IS_PAR_RD1) {
2163 if (net_ratelimit())
2164 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2165 dev->name);
2166 /* Clear IRQ */
2167 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2168 }
2169
2170 if (status & Y2_IS_PAR_WR1) {
2171 if (net_ratelimit())
2172 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2173 dev->name);
2174
2175 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2176 }
2177
2178 if (status & Y2_IS_PAR_MAC1) {
2179 if (net_ratelimit())
2180 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2181 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2182 }
2183
2184 if (status & Y2_IS_PAR_RX1) {
2185 if (net_ratelimit())
2186 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2187 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2188 }
2189
2190 if (status & Y2_IS_TCP_TXA1) {
2191 if (net_ratelimit())
2192 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2193 dev->name);
2194 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2195 }
2196 }
2197
2198 static void sky2_hw_intr(struct sky2_hw *hw)
2199 {
2200 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2201
2202 if (status & Y2_IS_TIST_OV)
2203 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2204
2205 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2206 u16 pci_err;
2207
2208 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2209 if (net_ratelimit())
2210 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2211 pci_name(hw->pdev), pci_err);
2212
2213 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2214 sky2_pci_write16(hw, PCI_STATUS,
2215 pci_err | PCI_STATUS_ERROR_BITS);
2216 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2217 }
2218
2219 if (status & Y2_IS_PCI_EXP) {
2220 /* PCI-Express uncorrectable Error occurred */
2221 u32 pex_err;
2222
2223 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2224
2225 if (net_ratelimit())
2226 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2227 pci_name(hw->pdev), pex_err);
2228
2229 /* clear the interrupt */
2230 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2231 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2232 0xffffffffUL);
2233 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2234
2235 if (pex_err & PEX_FATAL_ERRORS) {
2236 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2237 hwmsk &= ~Y2_IS_PCI_EXP;
2238 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2239 }
2240 }
2241
2242 if (status & Y2_HWE_L1_MASK)
2243 sky2_hw_error(hw, 0, status);
2244 status >>= 8;
2245 if (status & Y2_HWE_L1_MASK)
2246 sky2_hw_error(hw, 1, status);
2247 }
2248
2249 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2250 {
2251 struct net_device *dev = hw->dev[port];
2252 struct sky2_port *sky2 = netdev_priv(dev);
2253 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2254
2255 if (netif_msg_intr(sky2))
2256 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2257 dev->name, status);
2258
2259 if (status & GM_IS_RX_FF_OR) {
2260 ++sky2->net_stats.rx_fifo_errors;
2261 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2262 }
2263
2264 if (status & GM_IS_TX_FF_UR) {
2265 ++sky2->net_stats.tx_fifo_errors;
2266 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2267 }
2268 }
2269
2270 /* This should never happen it is a fatal situation */
2271 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2272 const char *rxtx, u32 mask)
2273 {
2274 struct net_device *dev = hw->dev[port];
2275 struct sky2_port *sky2 = netdev_priv(dev);
2276 u32 imask;
2277
2278 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2279 dev ? dev->name : "<not registered>", rxtx);
2280
2281 imask = sky2_read32(hw, B0_IMSK);
2282 imask &= ~mask;
2283 sky2_write32(hw, B0_IMSK, imask);
2284
2285 if (dev) {
2286 spin_lock(&sky2->phy_lock);
2287 sky2_link_down(sky2);
2288 spin_unlock(&sky2->phy_lock);
2289 }
2290 }
2291
2292 /* If idle then force a fake soft NAPI poll once a second
2293 * to work around cases where sharing an edge triggered interrupt.
2294 */
2295 static inline void sky2_idle_start(struct sky2_hw *hw)
2296 {
2297 if (idle_timeout > 0)
2298 mod_timer(&hw->idle_timer,
2299 jiffies + msecs_to_jiffies(idle_timeout));
2300 }
2301
2302 static void sky2_idle(unsigned long arg)
2303 {
2304 struct sky2_hw *hw = (struct sky2_hw *) arg;
2305 struct net_device *dev = hw->dev[0];
2306
2307 if (__netif_rx_schedule_prep(dev))
2308 __netif_rx_schedule(dev);
2309
2310 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2311 }
2312
2313
2314 static int sky2_poll(struct net_device *dev0, int *budget)
2315 {
2316 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2317 int work_limit = min(dev0->quota, *budget);
2318 int work_done = 0;
2319 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2320
2321 if (status & Y2_IS_HW_ERR)
2322 sky2_hw_intr(hw);
2323
2324 if (status & Y2_IS_IRQ_PHY1)
2325 sky2_phy_intr(hw, 0);
2326
2327 if (status & Y2_IS_IRQ_PHY2)
2328 sky2_phy_intr(hw, 1);
2329
2330 if (status & Y2_IS_IRQ_MAC1)
2331 sky2_mac_intr(hw, 0);
2332
2333 if (status & Y2_IS_IRQ_MAC2)
2334 sky2_mac_intr(hw, 1);
2335
2336 if (status & Y2_IS_CHK_RX1)
2337 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2338
2339 if (status & Y2_IS_CHK_RX2)
2340 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2341
2342 if (status & Y2_IS_CHK_TXA1)
2343 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2344
2345 if (status & Y2_IS_CHK_TXA2)
2346 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2347
2348 work_done = sky2_status_intr(hw, work_limit);
2349 if (work_done < work_limit) {
2350 netif_rx_complete(dev0);
2351
2352 sky2_read32(hw, B0_Y2_SP_LISR);
2353 return 0;
2354 } else {
2355 *budget -= work_done;
2356 dev0->quota -= work_done;
2357 return 1;
2358 }
2359 }
2360
2361 static irqreturn_t sky2_intr(int irq, void *dev_id)
2362 {
2363 struct sky2_hw *hw = dev_id;
2364 struct net_device *dev0 = hw->dev[0];
2365 u32 status;
2366
2367 /* Reading this mask interrupts as side effect */
2368 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2369 if (status == 0 || status == ~0)
2370 return IRQ_NONE;
2371
2372 prefetch(&hw->st_le[hw->st_idx]);
2373 if (likely(__netif_rx_schedule_prep(dev0)))
2374 __netif_rx_schedule(dev0);
2375
2376 return IRQ_HANDLED;
2377 }
2378
2379 #ifdef CONFIG_NET_POLL_CONTROLLER
2380 static void sky2_netpoll(struct net_device *dev)
2381 {
2382 struct sky2_port *sky2 = netdev_priv(dev);
2383 struct net_device *dev0 = sky2->hw->dev[0];
2384
2385 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2386 __netif_rx_schedule(dev0);
2387 }
2388 #endif
2389
2390 /* Chip internal frequency for clock calculations */
2391 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2392 {
2393 switch (hw->chip_id) {
2394 case CHIP_ID_YUKON_EC:
2395 case CHIP_ID_YUKON_EC_U:
2396 return 125; /* 125 Mhz */
2397 case CHIP_ID_YUKON_FE:
2398 return 100; /* 100 Mhz */
2399 default: /* YUKON_XL */
2400 return 156; /* 156 Mhz */
2401 }
2402 }
2403
2404 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2405 {
2406 return sky2_mhz(hw) * us;
2407 }
2408
2409 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2410 {
2411 return clk / sky2_mhz(hw);
2412 }
2413
2414
2415 static int sky2_reset(struct sky2_hw *hw)
2416 {
2417 u16 status;
2418 u8 t8;
2419 int i;
2420
2421 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2422
2423 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2424 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2425 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2426 pci_name(hw->pdev), hw->chip_id);
2427 return -EOPNOTSUPP;
2428 }
2429
2430 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2431
2432 /* This rev is really old, and requires untested workarounds */
2433 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2434 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2435 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2436 hw->chip_id, hw->chip_rev);
2437 return -EOPNOTSUPP;
2438 }
2439
2440 /* disable ASF */
2441 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2442 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2443 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2444 }
2445
2446 /* do a SW reset */
2447 sky2_write8(hw, B0_CTST, CS_RST_SET);
2448 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2449
2450 /* clear PCI errors, if any */
2451 status = sky2_pci_read16(hw, PCI_STATUS);
2452
2453 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2454 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2455
2456
2457 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2458
2459 /* clear any PEX errors */
2460 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2461 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2462
2463
2464 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2465 hw->ports = 1;
2466 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2467 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2468 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2469 ++hw->ports;
2470 }
2471
2472 sky2_set_power_state(hw, PCI_D0);
2473
2474 for (i = 0; i < hw->ports; i++) {
2475 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2476 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2477 }
2478
2479 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2480
2481 /* Clear I2C IRQ noise */
2482 sky2_write32(hw, B2_I2C_IRQ, 1);
2483
2484 /* turn off hardware timer (unused) */
2485 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2486 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2487
2488 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2489
2490 /* Turn off descriptor polling */
2491 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2492
2493 /* Turn off receive timestamp */
2494 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2495 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2496
2497 /* enable the Tx Arbiters */
2498 for (i = 0; i < hw->ports; i++)
2499 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2500
2501 /* Initialize ram interface */
2502 for (i = 0; i < hw->ports; i++) {
2503 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2504
2505 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2506 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2507 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2508 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2509 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2510 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2511 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2512 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2513 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2514 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2515 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2516 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2517 }
2518
2519 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2520
2521 for (i = 0; i < hw->ports; i++)
2522 sky2_gmac_reset(hw, i);
2523
2524 memset(hw->st_le, 0, STATUS_LE_BYTES);
2525 hw->st_idx = 0;
2526
2527 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2528 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2529
2530 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2531 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2532
2533 /* Set the list last index */
2534 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2535
2536 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2537 sky2_write8(hw, STAT_FIFO_WM, 16);
2538
2539 /* set Status-FIFO ISR watermark */
2540 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2541 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2542 else
2543 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2544
2545 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2546 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2547 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2548
2549 /* enable status unit */
2550 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2551
2552 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2553 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2554 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2555
2556 return 0;
2557 }
2558
2559 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2560 {
2561 if (sky2_is_copper(hw)) {
2562 u32 modes = SUPPORTED_10baseT_Half
2563 | SUPPORTED_10baseT_Full
2564 | SUPPORTED_100baseT_Half
2565 | SUPPORTED_100baseT_Full
2566 | SUPPORTED_Autoneg | SUPPORTED_TP;
2567
2568 if (hw->chip_id != CHIP_ID_YUKON_FE)
2569 modes |= SUPPORTED_1000baseT_Half
2570 | SUPPORTED_1000baseT_Full;
2571 return modes;
2572 } else
2573 return SUPPORTED_1000baseT_Half
2574 | SUPPORTED_1000baseT_Full
2575 | SUPPORTED_Autoneg
2576 | SUPPORTED_FIBRE;
2577 }
2578
2579 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2580 {
2581 struct sky2_port *sky2 = netdev_priv(dev);
2582 struct sky2_hw *hw = sky2->hw;
2583
2584 ecmd->transceiver = XCVR_INTERNAL;
2585 ecmd->supported = sky2_supported_modes(hw);
2586 ecmd->phy_address = PHY_ADDR_MARV;
2587 if (sky2_is_copper(hw)) {
2588 ecmd->supported = SUPPORTED_10baseT_Half
2589 | SUPPORTED_10baseT_Full
2590 | SUPPORTED_100baseT_Half
2591 | SUPPORTED_100baseT_Full
2592 | SUPPORTED_1000baseT_Half
2593 | SUPPORTED_1000baseT_Full
2594 | SUPPORTED_Autoneg | SUPPORTED_TP;
2595 ecmd->port = PORT_TP;
2596 ecmd->speed = sky2->speed;
2597 } else {
2598 ecmd->speed = SPEED_1000;
2599 ecmd->port = PORT_FIBRE;
2600 }
2601
2602 ecmd->advertising = sky2->advertising;
2603 ecmd->autoneg = sky2->autoneg;
2604 ecmd->duplex = sky2->duplex;
2605 return 0;
2606 }
2607
2608 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2609 {
2610 struct sky2_port *sky2 = netdev_priv(dev);
2611 const struct sky2_hw *hw = sky2->hw;
2612 u32 supported = sky2_supported_modes(hw);
2613
2614 if (ecmd->autoneg == AUTONEG_ENABLE) {
2615 ecmd->advertising = supported;
2616 sky2->duplex = -1;
2617 sky2->speed = -1;
2618 } else {
2619 u32 setting;
2620
2621 switch (ecmd->speed) {
2622 case SPEED_1000:
2623 if (ecmd->duplex == DUPLEX_FULL)
2624 setting = SUPPORTED_1000baseT_Full;
2625 else if (ecmd->duplex == DUPLEX_HALF)
2626 setting = SUPPORTED_1000baseT_Half;
2627 else
2628 return -EINVAL;
2629 break;
2630 case SPEED_100:
2631 if (ecmd->duplex == DUPLEX_FULL)
2632 setting = SUPPORTED_100baseT_Full;
2633 else if (ecmd->duplex == DUPLEX_HALF)
2634 setting = SUPPORTED_100baseT_Half;
2635 else
2636 return -EINVAL;
2637 break;
2638
2639 case SPEED_10:
2640 if (ecmd->duplex == DUPLEX_FULL)
2641 setting = SUPPORTED_10baseT_Full;
2642 else if (ecmd->duplex == DUPLEX_HALF)
2643 setting = SUPPORTED_10baseT_Half;
2644 else
2645 return -EINVAL;
2646 break;
2647 default:
2648 return -EINVAL;
2649 }
2650
2651 if ((setting & supported) == 0)
2652 return -EINVAL;
2653
2654 sky2->speed = ecmd->speed;
2655 sky2->duplex = ecmd->duplex;
2656 }
2657
2658 sky2->autoneg = ecmd->autoneg;
2659 sky2->advertising = ecmd->advertising;
2660
2661 if (netif_running(dev))
2662 sky2_phy_reinit(sky2);
2663
2664 return 0;
2665 }
2666
2667 static void sky2_get_drvinfo(struct net_device *dev,
2668 struct ethtool_drvinfo *info)
2669 {
2670 struct sky2_port *sky2 = netdev_priv(dev);
2671
2672 strcpy(info->driver, DRV_NAME);
2673 strcpy(info->version, DRV_VERSION);
2674 strcpy(info->fw_version, "N/A");
2675 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2676 }
2677
2678 static const struct sky2_stat {
2679 char name[ETH_GSTRING_LEN];
2680 u16 offset;
2681 } sky2_stats[] = {
2682 { "tx_bytes", GM_TXO_OK_HI },
2683 { "rx_bytes", GM_RXO_OK_HI },
2684 { "tx_broadcast", GM_TXF_BC_OK },
2685 { "rx_broadcast", GM_RXF_BC_OK },
2686 { "tx_multicast", GM_TXF_MC_OK },
2687 { "rx_multicast", GM_RXF_MC_OK },
2688 { "tx_unicast", GM_TXF_UC_OK },
2689 { "rx_unicast", GM_RXF_UC_OK },
2690 { "tx_mac_pause", GM_TXF_MPAUSE },
2691 { "rx_mac_pause", GM_RXF_MPAUSE },
2692 { "collisions", GM_TXF_COL },
2693 { "late_collision",GM_TXF_LAT_COL },
2694 { "aborted", GM_TXF_ABO_COL },
2695 { "single_collisions", GM_TXF_SNG_COL },
2696 { "multi_collisions", GM_TXF_MUL_COL },
2697
2698 { "rx_short", GM_RXF_SHT },
2699 { "rx_runt", GM_RXE_FRAG },
2700 { "rx_64_byte_packets", GM_RXF_64B },
2701 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2702 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2703 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2704 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2705 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2706 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2707 { "rx_too_long", GM_RXF_LNG_ERR },
2708 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2709 { "rx_jabber", GM_RXF_JAB_PKT },
2710 { "rx_fcs_error", GM_RXF_FCS_ERR },
2711
2712 { "tx_64_byte_packets", GM_TXF_64B },
2713 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2714 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2715 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2716 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2717 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2718 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2719 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2720 };
2721
2722 static u32 sky2_get_rx_csum(struct net_device *dev)
2723 {
2724 struct sky2_port *sky2 = netdev_priv(dev);
2725
2726 return sky2->rx_csum;
2727 }
2728
2729 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2730 {
2731 struct sky2_port *sky2 = netdev_priv(dev);
2732
2733 sky2->rx_csum = data;
2734
2735 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2736 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2737
2738 return 0;
2739 }
2740
2741 static u32 sky2_get_msglevel(struct net_device *netdev)
2742 {
2743 struct sky2_port *sky2 = netdev_priv(netdev);
2744 return sky2->msg_enable;
2745 }
2746
2747 static int sky2_nway_reset(struct net_device *dev)
2748 {
2749 struct sky2_port *sky2 = netdev_priv(dev);
2750
2751 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2752 return -EINVAL;
2753
2754 sky2_phy_reinit(sky2);
2755
2756 return 0;
2757 }
2758
2759 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2760 {
2761 struct sky2_hw *hw = sky2->hw;
2762 unsigned port = sky2->port;
2763 int i;
2764
2765 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2766 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2767 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2768 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2769
2770 for (i = 2; i < count; i++)
2771 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2772 }
2773
2774 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2775 {
2776 struct sky2_port *sky2 = netdev_priv(netdev);
2777 sky2->msg_enable = value;
2778 }
2779
2780 static int sky2_get_stats_count(struct net_device *dev)
2781 {
2782 return ARRAY_SIZE(sky2_stats);
2783 }
2784
2785 static void sky2_get_ethtool_stats(struct net_device *dev,
2786 struct ethtool_stats *stats, u64 * data)
2787 {
2788 struct sky2_port *sky2 = netdev_priv(dev);
2789
2790 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2791 }
2792
2793 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2794 {
2795 int i;
2796
2797 switch (stringset) {
2798 case ETH_SS_STATS:
2799 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2800 memcpy(data + i * ETH_GSTRING_LEN,
2801 sky2_stats[i].name, ETH_GSTRING_LEN);
2802 break;
2803 }
2804 }
2805
2806 /* Use hardware MIB variables for critical path statistics and
2807 * transmit feedback not reported at interrupt.
2808 * Other errors are accounted for in interrupt handler.
2809 */
2810 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2811 {
2812 struct sky2_port *sky2 = netdev_priv(dev);
2813 u64 data[13];
2814
2815 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2816
2817 sky2->net_stats.tx_bytes = data[0];
2818 sky2->net_stats.rx_bytes = data[1];
2819 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2820 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2821 sky2->net_stats.multicast = data[3] + data[5];
2822 sky2->net_stats.collisions = data[10];
2823 sky2->net_stats.tx_aborted_errors = data[12];
2824
2825 return &sky2->net_stats;
2826 }
2827
2828 static int sky2_set_mac_address(struct net_device *dev, void *p)
2829 {
2830 struct sky2_port *sky2 = netdev_priv(dev);
2831 struct sky2_hw *hw = sky2->hw;
2832 unsigned port = sky2->port;
2833 const struct sockaddr *addr = p;
2834
2835 if (!is_valid_ether_addr(addr->sa_data))
2836 return -EADDRNOTAVAIL;
2837
2838 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2839 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2840 dev->dev_addr, ETH_ALEN);
2841 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2842 dev->dev_addr, ETH_ALEN);
2843
2844 /* virtual address for data */
2845 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2846
2847 /* physical address: used for pause frames */
2848 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2849
2850 return 0;
2851 }
2852
2853 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2854 {
2855 u32 bit;
2856
2857 bit = ether_crc(ETH_ALEN, addr) & 63;
2858 filter[bit >> 3] |= 1 << (bit & 7);
2859 }
2860
2861 static void sky2_set_multicast(struct net_device *dev)
2862 {
2863 struct sky2_port *sky2 = netdev_priv(dev);
2864 struct sky2_hw *hw = sky2->hw;
2865 unsigned port = sky2->port;
2866 struct dev_mc_list *list = dev->mc_list;
2867 u16 reg;
2868 u8 filter[8];
2869 int rx_pause;
2870 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2871
2872 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
2873 memset(filter, 0, sizeof(filter));
2874
2875 reg = gma_read16(hw, port, GM_RX_CTRL);
2876 reg |= GM_RXCR_UCF_ENA;
2877
2878 if (dev->flags & IFF_PROMISC) /* promiscuous */
2879 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2880 else if (dev->flags & IFF_ALLMULTI)
2881 memset(filter, 0xff, sizeof(filter));
2882 else if (dev->mc_count == 0 && !rx_pause)
2883 reg &= ~GM_RXCR_MCF_ENA;
2884 else {
2885 int i;
2886 reg |= GM_RXCR_MCF_ENA;
2887
2888 if (rx_pause)
2889 sky2_add_filter(filter, pause_mc_addr);
2890
2891 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2892 sky2_add_filter(filter, list->dmi_addr);
2893 }
2894
2895 gma_write16(hw, port, GM_MC_ADDR_H1,
2896 (u16) filter[0] | ((u16) filter[1] << 8));
2897 gma_write16(hw, port, GM_MC_ADDR_H2,
2898 (u16) filter[2] | ((u16) filter[3] << 8));
2899 gma_write16(hw, port, GM_MC_ADDR_H3,
2900 (u16) filter[4] | ((u16) filter[5] << 8));
2901 gma_write16(hw, port, GM_MC_ADDR_H4,
2902 (u16) filter[6] | ((u16) filter[7] << 8));
2903
2904 gma_write16(hw, port, GM_RX_CTRL, reg);
2905 }
2906
2907 /* Can have one global because blinking is controlled by
2908 * ethtool and that is always under RTNL mutex
2909 */
2910 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2911 {
2912 u16 pg;
2913
2914 switch (hw->chip_id) {
2915 case CHIP_ID_YUKON_XL:
2916 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2917 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2918 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2919 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2920 PHY_M_LEDC_INIT_CTRL(7) |
2921 PHY_M_LEDC_STA1_CTRL(7) |
2922 PHY_M_LEDC_STA0_CTRL(7))
2923 : 0);
2924
2925 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2926 break;
2927
2928 default:
2929 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2930 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2931 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2932 PHY_M_LED_MO_10(MO_LED_ON) |
2933 PHY_M_LED_MO_100(MO_LED_ON) |
2934 PHY_M_LED_MO_1000(MO_LED_ON) |
2935 PHY_M_LED_MO_RX(MO_LED_ON)
2936 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2937 PHY_M_LED_MO_10(MO_LED_OFF) |
2938 PHY_M_LED_MO_100(MO_LED_OFF) |
2939 PHY_M_LED_MO_1000(MO_LED_OFF) |
2940 PHY_M_LED_MO_RX(MO_LED_OFF));
2941
2942 }
2943 }
2944
2945 /* blink LED's for finding board */
2946 static int sky2_phys_id(struct net_device *dev, u32 data)
2947 {
2948 struct sky2_port *sky2 = netdev_priv(dev);
2949 struct sky2_hw *hw = sky2->hw;
2950 unsigned port = sky2->port;
2951 u16 ledctrl, ledover = 0;
2952 long ms;
2953 int interrupted;
2954 int onoff = 1;
2955
2956 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2957 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2958 else
2959 ms = data * 1000;
2960
2961 /* save initial values */
2962 spin_lock_bh(&sky2->phy_lock);
2963 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2964 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2965 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2966 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2967 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2968 } else {
2969 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2970 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2971 }
2972
2973 interrupted = 0;
2974 while (!interrupted && ms > 0) {
2975 sky2_led(hw, port, onoff);
2976 onoff = !onoff;
2977
2978 spin_unlock_bh(&sky2->phy_lock);
2979 interrupted = msleep_interruptible(250);
2980 spin_lock_bh(&sky2->phy_lock);
2981
2982 ms -= 250;
2983 }
2984
2985 /* resume regularly scheduled programming */
2986 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2987 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2988 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2989 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2990 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2991 } else {
2992 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2993 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2994 }
2995 spin_unlock_bh(&sky2->phy_lock);
2996
2997 return 0;
2998 }
2999
3000 static void sky2_get_pauseparam(struct net_device *dev,
3001 struct ethtool_pauseparam *ecmd)
3002 {
3003 struct sky2_port *sky2 = netdev_priv(dev);
3004
3005 switch (sky2->flow_mode) {
3006 case FC_NONE:
3007 ecmd->tx_pause = ecmd->rx_pause = 0;
3008 break;
3009 case FC_TX:
3010 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3011 break;
3012 case FC_RX:
3013 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3014 break;
3015 case FC_BOTH:
3016 ecmd->tx_pause = ecmd->rx_pause = 1;
3017 }
3018
3019 ecmd->autoneg = sky2->autoneg;
3020 }
3021
3022 static int sky2_set_pauseparam(struct net_device *dev,
3023 struct ethtool_pauseparam *ecmd)
3024 {
3025 struct sky2_port *sky2 = netdev_priv(dev);
3026
3027 sky2->autoneg = ecmd->autoneg;
3028 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3029
3030 if (netif_running(dev))
3031 sky2_phy_reinit(sky2);
3032
3033 return 0;
3034 }
3035
3036 static int sky2_get_coalesce(struct net_device *dev,
3037 struct ethtool_coalesce *ecmd)
3038 {
3039 struct sky2_port *sky2 = netdev_priv(dev);
3040 struct sky2_hw *hw = sky2->hw;
3041
3042 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3043 ecmd->tx_coalesce_usecs = 0;
3044 else {
3045 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3046 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3047 }
3048 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3049
3050 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3051 ecmd->rx_coalesce_usecs = 0;
3052 else {
3053 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3054 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3055 }
3056 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3057
3058 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3059 ecmd->rx_coalesce_usecs_irq = 0;
3060 else {
3061 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3062 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3063 }
3064
3065 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3066
3067 return 0;
3068 }
3069
3070 /* Note: this affect both ports */
3071 static int sky2_set_coalesce(struct net_device *dev,
3072 struct ethtool_coalesce *ecmd)
3073 {
3074 struct sky2_port *sky2 = netdev_priv(dev);
3075 struct sky2_hw *hw = sky2->hw;
3076 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3077
3078 if (ecmd->tx_coalesce_usecs > tmax ||
3079 ecmd->rx_coalesce_usecs > tmax ||
3080 ecmd->rx_coalesce_usecs_irq > tmax)
3081 return -EINVAL;
3082
3083 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3084 return -EINVAL;
3085 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3086 return -EINVAL;
3087 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3088 return -EINVAL;
3089
3090 if (ecmd->tx_coalesce_usecs == 0)
3091 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3092 else {
3093 sky2_write32(hw, STAT_TX_TIMER_INI,
3094 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3095 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3096 }
3097 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3098
3099 if (ecmd->rx_coalesce_usecs == 0)
3100 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3101 else {
3102 sky2_write32(hw, STAT_LEV_TIMER_INI,
3103 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3104 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3105 }
3106 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3107
3108 if (ecmd->rx_coalesce_usecs_irq == 0)
3109 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3110 else {
3111 sky2_write32(hw, STAT_ISR_TIMER_INI,
3112 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3113 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3114 }
3115 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3116 return 0;
3117 }
3118
3119 static void sky2_get_ringparam(struct net_device *dev,
3120 struct ethtool_ringparam *ering)
3121 {
3122 struct sky2_port *sky2 = netdev_priv(dev);
3123
3124 ering->rx_max_pending = RX_MAX_PENDING;
3125 ering->rx_mini_max_pending = 0;
3126 ering->rx_jumbo_max_pending = 0;
3127 ering->tx_max_pending = TX_RING_SIZE - 1;
3128
3129 ering->rx_pending = sky2->rx_pending;
3130 ering->rx_mini_pending = 0;
3131 ering->rx_jumbo_pending = 0;
3132 ering->tx_pending = sky2->tx_pending;
3133 }
3134
3135 static int sky2_set_ringparam(struct net_device *dev,
3136 struct ethtool_ringparam *ering)
3137 {
3138 struct sky2_port *sky2 = netdev_priv(dev);
3139 int err = 0;
3140
3141 if (ering->rx_pending > RX_MAX_PENDING ||
3142 ering->rx_pending < 8 ||
3143 ering->tx_pending < MAX_SKB_TX_LE ||
3144 ering->tx_pending > TX_RING_SIZE - 1)
3145 return -EINVAL;
3146
3147 if (netif_running(dev))
3148 sky2_down(dev);
3149
3150 sky2->rx_pending = ering->rx_pending;
3151 sky2->tx_pending = ering->tx_pending;
3152
3153 if (netif_running(dev)) {
3154 err = sky2_up(dev);
3155 if (err)
3156 dev_close(dev);
3157 else
3158 sky2_set_multicast(dev);
3159 }
3160
3161 return err;
3162 }
3163
3164 static int sky2_get_regs_len(struct net_device *dev)
3165 {
3166 return 0x4000;
3167 }
3168
3169 /*
3170 * Returns copy of control register region
3171 * Note: access to the RAM address register set will cause timeouts.
3172 */
3173 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3174 void *p)
3175 {
3176 const struct sky2_port *sky2 = netdev_priv(dev);
3177 const void __iomem *io = sky2->hw->regs;
3178
3179 BUG_ON(regs->len < B3_RI_WTO_R1);
3180 regs->version = 1;
3181 memset(p, 0, regs->len);
3182
3183 memcpy_fromio(p, io, B3_RAM_ADDR);
3184
3185 memcpy_fromio(p + B3_RI_WTO_R1,
3186 io + B3_RI_WTO_R1,
3187 regs->len - B3_RI_WTO_R1);
3188 }
3189
3190 static const struct ethtool_ops sky2_ethtool_ops = {
3191 .get_settings = sky2_get_settings,
3192 .set_settings = sky2_set_settings,
3193 .get_drvinfo = sky2_get_drvinfo,
3194 .get_msglevel = sky2_get_msglevel,
3195 .set_msglevel = sky2_set_msglevel,
3196 .nway_reset = sky2_nway_reset,
3197 .get_regs_len = sky2_get_regs_len,
3198 .get_regs = sky2_get_regs,
3199 .get_link = ethtool_op_get_link,
3200 .get_sg = ethtool_op_get_sg,
3201 .set_sg = ethtool_op_set_sg,
3202 .get_tx_csum = ethtool_op_get_tx_csum,
3203 .set_tx_csum = ethtool_op_set_tx_csum,
3204 .get_tso = ethtool_op_get_tso,
3205 .set_tso = ethtool_op_set_tso,
3206 .get_rx_csum = sky2_get_rx_csum,
3207 .set_rx_csum = sky2_set_rx_csum,
3208 .get_strings = sky2_get_strings,
3209 .get_coalesce = sky2_get_coalesce,
3210 .set_coalesce = sky2_set_coalesce,
3211 .get_ringparam = sky2_get_ringparam,
3212 .set_ringparam = sky2_set_ringparam,
3213 .get_pauseparam = sky2_get_pauseparam,
3214 .set_pauseparam = sky2_set_pauseparam,
3215 .phys_id = sky2_phys_id,
3216 .get_stats_count = sky2_get_stats_count,
3217 .get_ethtool_stats = sky2_get_ethtool_stats,
3218 .get_perm_addr = ethtool_op_get_perm_addr,
3219 };
3220
3221 /* Initialize network device */
3222 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3223 unsigned port, int highmem)
3224 {
3225 struct sky2_port *sky2;
3226 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3227
3228 if (!dev) {
3229 printk(KERN_ERR "sky2 etherdev alloc failed");
3230 return NULL;
3231 }
3232
3233 SET_MODULE_OWNER(dev);
3234 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3235 dev->irq = hw->pdev->irq;
3236 dev->open = sky2_up;
3237 dev->stop = sky2_down;
3238 dev->do_ioctl = sky2_ioctl;
3239 dev->hard_start_xmit = sky2_xmit_frame;
3240 dev->get_stats = sky2_get_stats;
3241 dev->set_multicast_list = sky2_set_multicast;
3242 dev->set_mac_address = sky2_set_mac_address;
3243 dev->change_mtu = sky2_change_mtu;
3244 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3245 dev->tx_timeout = sky2_tx_timeout;
3246 dev->watchdog_timeo = TX_WATCHDOG;
3247 if (port == 0)
3248 dev->poll = sky2_poll;
3249 dev->weight = NAPI_WEIGHT;
3250 #ifdef CONFIG_NET_POLL_CONTROLLER
3251 dev->poll_controller = sky2_netpoll;
3252 #endif
3253
3254 sky2 = netdev_priv(dev);
3255 sky2->netdev = dev;
3256 sky2->hw = hw;
3257 sky2->msg_enable = netif_msg_init(debug, default_msg);
3258
3259 /* Auto speed and flow control */
3260 sky2->autoneg = AUTONEG_ENABLE;
3261 sky2->flow_mode = FC_BOTH;
3262
3263 sky2->duplex = -1;
3264 sky2->speed = -1;
3265 sky2->advertising = sky2_supported_modes(hw);
3266 sky2->rx_csum = 1;
3267
3268 spin_lock_init(&sky2->phy_lock);
3269 sky2->tx_pending = TX_DEF_PENDING;
3270 sky2->rx_pending = RX_DEF_PENDING;
3271
3272 hw->dev[port] = dev;
3273
3274 sky2->port = port;
3275
3276 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3277 dev->features |= NETIF_F_TSO;
3278 if (highmem)
3279 dev->features |= NETIF_F_HIGHDMA;
3280 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3281
3282 #ifdef SKY2_VLAN_TAG_USED
3283 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3284 dev->vlan_rx_register = sky2_vlan_rx_register;
3285 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3286 #endif
3287
3288 /* read the mac address */
3289 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3290 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3291
3292 /* device is off until link detection */
3293 netif_carrier_off(dev);
3294 netif_stop_queue(dev);
3295
3296 return dev;
3297 }
3298
3299 static void __devinit sky2_show_addr(struct net_device *dev)
3300 {
3301 const struct sky2_port *sky2 = netdev_priv(dev);
3302
3303 if (netif_msg_probe(sky2))
3304 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3305 dev->name,
3306 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3307 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3308 }
3309
3310 /* Handle software interrupt used during MSI test */
3311 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3312 {
3313 struct sky2_hw *hw = dev_id;
3314 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3315
3316 if (status == 0)
3317 return IRQ_NONE;
3318
3319 if (status & Y2_IS_IRQ_SW) {
3320 hw->msi_detected = 1;
3321 wake_up(&hw->msi_wait);
3322 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3323 }
3324 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3325
3326 return IRQ_HANDLED;
3327 }
3328
3329 /* Test interrupt path by forcing a a software IRQ */
3330 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3331 {
3332 struct pci_dev *pdev = hw->pdev;
3333 int err;
3334
3335 init_waitqueue_head (&hw->msi_wait);
3336
3337 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3338
3339 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
3340 if (err) {
3341 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3342 pci_name(pdev), pdev->irq);
3343 return err;
3344 }
3345
3346 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3347 sky2_read8(hw, B0_CTST);
3348
3349 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3350
3351 if (!hw->msi_detected) {
3352 /* MSI test failed, go back to INTx mode */
3353 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3354 "switching to INTx mode.\n",
3355 pci_name(pdev));
3356
3357 err = -EOPNOTSUPP;
3358 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3359 }
3360
3361 sky2_write32(hw, B0_IMSK, 0);
3362 sky2_read32(hw, B0_IMSK);
3363
3364 free_irq(pdev->irq, hw);
3365
3366 return err;
3367 }
3368
3369 static int __devinit sky2_probe(struct pci_dev *pdev,
3370 const struct pci_device_id *ent)
3371 {
3372 struct net_device *dev, *dev1 = NULL;
3373 struct sky2_hw *hw;
3374 int err, pm_cap, using_dac = 0;
3375
3376 err = pci_enable_device(pdev);
3377 if (err) {
3378 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3379 pci_name(pdev));
3380 goto err_out;
3381 }
3382
3383 err = pci_request_regions(pdev, DRV_NAME);
3384 if (err) {
3385 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3386 pci_name(pdev));
3387 goto err_out;
3388 }
3389
3390 pci_set_master(pdev);
3391
3392 /* Find power-management capability. */
3393 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3394 if (pm_cap == 0) {
3395 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3396 "aborting.\n");
3397 err = -EIO;
3398 goto err_out_free_regions;
3399 }
3400
3401 if (sizeof(dma_addr_t) > sizeof(u32) &&
3402 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3403 using_dac = 1;
3404 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3405 if (err < 0) {
3406 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3407 "for consistent allocations\n", pci_name(pdev));
3408 goto err_out_free_regions;
3409 }
3410
3411 } else {
3412 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3413 if (err) {
3414 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3415 pci_name(pdev));
3416 goto err_out_free_regions;
3417 }
3418 }
3419
3420 err = -ENOMEM;
3421 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3422 if (!hw) {
3423 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3424 pci_name(pdev));
3425 goto err_out_free_regions;
3426 }
3427
3428 hw->pdev = pdev;
3429
3430 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3431 if (!hw->regs) {
3432 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3433 pci_name(pdev));
3434 goto err_out_free_hw;
3435 }
3436 hw->pm_cap = pm_cap;
3437
3438 #ifdef __BIG_ENDIAN
3439 /* The sk98lin vendor driver uses hardware byte swapping but
3440 * this driver uses software swapping.
3441 */
3442 {
3443 u32 reg;
3444 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3445 reg &= ~PCI_REV_DESC;
3446 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3447 }
3448 #endif
3449
3450 /* ring for status responses */
3451 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3452 &hw->st_dma);
3453 if (!hw->st_le)
3454 goto err_out_iounmap;
3455
3456 err = sky2_reset(hw);
3457 if (err)
3458 goto err_out_iounmap;
3459
3460 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3461 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3462 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3463 hw->chip_id, hw->chip_rev);
3464
3465 dev = sky2_init_netdev(hw, 0, using_dac);
3466 if (!dev)
3467 goto err_out_free_pci;
3468
3469 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3470 err = sky2_test_msi(hw);
3471 if (err == -EOPNOTSUPP)
3472 pci_disable_msi(pdev);
3473 else if (err)
3474 goto err_out_free_netdev;
3475 }
3476
3477 err = register_netdev(dev);
3478 if (err) {
3479 printk(KERN_ERR PFX "%s: cannot register net device\n",
3480 pci_name(pdev));
3481 goto err_out_free_netdev;
3482 }
3483
3484 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, dev->name, hw);
3485 if (err) {
3486 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3487 pci_name(pdev), pdev->irq);
3488 goto err_out_unregister;
3489 }
3490 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3491
3492 sky2_show_addr(dev);
3493
3494 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3495 if (register_netdev(dev1) == 0)
3496 sky2_show_addr(dev1);
3497 else {
3498 /* Failure to register second port need not be fatal */
3499 printk(KERN_WARNING PFX
3500 "register of second port failed\n");
3501 hw->dev[1] = NULL;
3502 free_netdev(dev1);
3503 }
3504 }
3505
3506 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3507 sky2_idle_start(hw);
3508
3509 pci_set_drvdata(pdev, hw);
3510
3511 return 0;
3512
3513 err_out_unregister:
3514 pci_disable_msi(pdev);
3515 unregister_netdev(dev);
3516 err_out_free_netdev:
3517 free_netdev(dev);
3518 err_out_free_pci:
3519 sky2_write8(hw, B0_CTST, CS_RST_SET);
3520 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3521 err_out_iounmap:
3522 iounmap(hw->regs);
3523 err_out_free_hw:
3524 kfree(hw);
3525 err_out_free_regions:
3526 pci_release_regions(pdev);
3527 pci_disable_device(pdev);
3528 err_out:
3529 return err;
3530 }
3531
3532 static void __devexit sky2_remove(struct pci_dev *pdev)
3533 {
3534 struct sky2_hw *hw = pci_get_drvdata(pdev);
3535 struct net_device *dev0, *dev1;
3536
3537 if (!hw)
3538 return;
3539
3540 del_timer_sync(&hw->idle_timer);
3541
3542 sky2_write32(hw, B0_IMSK, 0);
3543 synchronize_irq(hw->pdev->irq);
3544
3545 dev0 = hw->dev[0];
3546 dev1 = hw->dev[1];
3547 if (dev1)
3548 unregister_netdev(dev1);
3549 unregister_netdev(dev0);
3550
3551 sky2_set_power_state(hw, PCI_D3hot);
3552 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3553 sky2_write8(hw, B0_CTST, CS_RST_SET);
3554 sky2_read8(hw, B0_CTST);
3555
3556 free_irq(pdev->irq, hw);
3557 pci_disable_msi(pdev);
3558 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3559 pci_release_regions(pdev);
3560 pci_disable_device(pdev);
3561
3562 if (dev1)
3563 free_netdev(dev1);
3564 free_netdev(dev0);
3565 iounmap(hw->regs);
3566 kfree(hw);
3567
3568 pci_set_drvdata(pdev, NULL);
3569 }
3570
3571 #ifdef CONFIG_PM
3572 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3573 {
3574 struct sky2_hw *hw = pci_get_drvdata(pdev);
3575 int i;
3576 pci_power_t pstate = pci_choose_state(pdev, state);
3577
3578 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3579 return -EINVAL;
3580
3581 del_timer_sync(&hw->idle_timer);
3582 netif_poll_disable(hw->dev[0]);
3583
3584 for (i = 0; i < hw->ports; i++) {
3585 struct net_device *dev = hw->dev[i];
3586
3587 if (netif_running(dev)) {
3588 sky2_down(dev);
3589 netif_device_detach(dev);
3590 }
3591 }
3592
3593 sky2_write32(hw, B0_IMSK, 0);
3594 pci_save_state(pdev);
3595 sky2_set_power_state(hw, pstate);
3596 return 0;
3597 }
3598
3599 static int sky2_resume(struct pci_dev *pdev)
3600 {
3601 struct sky2_hw *hw = pci_get_drvdata(pdev);
3602 int i, err;
3603
3604 pci_restore_state(pdev);
3605 pci_enable_wake(pdev, PCI_D0, 0);
3606 sky2_set_power_state(hw, PCI_D0);
3607
3608 err = sky2_reset(hw);
3609 if (err)
3610 goto out;
3611
3612 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3613
3614 for (i = 0; i < hw->ports; i++) {
3615 struct net_device *dev = hw->dev[i];
3616 if (netif_running(dev)) {
3617 netif_device_attach(dev);
3618
3619 err = sky2_up(dev);
3620 if (err) {
3621 printk(KERN_ERR PFX "%s: could not up: %d\n",
3622 dev->name, err);
3623 dev_close(dev);
3624 goto out;
3625 }
3626 }
3627 }
3628
3629 netif_poll_enable(hw->dev[0]);
3630 sky2_idle_start(hw);
3631 out:
3632 return err;
3633 }
3634 #endif
3635
3636 static struct pci_driver sky2_driver = {
3637 .name = DRV_NAME,
3638 .id_table = sky2_id_table,
3639 .probe = sky2_probe,
3640 .remove = __devexit_p(sky2_remove),
3641 #ifdef CONFIG_PM
3642 .suspend = sky2_suspend,
3643 .resume = sky2_resume,
3644 #endif
3645 };
3646
3647 static int __init sky2_init_module(void)
3648 {
3649 return pci_register_driver(&sky2_driver);
3650 }
3651
3652 static void __exit sky2_cleanup_module(void)
3653 {
3654 pci_unregister_driver(&sky2_driver);
3655 }
3656
3657 module_init(sky2_init_module);
3658 module_exit(sky2_cleanup_module);
3659
3660 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3661 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3662 MODULE_LICENSE("GPL");
3663 MODULE_VERSION(DRV_VERSION);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree