drivers/gpu/drm/nouveau/nouveau_channel.c

   1 /*
   2  * Copyright 2005-2006 Stephane Marchesin
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "drmP.h"
  26 #include "drm.h"
  27 #include "nouveau_drv.h"
  28 #include "nouveau_drm.h"
  29 #include "nouveau_dma.h"
  30 #include "nouveau_ramht.h"
  31
  32 static int
  33 nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
  34 {
  35         u32 mem = nouveau_vram_pushbuf ? TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT;
  36         struct drm_device *dev = chan->dev;
  37         struct drm_nouveau_private *dev_priv = dev->dev_private;
  38         int ret;
  39
  40         /* allocate buffer object */
  41         ret = nouveau_bo_new(dev, NULL, 65536, 0, mem, 0, 0, &chan->pushbuf_bo);
  42         if (ret)
  43                 goto out;
  44
  45         ret = nouveau_bo_pin(chan->pushbuf_bo, mem);
  46         if (ret)
  47                 goto out;
  48
  49         ret = nouveau_bo_map(chan->pushbuf_bo);
  50         if (ret)
  51                 goto out;
  52
  53         /* create DMA object covering the entire memtype where the push
  54          * buffer resides, userspace can submit its own push buffers from
  55          * anywhere within the same memtype.
  56          */
  57         chan->pushbuf_base = chan->pushbuf_bo->bo.offset;
  58         if (dev_priv->card_type >= NV_50) {
  59                 if (dev_priv->card_type < NV_C0) {
  60                         ret = nouveau_gpuobj_dma_new(chan,
  61                                                      NV_CLASS_DMA_IN_MEMORY, 0,
  62                                                      (1ULL << 40),
  63                                                      NV_MEM_ACCESS_RO,
  64                                                      NV_MEM_TARGET_VM,
  65                                                      &chan->pushbuf);
  66                 }
  67                 chan->pushbuf_base = chan->pushbuf_bo->vma.offset;
  68         } else
  69         if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) {
  70                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
  71                                              dev_priv->gart_info.aper_size,
  72                                              NV_MEM_ACCESS_RO,
  73                                              NV_MEM_TARGET_GART,
  74                                              &chan->pushbuf);
  75         } else
  76         if (dev_priv->card_type != NV_04) {
  77                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
  78                                              dev_priv->fb_available_size,
  79                                              NV_MEM_ACCESS_RO,
  80                                              NV_MEM_TARGET_VRAM,
  81                                              &chan->pushbuf);
  82         } else {
  83                 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
  84                  * exact reason for existing :)  PCI access to cmdbuf in
  85                  * VRAM.
  86                  */
  87                 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
  88                                              pci_resource_start(dev->pdev, 1),
  89                                              dev_priv->fb_available_size,
  90                                              NV_MEM_ACCESS_RO,
  91                                              NV_MEM_TARGET_PCI,
  92                                              &chan->pushbuf);
  93         }
  94
  95 out:
  96         if (ret) {
  97                 NV_ERROR(dev, "error initialising pushbuf: %d\n", ret);
  98                 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
  99                 if (chan->pushbuf_bo) {
 100                         nouveau_bo_unmap(chan->pushbuf_bo);
 101                         nouveau_bo_ref(NULL, &chan->pushbuf_bo);
 102                 }
 103         }
 104
 105         return 0;
 106 }
 107
 108 /* allocates and initializes a fifo for user space consumption */
 109 int
 110 nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
 111                       struct drm_file *file_priv,
 112                       uint32_t vram_handle, uint32_t gart_handle)
 113 {
 114         struct drm_nouveau_private *dev_priv = dev->dev_private;
 115         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 116         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
 117         struct nouveau_channel *chan;
 118         unsigned long flags;
 119         int ret;
 120
 121         /* allocate and lock channel structure */
 122         chan = kzalloc(sizeof(*chan), GFP_KERNEL);
 123         if (!chan)
 124                 return -ENOMEM;
 125         chan->dev = dev;
 126         chan->file_priv = file_priv;
 127         chan->vram_handle = vram_handle;
 128         chan->gart_handle = gart_handle;
 129
 130         kref_init(&chan->ref);
 131         atomic_set(&chan->users, 1);
 132         mutex_init(&chan->mutex);
 133         mutex_lock(&chan->mutex);
 134
 135         /* allocate hw channel id */
 136         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 137         for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
 138                 if (!dev_priv->channels.ptr[chan->id]) {
 139                         nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
 140                         break;
 141                 }
 142         }
 143         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 144
 145         if (chan->id == pfifo->channels) {
 146                 mutex_unlock(&chan->mutex);
 147                 kfree(chan);
 148                 return -ENODEV;
 149         }
 150
 151         NV_DEBUG(dev, "initialising channel %d\n", chan->id);
 152         INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
 153         INIT_LIST_HEAD(&chan->nvsw.flip);
 154         INIT_LIST_HEAD(&chan->fence.pending);
 155
 156         /* setup channel's memory and vm */
 157         ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
 158         if (ret) {
 159                 NV_ERROR(dev, "gpuobj %d\n", ret);
 160                 nouveau_channel_put(&chan);
 161                 return ret;
 162         }
 163
 164         /* Allocate space for per-channel fixed notifier memory */
 165         ret = nouveau_notifier_init_channel(chan);
 166         if (ret) {
 167                 NV_ERROR(dev, "ntfy %d\n", ret);
 168                 nouveau_channel_put(&chan);
 169                 return ret;
 170         }
 171
 172         /* Allocate DMA push buffer */
 173         ret = nouveau_channel_pushbuf_init(chan);
 174         if (ret) {
 175                 NV_ERROR(dev, "pushbuf %d\n", ret);
 176                 nouveau_channel_put(&chan);
 177                 return ret;
 178         }
 179
 180         nouveau_dma_pre_init(chan);
 181         chan->user_put = 0x40;
 182         chan->user_get = 0x44;
 183
 184         /* disable the fifo caches */
 185         pfifo->reassign(dev, false);
 186
 187         /* Construct initial RAMFC for new channel */
 188         ret = pfifo->create_context(chan);
 189         if (ret) {
 190                 nouveau_channel_put(&chan);
 191                 return ret;
 192         }
 193
 194         pfifo->reassign(dev, true);
 195
 196         ret = nouveau_dma_init(chan);
 197         if (!ret)
 198                 ret = nouveau_fence_channel_init(chan);
 199         if (ret) {
 200                 nouveau_channel_put(&chan);
 201                 return ret;
 202         }
 203
 204         nouveau_debugfs_channel_init(chan);
 205
 206         NV_DEBUG(dev, "channel %d initialised\n", chan->id);
 207         if (fpriv) {
 208                 spin_lock(&fpriv->lock);
 209                 list_add(&chan->list, &fpriv->channels);
 210                 spin_unlock(&fpriv->lock);
 211         }
 212         *chan_ret = chan;
 213         return 0;
 214 }
 215
 216 struct nouveau_channel *
 217 nouveau_channel_get_unlocked(struct nouveau_channel *ref)
 218 {
 219         struct nouveau_channel *chan = NULL;
 220
 221         if (likely(ref && atomic_inc_not_zero(&ref->users)))
 222                 nouveau_channel_ref(ref, &chan);
 223
 224         return chan;
 225 }
 226
 227 struct nouveau_channel *
 228 nouveau_channel_get(struct drm_file *file_priv, int id)
 229 {
 230         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
 231         struct nouveau_channel *chan;
 232
 233         spin_lock(&fpriv->lock);
 234         list_for_each_entry(chan, &fpriv->channels, list) {
 235                 if (chan->id == id) {
 236                         chan = nouveau_channel_get_unlocked(chan);
 237                         spin_unlock(&fpriv->lock);
 238                         mutex_lock(&chan->mutex);
 239                         return chan;
 240                 }
 241         }
 242         spin_unlock(&fpriv->lock);
 243
 244         return ERR_PTR(-EINVAL);
 245 }
 246
 247 void
 248 nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
 249 {
 250         struct nouveau_channel *chan = *pchan;
 251         struct drm_device *dev = chan->dev;
 252         struct drm_nouveau_private *dev_priv = dev->dev_private;
 253         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
 254         unsigned long flags;
 255         int i;
 256
 257         /* decrement the refcount, and we're done if there's still refs */
 258         if (likely(!atomic_dec_and_test(&chan->users))) {
 259                 nouveau_channel_ref(NULL, pchan);
 260                 return;
 261         }
 262
 263         /* no one wants the channel anymore */
 264         NV_DEBUG(dev, "freeing channel %d\n", chan->id);
 265         nouveau_debugfs_channel_fini(chan);
 266
 267         /* give it chance to idle */
 268         nouveau_channel_idle(chan);
 269
 270         /* ensure all outstanding fences are signaled.  they should be if the
 271          * above attempts at idling were OK, but if we failed this'll tell TTM
 272          * we're done with the buffers.
 273          */
 274         nouveau_fence_channel_fini(chan);
 275
 276         /* boot it off the hardware */
 277         pfifo->reassign(dev, false);
 278
 279         /* destroy the engine specific contexts */
 280         pfifo->destroy_context(chan);
 281         for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
 282                 if (chan->engctx[i])
 283                         dev_priv->eng[i]->context_del(chan, i);
 284         }
 285
 286         pfifo->reassign(dev, true);
 287
 288         /* aside from its resources, the channel should now be dead,
 289          * remove it from the channel list
 290          */
 291         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 292         nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
 293         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 294
 295         /* destroy any resources the channel owned */
 296         nouveau_gpuobj_ref(NULL, &chan->pushbuf);
 297         if (chan->pushbuf_bo) {
 298                 nouveau_bo_unmap(chan->pushbuf_bo);
 299                 nouveau_bo_unpin(chan->pushbuf_bo);
 300                 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
 301         }
 302         nouveau_ramht_ref(NULL, &chan->ramht, chan);
 303         nouveau_notifier_takedown_channel(chan);
 304         nouveau_gpuobj_channel_takedown(chan);
 305
 306         nouveau_channel_ref(NULL, pchan);
 307 }
 308
 309 void
 310 nouveau_channel_put(struct nouveau_channel **pchan)
 311 {
 312         mutex_unlock(&(*pchan)->mutex);
 313         nouveau_channel_put_unlocked(pchan);
 314 }
 315
 316 static void
 317 nouveau_channel_del(struct kref *ref)
 318 {
 319         struct nouveau_channel *chan =
 320                 container_of(ref, struct nouveau_channel, ref);
 321
 322         kfree(chan);
 323 }
 324
 325 void
 326 nouveau_channel_ref(struct nouveau_channel *chan,
 327                     struct nouveau_channel **pchan)
 328 {
 329         if (chan)
 330                 kref_get(&chan->ref);
 331
 332         if (*pchan)
 333                 kref_put(&(*pchan)->ref, nouveau_channel_del);
 334
 335         *pchan = chan;
 336 }
 337
 338 void
 339 nouveau_channel_idle(struct nouveau_channel *chan)
 340 {
 341         struct drm_device *dev = chan->dev;
 342         struct nouveau_fence *fence = NULL;
 343         int ret;
 344
 345         nouveau_fence_update(chan);
 346
 347         if (chan->fence.sequence != chan->fence.sequence_ack) {
 348                 ret = nouveau_fence_new(chan, &fence, true);
 349                 if (!ret) {
 350                         ret = nouveau_fence_wait(fence, false, false);
 351                         nouveau_fence_unref(&fence);
 352                 }
 353
 354                 if (ret)
 355                         NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
 356         }
 357 }
 358
 359 /* cleans up all the fifos from file_priv */
 360 void
 361 nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
 362 {
 363         struct drm_nouveau_private *dev_priv = dev->dev_private;
 364         struct nouveau_engine *engine = &dev_priv->engine;
 365         struct nouveau_channel *chan;
 366         int i;
 367
 368         NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
 369         for (i = 0; i < engine->fifo.channels; i++) {
 370                 chan = nouveau_channel_get(file_priv, i);
 371                 if (IS_ERR(chan))
 372                         continue;
 373
 374                 list_del(&chan->list);
 375                 atomic_dec(&chan->users);
 376                 nouveau_channel_put(&chan);
 377         }
 378 }
 379
 380
 381 /***********************************
 382  * ioctls wrapping the functions
 383  ***********************************/
 384
 385 static int
 386 nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
 387                          struct drm_file *file_priv)
 388 {
 389         struct drm_nouveau_private *dev_priv = dev->dev_private;
 390         struct drm_nouveau_channel_alloc *init = data;
 391         struct nouveau_channel *chan;
 392         int ret;
 393
 394         if (!dev_priv->eng[NVOBJ_ENGINE_GR])
 395                 return -ENODEV;
 396
 397         if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
 398                 return -EINVAL;
 399
 400         ret = nouveau_channel_alloc(dev, &chan, file_priv,
 401                                     init->fb_ctxdma_handle,
 402                                     init->tt_ctxdma_handle);
 403         if (ret)
 404                 return ret;
 405         init->channel  = chan->id;
 406
 407         if (chan->dma.ib_max)
 408                 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
 409                                         NOUVEAU_GEM_DOMAIN_GART;
 410         else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
 411                 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
 412         else
 413                 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
 414
 415         if (dev_priv->card_type < NV_C0) {
 416                 init->subchan[0].handle = NvM2MF;
 417                 if (dev_priv->card_type < NV_50)
 418                         init->subchan[0].grclass = 0x0039;
 419                 else
 420                         init->subchan[0].grclass = 0x5039;
 421                 init->subchan[1].handle = NvSw;
 422                 init->subchan[1].grclass = NV_SW;
 423                 init->nr_subchan = 2;
 424         } else {
 425                 init->subchan[0].handle  = 0x9039;
 426                 init->subchan[0].grclass = 0x9039;
 427                 init->nr_subchan = 1;
 428         }
 429
 430         /* Named memory object area */
 431         ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
 432                                     &init->notifier_handle);
 433
 434         if (ret == 0)
 435                 atomic_inc(&chan->users); /* userspace reference */
 436         nouveau_channel_put(&chan);
 437         return ret;
 438 }
 439
 440 static int
 441 nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
 442                         struct drm_file *file_priv)
 443 {
 444         struct drm_nouveau_channel_free *req = data;
 445         struct nouveau_channel *chan;
 446
 447         chan = nouveau_channel_get(file_priv, req->channel);
 448         if (IS_ERR(chan))
 449                 return PTR_ERR(chan);
 450
 451         list_del(&chan->list);
 452         atomic_dec(&chan->users);
 453         nouveau_channel_put(&chan);
 454         return 0;
 455 }
 456
 457 /***********************************
 458  * finally, the ioctl table
 459  ***********************************/
 460
 461 struct drm_ioctl_desc nouveau_ioctls[] = {
 462         DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
 463         DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 464         DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
 465         DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
 466         DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
 467         DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
 468         DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
 469         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
 470         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
 471         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
 472         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
 473         DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
 474 };
 475
 476 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);