1 // include/asm-arm/mach-omap/usb.h
3 #ifndef __ASM_ARCH_OMAP_USB_H
4 #define __ASM_ARCH_OMAP_USB_H
6 #include <linux/usb/musb.h>
7 #include <plat/board.h>
9 #define OMAP3_HS_USB_PORTS 3
11 enum usbhs_omap_port_mode
{
12 OMAP_USBHS_PORT_MODE_UNUSED
,
13 OMAP_EHCI_PORT_MODE_PHY
,
14 OMAP_EHCI_PORT_MODE_TLL
,
15 OMAP_EHCI_PORT_MODE_HSIC
,
16 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0
,
17 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM
,
18 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0
,
19 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM
,
20 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0
,
21 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM
,
22 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0
,
23 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM
,
24 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0
,
25 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
28 struct usbhs_omap_board_data
{
29 enum usbhs_omap_port_mode port_mode
[OMAP3_HS_USB_PORTS
];
31 /* have to be valid if phy_reset is true and portx is in phy mode */
32 int reset_gpio_port
[OMAP3_HS_USB_PORTS
];
34 /* Set this to true for ES2.x silicon */
35 unsigned es2_compatibility
:1;
40 * Regulators for USB PHYs.
41 * Each PHY can have a separate regulator.
43 struct regulator
*regulator
[OMAP3_HS_USB_PORTS
];
46 struct ehci_hcd_omap_platform_data
{
47 enum usbhs_omap_port_mode port_mode
[OMAP3_HS_USB_PORTS
];
48 int reset_gpio_port
[OMAP3_HS_USB_PORTS
];
49 struct regulator
*regulator
[OMAP3_HS_USB_PORTS
];
53 struct ohci_hcd_omap_platform_data
{
54 enum usbhs_omap_port_mode port_mode
[OMAP3_HS_USB_PORTS
];
55 unsigned es2_compatibility
:1;
58 struct usbhs_omap_platform_data
{
59 enum usbhs_omap_port_mode port_mode
[OMAP3_HS_USB_PORTS
];
61 struct ehci_hcd_omap_platform_data
*ehci_data
;
62 struct ohci_hcd_omap_platform_data
*ohci_data
;
64 /*-------------------------------------------------------------------------*/
66 #define OMAP1_OTG_BASE 0xfffb0400
67 #define OMAP1_UDC_BASE 0xfffb4000
68 #define OMAP1_OHCI_BASE 0xfffba000
70 #define OMAP2_OHCI_BASE 0x4805e000
71 #define OMAP2_UDC_BASE 0x4805e200
72 #define OMAP2_OTG_BASE 0x4805e300
74 #ifdef CONFIG_ARCH_OMAP1
76 #define OTG_BASE OMAP1_OTG_BASE
77 #define UDC_BASE OMAP1_UDC_BASE
78 #define OMAP_OHCI_BASE OMAP1_OHCI_BASE
82 #define OTG_BASE OMAP2_OTG_BASE
83 #define UDC_BASE OMAP2_UDC_BASE
84 #define OMAP_OHCI_BASE OMAP2_OHCI_BASE
86 struct omap_musb_board_data
{
91 void (*set_phy_power
)(u8 on
);
92 void (*clear_irq
)(void);
93 void (*set_mode
)(u8 mode
);
97 enum musb_interface
{MUSB_INTERFACE_ULPI
, MUSB_INTERFACE_UTMI
};
99 extern void usb_musb_init(struct omap_musb_board_data
*board_data
);
101 extern void usb_ehci_init(const struct usbhs_omap_board_data
*pdata
);
103 extern void usb_ohci_init(const struct usbhs_omap_board_data
*pdata
);
105 extern int omap_usbhs_enable(struct device
*dev
);
106 extern void omap_usbhs_disable(struct device
*dev
);
108 extern int omap4430_phy_power(struct device
*dev
, int ID
, int on
);
109 extern int omap4430_phy_set_clk(struct device
*dev
, int on
);
110 extern int omap4430_phy_init(struct device
*dev
);
111 extern int omap4430_phy_exit(struct device
*dev
);
112 extern int omap4430_phy_suspend(struct device
*dev
, int suspend
);
116 * FIXME correct answer depends on hmc_mode,
117 * as does (on omap1) any nonzero value for config->otg port number
119 #ifdef CONFIG_USB_GADGET_OMAP
120 #define is_usb0_device(config) 1
122 #define is_usb0_device(config) 0
125 void omap_otg_init(struct omap_usb_config
*config
);
127 #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
128 void omap1_usb_init(struct omap_usb_config
*pdata
);
130 static inline void omap1_usb_init(struct omap_usb_config
*pdata
)
135 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
136 void omap2_usbfs_init(struct omap_usb_config
*pdata
);
138 static inline void omap2_usbfs_init(struct omap_usb_config
*pdata
)
143 /*-------------------------------------------------------------------------*/
146 * OTG and transceiver registers, for OMAPs starting with ARM926
148 #define OTG_REV (OTG_BASE + 0x00)
149 #define OTG_SYSCON_1 (OTG_BASE + 0x04)
150 # define USB2_TRX_MODE(w) (((w)>>24)&0x07)
151 # define USB1_TRX_MODE(w) (((w)>>20)&0x07)
152 # define USB0_TRX_MODE(w) (((w)>>16)&0x07)
153 # define OTG_IDLE_EN (1 << 15)
154 # define HST_IDLE_EN (1 << 14)
155 # define DEV_IDLE_EN (1 << 13)
156 # define OTG_RESET_DONE (1 << 2)
157 # define OTG_SOFT_RESET (1 << 1)
158 #define OTG_SYSCON_2 (OTG_BASE + 0x08)
159 # define OTG_EN (1 << 31)
160 # define USBX_SYNCHRO (1 << 30)
161 # define OTG_MST16 (1 << 29)
162 # define SRP_GPDATA (1 << 28)
163 # define SRP_GPDVBUS (1 << 27)
164 # define SRP_GPUVBUS(w) (((w)>>24)&0x07)
165 # define A_WAIT_VRISE(w) (((w)>>20)&0x07)
166 # define B_ASE_BRST(w) (((w)>>16)&0x07)
167 # define SRP_DPW (1 << 14)
168 # define SRP_DATA (1 << 13)
169 # define SRP_VBUS (1 << 12)
170 # define OTG_PADEN (1 << 10)
171 # define HMC_PADEN (1 << 9)
172 # define UHOST_EN (1 << 8)
173 # define HMC_TLLSPEED (1 << 7)
174 # define HMC_TLLATTACH (1 << 6)
175 # define OTG_HMC(w) (((w)>>0)&0x3f)
176 #define OTG_CTRL (OTG_BASE + 0x0c)
177 # define OTG_USB2_EN (1 << 29)
178 # define OTG_USB2_DP (1 << 28)
179 # define OTG_USB2_DM (1 << 27)
180 # define OTG_USB1_EN (1 << 26)
181 # define OTG_USB1_DP (1 << 25)
182 # define OTG_USB1_DM (1 << 24)
183 # define OTG_USB0_EN (1 << 23)
184 # define OTG_USB0_DP (1 << 22)
185 # define OTG_USB0_DM (1 << 21)
186 # define OTG_ASESSVLD (1 << 20)
187 # define OTG_BSESSEND (1 << 19)
188 # define OTG_BSESSVLD (1 << 18)
189 # define OTG_VBUSVLD (1 << 17)
190 # define OTG_ID (1 << 16)
191 # define OTG_DRIVER_SEL (1 << 15)
192 # define OTG_A_SETB_HNPEN (1 << 12)
193 # define OTG_A_BUSREQ (1 << 11)
194 # define OTG_B_HNPEN (1 << 9)
195 # define OTG_B_BUSREQ (1 << 8)
196 # define OTG_BUSDROP (1 << 7)
197 # define OTG_PULLDOWN (1 << 5)
198 # define OTG_PULLUP (1 << 4)
199 # define OTG_DRV_VBUS (1 << 3)
200 # define OTG_PD_VBUS (1 << 2)
201 # define OTG_PU_VBUS (1 << 1)
202 # define OTG_PU_ID (1 << 0)
203 #define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
204 # define DRIVER_SWITCH (1 << 15)
205 # define A_VBUS_ERR (1 << 13)
206 # define A_REQ_TMROUT (1 << 12)
207 # define A_SRP_DETECT (1 << 11)
208 # define B_HNP_FAIL (1 << 10)
209 # define B_SRP_TMROUT (1 << 9)
210 # define B_SRP_DONE (1 << 8)
211 # define B_SRP_STARTED (1 << 7)
212 # define OPRT_CHG (1 << 0)
213 #define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
214 // same bits as in IRQ_EN
215 #define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
216 # define OTGVPD (1 << 14)
217 # define OTGVPU (1 << 13)
218 # define OTGPUID (1 << 12)
219 # define USB2VDR (1 << 10)
220 # define USB2PDEN (1 << 9)
221 # define USB2PUEN (1 << 8)
222 # define USB1VDR (1 << 6)
223 # define USB1PDEN (1 << 5)
224 # define USB1PUEN (1 << 4)
225 # define USB0VDR (1 << 2)
226 # define USB0PDEN (1 << 1)
227 # define USB0PUEN (1 << 0)
228 #define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
229 #define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
231 /*-------------------------------------------------------------------------*/
234 #define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
235 # define CONF_USB2_UNI_R (1 << 8)
236 # define CONF_USB1_UNI_R (1 << 7)
237 # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
238 # define CONF_USB0_ISOLATE_R (1 << 3)
239 # define CONF_USB_PWRDN_DM_R (1 << 2)
240 # define CONF_USB_PWRDN_DP_R (1 << 1)
243 # define USB_UNIDIR 0x0
244 # define USB_UNIDIR_TLL 0x1
245 # define USB_BIDIR 0x2
246 # define USB_BIDIR_TLL 0x3
247 # define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2)))
248 # define USBT2TLL5PI (1 << 17)
249 # define USB0PUENACTLOI (1 << 16)
250 # define USBSTANDBYCTRL (1 << 15)
252 /* USB 2.0 PHY Control */
253 #define CONF2_PHY_GPIOMODE (1 << 23)
254 #define CONF2_OTGMODE (3 << 14)
255 #define CONF2_NO_OVERRIDE (0 << 14)
256 #define CONF2_FORCE_HOST (1 << 14)
257 #define CONF2_FORCE_DEVICE (2 << 14)
258 #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
259 #define CONF2_SESENDEN (1 << 13)
260 #define CONF2_VBDTCTEN (1 << 12)
261 #define CONF2_REFFREQ_24MHZ (2 << 8)
262 #define CONF2_REFFREQ_26MHZ (7 << 8)
263 #define CONF2_REFFREQ_13MHZ (6 << 8)
264 #define CONF2_REFFREQ (0xf << 8)
265 #define CONF2_PHYCLKGD (1 << 7)
266 #define CONF2_VBUSSENSE (1 << 6)
267 #define CONF2_PHY_PLLON (1 << 5)
268 #define CONF2_RESET (1 << 4)
269 #define CONF2_PHYPWRDN (1 << 3)
270 #define CONF2_OTGPWRDN (1 << 2)
271 #define CONF2_DATPOL (1 << 1)
273 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
274 u32
omap1_usb0_init(unsigned nwires
, unsigned is_device
);
275 u32
omap1_usb1_init(unsigned nwires
);
276 u32
omap1_usb2_init(unsigned nwires
, unsigned alt_pingroup
);
278 static inline u32
omap1_usb0_init(unsigned nwires
, unsigned is_device
)
282 static inline u32
omap1_usb1_init(unsigned nwires
)
287 static inline u32
omap1_usb2_init(unsigned nwires
, unsigned alt_pingroup
)
293 #endif /* __ASM_ARCH_OMAP_USB_H */