1 /******************************************************************************
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <net/mac80211.h>
32 #include "iwl-eeprom.h"
37 #include "iwl-helpers.h"
40 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
42 * Does NOT advance any TFD circular buffer read/write indexes
43 * Does NOT free the TFD itself (which is within circular buffer)
45 int iwl_hw_txq_free_tfd(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
47 struct iwl_tfd_frame
*bd_tmp
= (struct iwl_tfd_frame
*)&txq
->bd
[0];
48 struct iwl_tfd_frame
*bd
= &bd_tmp
[txq
->q
.read_ptr
];
49 struct pci_dev
*dev
= priv
->pci_dev
;
54 /* Host command buffers stay mapped in memory, nothing to clean */
55 if (txq
->q
.id
== IWL_CMD_QUEUE_NUM
)
58 /* Sanity check on number of chunks */
59 counter
= IWL_GET_BITS(*bd
, num_tbs
);
60 if (counter
> MAX_NUM_OF_TBS
) {
61 IWL_ERROR("Too many chunks: %i\n", counter
);
62 /* @todo issue fatal error, it is quite serious situation */
66 /* Unmap chunks, if any.
67 * TFD info for odd chunks is different format than for even chunks. */
68 for (i
= 0; i
< counter
; i
++) {
75 IWL_GET_BITS(bd
->pa
[index
], tb2_addr_lo16
) |
76 (IWL_GET_BITS(bd
->pa
[index
],
77 tb2_addr_hi20
) << 16),
78 IWL_GET_BITS(bd
->pa
[index
], tb2_len
),
83 le32_to_cpu(bd
->pa
[index
].tb1_addr
),
84 IWL_GET_BITS(bd
->pa
[index
], tb1_len
),
87 /* Free SKB, if any, for this chunk */
88 if (txq
->txb
[txq
->q
.read_ptr
].skb
[i
]) {
89 struct sk_buff
*skb
= txq
->txb
[txq
->q
.read_ptr
].skb
[i
];
92 txq
->txb
[txq
->q
.read_ptr
].skb
[i
] = NULL
;
97 EXPORT_SYMBOL(iwl_hw_txq_free_tfd
);
100 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv
*priv
, void *ptr
,
101 dma_addr_t addr
, u16 len
)
104 struct iwl_tfd_frame
*tfd
= ptr
;
105 u32 num_tbs
= IWL_GET_BITS(*tfd
, num_tbs
);
107 /* Each TFD can point to a maximum 20 Tx buffers */
108 if ((num_tbs
>= MAX_NUM_OF_TBS
) || (num_tbs
< 0)) {
109 IWL_ERROR("Error can not send more than %d chunks\n",
115 is_odd
= num_tbs
& 0x1;
118 tfd
->pa
[index
].tb1_addr
= cpu_to_le32(addr
);
119 IWL_SET_BITS(tfd
->pa
[index
], tb1_addr_hi
,
120 iwl_get_dma_hi_address(addr
));
121 IWL_SET_BITS(tfd
->pa
[index
], tb1_len
, len
);
123 IWL_SET_BITS(tfd
->pa
[index
], tb2_addr_lo16
,
124 (u32
) (addr
& 0xffff));
125 IWL_SET_BITS(tfd
->pa
[index
], tb2_addr_hi20
, addr
>> 16);
126 IWL_SET_BITS(tfd
->pa
[index
], tb2_len
, len
);
129 IWL_SET_BITS(*tfd
, num_tbs
, num_tbs
+ 1);
133 EXPORT_SYMBOL(iwl_hw_txq_attach_buf_to_tfd
);
136 * iwl_txq_update_write_ptr - Send new write index to hardware
138 int iwl_txq_update_write_ptr(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
142 int txq_id
= txq
->q
.id
;
144 if (txq
->need_update
== 0)
147 /* if we're trying to save power */
148 if (test_bit(STATUS_POWER_PMI
, &priv
->status
)) {
149 /* wake up nic if it's powered down ...
150 * uCode will wake up, and interrupt us again, so next
151 * time we'll skip this part. */
152 reg
= iwl_read32(priv
, CSR_UCODE_DRV_GP1
);
154 if (reg
& CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP
) {
155 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg
);
156 iwl_set_bit(priv
, CSR_GP_CNTRL
,
157 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
161 /* restore this queue's parameters in nic hardware. */
162 ret
= iwl_grab_nic_access(priv
);
165 iwl_write_direct32(priv
, HBUS_TARG_WRPTR
,
166 txq
->q
.write_ptr
| (txq_id
<< 8));
167 iwl_release_nic_access(priv
);
169 /* else not in power-save mode, uCode will never sleep when we're
170 * trying to tx (during RFKILL, we're not trying to tx). */
172 iwl_write32(priv
, HBUS_TARG_WRPTR
,
173 txq
->q
.write_ptr
| (txq_id
<< 8));
175 txq
->need_update
= 0;
179 EXPORT_SYMBOL(iwl_txq_update_write_ptr
);
183 * iwl_tx_queue_free - Deallocate DMA queue.
184 * @txq: Transmit queue to deallocate.
186 * Empty queue by removing and destroying all BD's.
188 * 0-fill, but do not free "txq" descriptor structure.
190 static void iwl_tx_queue_free(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
192 struct iwl_queue
*q
= &txq
->q
;
193 struct pci_dev
*dev
= priv
->pci_dev
;
199 /* first, empty all BD's */
200 for (; q
->write_ptr
!= q
->read_ptr
;
201 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
))
202 iwl_hw_txq_free_tfd(priv
, txq
);
204 len
= sizeof(struct iwl_cmd
) * q
->n_window
;
205 if (q
->id
== IWL_CMD_QUEUE_NUM
)
206 len
+= IWL_MAX_SCAN_SIZE
;
208 /* De-alloc array of command/tx buffers */
209 pci_free_consistent(dev
, len
, txq
->cmd
, txq
->dma_addr_cmd
);
211 /* De-alloc circular buffer of TFDs */
213 pci_free_consistent(dev
, sizeof(struct iwl_tfd_frame
) *
214 txq
->q
.n_bd
, txq
->bd
, txq
->q
.dma_addr
);
216 /* De-alloc array of per-TFD driver data */
220 /* 0-fill queue descriptor structure */
221 memset(txq
, 0, sizeof(*txq
));
224 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
227 * Theory of operation
229 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
230 * of buffer descriptors, each of which points to one or more data buffers for
231 * the device to read from or fill. Driver and device exchange status of each
232 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
233 * entries in each circular buffer, to protect against confusing empty and full
236 * The device reads or writes the data in the queues via the device's several
237 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
239 * For Tx queue, there are low mark and high mark limits. If, after queuing
240 * the packet for Tx, free space become < low mark, Tx queue stopped. When
241 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
244 * See more detailed info in iwl-4965-hw.h.
245 ***************************************************/
247 int iwl_queue_space(const struct iwl_queue
*q
)
249 int s
= q
->read_ptr
- q
->write_ptr
;
251 if (q
->read_ptr
> q
->write_ptr
)
256 /* keep some reserve to not confuse empty and full situations */
262 EXPORT_SYMBOL(iwl_queue_space
);
266 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
268 static int iwl_queue_init(struct iwl_priv
*priv
, struct iwl_queue
*q
,
269 int count
, int slots_num
, u32 id
)
272 q
->n_window
= slots_num
;
275 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
276 * and iwl_queue_dec_wrap are broken. */
277 BUG_ON(!is_power_of_2(count
));
279 /* slots_num must be power-of-two size, otherwise
280 * get_cmd_index is broken. */
281 BUG_ON(!is_power_of_2(slots_num
));
283 q
->low_mark
= q
->n_window
/ 4;
287 q
->high_mark
= q
->n_window
/ 8;
288 if (q
->high_mark
< 2)
291 q
->write_ptr
= q
->read_ptr
= 0;
297 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
299 static int iwl_tx_queue_alloc(struct iwl_priv
*priv
,
300 struct iwl_tx_queue
*txq
, u32 id
)
302 struct pci_dev
*dev
= priv
->pci_dev
;
304 /* Driver private data, only for Tx (not command) queues,
305 * not shared with device. */
306 if (id
!= IWL_CMD_QUEUE_NUM
) {
307 txq
->txb
= kmalloc(sizeof(txq
->txb
[0]) *
308 TFD_QUEUE_SIZE_MAX
, GFP_KERNEL
);
310 IWL_ERROR("kmalloc for auxiliary BD "
311 "structures failed\n");
317 /* Circular buffer of transmit frame descriptors (TFDs),
318 * shared with device */
319 txq
->bd
= pci_alloc_consistent(dev
,
320 sizeof(txq
->bd
[0]) * TFD_QUEUE_SIZE_MAX
,
324 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
325 sizeof(txq
->bd
[0]) * TFD_QUEUE_SIZE_MAX
);
340 * Tell nic where to find circular buffer of Tx Frame Descriptors for
341 * given Tx queue, and enable the DMA channel used for that queue.
343 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
344 * channels supported in hardware.
346 static int iwl_hw_tx_queue_init(struct iwl_priv
*priv
,
347 struct iwl_tx_queue
*txq
)
351 int txq_id
= txq
->q
.id
;
353 spin_lock_irqsave(&priv
->lock
, flags
);
354 rc
= iwl_grab_nic_access(priv
);
356 spin_unlock_irqrestore(&priv
->lock
, flags
);
360 /* Circular buffer (TFD queue in DRAM) physical base address */
361 iwl_write_direct32(priv
, FH_MEM_CBBC_QUEUE(txq_id
),
362 txq
->q
.dma_addr
>> 8);
364 /* Enable DMA channel, using same id as for TFD queue */
366 priv
, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id
),
367 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
368 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
);
369 iwl_release_nic_access(priv
);
370 spin_unlock_irqrestore(&priv
->lock
, flags
);
376 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
378 static int iwl_tx_queue_init(struct iwl_priv
*priv
,
379 struct iwl_tx_queue
*txq
,
380 int slots_num
, u32 txq_id
)
382 struct pci_dev
*dev
= priv
->pci_dev
;
387 * Alloc buffer array for commands (Tx or other types of commands).
388 * For the command queue (#4), allocate command space + one big
389 * command for scan, since scan command is very huge; the system will
390 * not have two scans at the same time, so only one is needed.
391 * For normal Tx queues (all other queues), no super-size command
394 len
= sizeof(struct iwl_cmd
) * slots_num
;
395 if (txq_id
== IWL_CMD_QUEUE_NUM
)
396 len
+= IWL_MAX_SCAN_SIZE
;
397 txq
->cmd
= pci_alloc_consistent(dev
, len
, &txq
->dma_addr_cmd
);
401 /* Alloc driver data array and TFD circular buffer */
402 rc
= iwl_tx_queue_alloc(priv
, txq
, txq_id
);
404 pci_free_consistent(dev
, len
, txq
->cmd
, txq
->dma_addr_cmd
);
408 txq
->need_update
= 0;
410 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
411 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
412 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX
& (TFD_QUEUE_SIZE_MAX
- 1));
414 /* Initialize queue's high/low-water marks, and head/tail indexes */
415 iwl_queue_init(priv
, &txq
->q
, TFD_QUEUE_SIZE_MAX
, slots_num
, txq_id
);
417 /* Tell device where to find queue */
418 iwl_hw_tx_queue_init(priv
, txq
);
423 * iwl_hw_txq_ctx_free - Free TXQ Context
425 * Destroy all TX DMA queues and structures
427 void iwl_hw_txq_ctx_free(struct iwl_priv
*priv
)
432 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++)
433 iwl_tx_queue_free(priv
, &priv
->txq
[txq_id
]);
435 /* Keep-warm buffer */
438 EXPORT_SYMBOL(iwl_hw_txq_ctx_free
);
442 * iwl_txq_ctx_reset - Reset TX queue context
443 * Destroys all DMA structures and initialise them again
448 int iwl_txq_ctx_reset(struct iwl_priv
*priv
)
451 int txq_id
, slots_num
;
456 /* Free all tx/cmd queues and keep-warm buffer */
457 iwl_hw_txq_ctx_free(priv
);
459 /* Alloc keep-warm buffer */
460 ret
= iwl_kw_alloc(priv
);
462 IWL_ERROR("Keep Warm allocation failed");
465 spin_lock_irqsave(&priv
->lock
, flags
);
466 ret
= iwl_grab_nic_access(priv
);
468 spin_unlock_irqrestore(&priv
->lock
, flags
);
472 /* Turn off all Tx DMA fifos */
473 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
475 iwl_release_nic_access(priv
);
476 spin_unlock_irqrestore(&priv
->lock
, flags
);
479 /* Tell nic where to find the keep-warm buffer */
480 ret
= iwl_kw_init(priv
);
482 IWL_ERROR("kw_init failed\n");
486 /* Alloc and init all Tx queues, including the command queue (#4) */
487 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
488 slots_num
= (txq_id
== IWL_CMD_QUEUE_NUM
) ?
489 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
490 ret
= iwl_tx_queue_init(priv
, &priv
->txq
[txq_id
], slots_num
,
493 IWL_ERROR("Tx %d queue init failed\n", txq_id
);
501 iwl_hw_txq_ctx_free(priv
);
508 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
510 void iwl_txq_ctx_stop(struct iwl_priv
*priv
)
517 /* Turn off all Tx DMA fifos */
518 spin_lock_irqsave(&priv
->lock
, flags
);
519 if (iwl_grab_nic_access(priv
)) {
520 spin_unlock_irqrestore(&priv
->lock
, flags
);
524 priv
->cfg
->ops
->lib
->txq_set_sched(priv
, 0);
526 /* Stop each Tx DMA channel, and wait for it to be idle */
527 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
528 iwl_write_direct32(priv
,
529 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id
), 0x0);
530 iwl_poll_direct_bit(priv
, FH_TSSR_TX_STATUS_REG
,
531 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
534 iwl_release_nic_access(priv
);
535 spin_unlock_irqrestore(&priv
->lock
, flags
);
537 /* Deallocate memory for all Tx queues */
538 iwl_hw_txq_ctx_free(priv
);
540 EXPORT_SYMBOL(iwl_txq_ctx_stop
);
543 * handle build REPLY_TX command notification.
545 static void iwl_tx_cmd_build_basic(struct iwl_priv
*priv
,
546 struct iwl_tx_cmd
*tx_cmd
,
547 struct ieee80211_tx_info
*info
,
548 struct ieee80211_hdr
*hdr
,
549 int is_unicast
, u8 std_id
)
551 u16 fc
= le16_to_cpu(hdr
->frame_control
);
552 __le32 tx_flags
= tx_cmd
->tx_flags
;
554 tx_cmd
->stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
555 if (!(info
->flags
& IEEE80211_TX_CTL_NO_ACK
)) {
556 tx_flags
|= TX_CMD_FLG_ACK_MSK
;
557 if ((fc
& IEEE80211_FCTL_FTYPE
) == IEEE80211_FTYPE_MGMT
)
558 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
559 if (ieee80211_is_probe_response(fc
) &&
560 !(le16_to_cpu(hdr
->seq_ctrl
) & 0xf))
561 tx_flags
|= TX_CMD_FLG_TSF_MSK
;
563 tx_flags
&= (~TX_CMD_FLG_ACK_MSK
);
564 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
567 if (ieee80211_is_back_request(fc
))
568 tx_flags
|= TX_CMD_FLG_ACK_MSK
| TX_CMD_FLG_IMM_BA_RSP_MASK
;
571 tx_cmd
->sta_id
= std_id
;
572 if (ieee80211_get_morefrag(hdr
))
573 tx_flags
|= TX_CMD_FLG_MORE_FRAG_MSK
;
575 if (ieee80211_is_qos_data(fc
)) {
576 u8
*qc
= ieee80211_get_qos_ctrl(hdr
, ieee80211_get_hdrlen(fc
));
577 tx_cmd
->tid_tspec
= qc
[0] & 0xf;
578 tx_flags
&= ~TX_CMD_FLG_SEQ_CTL_MSK
;
580 tx_flags
|= TX_CMD_FLG_SEQ_CTL_MSK
;
583 if (info
->flags
& IEEE80211_TX_CTL_USE_RTS_CTS
) {
584 tx_flags
|= TX_CMD_FLG_RTS_MSK
;
585 tx_flags
&= ~TX_CMD_FLG_CTS_MSK
;
586 } else if (info
->flags
& IEEE80211_TX_CTL_USE_CTS_PROTECT
) {
587 tx_flags
&= ~TX_CMD_FLG_RTS_MSK
;
588 tx_flags
|= TX_CMD_FLG_CTS_MSK
;
591 if ((tx_flags
& TX_CMD_FLG_RTS_MSK
) || (tx_flags
& TX_CMD_FLG_CTS_MSK
))
592 tx_flags
|= TX_CMD_FLG_FULL_TXOP_PROT_MSK
;
594 tx_flags
&= ~(TX_CMD_FLG_ANT_SEL_MSK
);
595 if ((fc
& IEEE80211_FCTL_FTYPE
) == IEEE80211_FTYPE_MGMT
) {
596 if ((fc
& IEEE80211_FCTL_STYPE
) == IEEE80211_STYPE_ASSOC_REQ
||
597 (fc
& IEEE80211_FCTL_STYPE
) == IEEE80211_STYPE_REASSOC_REQ
)
598 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(3);
600 tx_cmd
->timeout
.pm_frame_timeout
= cpu_to_le16(2);
602 tx_cmd
->timeout
.pm_frame_timeout
= 0;
605 tx_cmd
->driver_txop
= 0;
606 tx_cmd
->tx_flags
= tx_flags
;
607 tx_cmd
->next_frame_len
= 0;
610 #define RTS_HCCA_RETRY_LIMIT 3
611 #define RTS_DFAULT_RETRY_LIMIT 60
613 static void iwl_tx_cmd_build_rate(struct iwl_priv
*priv
,
614 struct iwl_tx_cmd
*tx_cmd
,
615 struct ieee80211_tx_info
*info
,
619 u8 rts_retry_limit
= 0;
620 u8 data_retry_limit
= 0;
625 rate_idx
= min(ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
& 0xffff,
628 rate_plcp
= iwl_rates
[rate_idx
].plcp
;
630 rts_retry_limit
= (is_hcca
) ?
631 RTS_HCCA_RETRY_LIMIT
: RTS_DFAULT_RETRY_LIMIT
;
633 if ((rate_idx
>= IWL_FIRST_CCK_RATE
) && (rate_idx
<= IWL_LAST_CCK_RATE
))
634 rate_flags
|= RATE_MCS_CCK_MSK
;
637 if (ieee80211_is_probe_response(fc
)) {
638 data_retry_limit
= 3;
639 if (data_retry_limit
< rts_retry_limit
)
640 rts_retry_limit
= data_retry_limit
;
642 data_retry_limit
= IWL_DEFAULT_TX_RETRY
;
644 if (priv
->data_retry_limit
!= -1)
645 data_retry_limit
= priv
->data_retry_limit
;
648 if (ieee80211_is_data(fc
)) {
649 tx_cmd
->initial_rate_index
= 0;
650 tx_cmd
->tx_flags
|= TX_CMD_FLG_STA_RATE_MSK
;
652 switch (fc
& IEEE80211_FCTL_STYPE
) {
653 case IEEE80211_STYPE_AUTH
:
654 case IEEE80211_STYPE_DEAUTH
:
655 case IEEE80211_STYPE_ASSOC_REQ
:
656 case IEEE80211_STYPE_REASSOC_REQ
:
657 if (tx_cmd
->tx_flags
& TX_CMD_FLG_RTS_MSK
) {
658 tx_cmd
->tx_flags
&= ~TX_CMD_FLG_RTS_MSK
;
659 tx_cmd
->tx_flags
|= TX_CMD_FLG_CTS_MSK
;
666 /* Alternate between antenna A and B for successive frames */
667 if (priv
->use_ant_b_for_management_frame
) {
668 priv
->use_ant_b_for_management_frame
= 0;
669 rate_flags
|= RATE_MCS_ANT_B_MSK
;
671 priv
->use_ant_b_for_management_frame
= 1;
672 rate_flags
|= RATE_MCS_ANT_A_MSK
;
676 tx_cmd
->rts_retry_limit
= rts_retry_limit
;
677 tx_cmd
->data_retry_limit
= data_retry_limit
;
678 tx_cmd
->rate_n_flags
= iwl4965_hw_set_rate_n_flags(rate_plcp
, rate_flags
);
681 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv
*priv
,
682 struct ieee80211_tx_info
*info
,
683 struct iwl_tx_cmd
*tx_cmd
,
684 struct sk_buff
*skb_frag
,
687 struct ieee80211_key_conf
*keyconf
= info
->control
.hw_key
;
689 switch (keyconf
->alg
) {
691 tx_cmd
->sec_ctl
= TX_CMD_SEC_CCM
;
692 memcpy(tx_cmd
->key
, keyconf
->key
, keyconf
->keylen
);
693 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
694 tx_cmd
->tx_flags
|= TX_CMD_FLG_AGG_CCMP_MSK
;
695 IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
699 tx_cmd
->sec_ctl
= TX_CMD_SEC_TKIP
;
700 ieee80211_get_tkip_key(keyconf
, skb_frag
,
701 IEEE80211_TKIP_P2_KEY
, tx_cmd
->key
);
702 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
706 tx_cmd
->sec_ctl
|= (TX_CMD_SEC_WEP
|
707 (keyconf
->keyidx
& TX_CMD_SEC_MSK
) << TX_CMD_SEC_SHIFT
);
709 if (keyconf
->keylen
== WEP_KEY_LEN_128
)
710 tx_cmd
->sec_ctl
|= TX_CMD_SEC_KEY128
;
712 memcpy(&tx_cmd
->key
[3], keyconf
->key
, keyconf
->keylen
);
714 IWL_DEBUG_TX("Configuring packet for WEP encryption "
715 "with key %d\n", keyconf
->keyidx
);
719 printk(KERN_ERR
"Unknown encode alg %d\n", keyconf
->alg
);
724 static void iwl_update_tx_stats(struct iwl_priv
*priv
, u16 fc
, u16 len
)
726 /* 0 - mgmt, 1 - cnt, 2 - data */
727 int idx
= (fc
& IEEE80211_FCTL_FTYPE
) >> 2;
728 priv
->tx_stats
[idx
].cnt
++;
729 priv
->tx_stats
[idx
].bytes
+= len
;
733 * start REPLY_TX command process
735 int iwl_tx_skb(struct iwl_priv
*priv
, struct sk_buff
*skb
)
737 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
738 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
739 struct iwl_tfd_frame
*tfd
;
741 int txq_id
= skb_get_queue_mapping(skb
);
742 struct iwl_tx_queue
*txq
= NULL
;
743 struct iwl_queue
*q
= NULL
;
744 dma_addr_t phys_addr
;
745 dma_addr_t txcmd_phys
;
746 dma_addr_t scratch_phys
;
747 struct iwl_cmd
*out_cmd
= NULL
;
748 struct iwl_tx_cmd
*tx_cmd
;
749 u16 len
, idx
, len_org
;
751 u8 id
, hdr_len
, unicast
;
754 u8 wait_write_ptr
= 0;
760 spin_lock_irqsave(&priv
->lock
, flags
);
761 if (iwl_is_rfkill(priv
)) {
762 IWL_DEBUG_DROP("Dropping - RF KILL\n");
767 IWL_DEBUG_DROP("Dropping - !priv->vif\n");
771 if ((ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
& 0xFF) ==
773 IWL_ERROR("ERROR: No TX rate available.\n");
777 unicast
= !is_multicast_ether_addr(hdr
->addr1
);
780 fc
= le16_to_cpu(hdr
->frame_control
);
782 #ifdef CONFIG_IWLWIFI_DEBUG
783 if (ieee80211_is_auth(fc
))
784 IWL_DEBUG_TX("Sending AUTH frame\n");
785 else if (ieee80211_is_assoc_request(fc
))
786 IWL_DEBUG_TX("Sending ASSOC frame\n");
787 else if (ieee80211_is_reassoc_request(fc
))
788 IWL_DEBUG_TX("Sending REASSOC frame\n");
791 /* drop all data frame if we are not associated */
792 if (((fc
& IEEE80211_FCTL_FTYPE
) == IEEE80211_FTYPE_DATA
) &&
793 (!iwl_is_associated(priv
) ||
794 ((priv
->iw_mode
== IEEE80211_IF_TYPE_STA
) && !priv
->assoc_id
) ||
795 !priv
->assoc_station_added
)) {
796 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
800 spin_unlock_irqrestore(&priv
->lock
, flags
);
802 hdr_len
= ieee80211_get_hdrlen(fc
);
804 /* Find (or create) index into station table for destination station */
805 sta_id
= iwl_get_sta_id(priv
, hdr
);
806 if (sta_id
== IWL_INVALID_STATION
) {
807 DECLARE_MAC_BUF(mac
);
809 IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
810 print_mac(mac
, hdr
->addr1
));
814 IWL_DEBUG_TX("station Id %d\n", sta_id
);
816 if (ieee80211_is_qos_data(fc
)) {
817 qc
= ieee80211_get_qos_ctrl(hdr
, hdr_len
);
819 seq_number
= priv
->stations
[sta_id
].tid
[tid
].seq_number
&
821 hdr
->seq_ctrl
= cpu_to_le16(seq_number
) |
823 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG
));
825 #ifdef CONFIG_IWL4965_HT
826 /* aggregation is on for this <sta,tid> */
827 if (info
->flags
& IEEE80211_TX_CTL_AMPDU
)
828 txq_id
= priv
->stations
[sta_id
].tid
[tid
].agg
.txq_id
;
829 priv
->stations
[sta_id
].tid
[tid
].tfds_in_queue
++;
830 #endif /* CONFIG_IWL4965_HT */
833 /* Descriptor for chosen Tx queue */
834 txq
= &priv
->txq
[txq_id
];
837 spin_lock_irqsave(&priv
->lock
, flags
);
839 /* Set up first empty TFD within this queue's circular TFD buffer */
840 tfd
= &txq
->bd
[q
->write_ptr
];
841 memset(tfd
, 0, sizeof(*tfd
));
842 control_flags
= (u32
*) tfd
;
843 idx
= get_cmd_index(q
, q
->write_ptr
, 0);
845 /* Set up driver data for this TFD */
846 memset(&(txq
->txb
[q
->write_ptr
]), 0, sizeof(struct iwl_tx_info
));
847 txq
->txb
[q
->write_ptr
].skb
[0] = skb
;
849 /* Set up first empty entry in queue's array of Tx/cmd buffers */
850 out_cmd
= &txq
->cmd
[idx
];
851 tx_cmd
= &out_cmd
->cmd
.tx
;
852 memset(&out_cmd
->hdr
, 0, sizeof(out_cmd
->hdr
));
853 memset(tx_cmd
, 0, sizeof(struct iwl_tx_cmd
));
856 * Set up the Tx-command (not MAC!) header.
857 * Store the chosen Tx queue and TFD index within the sequence field;
858 * after Tx, uCode's Tx response will return this value so driver can
859 * locate the frame within the tx queue and do post-tx processing.
861 out_cmd
->hdr
.cmd
= REPLY_TX
;
862 out_cmd
->hdr
.sequence
= cpu_to_le16((u16
)(QUEUE_TO_SEQ(txq_id
) |
863 INDEX_TO_SEQ(q
->write_ptr
)));
865 /* Copy MAC header from skb into command buffer */
866 memcpy(tx_cmd
->hdr
, hdr
, hdr_len
);
869 * Use the first empty entry in this queue's command buffer array
870 * to contain the Tx command and MAC header concatenated together
871 * (payload data will be in another buffer).
872 * Size of this varies, due to varying MAC header length.
873 * If end is not dword aligned, we'll have 2 extra bytes at the end
874 * of the MAC header (device reads on dword boundaries).
875 * We'll tell device about this padding later.
877 len
= sizeof(struct iwl_tx_cmd
) +
878 sizeof(struct iwl_cmd_header
) + hdr_len
;
881 len
= (len
+ 3) & ~3;
888 /* Physical address of this Tx command's header (not MAC header!),
889 * within command buffer array. */
890 txcmd_phys
= txq
->dma_addr_cmd
+ sizeof(struct iwl_cmd
) * idx
+
891 offsetof(struct iwl_cmd
, hdr
);
893 /* Add buffer containing Tx command and MAC(!) header to TFD's
895 iwl_hw_txq_attach_buf_to_tfd(priv
, tfd
, txcmd_phys
, len
);
897 if (!(info
->flags
& IEEE80211_TX_CTL_DO_NOT_ENCRYPT
))
898 iwl_tx_cmd_build_hwcrypto(priv
, info
, tx_cmd
, skb
, sta_id
);
900 /* Set up TFD's 2nd entry to point directly to remainder of skb,
901 * if any (802.11 null frames have no payload). */
902 len
= skb
->len
- hdr_len
;
904 phys_addr
= pci_map_single(priv
->pci_dev
, skb
->data
+ hdr_len
,
905 len
, PCI_DMA_TODEVICE
);
906 iwl_hw_txq_attach_buf_to_tfd(priv
, tfd
, phys_addr
, len
);
909 /* Tell NIC about any 2-byte padding after MAC header */
911 tx_cmd
->tx_flags
|= TX_CMD_FLG_MH_PAD_MSK
;
913 /* Total # bytes to be transmitted */
915 tx_cmd
->len
= cpu_to_le16(len
);
916 /* TODO need this for burst mode later on */
917 iwl_tx_cmd_build_basic(priv
, tx_cmd
, info
, hdr
, unicast
, sta_id
);
919 /* set is_hcca to 0; it probably will never be implemented */
920 iwl_tx_cmd_build_rate(priv
, tx_cmd
, info
, fc
, sta_id
, 0);
922 iwl_update_tx_stats(priv
, fc
, len
);
924 scratch_phys
= txcmd_phys
+ sizeof(struct iwl_cmd_header
) +
925 offsetof(struct iwl_tx_cmd
, scratch
);
926 tx_cmd
->dram_lsb_ptr
= cpu_to_le32(scratch_phys
);
927 tx_cmd
->dram_msb_ptr
= iwl_get_dma_hi_address(scratch_phys
);
929 if (!ieee80211_get_morefrag(hdr
)) {
930 txq
->need_update
= 1;
932 priv
->stations
[sta_id
].tid
[tid
].seq_number
= seq_number
;
935 txq
->need_update
= 0;
938 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
, sizeof(*tx_cmd
));
940 iwl_print_hex_dump(priv
, IWL_DL_TX
, (u8
*)tx_cmd
->hdr
, hdr_len
);
942 /* Set up entry for this TFD in Tx byte-count array */
943 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
, len
);
945 /* Tell device the write index *just past* this latest filled TFD */
946 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
947 ret
= iwl_txq_update_write_ptr(priv
, txq
);
948 spin_unlock_irqrestore(&priv
->lock
, flags
);
953 if ((iwl_queue_space(q
) < q
->high_mark
)
954 && priv
->mac80211_registered
) {
955 if (wait_write_ptr
) {
956 spin_lock_irqsave(&priv
->lock
, flags
);
957 txq
->need_update
= 1;
958 iwl_txq_update_write_ptr(priv
, txq
);
959 spin_unlock_irqrestore(&priv
->lock
, flags
);
962 ieee80211_stop_queue(priv
->hw
, skb_get_queue_mapping(skb
));
968 spin_unlock_irqrestore(&priv
->lock
, flags
);
972 EXPORT_SYMBOL(iwl_tx_skb
);
974 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
977 * iwl_enqueue_hcmd - enqueue a uCode command
978 * @priv: device private data point
979 * @cmd: a point to the ucode command structure
981 * The function returns < 0 values to indicate the operation is
982 * failed. On success, it turns the index (> 0) of command in the
985 int iwl_enqueue_hcmd(struct iwl_priv
*priv
, struct iwl_host_cmd
*cmd
)
987 struct iwl_tx_queue
*txq
= &priv
->txq
[IWL_CMD_QUEUE_NUM
];
988 struct iwl_queue
*q
= &txq
->q
;
989 struct iwl_tfd_frame
*tfd
;
991 struct iwl_cmd
*out_cmd
;
994 dma_addr_t phys_addr
;
998 cmd
->len
= priv
->cfg
->ops
->utils
->get_hcmd_size(cmd
->id
, cmd
->len
);
999 fix_size
= (u16
)(cmd
->len
+ sizeof(out_cmd
->hdr
));
1001 /* If any of the command structures end up being larger than
1002 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1003 * we will need to increase the size of the TFD entries */
1004 BUG_ON((fix_size
> TFD_MAX_PAYLOAD_SIZE
) &&
1005 !(cmd
->meta
.flags
& CMD_SIZE_HUGE
));
1007 if (iwl_is_rfkill(priv
)) {
1008 IWL_DEBUG_INFO("Not sending command - RF KILL");
1012 if (iwl_queue_space(q
) < ((cmd
->meta
.flags
& CMD_ASYNC
) ? 2 : 1)) {
1013 IWL_ERROR("No space for Tx\n");
1017 spin_lock_irqsave(&priv
->hcmd_lock
, flags
);
1019 tfd
= &txq
->bd
[q
->write_ptr
];
1020 memset(tfd
, 0, sizeof(*tfd
));
1022 control_flags
= (u32
*) tfd
;
1024 idx
= get_cmd_index(q
, q
->write_ptr
, cmd
->meta
.flags
& CMD_SIZE_HUGE
);
1025 out_cmd
= &txq
->cmd
[idx
];
1027 out_cmd
->hdr
.cmd
= cmd
->id
;
1028 memcpy(&out_cmd
->meta
, &cmd
->meta
, sizeof(cmd
->meta
));
1029 memcpy(&out_cmd
->cmd
.payload
, cmd
->data
, cmd
->len
);
1031 /* At this point, the out_cmd now has all of the incoming cmd
1034 out_cmd
->hdr
.flags
= 0;
1035 out_cmd
->hdr
.sequence
= cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM
) |
1036 INDEX_TO_SEQ(q
->write_ptr
));
1037 if (out_cmd
->meta
.flags
& CMD_SIZE_HUGE
)
1038 out_cmd
->hdr
.sequence
|= cpu_to_le16(SEQ_HUGE_FRAME
);
1040 phys_addr
= txq
->dma_addr_cmd
+ sizeof(txq
->cmd
[0]) * idx
+
1041 offsetof(struct iwl_cmd
, hdr
);
1042 iwl_hw_txq_attach_buf_to_tfd(priv
, tfd
, phys_addr
, fix_size
);
1044 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1045 "%d bytes at %d[%d]:%d\n",
1046 get_cmd_string(out_cmd
->hdr
.cmd
),
1047 out_cmd
->hdr
.cmd
, le16_to_cpu(out_cmd
->hdr
.sequence
),
1048 fix_size
, q
->write_ptr
, idx
, IWL_CMD_QUEUE_NUM
);
1050 txq
->need_update
= 1;
1052 /* Set up entry in queue's byte count circular buffer */
1053 priv
->cfg
->ops
->lib
->txq_update_byte_cnt_tbl(priv
, txq
, 0);
1055 /* Increment and update queue's write index */
1056 q
->write_ptr
= iwl_queue_inc_wrap(q
->write_ptr
, q
->n_bd
);
1057 ret
= iwl_txq_update_write_ptr(priv
, txq
);
1059 spin_unlock_irqrestore(&priv
->hcmd_lock
, flags
);
1060 return ret
? ret
: idx
;
1063 int iwl_tx_queue_reclaim(struct iwl_priv
*priv
, int txq_id
, int index
)
1065 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1066 struct iwl_queue
*q
= &txq
->q
;
1067 struct iwl_tx_info
*tx_info
;
1070 if ((index
>= q
->n_bd
) || (iwl_queue_used(q
, index
) == 0)) {
1071 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1072 "is out of range [0-%d] %d %d.\n", txq_id
,
1073 index
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1077 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
); q
->read_ptr
!= index
;
1078 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1080 tx_info
= &txq
->txb
[txq
->q
.read_ptr
];
1081 ieee80211_tx_status_irqsafe(priv
->hw
, tx_info
->skb
[0]);
1082 tx_info
->skb
[0] = NULL
;
1083 iwl_hw_txq_free_tfd(priv
, txq
);
1089 EXPORT_SYMBOL(iwl_tx_queue_reclaim
);
1093 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1095 * When FW advances 'R' index, all entries between old and new 'R' index
1096 * need to be reclaimed. As result, some free space forms. If there is
1097 * enough free space (> low mark), wake the stack that feeds us.
1099 static void iwl_hcmd_queue_reclaim(struct iwl_priv
*priv
, int txq_id
, int index
)
1101 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
1102 struct iwl_queue
*q
= &txq
->q
;
1105 if ((index
>= q
->n_bd
) || (iwl_queue_used(q
, index
) == 0)) {
1106 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1107 "is out of range [0-%d] %d %d.\n", txq_id
,
1108 index
, q
->n_bd
, q
->write_ptr
, q
->read_ptr
);
1112 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
); q
->read_ptr
!= index
;
1113 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
1116 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index
,
1117 q
->write_ptr
, q
->read_ptr
);
1118 queue_work(priv
->workqueue
, &priv
->restart
);
1125 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1126 * @rxb: Rx buffer to reclaim
1128 * If an Rx buffer has an async callback associated with it the callback
1129 * will be executed. The attached skb (if present) will only be freed
1130 * if the callback returns 1
1132 void iwl_tx_cmd_complete(struct iwl_priv
*priv
, struct iwl_rx_mem_buffer
*rxb
)
1134 struct iwl_rx_packet
*pkt
= (struct iwl_rx_packet
*)rxb
->skb
->data
;
1135 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
1136 int txq_id
= SEQ_TO_QUEUE(sequence
);
1137 int index
= SEQ_TO_INDEX(sequence
);
1138 int huge
= sequence
& SEQ_HUGE_FRAME
;
1140 struct iwl_cmd
*cmd
;
1142 /* If a Tx command is being handled and it isn't in the actual
1143 * command queue then there a command routing bug has been introduced
1144 * in the queue management code. */
1145 if (txq_id
!= IWL_CMD_QUEUE_NUM
)
1146 IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
1147 txq_id
, pkt
->hdr
.cmd
);
1148 BUG_ON(txq_id
!= IWL_CMD_QUEUE_NUM
);
1150 cmd_index
= get_cmd_index(&priv
->txq
[IWL_CMD_QUEUE_NUM
].q
, index
, huge
);
1151 cmd
= &priv
->txq
[IWL_CMD_QUEUE_NUM
].cmd
[cmd_index
];
1153 /* Input error checking is done when commands are added to queue. */
1154 if (cmd
->meta
.flags
& CMD_WANT_SKB
) {
1155 cmd
->meta
.source
->u
.skb
= rxb
->skb
;
1157 } else if (cmd
->meta
.u
.callback
&&
1158 !cmd
->meta
.u
.callback(priv
, cmd
, rxb
->skb
))
1161 iwl_hcmd_queue_reclaim(priv
, txq_id
, index
);
1163 if (!(cmd
->meta
.flags
& CMD_ASYNC
)) {
1164 clear_bit(STATUS_HCMD_ACTIVE
, &priv
->status
);
1165 wake_up_interruptible(&priv
->wait_command_queue
);
1168 EXPORT_SYMBOL(iwl_tx_cmd_complete
);
1171 #ifdef CONFIG_IWLWIF_DEBUG
1172 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1174 const char *iwl_get_tx_fail_reason(u32 status
)
1176 switch (status
& TX_STATUS_MSK
) {
1177 case TX_STATUS_SUCCESS
:
1179 TX_STATUS_ENTRY(SHORT_LIMIT
);
1180 TX_STATUS_ENTRY(LONG_LIMIT
);
1181 TX_STATUS_ENTRY(FIFO_UNDERRUN
);
1182 TX_STATUS_ENTRY(MGMNT_ABORT
);
1183 TX_STATUS_ENTRY(NEXT_FRAG
);
1184 TX_STATUS_ENTRY(LIFE_EXPIRE
);
1185 TX_STATUS_ENTRY(DEST_PS
);
1186 TX_STATUS_ENTRY(ABORTED
);
1187 TX_STATUS_ENTRY(BT_RETRY
);
1188 TX_STATUS_ENTRY(STA_INVALID
);
1189 TX_STATUS_ENTRY(FRAG_DROPPED
);
1190 TX_STATUS_ENTRY(TID_DISABLE
);
1191 TX_STATUS_ENTRY(FRAME_FLUSHED
);
1192 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL
);
1193 TX_STATUS_ENTRY(TX_LOCKED
);
1194 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR
);
1199 EXPORT_SYMBOL(iwl_get_tx_fail_reason
);
1200 #endif /* CONFIG_IWLWIFI_DEBUG */