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Merge branch 'for-linus' into for-next
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / pci / hda / hda_intel.c
blob2cc07c184d312ee9b8aca3ec414aeedb60fa5461
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <linux/vgaarb.h>
61 #include <linux/vga_switcheroo.h>
62 #include <linux/firmware.h>
63 #include "hda_codec.h"
64
65
66 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
67 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
68 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
69 static char *model[SNDRV_CARDS];
70 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
71 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
72 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int probe_only[SNDRV_CARDS];
74 static int jackpoll_ms[SNDRV_CARDS];
75 static bool single_cmd;
76 static int enable_msi = -1;
77 #ifdef CONFIG_SND_HDA_PATCH_LOADER
78 static char *patch[SNDRV_CARDS];
79 #endif
80 #ifdef CONFIG_SND_HDA_INPUT_BEEP
81 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
82 CONFIG_SND_HDA_INPUT_BEEP_MODE};
83 #endif
84
85 module_param_array(index, int, NULL, 0444);
86 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
87 module_param_array(id, charp, NULL, 0444);
88 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
89 module_param_array(enable, bool, NULL, 0444);
90 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
91 module_param_array(model, charp, NULL, 0444);
92 MODULE_PARM_DESC(model, "Use the given board model.");
93 module_param_array(position_fix, int, NULL, 0444);
94 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
95 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
96 module_param_array(bdl_pos_adj, int, NULL, 0644);
97 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
98 module_param_array(probe_mask, int, NULL, 0444);
99 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
100 module_param_array(probe_only, int, NULL, 0444);
101 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
102 module_param_array(jackpoll_ms, int, NULL, 0444);
103 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
104 module_param(single_cmd, bool, 0444);
105 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
106 "(for debugging only).");
107 module_param(enable_msi, bint, 0444);
108 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
109 #ifdef CONFIG_SND_HDA_PATCH_LOADER
110 module_param_array(patch, charp, NULL, 0444);
111 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
112 #endif
113 #ifdef CONFIG_SND_HDA_INPUT_BEEP
114 module_param_array(beep_mode, bool, NULL, 0444);
115 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
116 "(0=off, 1=on) (default=1).");
117 #endif
118
119 #ifdef CONFIG_PM
120 static int param_set_xint(const char *val, const struct kernel_param *kp);
121 static struct kernel_param_ops param_ops_xint = {
122 .set = param_set_xint,
123 .get = param_get_int,
124 };
125 #define param_check_xint param_check_int
126
127 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
128 module_param(power_save, xint, 0644);
129 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
130 "(in second, 0 = disable).");
131
132 /* reset the HD-audio controller in power save mode.
133 * this may give more power-saving, but will take longer time to
134 * wake up.
135 */
136 static bool power_save_controller = 1;
137 module_param(power_save_controller, bool, 0644);
138 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
139 #endif /* CONFIG_PM */
140
141 static int align_buffer_size = -1;
142 module_param(align_buffer_size, bint, 0644);
143 MODULE_PARM_DESC(align_buffer_size,
144 "Force buffer and period sizes to be multiple of 128 bytes.");
145
146 #ifdef CONFIG_X86
147 static bool hda_snoop = true;
148 module_param_named(snoop, hda_snoop, bool, 0444);
149 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
150 #define azx_snoop(chip) (chip)->snoop
151 #else
152 #define hda_snoop true
153 #define azx_snoop(chip) true
154 #endif
155
156
157 MODULE_LICENSE("GPL");
158 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
159 "{Intel, ICH6M},"
160 "{Intel, ICH7},"
161 "{Intel, ESB2},"
162 "{Intel, ICH8},"
163 "{Intel, ICH9},"
164 "{Intel, ICH10},"
165 "{Intel, PCH},"
166 "{Intel, CPT},"
167 "{Intel, PPT},"
168 "{Intel, LPT},"
169 "{Intel, LPT_LP},"
170 "{Intel, HPT},"
171 "{Intel, PBG},"
172 "{Intel, SCH},"
173 "{ATI, SB450},"
174 "{ATI, SB600},"
175 "{ATI, RS600},"
176 "{ATI, RS690},"
177 "{ATI, RS780},"
178 "{ATI, R600},"
179 "{ATI, RV630},"
180 "{ATI, RV610},"
181 "{ATI, RV670},"
182 "{ATI, RV635},"
183 "{ATI, RV620},"
184 "{ATI, RV770},"
185 "{VIA, VT8251},"
186 "{VIA, VT8237A},"
187 "{SiS, SIS966},"
188 "{ULI, M5461}}");
189 MODULE_DESCRIPTION("Intel HDA driver");
190
191 #ifdef CONFIG_SND_VERBOSE_PRINTK
192 #define SFX /* nop */
193 #else
194 #define SFX "hda-intel: "
195 #endif
196
197 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
198 #ifdef CONFIG_SND_HDA_CODEC_HDMI
199 #define SUPPORT_VGA_SWITCHEROO
200 #endif
201 #endif
202
203
204 /*
205 * registers
206 */
207 #define ICH6_REG_GCAP 0x00
208 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
209 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
210 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
211 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
212 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
213 #define ICH6_REG_VMIN 0x02
214 #define ICH6_REG_VMAJ 0x03
215 #define ICH6_REG_OUTPAY 0x04
216 #define ICH6_REG_INPAY 0x06
217 #define ICH6_REG_GCTL 0x08
218 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
219 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
220 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
221 #define ICH6_REG_WAKEEN 0x0c
222 #define ICH6_REG_STATESTS 0x0e
223 #define ICH6_REG_GSTS 0x10
224 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
225 #define ICH6_REG_INTCTL 0x20
226 #define ICH6_REG_INTSTS 0x24
227 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
228 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
229 #define ICH6_REG_SSYNC 0x38
230 #define ICH6_REG_CORBLBASE 0x40
231 #define ICH6_REG_CORBUBASE 0x44
232 #define ICH6_REG_CORBWP 0x48
233 #define ICH6_REG_CORBRP 0x4a
234 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
235 #define ICH6_REG_CORBCTL 0x4c
236 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
237 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
238 #define ICH6_REG_CORBSTS 0x4d
239 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
240 #define ICH6_REG_CORBSIZE 0x4e
241
242 #define ICH6_REG_RIRBLBASE 0x50
243 #define ICH6_REG_RIRBUBASE 0x54
244 #define ICH6_REG_RIRBWP 0x58
245 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
246 #define ICH6_REG_RINTCNT 0x5a
247 #define ICH6_REG_RIRBCTL 0x5c
248 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
249 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
250 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
251 #define ICH6_REG_RIRBSTS 0x5d
252 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
253 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
254 #define ICH6_REG_RIRBSIZE 0x5e
255
256 #define ICH6_REG_IC 0x60
257 #define ICH6_REG_IR 0x64
258 #define ICH6_REG_IRS 0x68
259 #define ICH6_IRS_VALID (1<<1)
260 #define ICH6_IRS_BUSY (1<<0)
261
262 #define ICH6_REG_DPLBASE 0x70
263 #define ICH6_REG_DPUBASE 0x74
264 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
265
266 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
267 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
268
269 /* stream register offsets from stream base */
270 #define ICH6_REG_SD_CTL 0x00
271 #define ICH6_REG_SD_STS 0x03
272 #define ICH6_REG_SD_LPIB 0x04
273 #define ICH6_REG_SD_CBL 0x08
274 #define ICH6_REG_SD_LVI 0x0c
275 #define ICH6_REG_SD_FIFOW 0x0e
276 #define ICH6_REG_SD_FIFOSIZE 0x10
277 #define ICH6_REG_SD_FORMAT 0x12
278 #define ICH6_REG_SD_BDLPL 0x18
279 #define ICH6_REG_SD_BDLPU 0x1c
280
281 /* PCI space */
282 #define ICH6_PCIREG_TCSEL 0x44
283
284 /*
285 * other constants
286 */
287
288 /* max number of SDs */
289 /* ICH, ATI and VIA have 4 playback and 4 capture */
290 #define ICH6_NUM_CAPTURE 4
291 #define ICH6_NUM_PLAYBACK 4
292
293 /* ULI has 6 playback and 5 capture */
294 #define ULI_NUM_CAPTURE 5
295 #define ULI_NUM_PLAYBACK 6
296
297 /* ATI HDMI has 1 playback and 0 capture */
298 #define ATIHDMI_NUM_CAPTURE 0
299 #define ATIHDMI_NUM_PLAYBACK 1
300
301 /* TERA has 4 playback and 3 capture */
302 #define TERA_NUM_CAPTURE 3
303 #define TERA_NUM_PLAYBACK 4
304
305 /* this number is statically defined for simplicity */
306 #define MAX_AZX_DEV 16
307
308 /* max number of fragments - we may use more if allocating more pages for BDL */
309 #define BDL_SIZE 4096
310 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
311 #define AZX_MAX_FRAG 32
312 /* max buffer size - no h/w limit, you can increase as you like */
313 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
314
315 /* RIRB int mask: overrun[2], response[0] */
316 #define RIRB_INT_RESPONSE 0x01
317 #define RIRB_INT_OVERRUN 0x04
318 #define RIRB_INT_MASK 0x05
319
320 /* STATESTS int mask: S3,SD2,SD1,SD0 */
321 #define AZX_MAX_CODECS 8
322 #define AZX_DEFAULT_CODECS 4
323 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
324
325 /* SD_CTL bits */
326 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
327 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
328 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
329 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
330 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
331 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
332 #define SD_CTL_STREAM_TAG_SHIFT 20
333
334 /* SD_CTL and SD_STS */
335 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
336 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
337 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
338 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
339 SD_INT_COMPLETE)
340
341 /* SD_STS */
342 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
343
344 /* INTCTL and INTSTS */
345 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
346 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
347 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
348
349 /* below are so far hardcoded - should read registers in future */
350 #define ICH6_MAX_CORB_ENTRIES 256
351 #define ICH6_MAX_RIRB_ENTRIES 256
352
353 /* position fix mode */
354 enum {
355 POS_FIX_AUTO,
356 POS_FIX_LPIB,
357 POS_FIX_POSBUF,
358 POS_FIX_VIACOMBO,
359 POS_FIX_COMBO,
360 };
361
362 /* Defines for ATI HD Audio support in SB450 south bridge */
363 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
364 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
365
366 /* Defines for Nvidia HDA support */
367 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
368 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
369 #define NVIDIA_HDA_ISTRM_COH 0x4d
370 #define NVIDIA_HDA_OSTRM_COH 0x4c
371 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
372
373 /* Defines for Intel SCH HDA snoop control */
374 #define INTEL_SCH_HDA_DEVC 0x78
375 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
376
377 /* Define IN stream 0 FIFO size offset in VIA controller */
378 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
379 /* Define VIA HD Audio Device ID*/
380 #define VIA_HDAC_DEVICE_ID 0x3288
381
382 /* HD Audio class code */
383 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
384
385 /*
386 */
387
388 struct azx_dev {
389 struct snd_dma_buffer bdl; /* BDL buffer */
390 u32 *posbuf; /* position buffer pointer */
391
392 unsigned int bufsize; /* size of the play buffer in bytes */
393 unsigned int period_bytes; /* size of the period in bytes */
394 unsigned int frags; /* number for period in the play buffer */
395 unsigned int fifo_size; /* FIFO size */
396 unsigned long start_wallclk; /* start + minimum wallclk */
397 unsigned long period_wallclk; /* wallclk for period */
398
399 void __iomem *sd_addr; /* stream descriptor pointer */
400
401 u32 sd_int_sta_mask; /* stream int status mask */
402
403 /* pcm support */
404 struct snd_pcm_substream *substream; /* assigned substream,
405 * set in PCM open
406 */
407 unsigned int format_val; /* format value to be set in the
408 * controller and the codec
409 */
410 unsigned char stream_tag; /* assigned stream */
411 unsigned char index; /* stream index */
412 int assigned_key; /* last device# key assigned to */
413
414 unsigned int opened :1;
415 unsigned int running :1;
416 unsigned int irq_pending :1;
417 /*
418 * For VIA:
419 * A flag to ensure DMA position is 0
420 * when link position is not greater than FIFO size
421 */
422 unsigned int insufficient :1;
423 unsigned int wc_marked:1;
424 unsigned int no_period_wakeup:1;
425
426 struct timecounter azx_tc;
427 struct cyclecounter azx_cc;
428 };
429
430 /* CORB/RIRB */
431 struct azx_rb {
432 u32 *buf; /* CORB/RIRB buffer
433 * Each CORB entry is 4byte, RIRB is 8byte
434 */
435 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
436 /* for RIRB */
437 unsigned short rp, wp; /* read/write pointers */
438 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
439 u32 res[AZX_MAX_CODECS]; /* last read value */
440 };
441
442 struct azx_pcm {
443 struct azx *chip;
444 struct snd_pcm *pcm;
445 struct hda_codec *codec;
446 struct hda_pcm_stream *hinfo[2];
447 struct list_head list;
448 };
449
450 struct azx {
451 struct snd_card *card;
452 struct pci_dev *pci;
453 int dev_index;
454
455 /* chip type specific */
456 int driver_type;
457 unsigned int driver_caps;
458 int playback_streams;
459 int playback_index_offset;
460 int capture_streams;
461 int capture_index_offset;
462 int num_streams;
463
464 /* pci resources */
465 unsigned long addr;
466 void __iomem *remap_addr;
467 int irq;
468
469 /* locks */
470 spinlock_t reg_lock;
471 struct mutex open_mutex;
472
473 /* streams (x num_streams) */
474 struct azx_dev *azx_dev;
475
476 /* PCM */
477 struct list_head pcm_list; /* azx_pcm list */
478
479 /* HD codec */
480 unsigned short codec_mask;
481 int codec_probe_mask; /* copied from probe_mask option */
482 struct hda_bus *bus;
483 unsigned int beep_mode;
484
485 /* CORB/RIRB */
486 struct azx_rb corb;
487 struct azx_rb rirb;
488
489 /* CORB/RIRB and position buffers */
490 struct snd_dma_buffer rb;
491 struct snd_dma_buffer posbuf;
492
493 #ifdef CONFIG_SND_HDA_PATCH_LOADER
494 const struct firmware *fw;
495 #endif
496
497 /* flags */
498 int position_fix[2]; /* for both playback/capture streams */
499 int poll_count;
500 unsigned int running :1;
501 unsigned int initialized :1;
502 unsigned int single_cmd :1;
503 unsigned int polling_mode :1;
504 unsigned int msi :1;
505 unsigned int irq_pending_warned :1;
506 unsigned int probing :1; /* codec probing phase */
507 unsigned int snoop:1;
508 unsigned int align_buffer_size:1;
509 unsigned int region_requested:1;
510
511 /* VGA-switcheroo setup */
512 unsigned int use_vga_switcheroo:1;
513 unsigned int vga_switcheroo_registered:1;
514 unsigned int init_failed:1; /* delayed init failed */
515 unsigned int disabled:1; /* disabled by VGA-switcher */
516
517 /* for debugging */
518 unsigned int last_cmd[AZX_MAX_CODECS];
519
520 /* for pending irqs */
521 struct work_struct irq_pending_work;
522
523 /* reboot notifier (for mysterious hangup problem at power-down) */
524 struct notifier_block reboot_notifier;
525
526 /* card list (for power_save trigger) */
527 struct list_head list;
528 };
529
530 #define CREATE_TRACE_POINTS
531 #include "hda_intel_trace.h"
532
533 /* driver types */
534 enum {
535 AZX_DRIVER_ICH,
536 AZX_DRIVER_PCH,
537 AZX_DRIVER_SCH,
538 AZX_DRIVER_ATI,
539 AZX_DRIVER_ATIHDMI,
540 AZX_DRIVER_ATIHDMI_NS,
541 AZX_DRIVER_VIA,
542 AZX_DRIVER_SIS,
543 AZX_DRIVER_ULI,
544 AZX_DRIVER_NVIDIA,
545 AZX_DRIVER_TERA,
546 AZX_DRIVER_CTX,
547 AZX_DRIVER_CTHDA,
548 AZX_DRIVER_GENERIC,
549 AZX_NUM_DRIVERS, /* keep this as last entry */
550 };
551
552 /* driver quirks (capabilities) */
553 /* bits 0-7 are used for indicating driver type */
554 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
555 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
556 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
557 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
558 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
559 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
560 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
561 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
562 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
563 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
564 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
565 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
566 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
567 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
568 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
569 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
570 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
571
572 /* quirks for ATI SB / AMD Hudson */
573 #define AZX_DCAPS_PRESET_ATI_SB \
574 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
575 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
576
577 /* quirks for ATI/AMD HDMI */
578 #define AZX_DCAPS_PRESET_ATI_HDMI \
579 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
580
581 /* quirks for Nvidia */
582 #define AZX_DCAPS_PRESET_NVIDIA \
583 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
584 AZX_DCAPS_ALIGN_BUFSIZE)
585
586 #define AZX_DCAPS_PRESET_CTHDA \
587 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
588
589 /*
590 * VGA-switcher support
591 */
592 #ifdef SUPPORT_VGA_SWITCHEROO
593 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
594 #else
595 #define use_vga_switcheroo(chip) 0
596 #endif
597
598 #if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
599 #define DELAYED_INIT_MARK
600 #define DELAYED_INITDATA_MARK
601 #else
602 #define DELAYED_INIT_MARK __devinit
603 #define DELAYED_INITDATA_MARK __devinitdata
604 #endif
605
606 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
607 [AZX_DRIVER_ICH] = "HDA Intel",
608 [AZX_DRIVER_PCH] = "HDA Intel PCH",
609 [AZX_DRIVER_SCH] = "HDA Intel MID",
610 [AZX_DRIVER_ATI] = "HDA ATI SB",
611 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
612 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
613 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
614 [AZX_DRIVER_SIS] = "HDA SIS966",
615 [AZX_DRIVER_ULI] = "HDA ULI M5461",
616 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
617 [AZX_DRIVER_TERA] = "HDA Teradici",
618 [AZX_DRIVER_CTX] = "HDA Creative",
619 [AZX_DRIVER_CTHDA] = "HDA Creative",
620 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
621 };
622
623 /*
624 * macros for easy use
625 */
626 #define azx_writel(chip,reg,value) \
627 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
628 #define azx_readl(chip,reg) \
629 readl((chip)->remap_addr + ICH6_REG_##reg)
630 #define azx_writew(chip,reg,value) \
631 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
632 #define azx_readw(chip,reg) \
633 readw((chip)->remap_addr + ICH6_REG_##reg)
634 #define azx_writeb(chip,reg,value) \
635 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
636 #define azx_readb(chip,reg) \
637 readb((chip)->remap_addr + ICH6_REG_##reg)
638
639 #define azx_sd_writel(dev,reg,value) \
640 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
641 #define azx_sd_readl(dev,reg) \
642 readl((dev)->sd_addr + ICH6_REG_##reg)
643 #define azx_sd_writew(dev,reg,value) \
644 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
645 #define azx_sd_readw(dev,reg) \
646 readw((dev)->sd_addr + ICH6_REG_##reg)
647 #define azx_sd_writeb(dev,reg,value) \
648 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
649 #define azx_sd_readb(dev,reg) \
650 readb((dev)->sd_addr + ICH6_REG_##reg)
651
652 /* for pcm support */
653 #define get_azx_dev(substream) (substream->runtime->private_data)
654
655 #ifdef CONFIG_X86
656 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
657 {
658 if (azx_snoop(chip))
659 return;
660 if (addr && size) {
661 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
662 if (on)
663 set_memory_wc((unsigned long)addr, pages);
664 else
665 set_memory_wb((unsigned long)addr, pages);
666 }
667 }
668
669 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
670 bool on)
671 {
672 __mark_pages_wc(chip, buf->area, buf->bytes, on);
673 }
674 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
675 struct snd_pcm_runtime *runtime, bool on)
676 {
677 if (azx_dev->wc_marked != on) {
678 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
679 azx_dev->wc_marked = on;
680 }
681 }
682 #else
683 /* NOP for other archs */
684 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
685 bool on)
686 {
687 }
688 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
689 struct snd_pcm_runtime *runtime, bool on)
690 {
691 }
692 #endif
693
694 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
695 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
696 /*
697 * Interface for HD codec
698 */
699
700 /*
701 * CORB / RIRB interface
702 */
703 static int azx_alloc_cmd_io(struct azx *chip)
704 {
705 int err;
706
707 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
708 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
709 snd_dma_pci_data(chip->pci),
710 PAGE_SIZE, &chip->rb);
711 if (err < 0) {
712 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
713 return err;
714 }
715 mark_pages_wc(chip, &chip->rb, true);
716 return 0;
717 }
718
719 static void azx_init_cmd_io(struct azx *chip)
720 {
721 spin_lock_irq(&chip->reg_lock);
722 /* CORB set up */
723 chip->corb.addr = chip->rb.addr;
724 chip->corb.buf = (u32 *)chip->rb.area;
725 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
726 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
727
728 /* set the corb size to 256 entries (ULI requires explicitly) */
729 azx_writeb(chip, CORBSIZE, 0x02);
730 /* set the corb write pointer to 0 */
731 azx_writew(chip, CORBWP, 0);
732 /* reset the corb hw read pointer */
733 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
734 /* enable corb dma */
735 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
736
737 /* RIRB set up */
738 chip->rirb.addr = chip->rb.addr + 2048;
739 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
740 chip->rirb.wp = chip->rirb.rp = 0;
741 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
742 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
743 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
744
745 /* set the rirb size to 256 entries (ULI requires explicitly) */
746 azx_writeb(chip, RIRBSIZE, 0x02);
747 /* reset the rirb hw write pointer */
748 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
749 /* set N=1, get RIRB response interrupt for new entry */
750 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
751 azx_writew(chip, RINTCNT, 0xc0);
752 else
753 azx_writew(chip, RINTCNT, 1);
754 /* enable rirb dma and response irq */
755 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
756 spin_unlock_irq(&chip->reg_lock);
757 }
758
759 static void azx_free_cmd_io(struct azx *chip)
760 {
761 spin_lock_irq(&chip->reg_lock);
762 /* disable ringbuffer DMAs */
763 azx_writeb(chip, RIRBCTL, 0);
764 azx_writeb(chip, CORBCTL, 0);
765 spin_unlock_irq(&chip->reg_lock);
766 }
767
768 static unsigned int azx_command_addr(u32 cmd)
769 {
770 unsigned int addr = cmd >> 28;
771
772 if (addr >= AZX_MAX_CODECS) {
773 snd_BUG();
774 addr = 0;
775 }
776
777 return addr;
778 }
779
780 static unsigned int azx_response_addr(u32 res)
781 {
782 unsigned int addr = res & 0xf;
783
784 if (addr >= AZX_MAX_CODECS) {
785 snd_BUG();
786 addr = 0;
787 }
788
789 return addr;
790 }
791
792 /* send a command */
793 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
794 {
795 struct azx *chip = bus->private_data;
796 unsigned int addr = azx_command_addr(val);
797 unsigned int wp;
798
799 spin_lock_irq(&chip->reg_lock);
800
801 /* add command to corb */
802 wp = azx_readb(chip, CORBWP);
803 wp++;
804 wp %= ICH6_MAX_CORB_ENTRIES;
805
806 chip->rirb.cmds[addr]++;
807 chip->corb.buf[wp] = cpu_to_le32(val);
808 azx_writel(chip, CORBWP, wp);
809
810 spin_unlock_irq(&chip->reg_lock);
811
812 return 0;
813 }
814
815 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
816
817 /* retrieve RIRB entry - called from interrupt handler */
818 static void azx_update_rirb(struct azx *chip)
819 {
820 unsigned int rp, wp;
821 unsigned int addr;
822 u32 res, res_ex;
823
824 wp = azx_readb(chip, RIRBWP);
825 if (wp == chip->rirb.wp)
826 return;
827 chip->rirb.wp = wp;
828
829 while (chip->rirb.rp != wp) {
830 chip->rirb.rp++;
831 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
832
833 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
834 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
835 res = le32_to_cpu(chip->rirb.buf[rp]);
836 addr = azx_response_addr(res_ex);
837 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
838 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
839 else if (chip->rirb.cmds[addr]) {
840 chip->rirb.res[addr] = res;
841 smp_wmb();
842 chip->rirb.cmds[addr]--;
843 } else
844 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
845 "last cmd=%#08x\n",
846 pci_name(chip->pci),
847 res, res_ex,
848 chip->last_cmd[addr]);
849 }
850 }
851
852 /* receive a response */
853 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
854 unsigned int addr)
855 {
856 struct azx *chip = bus->private_data;
857 unsigned long timeout;
858 unsigned long loopcounter;
859 int do_poll = 0;
860
861 again:
862 timeout = jiffies + msecs_to_jiffies(1000);
863
864 for (loopcounter = 0;; loopcounter++) {
865 if (chip->polling_mode || do_poll) {
866 spin_lock_irq(&chip->reg_lock);
867 azx_update_rirb(chip);
868 spin_unlock_irq(&chip->reg_lock);
869 }
870 if (!chip->rirb.cmds[addr]) {
871 smp_rmb();
872 bus->rirb_error = 0;
873
874 if (!do_poll)
875 chip->poll_count = 0;
876 return chip->rirb.res[addr]; /* the last value */
877 }
878 if (time_after(jiffies, timeout))
879 break;
880 if (bus->needs_damn_long_delay || loopcounter > 3000)
881 msleep(2); /* temporary workaround */
882 else {
883 udelay(10);
884 cond_resched();
885 }
886 }
887
888 if (!chip->polling_mode && chip->poll_count < 2) {
889 snd_printdd(SFX "azx_get_response timeout, "
890 "polling the codec once: last cmd=0x%08x\n",
891 chip->last_cmd[addr]);
892 do_poll = 1;
893 chip->poll_count++;
894 goto again;
895 }
896
897
898 if (!chip->polling_mode) {
899 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
900 "switching to polling mode: last cmd=0x%08x\n",
901 chip->last_cmd[addr]);
902 chip->polling_mode = 1;
903 goto again;
904 }
905
906 if (chip->msi) {
907 snd_printk(KERN_WARNING SFX "No response from codec, "
908 "disabling MSI: last cmd=0x%08x\n",
909 chip->last_cmd[addr]);
910 free_irq(chip->irq, chip);
911 chip->irq = -1;
912 pci_disable_msi(chip->pci);
913 chip->msi = 0;
914 if (azx_acquire_irq(chip, 1) < 0) {
915 bus->rirb_error = 1;
916 return -1;
917 }
918 goto again;
919 }
920
921 if (chip->probing) {
922 /* If this critical timeout happens during the codec probing
923 * phase, this is likely an access to a non-existing codec
924 * slot. Better to return an error and reset the system.
925 */
926 return -1;
927 }
928
929 /* a fatal communication error; need either to reset or to fallback
930 * to the single_cmd mode
931 */
932 bus->rirb_error = 1;
933 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
934 bus->response_reset = 1;
935 return -1; /* give a chance to retry */
936 }
937
938 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
939 "switching to single_cmd mode: last cmd=0x%08x\n",
940 chip->last_cmd[addr]);
941 chip->single_cmd = 1;
942 bus->response_reset = 0;
943 /* release CORB/RIRB */
944 azx_free_cmd_io(chip);
945 /* disable unsolicited responses */
946 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
947 return -1;
948 }
949
950 /*
951 * Use the single immediate command instead of CORB/RIRB for simplicity
952 *
953 * Note: according to Intel, this is not preferred use. The command was
954 * intended for the BIOS only, and may get confused with unsolicited
955 * responses. So, we shouldn't use it for normal operation from the
956 * driver.
957 * I left the codes, however, for debugging/testing purposes.
958 */
959
960 /* receive a response */
961 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
962 {
963 int timeout = 50;
964
965 while (timeout--) {
966 /* check IRV busy bit */
967 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
968 /* reuse rirb.res as the response return value */
969 chip->rirb.res[addr] = azx_readl(chip, IR);
970 return 0;
971 }
972 udelay(1);
973 }
974 if (printk_ratelimit())
975 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
976 azx_readw(chip, IRS));
977 chip->rirb.res[addr] = -1;
978 return -EIO;
979 }
980
981 /* send a command */
982 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
983 {
984 struct azx *chip = bus->private_data;
985 unsigned int addr = azx_command_addr(val);
986 int timeout = 50;
987
988 bus->rirb_error = 0;
989 while (timeout--) {
990 /* check ICB busy bit */
991 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
992 /* Clear IRV valid bit */
993 azx_writew(chip, IRS, azx_readw(chip, IRS) |
994 ICH6_IRS_VALID);
995 azx_writel(chip, IC, val);
996 azx_writew(chip, IRS, azx_readw(chip, IRS) |
997 ICH6_IRS_BUSY);
998 return azx_single_wait_for_response(chip, addr);
999 }
1000 udelay(1);
1001 }
1002 if (printk_ratelimit())
1003 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
1004 azx_readw(chip, IRS), val);
1005 return -EIO;
1006 }
1007
1008 /* receive a response */
1009 static unsigned int azx_single_get_response(struct hda_bus *bus,
1010 unsigned int addr)
1011 {
1012 struct azx *chip = bus->private_data;
1013 return chip->rirb.res[addr];
1014 }
1015
1016 /*
1017 * The below are the main callbacks from hda_codec.
1018 *
1019 * They are just the skeleton to call sub-callbacks according to the
1020 * current setting of chip->single_cmd.
1021 */
1022
1023 /* send a command */
1024 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1025 {
1026 struct azx *chip = bus->private_data;
1027
1028 if (chip->disabled)
1029 return 0;
1030 chip->last_cmd[azx_command_addr(val)] = val;
1031 if (chip->single_cmd)
1032 return azx_single_send_cmd(bus, val);
1033 else
1034 return azx_corb_send_cmd(bus, val);
1035 }
1036
1037 /* get a response */
1038 static unsigned int azx_get_response(struct hda_bus *bus,
1039 unsigned int addr)
1040 {
1041 struct azx *chip = bus->private_data;
1042 if (chip->disabled)
1043 return 0;
1044 if (chip->single_cmd)
1045 return azx_single_get_response(bus, addr);
1046 else
1047 return azx_rirb_get_response(bus, addr);
1048 }
1049
1050 #ifdef CONFIG_PM
1051 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1052 #endif
1053
1054 /* reset codec link */
1055 static int azx_reset(struct azx *chip, int full_reset)
1056 {
1057 int count;
1058
1059 if (!full_reset)
1060 goto __skip;
1061
1062 /* clear STATESTS */
1063 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1064
1065 /* reset controller */
1066 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1067
1068 count = 50;
1069 while (azx_readb(chip, GCTL) && --count)
1070 msleep(1);
1071
1072 /* delay for >= 100us for codec PLL to settle per spec
1073 * Rev 0.9 section 5.5.1
1074 */
1075 msleep(1);
1076
1077 /* Bring controller out of reset */
1078 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1079
1080 count = 50;
1081 while (!azx_readb(chip, GCTL) && --count)
1082 msleep(1);
1083
1084 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1085 msleep(1);
1086
1087 __skip:
1088 /* check to see if controller is ready */
1089 if (!azx_readb(chip, GCTL)) {
1090 snd_printd(SFX "azx_reset: controller not ready!\n");
1091 return -EBUSY;
1092 }
1093
1094 /* Accept unsolicited responses */
1095 if (!chip->single_cmd)
1096 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1097 ICH6_GCTL_UNSOL);
1098
1099 /* detect codecs */
1100 if (!chip->codec_mask) {
1101 chip->codec_mask = azx_readw(chip, STATESTS);
1102 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1103 }
1104
1105 return 0;
1106 }
1107
1108
1109 /*
1110 * Lowlevel interface
1111 */
1112
1113 /* enable interrupts */
1114 static void azx_int_enable(struct azx *chip)
1115 {
1116 /* enable controller CIE and GIE */
1117 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1118 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1119 }
1120
1121 /* disable interrupts */
1122 static void azx_int_disable(struct azx *chip)
1123 {
1124 int i;
1125
1126 /* disable interrupts in stream descriptor */
1127 for (i = 0; i < chip->num_streams; i++) {
1128 struct azx_dev *azx_dev = &chip->azx_dev[i];
1129 azx_sd_writeb(azx_dev, SD_CTL,
1130 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1131 }
1132
1133 /* disable SIE for all streams */
1134 azx_writeb(chip, INTCTL, 0);
1135
1136 /* disable controller CIE and GIE */
1137 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1138 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1139 }
1140
1141 /* clear interrupts */
1142 static void azx_int_clear(struct azx *chip)
1143 {
1144 int i;
1145
1146 /* clear stream status */
1147 for (i = 0; i < chip->num_streams; i++) {
1148 struct azx_dev *azx_dev = &chip->azx_dev[i];
1149 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1150 }
1151
1152 /* clear STATESTS */
1153 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1154
1155 /* clear rirb status */
1156 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1157
1158 /* clear int status */
1159 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1160 }
1161
1162 /* start a stream */
1163 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1164 {
1165 /*
1166 * Before stream start, initialize parameter
1167 */
1168 azx_dev->insufficient = 1;
1169
1170 /* enable SIE */
1171 azx_writel(chip, INTCTL,
1172 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1173 /* set DMA start and interrupt mask */
1174 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1175 SD_CTL_DMA_START | SD_INT_MASK);
1176 }
1177
1178 /* stop DMA */
1179 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1180 {
1181 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1182 ~(SD_CTL_DMA_START | SD_INT_MASK));
1183 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1184 }
1185
1186 /* stop a stream */
1187 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1188 {
1189 azx_stream_clear(chip, azx_dev);
1190 /* disable SIE */
1191 azx_writel(chip, INTCTL,
1192 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1193 }
1194
1195
1196 /*
1197 * reset and start the controller registers
1198 */
1199 static void azx_init_chip(struct azx *chip, int full_reset)
1200 {
1201 if (chip->initialized)
1202 return;
1203
1204 /* reset controller */
1205 azx_reset(chip, full_reset);
1206
1207 /* initialize interrupts */
1208 azx_int_clear(chip);
1209 azx_int_enable(chip);
1210
1211 /* initialize the codec command I/O */
1212 if (!chip->single_cmd)
1213 azx_init_cmd_io(chip);
1214
1215 /* program the position buffer */
1216 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1217 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1218
1219 chip->initialized = 1;
1220 }
1221
1222 /*
1223 * initialize the PCI registers
1224 */
1225 /* update bits in a PCI register byte */
1226 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1227 unsigned char mask, unsigned char val)
1228 {
1229 unsigned char data;
1230
1231 pci_read_config_byte(pci, reg, &data);
1232 data &= ~mask;
1233 data |= (val & mask);
1234 pci_write_config_byte(pci, reg, data);
1235 }
1236
1237 static void azx_init_pci(struct azx *chip)
1238 {
1239 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1240 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1241 * Ensuring these bits are 0 clears playback static on some HD Audio
1242 * codecs.
1243 * The PCI register TCSEL is defined in the Intel manuals.
1244 */
1245 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1246 snd_printdd(SFX "Clearing TCSEL\n");
1247 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1248 }
1249
1250 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1251 * we need to enable snoop.
1252 */
1253 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1254 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1255 update_pci_byte(chip->pci,
1256 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1257 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1258 }
1259
1260 /* For NVIDIA HDA, enable snoop */
1261 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1262 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1263 update_pci_byte(chip->pci,
1264 NVIDIA_HDA_TRANSREG_ADDR,
1265 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1266 update_pci_byte(chip->pci,
1267 NVIDIA_HDA_ISTRM_COH,
1268 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1269 update_pci_byte(chip->pci,
1270 NVIDIA_HDA_OSTRM_COH,
1271 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1272 }
1273
1274 /* Enable SCH/PCH snoop if needed */
1275 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1276 unsigned short snoop;
1277 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1278 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1279 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1280 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1281 if (!azx_snoop(chip))
1282 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1283 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1284 pci_read_config_word(chip->pci,
1285 INTEL_SCH_HDA_DEVC, &snoop);
1286 }
1287 snd_printdd(SFX "SCH snoop: %s\n",
1288 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1289 ? "Disabled" : "Enabled");
1290 }
1291 }
1292
1293
1294 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1295
1296 /*
1297 * interrupt handler
1298 */
1299 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1300 {
1301 struct azx *chip = dev_id;
1302 struct azx_dev *azx_dev;
1303 u32 status;
1304 u8 sd_status;
1305 int i, ok;
1306
1307 #ifdef CONFIG_PM_RUNTIME
1308 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1309 return IRQ_NONE;
1310 #endif
1311
1312 spin_lock(&chip->reg_lock);
1313
1314 if (chip->disabled) {
1315 spin_unlock(&chip->reg_lock);
1316 return IRQ_NONE;
1317 }
1318
1319 status = azx_readl(chip, INTSTS);
1320 if (status == 0) {
1321 spin_unlock(&chip->reg_lock);
1322 return IRQ_NONE;
1323 }
1324
1325 for (i = 0; i < chip->num_streams; i++) {
1326 azx_dev = &chip->azx_dev[i];
1327 if (status & azx_dev->sd_int_sta_mask) {
1328 sd_status = azx_sd_readb(azx_dev, SD_STS);
1329 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1330 if (!azx_dev->substream || !azx_dev->running ||
1331 !(sd_status & SD_INT_COMPLETE))
1332 continue;
1333 /* check whether this IRQ is really acceptable */
1334 ok = azx_position_ok(chip, azx_dev);
1335 if (ok == 1) {
1336 azx_dev->irq_pending = 0;
1337 spin_unlock(&chip->reg_lock);
1338 snd_pcm_period_elapsed(azx_dev->substream);
1339 spin_lock(&chip->reg_lock);
1340 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1341 /* bogus IRQ, process it later */
1342 azx_dev->irq_pending = 1;
1343 queue_work(chip->bus->workq,
1344 &chip->irq_pending_work);
1345 }
1346 }
1347 }
1348
1349 /* clear rirb int */
1350 status = azx_readb(chip, RIRBSTS);
1351 if (status & RIRB_INT_MASK) {
1352 if (status & RIRB_INT_RESPONSE) {
1353 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1354 udelay(80);
1355 azx_update_rirb(chip);
1356 }
1357 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1358 }
1359
1360 #if 0
1361 /* clear state status int */
1362 if (azx_readb(chip, STATESTS) & 0x04)
1363 azx_writeb(chip, STATESTS, 0x04);
1364 #endif
1365 spin_unlock(&chip->reg_lock);
1366
1367 return IRQ_HANDLED;
1368 }
1369
1370
1371 /*
1372 * set up a BDL entry
1373 */
1374 static int setup_bdle(struct azx *chip,
1375 struct snd_pcm_substream *substream,
1376 struct azx_dev *azx_dev, u32 **bdlp,
1377 int ofs, int size, int with_ioc)
1378 {
1379 u32 *bdl = *bdlp;
1380
1381 while (size > 0) {
1382 dma_addr_t addr;
1383 int chunk;
1384
1385 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1386 return -EINVAL;
1387
1388 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1389 /* program the address field of the BDL entry */
1390 bdl[0] = cpu_to_le32((u32)addr);
1391 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1392 /* program the size field of the BDL entry */
1393 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1394 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1395 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1396 u32 remain = 0x1000 - (ofs & 0xfff);
1397 if (chunk > remain)
1398 chunk = remain;
1399 }
1400 bdl[2] = cpu_to_le32(chunk);
1401 /* program the IOC to enable interrupt
1402 * only when the whole fragment is processed
1403 */
1404 size -= chunk;
1405 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1406 bdl += 4;
1407 azx_dev->frags++;
1408 ofs += chunk;
1409 }
1410 *bdlp = bdl;
1411 return ofs;
1412 }
1413
1414 /*
1415 * set up BDL entries
1416 */
1417 static int azx_setup_periods(struct azx *chip,
1418 struct snd_pcm_substream *substream,
1419 struct azx_dev *azx_dev)
1420 {
1421 u32 *bdl;
1422 int i, ofs, periods, period_bytes;
1423 int pos_adj;
1424
1425 /* reset BDL address */
1426 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1427 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1428
1429 period_bytes = azx_dev->period_bytes;
1430 periods = azx_dev->bufsize / period_bytes;
1431
1432 /* program the initial BDL entries */
1433 bdl = (u32 *)azx_dev->bdl.area;
1434 ofs = 0;
1435 azx_dev->frags = 0;
1436 pos_adj = bdl_pos_adj[chip->dev_index];
1437 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1438 struct snd_pcm_runtime *runtime = substream->runtime;
1439 int pos_align = pos_adj;
1440 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1441 if (!pos_adj)
1442 pos_adj = pos_align;
1443 else
1444 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1445 pos_align;
1446 pos_adj = frames_to_bytes(runtime, pos_adj);
1447 if (pos_adj >= period_bytes) {
1448 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1449 bdl_pos_adj[chip->dev_index]);
1450 pos_adj = 0;
1451 } else {
1452 ofs = setup_bdle(chip, substream, azx_dev,
1453 &bdl, ofs, pos_adj, true);
1454 if (ofs < 0)
1455 goto error;
1456 }
1457 } else
1458 pos_adj = 0;
1459 for (i = 0; i < periods; i++) {
1460 if (i == periods - 1 && pos_adj)
1461 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1462 period_bytes - pos_adj, 0);
1463 else
1464 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1465 period_bytes,
1466 !azx_dev->no_period_wakeup);
1467 if (ofs < 0)
1468 goto error;
1469 }
1470 return 0;
1471
1472 error:
1473 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1474 azx_dev->bufsize, period_bytes);
1475 return -EINVAL;
1476 }
1477
1478 /* reset stream */
1479 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1480 {
1481 unsigned char val;
1482 int timeout;
1483
1484 azx_stream_clear(chip, azx_dev);
1485
1486 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1487 SD_CTL_STREAM_RESET);
1488 udelay(3);
1489 timeout = 300;
1490 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1491 --timeout)
1492 ;
1493 val &= ~SD_CTL_STREAM_RESET;
1494 azx_sd_writeb(azx_dev, SD_CTL, val);
1495 udelay(3);
1496
1497 timeout = 300;
1498 /* waiting for hardware to report that the stream is out of reset */
1499 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1500 --timeout)
1501 ;
1502
1503 /* reset first position - may not be synced with hw at this time */
1504 *azx_dev->posbuf = 0;
1505 }
1506
1507 /*
1508 * set up the SD for streaming
1509 */
1510 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1511 {
1512 unsigned int val;
1513 /* make sure the run bit is zero for SD */
1514 azx_stream_clear(chip, azx_dev);
1515 /* program the stream_tag */
1516 val = azx_sd_readl(azx_dev, SD_CTL);
1517 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1518 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1519 if (!azx_snoop(chip))
1520 val |= SD_CTL_TRAFFIC_PRIO;
1521 azx_sd_writel(azx_dev, SD_CTL, val);
1522
1523 /* program the length of samples in cyclic buffer */
1524 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1525
1526 /* program the stream format */
1527 /* this value needs to be the same as the one programmed */
1528 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1529
1530 /* program the stream LVI (last valid index) of the BDL */
1531 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1532
1533 /* program the BDL address */
1534 /* lower BDL address */
1535 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1536 /* upper BDL address */
1537 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1538
1539 /* enable the position buffer */
1540 if (chip->position_fix[0] != POS_FIX_LPIB ||
1541 chip->position_fix[1] != POS_FIX_LPIB) {
1542 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1543 azx_writel(chip, DPLBASE,
1544 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1545 }
1546
1547 /* set the interrupt enable bits in the descriptor control register */
1548 azx_sd_writel(azx_dev, SD_CTL,
1549 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1550
1551 return 0;
1552 }
1553
1554 /*
1555 * Probe the given codec address
1556 */
1557 static int probe_codec(struct azx *chip, int addr)
1558 {
1559 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1560 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1561 unsigned int res;
1562
1563 mutex_lock(&chip->bus->cmd_mutex);
1564 chip->probing = 1;
1565 azx_send_cmd(chip->bus, cmd);
1566 res = azx_get_response(chip->bus, addr);
1567 chip->probing = 0;
1568 mutex_unlock(&chip->bus->cmd_mutex);
1569 if (res == -1)
1570 return -EIO;
1571 snd_printdd(SFX "codec #%d probed OK\n", addr);
1572 return 0;
1573 }
1574
1575 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1576 struct hda_pcm *cpcm);
1577 static void azx_stop_chip(struct azx *chip);
1578
1579 static void azx_bus_reset(struct hda_bus *bus)
1580 {
1581 struct azx *chip = bus->private_data;
1582
1583 bus->in_reset = 1;
1584 azx_stop_chip(chip);
1585 azx_init_chip(chip, 1);
1586 #ifdef CONFIG_PM
1587 if (chip->initialized) {
1588 struct azx_pcm *p;
1589 list_for_each_entry(p, &chip->pcm_list, list)
1590 snd_pcm_suspend_all(p->pcm);
1591 snd_hda_suspend(chip->bus);
1592 snd_hda_resume(chip->bus);
1593 }
1594 #endif
1595 bus->in_reset = 0;
1596 }
1597
1598 static int get_jackpoll_interval(struct azx *chip)
1599 {
1600 int i = jackpoll_ms[chip->dev_index];
1601 unsigned int j;
1602 if (i == 0)
1603 return 0;
1604 if (i < 50 || i > 60000)
1605 j = 0;
1606 else
1607 j = msecs_to_jiffies(i);
1608 if (j == 0)
1609 snd_printk(KERN_WARNING SFX
1610 "jackpoll_ms value out of range: %d\n", i);
1611 return j;
1612 }
1613
1614 /*
1615 * Codec initialization
1616 */
1617
1618 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1619 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1620 [AZX_DRIVER_NVIDIA] = 8,
1621 [AZX_DRIVER_TERA] = 1,
1622 };
1623
1624 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1625 {
1626 struct hda_bus_template bus_temp;
1627 int c, codecs, err;
1628 int max_slots;
1629
1630 memset(&bus_temp, 0, sizeof(bus_temp));
1631 bus_temp.private_data = chip;
1632 bus_temp.modelname = model;
1633 bus_temp.pci = chip->pci;
1634 bus_temp.ops.command = azx_send_cmd;
1635 bus_temp.ops.get_response = azx_get_response;
1636 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1637 bus_temp.ops.bus_reset = azx_bus_reset;
1638 #ifdef CONFIG_PM
1639 bus_temp.power_save = &power_save;
1640 bus_temp.ops.pm_notify = azx_power_notify;
1641 #endif
1642
1643 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1644 if (err < 0)
1645 return err;
1646
1647 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1648 snd_printd(SFX "Enable delay in RIRB handling\n");
1649 chip->bus->needs_damn_long_delay = 1;
1650 }
1651
1652 codecs = 0;
1653 max_slots = azx_max_codecs[chip->driver_type];
1654 if (!max_slots)
1655 max_slots = AZX_DEFAULT_CODECS;
1656
1657 /* First try to probe all given codec slots */
1658 for (c = 0; c < max_slots; c++) {
1659 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1660 if (probe_codec(chip, c) < 0) {
1661 /* Some BIOSen give you wrong codec addresses
1662 * that don't exist
1663 */
1664 snd_printk(KERN_WARNING SFX
1665 "Codec #%d probe error; "
1666 "disabling it...\n", c);
1667 chip->codec_mask &= ~(1 << c);
1668 /* More badly, accessing to a non-existing
1669 * codec often screws up the controller chip,
1670 * and disturbs the further communications.
1671 * Thus if an error occurs during probing,
1672 * better to reset the controller chip to
1673 * get back to the sanity state.
1674 */
1675 azx_stop_chip(chip);
1676 azx_init_chip(chip, 1);
1677 }
1678 }
1679 }
1680
1681 /* AMD chipsets often cause the communication stalls upon certain
1682 * sequence like the pin-detection. It seems that forcing the synced
1683 * access works around the stall. Grrr...
1684 */
1685 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1686 snd_printd(SFX "Enable sync_write for stable communication\n");
1687 chip->bus->sync_write = 1;
1688 chip->bus->allow_bus_reset = 1;
1689 }
1690
1691 /* Then create codec instances */
1692 for (c = 0; c < max_slots; c++) {
1693 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1694 struct hda_codec *codec;
1695 err = snd_hda_codec_new(chip->bus, c, &codec);
1696 if (err < 0)
1697 continue;
1698 codec->jackpoll_interval = get_jackpoll_interval(chip);
1699 codec->beep_mode = chip->beep_mode;
1700 codecs++;
1701 }
1702 }
1703 if (!codecs) {
1704 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1705 return -ENXIO;
1706 }
1707 return 0;
1708 }
1709
1710 /* configure each codec instance */
1711 static int __devinit azx_codec_configure(struct azx *chip)
1712 {
1713 struct hda_codec *codec;
1714 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1715 snd_hda_codec_configure(codec);
1716 }
1717 return 0;
1718 }
1719
1720
1721 /*
1722 * PCM support
1723 */
1724
1725 /* assign a stream for the PCM */
1726 static inline struct azx_dev *
1727 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1728 {
1729 int dev, i, nums;
1730 struct azx_dev *res = NULL;
1731 /* make a non-zero unique key for the substream */
1732 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1733 (substream->stream + 1);
1734
1735 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1736 dev = chip->playback_index_offset;
1737 nums = chip->playback_streams;
1738 } else {
1739 dev = chip->capture_index_offset;
1740 nums = chip->capture_streams;
1741 }
1742 for (i = 0; i < nums; i++, dev++)
1743 if (!chip->azx_dev[dev].opened) {
1744 res = &chip->azx_dev[dev];
1745 if (res->assigned_key == key)
1746 break;
1747 }
1748 if (res) {
1749 res->opened = 1;
1750 res->assigned_key = key;
1751 }
1752 return res;
1753 }
1754
1755 /* release the assigned stream */
1756 static inline void azx_release_device(struct azx_dev *azx_dev)
1757 {
1758 azx_dev->opened = 0;
1759 }
1760
1761 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1762 {
1763 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1764 struct snd_pcm_substream *substream = azx_dev->substream;
1765 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1766 struct azx *chip = apcm->chip;
1767
1768 return azx_readl(chip, WALLCLK);
1769 }
1770
1771 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1772 bool force, cycle_t last)
1773 {
1774 struct azx_dev *azx_dev = get_azx_dev(substream);
1775 struct timecounter *tc = &azx_dev->azx_tc;
1776 struct cyclecounter *cc = &azx_dev->azx_cc;
1777 u64 nsec;
1778
1779 cc->read = azx_cc_read;
1780 cc->mask = CLOCKSOURCE_MASK(32);
1781
1782 /*
1783 * Converting from 24 MHz to ns means applying a 125/3 factor.
1784 * To avoid any saturation issues in intermediate operations,
1785 * the 125 factor is applied first. The division is applied
1786 * last after reading the timecounter value.
1787 * Applying the 1/3 factor as part of the multiplication
1788 * requires at least 20 bits for a decent precision, however
1789 * overflows occur after about 4 hours or less, not a option.
1790 */
1791
1792 cc->mult = 125; /* saturation after 195 years */
1793 cc->shift = 0;
1794
1795 nsec = 0; /* audio time is elapsed time since trigger */
1796 timecounter_init(tc, cc, nsec);
1797 if (force)
1798 /*
1799 * force timecounter to use predefined value,
1800 * used for synchronized starts
1801 */
1802 tc->cycle_last = last;
1803 }
1804
1805 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1806 struct timespec *ts)
1807 {
1808 struct azx_dev *azx_dev = get_azx_dev(substream);
1809 u64 nsec;
1810
1811 nsec = timecounter_read(&azx_dev->azx_tc);
1812 nsec = div_u64(nsec, 3); /* can be optimized */
1813
1814 *ts = ns_to_timespec(nsec);
1815
1816 return 0;
1817 }
1818
1819 static struct snd_pcm_hardware azx_pcm_hw = {
1820 .info = (SNDRV_PCM_INFO_MMAP |
1821 SNDRV_PCM_INFO_INTERLEAVED |
1822 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1823 SNDRV_PCM_INFO_MMAP_VALID |
1824 /* No full-resume yet implemented */
1825 /* SNDRV_PCM_INFO_RESUME |*/
1826 SNDRV_PCM_INFO_PAUSE |
1827 SNDRV_PCM_INFO_SYNC_START |
1828 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1829 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1830 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1831 .rates = SNDRV_PCM_RATE_48000,
1832 .rate_min = 48000,
1833 .rate_max = 48000,
1834 .channels_min = 2,
1835 .channels_max = 2,
1836 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1837 .period_bytes_min = 128,
1838 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1839 .periods_min = 2,
1840 .periods_max = AZX_MAX_FRAG,
1841 .fifo_size = 0,
1842 };
1843
1844 static int azx_pcm_open(struct snd_pcm_substream *substream)
1845 {
1846 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1847 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1848 struct azx *chip = apcm->chip;
1849 struct azx_dev *azx_dev;
1850 struct snd_pcm_runtime *runtime = substream->runtime;
1851 unsigned long flags;
1852 int err;
1853 int buff_step;
1854
1855 mutex_lock(&chip->open_mutex);
1856 azx_dev = azx_assign_device(chip, substream);
1857 if (azx_dev == NULL) {
1858 mutex_unlock(&chip->open_mutex);
1859 return -EBUSY;
1860 }
1861 runtime->hw = azx_pcm_hw;
1862 runtime->hw.channels_min = hinfo->channels_min;
1863 runtime->hw.channels_max = hinfo->channels_max;
1864 runtime->hw.formats = hinfo->formats;
1865 runtime->hw.rates = hinfo->rates;
1866 snd_pcm_limit_hw_rates(runtime);
1867 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1868
1869 /* avoid wrap-around with wall-clock */
1870 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1871 20,
1872 178000000);
1873
1874 if (chip->align_buffer_size)
1875 /* constrain buffer sizes to be multiple of 128
1876 bytes. This is more efficient in terms of memory
1877 access but isn't required by the HDA spec and
1878 prevents users from specifying exact period/buffer
1879 sizes. For example for 44.1kHz, a period size set
1880 to 20ms will be rounded to 19.59ms. */
1881 buff_step = 128;
1882 else
1883 /* Don't enforce steps on buffer sizes, still need to
1884 be multiple of 4 bytes (HDA spec). Tested on Intel
1885 HDA controllers, may not work on all devices where
1886 option needs to be disabled */
1887 buff_step = 4;
1888
1889 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1890 buff_step);
1891 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1892 buff_step);
1893 snd_hda_power_up_d3wait(apcm->codec);
1894 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1895 if (err < 0) {
1896 azx_release_device(azx_dev);
1897 snd_hda_power_down(apcm->codec);
1898 mutex_unlock(&chip->open_mutex);
1899 return err;
1900 }
1901 snd_pcm_limit_hw_rates(runtime);
1902 /* sanity check */
1903 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1904 snd_BUG_ON(!runtime->hw.channels_max) ||
1905 snd_BUG_ON(!runtime->hw.formats) ||
1906 snd_BUG_ON(!runtime->hw.rates)) {
1907 azx_release_device(azx_dev);
1908 hinfo->ops.close(hinfo, apcm->codec, substream);
1909 snd_hda_power_down(apcm->codec);
1910 mutex_unlock(&chip->open_mutex);
1911 return -EINVAL;
1912 }
1913
1914 /* disable WALLCLOCK timestamps for capture streams
1915 until we figure out how to handle digital inputs */
1916 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1917 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1918
1919 spin_lock_irqsave(&chip->reg_lock, flags);
1920 azx_dev->substream = substream;
1921 azx_dev->running = 0;
1922 spin_unlock_irqrestore(&chip->reg_lock, flags);
1923
1924 runtime->private_data = azx_dev;
1925 snd_pcm_set_sync(substream);
1926 mutex_unlock(&chip->open_mutex);
1927 return 0;
1928 }
1929
1930 static int azx_pcm_close(struct snd_pcm_substream *substream)
1931 {
1932 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1933 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1934 struct azx *chip = apcm->chip;
1935 struct azx_dev *azx_dev = get_azx_dev(substream);
1936 unsigned long flags;
1937
1938 mutex_lock(&chip->open_mutex);
1939 spin_lock_irqsave(&chip->reg_lock, flags);
1940 azx_dev->substream = NULL;
1941 azx_dev->running = 0;
1942 spin_unlock_irqrestore(&chip->reg_lock, flags);
1943 azx_release_device(azx_dev);
1944 hinfo->ops.close(hinfo, apcm->codec, substream);
1945 snd_hda_power_down(apcm->codec);
1946 mutex_unlock(&chip->open_mutex);
1947 return 0;
1948 }
1949
1950 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1951 struct snd_pcm_hw_params *hw_params)
1952 {
1953 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1954 struct azx *chip = apcm->chip;
1955 struct snd_pcm_runtime *runtime = substream->runtime;
1956 struct azx_dev *azx_dev = get_azx_dev(substream);
1957 int ret;
1958
1959 mark_runtime_wc(chip, azx_dev, runtime, false);
1960 azx_dev->bufsize = 0;
1961 azx_dev->period_bytes = 0;
1962 azx_dev->format_val = 0;
1963 ret = snd_pcm_lib_malloc_pages(substream,
1964 params_buffer_bytes(hw_params));
1965 if (ret < 0)
1966 return ret;
1967 mark_runtime_wc(chip, azx_dev, runtime, true);
1968 return ret;
1969 }
1970
1971 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1972 {
1973 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1974 struct azx_dev *azx_dev = get_azx_dev(substream);
1975 struct azx *chip = apcm->chip;
1976 struct snd_pcm_runtime *runtime = substream->runtime;
1977 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1978
1979 /* reset BDL address */
1980 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1981 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1982 azx_sd_writel(azx_dev, SD_CTL, 0);
1983 azx_dev->bufsize = 0;
1984 azx_dev->period_bytes = 0;
1985 azx_dev->format_val = 0;
1986
1987 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1988
1989 mark_runtime_wc(chip, azx_dev, runtime, false);
1990 return snd_pcm_lib_free_pages(substream);
1991 }
1992
1993 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1994 {
1995 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1996 struct azx *chip = apcm->chip;
1997 struct azx_dev *azx_dev = get_azx_dev(substream);
1998 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1999 struct snd_pcm_runtime *runtime = substream->runtime;
2000 unsigned int bufsize, period_bytes, format_val, stream_tag;
2001 int err;
2002 struct hda_spdif_out *spdif =
2003 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2004 unsigned short ctls = spdif ? spdif->ctls : 0;
2005
2006 azx_stream_reset(chip, azx_dev);
2007 format_val = snd_hda_calc_stream_format(runtime->rate,
2008 runtime->channels,
2009 runtime->format,
2010 hinfo->maxbps,
2011 ctls);
2012 if (!format_val) {
2013 snd_printk(KERN_ERR SFX
2014 "invalid format_val, rate=%d, ch=%d, format=%d\n",
2015 runtime->rate, runtime->channels, runtime->format);
2016 return -EINVAL;
2017 }
2018
2019 bufsize = snd_pcm_lib_buffer_bytes(substream);
2020 period_bytes = snd_pcm_lib_period_bytes(substream);
2021
2022 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2023 bufsize, format_val);
2024
2025 if (bufsize != azx_dev->bufsize ||
2026 period_bytes != azx_dev->period_bytes ||
2027 format_val != azx_dev->format_val ||
2028 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2029 azx_dev->bufsize = bufsize;
2030 azx_dev->period_bytes = period_bytes;
2031 azx_dev->format_val = format_val;
2032 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2033 err = azx_setup_periods(chip, substream, azx_dev);
2034 if (err < 0)
2035 return err;
2036 }
2037
2038 /* wallclk has 24Mhz clock source */
2039 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2040 runtime->rate) * 1000);
2041 azx_setup_controller(chip, azx_dev);
2042 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2043 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2044 else
2045 azx_dev->fifo_size = 0;
2046
2047 stream_tag = azx_dev->stream_tag;
2048 /* CA-IBG chips need the playback stream starting from 1 */
2049 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2050 stream_tag > chip->capture_streams)
2051 stream_tag -= chip->capture_streams;
2052 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2053 azx_dev->format_val, substream);
2054 }
2055
2056 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2057 {
2058 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2059 struct azx *chip = apcm->chip;
2060 struct azx_dev *azx_dev;
2061 struct snd_pcm_substream *s;
2062 int rstart = 0, start, nsync = 0, sbits = 0;
2063 int nwait, timeout;
2064
2065 azx_dev = get_azx_dev(substream);
2066 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2067
2068 switch (cmd) {
2069 case SNDRV_PCM_TRIGGER_START:
2070 rstart = 1;
2071 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2072 case SNDRV_PCM_TRIGGER_RESUME:
2073 start = 1;
2074 break;
2075 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2076 case SNDRV_PCM_TRIGGER_SUSPEND:
2077 case SNDRV_PCM_TRIGGER_STOP:
2078 start = 0;
2079 break;
2080 default:
2081 return -EINVAL;
2082 }
2083
2084 snd_pcm_group_for_each_entry(s, substream) {
2085 if (s->pcm->card != substream->pcm->card)
2086 continue;
2087 azx_dev = get_azx_dev(s);
2088 sbits |= 1 << azx_dev->index;
2089 nsync++;
2090 snd_pcm_trigger_done(s, substream);
2091 }
2092
2093 spin_lock(&chip->reg_lock);
2094
2095 /* first, set SYNC bits of corresponding streams */
2096 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2097 azx_writel(chip, OLD_SSYNC,
2098 azx_readl(chip, OLD_SSYNC) | sbits);
2099 else
2100 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2101
2102 snd_pcm_group_for_each_entry(s, substream) {
2103 if (s->pcm->card != substream->pcm->card)
2104 continue;
2105 azx_dev = get_azx_dev(s);
2106 if (start) {
2107 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2108 if (!rstart)
2109 azx_dev->start_wallclk -=
2110 azx_dev->period_wallclk;
2111 azx_stream_start(chip, azx_dev);
2112 } else {
2113 azx_stream_stop(chip, azx_dev);
2114 }
2115 azx_dev->running = start;
2116 }
2117 spin_unlock(&chip->reg_lock);
2118 if (start) {
2119 /* wait until all FIFOs get ready */
2120 for (timeout = 5000; timeout; timeout--) {
2121 nwait = 0;
2122 snd_pcm_group_for_each_entry(s, substream) {
2123 if (s->pcm->card != substream->pcm->card)
2124 continue;
2125 azx_dev = get_azx_dev(s);
2126 if (!(azx_sd_readb(azx_dev, SD_STS) &
2127 SD_STS_FIFO_READY))
2128 nwait++;
2129 }
2130 if (!nwait)
2131 break;
2132 cpu_relax();
2133 }
2134 } else {
2135 /* wait until all RUN bits are cleared */
2136 for (timeout = 5000; timeout; timeout--) {
2137 nwait = 0;
2138 snd_pcm_group_for_each_entry(s, substream) {
2139 if (s->pcm->card != substream->pcm->card)
2140 continue;
2141 azx_dev = get_azx_dev(s);
2142 if (azx_sd_readb(azx_dev, SD_CTL) &
2143 SD_CTL_DMA_START)
2144 nwait++;
2145 }
2146 if (!nwait)
2147 break;
2148 cpu_relax();
2149 }
2150 }
2151 spin_lock(&chip->reg_lock);
2152 /* reset SYNC bits */
2153 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2154 azx_writel(chip, OLD_SSYNC,
2155 azx_readl(chip, OLD_SSYNC) & ~sbits);
2156 else
2157 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2158 if (start) {
2159 azx_timecounter_init(substream, 0, 0);
2160 if (nsync > 1) {
2161 cycle_t cycle_last;
2162
2163 /* same start cycle for master and group */
2164 azx_dev = get_azx_dev(substream);
2165 cycle_last = azx_dev->azx_tc.cycle_last;
2166
2167 snd_pcm_group_for_each_entry(s, substream) {
2168 if (s->pcm->card != substream->pcm->card)
2169 continue;
2170 azx_timecounter_init(s, 1, cycle_last);
2171 }
2172 }
2173 }
2174 spin_unlock(&chip->reg_lock);
2175 return 0;
2176 }
2177
2178 /* get the current DMA position with correction on VIA chips */
2179 static unsigned int azx_via_get_position(struct azx *chip,
2180 struct azx_dev *azx_dev)
2181 {
2182 unsigned int link_pos, mini_pos, bound_pos;
2183 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2184 unsigned int fifo_size;
2185
2186 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2187 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2188 /* Playback, no problem using link position */
2189 return link_pos;
2190 }
2191
2192 /* Capture */
2193 /* For new chipset,
2194 * use mod to get the DMA position just like old chipset
2195 */
2196 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2197 mod_dma_pos %= azx_dev->period_bytes;
2198
2199 /* azx_dev->fifo_size can't get FIFO size of in stream.
2200 * Get from base address + offset.
2201 */
2202 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2203
2204 if (azx_dev->insufficient) {
2205 /* Link position never gather than FIFO size */
2206 if (link_pos <= fifo_size)
2207 return 0;
2208
2209 azx_dev->insufficient = 0;
2210 }
2211
2212 if (link_pos <= fifo_size)
2213 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2214 else
2215 mini_pos = link_pos - fifo_size;
2216
2217 /* Find nearest previous boudary */
2218 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2219 mod_link_pos = link_pos % azx_dev->period_bytes;
2220 if (mod_link_pos >= fifo_size)
2221 bound_pos = link_pos - mod_link_pos;
2222 else if (mod_dma_pos >= mod_mini_pos)
2223 bound_pos = mini_pos - mod_mini_pos;
2224 else {
2225 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2226 if (bound_pos >= azx_dev->bufsize)
2227 bound_pos = 0;
2228 }
2229
2230 /* Calculate real DMA position we want */
2231 return bound_pos + mod_dma_pos;
2232 }
2233
2234 static unsigned int azx_get_position(struct azx *chip,
2235 struct azx_dev *azx_dev,
2236 bool with_check)
2237 {
2238 unsigned int pos;
2239 int stream = azx_dev->substream->stream;
2240 int delay = 0;
2241
2242 switch (chip->position_fix[stream]) {
2243 case POS_FIX_LPIB:
2244 /* read LPIB */
2245 pos = azx_sd_readl(azx_dev, SD_LPIB);
2246 break;
2247 case POS_FIX_VIACOMBO:
2248 pos = azx_via_get_position(chip, azx_dev);
2249 break;
2250 default:
2251 /* use the position buffer */
2252 pos = le32_to_cpu(*azx_dev->posbuf);
2253 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2254 if (!pos || pos == (u32)-1) {
2255 printk(KERN_WARNING
2256 "hda-intel: Invalid position buffer, "
2257 "using LPIB read method instead.\n");
2258 chip->position_fix[stream] = POS_FIX_LPIB;
2259 pos = azx_sd_readl(azx_dev, SD_LPIB);
2260 } else
2261 chip->position_fix[stream] = POS_FIX_POSBUF;
2262 }
2263 break;
2264 }
2265
2266 if (pos >= azx_dev->bufsize)
2267 pos = 0;
2268
2269 /* calculate runtime delay from LPIB */
2270 if (azx_dev->substream->runtime &&
2271 chip->position_fix[stream] == POS_FIX_POSBUF &&
2272 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2273 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2274 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2275 delay = pos - lpib_pos;
2276 else
2277 delay = lpib_pos - pos;
2278 if (delay < 0)
2279 delay += azx_dev->bufsize;
2280 if (delay >= azx_dev->period_bytes) {
2281 snd_printk(KERN_WARNING SFX
2282 "Unstable LPIB (%d >= %d); "
2283 "disabling LPIB delay counting\n",
2284 delay, azx_dev->period_bytes);
2285 delay = 0;
2286 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2287 }
2288 azx_dev->substream->runtime->delay =
2289 bytes_to_frames(azx_dev->substream->runtime, delay);
2290 }
2291 trace_azx_get_position(chip, azx_dev, pos, delay);
2292 return pos;
2293 }
2294
2295 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2296 {
2297 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2298 struct azx *chip = apcm->chip;
2299 struct azx_dev *azx_dev = get_azx_dev(substream);
2300 return bytes_to_frames(substream->runtime,
2301 azx_get_position(chip, azx_dev, false));
2302 }
2303
2304 /*
2305 * Check whether the current DMA position is acceptable for updating
2306 * periods. Returns non-zero if it's OK.
2307 *
2308 * Many HD-audio controllers appear pretty inaccurate about
2309 * the update-IRQ timing. The IRQ is issued before actually the
2310 * data is processed. So, we need to process it afterwords in a
2311 * workqueue.
2312 */
2313 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2314 {
2315 u32 wallclk;
2316 unsigned int pos;
2317
2318 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2319 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2320 return -1; /* bogus (too early) interrupt */
2321
2322 pos = azx_get_position(chip, azx_dev, true);
2323
2324 if (WARN_ONCE(!azx_dev->period_bytes,
2325 "hda-intel: zero azx_dev->period_bytes"))
2326 return -1; /* this shouldn't happen! */
2327 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2328 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2329 /* NG - it's below the first next period boundary */
2330 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2331 azx_dev->start_wallclk += wallclk;
2332 return 1; /* OK, it's fine */
2333 }
2334
2335 /*
2336 * The work for pending PCM period updates.
2337 */
2338 static void azx_irq_pending_work(struct work_struct *work)
2339 {
2340 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2341 int i, pending, ok;
2342
2343 if (!chip->irq_pending_warned) {
2344 printk(KERN_WARNING
2345 "hda-intel: IRQ timing workaround is activated "
2346 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2347 chip->card->number);
2348 chip->irq_pending_warned = 1;
2349 }
2350
2351 for (;;) {
2352 pending = 0;
2353 spin_lock_irq(&chip->reg_lock);
2354 for (i = 0; i < chip->num_streams; i++) {
2355 struct azx_dev *azx_dev = &chip->azx_dev[i];
2356 if (!azx_dev->irq_pending ||
2357 !azx_dev->substream ||
2358 !azx_dev->running)
2359 continue;
2360 ok = azx_position_ok(chip, azx_dev);
2361 if (ok > 0) {
2362 azx_dev->irq_pending = 0;
2363 spin_unlock(&chip->reg_lock);
2364 snd_pcm_period_elapsed(azx_dev->substream);
2365 spin_lock(&chip->reg_lock);
2366 } else if (ok < 0) {
2367 pending = 0; /* too early */
2368 } else
2369 pending++;
2370 }
2371 spin_unlock_irq(&chip->reg_lock);
2372 if (!pending)
2373 return;
2374 msleep(1);
2375 }
2376 }
2377
2378 /* clear irq_pending flags and assure no on-going workq */
2379 static void azx_clear_irq_pending(struct azx *chip)
2380 {
2381 int i;
2382
2383 spin_lock_irq(&chip->reg_lock);
2384 for (i = 0; i < chip->num_streams; i++)
2385 chip->azx_dev[i].irq_pending = 0;
2386 spin_unlock_irq(&chip->reg_lock);
2387 }
2388
2389 #ifdef CONFIG_X86
2390 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2391 struct vm_area_struct *area)
2392 {
2393 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2394 struct azx *chip = apcm->chip;
2395 if (!azx_snoop(chip))
2396 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2397 return snd_pcm_lib_default_mmap(substream, area);
2398 }
2399 #else
2400 #define azx_pcm_mmap NULL
2401 #endif
2402
2403 static struct snd_pcm_ops azx_pcm_ops = {
2404 .open = azx_pcm_open,
2405 .close = azx_pcm_close,
2406 .ioctl = snd_pcm_lib_ioctl,
2407 .hw_params = azx_pcm_hw_params,
2408 .hw_free = azx_pcm_hw_free,
2409 .prepare = azx_pcm_prepare,
2410 .trigger = azx_pcm_trigger,
2411 .pointer = azx_pcm_pointer,
2412 .wall_clock = azx_get_wallclock_tstamp,
2413 .mmap = azx_pcm_mmap,
2414 .page = snd_pcm_sgbuf_ops_page,
2415 };
2416
2417 static void azx_pcm_free(struct snd_pcm *pcm)
2418 {
2419 struct azx_pcm *apcm = pcm->private_data;
2420 if (apcm) {
2421 list_del(&apcm->list);
2422 kfree(apcm);
2423 }
2424 }
2425
2426 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2427
2428 static int
2429 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2430 struct hda_pcm *cpcm)
2431 {
2432 struct azx *chip = bus->private_data;
2433 struct snd_pcm *pcm;
2434 struct azx_pcm *apcm;
2435 int pcm_dev = cpcm->device;
2436 unsigned int size;
2437 int s, err;
2438
2439 list_for_each_entry(apcm, &chip->pcm_list, list) {
2440 if (apcm->pcm->device == pcm_dev) {
2441 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2442 return -EBUSY;
2443 }
2444 }
2445 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2446 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2447 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2448 &pcm);
2449 if (err < 0)
2450 return err;
2451 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2452 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2453 if (apcm == NULL)
2454 return -ENOMEM;
2455 apcm->chip = chip;
2456 apcm->pcm = pcm;
2457 apcm->codec = codec;
2458 pcm->private_data = apcm;
2459 pcm->private_free = azx_pcm_free;
2460 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2461 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2462 list_add_tail(&apcm->list, &chip->pcm_list);
2463 cpcm->pcm = pcm;
2464 for (s = 0; s < 2; s++) {
2465 apcm->hinfo[s] = &cpcm->stream[s];
2466 if (cpcm->stream[s].substreams)
2467 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2468 }
2469 /* buffer pre-allocation */
2470 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2471 if (size > MAX_PREALLOC_SIZE)
2472 size = MAX_PREALLOC_SIZE;
2473 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2474 snd_dma_pci_data(chip->pci),
2475 size, MAX_PREALLOC_SIZE);
2476 return 0;
2477 }
2478
2479 /*
2480 * mixer creation - all stuff is implemented in hda module
2481 */
2482 static int __devinit azx_mixer_create(struct azx *chip)
2483 {
2484 return snd_hda_build_controls(chip->bus);
2485 }
2486
2487
2488 /*
2489 * initialize SD streams
2490 */
2491 static int __devinit azx_init_stream(struct azx *chip)
2492 {
2493 int i;
2494
2495 /* initialize each stream (aka device)
2496 * assign the starting bdl address to each stream (device)
2497 * and initialize
2498 */
2499 for (i = 0; i < chip->num_streams; i++) {
2500 struct azx_dev *azx_dev = &chip->azx_dev[i];
2501 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2502 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2503 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2504 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2505 azx_dev->sd_int_sta_mask = 1 << i;
2506 /* stream tag: must be non-zero and unique */
2507 azx_dev->index = i;
2508 azx_dev->stream_tag = i + 1;
2509 }
2510
2511 return 0;
2512 }
2513
2514 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2515 {
2516 if (request_irq(chip->pci->irq, azx_interrupt,
2517 chip->msi ? 0 : IRQF_SHARED,
2518 KBUILD_MODNAME, chip)) {
2519 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2520 "disabling device\n", chip->pci->irq);
2521 if (do_disconnect)
2522 snd_card_disconnect(chip->card);
2523 return -1;
2524 }
2525 chip->irq = chip->pci->irq;
2526 pci_intx(chip->pci, !chip->msi);
2527 return 0;
2528 }
2529
2530
2531 static void azx_stop_chip(struct azx *chip)
2532 {
2533 if (!chip->initialized)
2534 return;
2535
2536 /* disable interrupts */
2537 azx_int_disable(chip);
2538 azx_int_clear(chip);
2539
2540 /* disable CORB/RIRB */
2541 azx_free_cmd_io(chip);
2542
2543 /* disable position buffer */
2544 azx_writel(chip, DPLBASE, 0);
2545 azx_writel(chip, DPUBASE, 0);
2546
2547 chip->initialized = 0;
2548 }
2549
2550 #ifdef CONFIG_PM
2551 /* power-up/down the controller */
2552 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2553 {
2554 struct azx *chip = bus->private_data;
2555
2556 if (power_up)
2557 pm_runtime_get_sync(&chip->pci->dev);
2558 else
2559 pm_runtime_put_sync(&chip->pci->dev);
2560 }
2561
2562 static DEFINE_MUTEX(card_list_lock);
2563 static LIST_HEAD(card_list);
2564
2565 static void azx_add_card_list(struct azx *chip)
2566 {
2567 mutex_lock(&card_list_lock);
2568 list_add(&chip->list, &card_list);
2569 mutex_unlock(&card_list_lock);
2570 }
2571
2572 static void azx_del_card_list(struct azx *chip)
2573 {
2574 mutex_lock(&card_list_lock);
2575 list_del_init(&chip->list);
2576 mutex_unlock(&card_list_lock);
2577 }
2578
2579 /* trigger power-save check at writing parameter */
2580 static int param_set_xint(const char *val, const struct kernel_param *kp)
2581 {
2582 struct azx *chip;
2583 struct hda_codec *c;
2584 int prev = power_save;
2585 int ret = param_set_int(val, kp);
2586
2587 if (ret || prev == power_save)
2588 return ret;
2589
2590 mutex_lock(&card_list_lock);
2591 list_for_each_entry(chip, &card_list, list) {
2592 if (!chip->bus || chip->disabled)
2593 continue;
2594 list_for_each_entry(c, &chip->bus->codec_list, list)
2595 snd_hda_power_sync(c);
2596 }
2597 mutex_unlock(&card_list_lock);
2598 return 0;
2599 }
2600 #else
2601 #define azx_add_card_list(chip) /* NOP */
2602 #define azx_del_card_list(chip) /* NOP */
2603 #endif /* CONFIG_PM */
2604
2605 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2606 /*
2607 * power management
2608 */
2609 static int azx_suspend(struct device *dev)
2610 {
2611 struct pci_dev *pci = to_pci_dev(dev);
2612 struct snd_card *card = dev_get_drvdata(dev);
2613 struct azx *chip = card->private_data;
2614 struct azx_pcm *p;
2615
2616 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2617 azx_clear_irq_pending(chip);
2618 list_for_each_entry(p, &chip->pcm_list, list)
2619 snd_pcm_suspend_all(p->pcm);
2620 if (chip->initialized)
2621 snd_hda_suspend(chip->bus);
2622 azx_stop_chip(chip);
2623 if (chip->irq >= 0) {
2624 free_irq(chip->irq, chip);
2625 chip->irq = -1;
2626 }
2627 if (chip->msi)
2628 pci_disable_msi(chip->pci);
2629 pci_disable_device(pci);
2630 pci_save_state(pci);
2631 pci_set_power_state(pci, PCI_D3hot);
2632 return 0;
2633 }
2634
2635 static int azx_resume(struct device *dev)
2636 {
2637 struct pci_dev *pci = to_pci_dev(dev);
2638 struct snd_card *card = dev_get_drvdata(dev);
2639 struct azx *chip = card->private_data;
2640
2641 pci_set_power_state(pci, PCI_D0);
2642 pci_restore_state(pci);
2643 if (pci_enable_device(pci) < 0) {
2644 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2645 "disabling device\n");
2646 snd_card_disconnect(card);
2647 return -EIO;
2648 }
2649 pci_set_master(pci);
2650 if (chip->msi)
2651 if (pci_enable_msi(pci) < 0)
2652 chip->msi = 0;
2653 if (azx_acquire_irq(chip, 1) < 0)
2654 return -EIO;
2655 azx_init_pci(chip);
2656
2657 azx_init_chip(chip, 1);
2658
2659 snd_hda_resume(chip->bus);
2660 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2661 return 0;
2662 }
2663 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2664
2665 #ifdef CONFIG_PM_RUNTIME
2666 static int azx_runtime_suspend(struct device *dev)
2667 {
2668 struct snd_card *card = dev_get_drvdata(dev);
2669 struct azx *chip = card->private_data;
2670
2671 if (!power_save_controller)
2672 return -EAGAIN;
2673
2674 azx_stop_chip(chip);
2675 azx_clear_irq_pending(chip);
2676 return 0;
2677 }
2678
2679 static int azx_runtime_resume(struct device *dev)
2680 {
2681 struct snd_card *card = dev_get_drvdata(dev);
2682 struct azx *chip = card->private_data;
2683
2684 azx_init_pci(chip);
2685 azx_init_chip(chip, 1);
2686 return 0;
2687 }
2688 #endif /* CONFIG_PM_RUNTIME */
2689
2690 #ifdef CONFIG_PM
2691 static const struct dev_pm_ops azx_pm = {
2692 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2693 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2694 };
2695
2696 #define AZX_PM_OPS &azx_pm
2697 #else
2698 #define AZX_PM_OPS NULL
2699 #endif /* CONFIG_PM */
2700
2701
2702 /*
2703 * reboot notifier for hang-up problem at power-down
2704 */
2705 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2706 {
2707 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2708 snd_hda_bus_reboot_notify(chip->bus);
2709 azx_stop_chip(chip);
2710 return NOTIFY_OK;
2711 }
2712
2713 static void azx_notifier_register(struct azx *chip)
2714 {
2715 chip->reboot_notifier.notifier_call = azx_halt;
2716 register_reboot_notifier(&chip->reboot_notifier);
2717 }
2718
2719 static void azx_notifier_unregister(struct azx *chip)
2720 {
2721 if (chip->reboot_notifier.notifier_call)
2722 unregister_reboot_notifier(&chip->reboot_notifier);
2723 }
2724
2725 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2726 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2727
2728 #ifdef SUPPORT_VGA_SWITCHEROO
2729 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2730
2731 static void azx_vs_set_state(struct pci_dev *pci,
2732 enum vga_switcheroo_state state)
2733 {
2734 struct snd_card *card = pci_get_drvdata(pci);
2735 struct azx *chip = card->private_data;
2736 bool disabled;
2737
2738 if (chip->init_failed)
2739 return;
2740
2741 disabled = (state == VGA_SWITCHEROO_OFF);
2742 if (chip->disabled == disabled)
2743 return;
2744
2745 if (!chip->bus) {
2746 chip->disabled = disabled;
2747 if (!disabled) {
2748 snd_printk(KERN_INFO SFX
2749 "%s: Start delayed initialization\n",
2750 pci_name(chip->pci));
2751 if (azx_first_init(chip) < 0 ||
2752 azx_probe_continue(chip) < 0) {
2753 snd_printk(KERN_ERR SFX
2754 "%s: initialization error\n",
2755 pci_name(chip->pci));
2756 chip->init_failed = true;
2757 }
2758 }
2759 } else {
2760 snd_printk(KERN_INFO SFX
2761 "%s %s via VGA-switcheroo\n",
2762 disabled ? "Disabling" : "Enabling",
2763 pci_name(chip->pci));
2764 if (disabled) {
2765 azx_suspend(&pci->dev);
2766 chip->disabled = true;
2767 if (snd_hda_lock_devices(chip->bus))
2768 snd_printk(KERN_WARNING SFX
2769 "Cannot lock devices!\n");
2770 } else {
2771 snd_hda_unlock_devices(chip->bus);
2772 chip->disabled = false;
2773 azx_resume(&pci->dev);
2774 }
2775 }
2776 }
2777
2778 static bool azx_vs_can_switch(struct pci_dev *pci)
2779 {
2780 struct snd_card *card = pci_get_drvdata(pci);
2781 struct azx *chip = card->private_data;
2782
2783 if (chip->init_failed)
2784 return false;
2785 if (chip->disabled || !chip->bus)
2786 return true;
2787 if (snd_hda_lock_devices(chip->bus))
2788 return false;
2789 snd_hda_unlock_devices(chip->bus);
2790 return true;
2791 }
2792
2793 static void __devinit init_vga_switcheroo(struct azx *chip)
2794 {
2795 struct pci_dev *p = get_bound_vga(chip->pci);
2796 if (p) {
2797 snd_printk(KERN_INFO SFX
2798 "%s: Handle VGA-switcheroo audio client\n",
2799 pci_name(chip->pci));
2800 chip->use_vga_switcheroo = 1;
2801 pci_dev_put(p);
2802 }
2803 }
2804
2805 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2806 .set_gpu_state = azx_vs_set_state,
2807 .can_switch = azx_vs_can_switch,
2808 };
2809
2810 static int __devinit register_vga_switcheroo(struct azx *chip)
2811 {
2812 int err;
2813
2814 if (!chip->use_vga_switcheroo)
2815 return 0;
2816 /* FIXME: currently only handling DIS controller
2817 * is there any machine with two switchable HDMI audio controllers?
2818 */
2819 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2820 VGA_SWITCHEROO_DIS,
2821 chip->bus != NULL);
2822 if (err < 0)
2823 return err;
2824 chip->vga_switcheroo_registered = 1;
2825 return 0;
2826 }
2827 #else
2828 #define init_vga_switcheroo(chip) /* NOP */
2829 #define register_vga_switcheroo(chip) 0
2830 #define check_hdmi_disabled(pci) false
2831 #endif /* SUPPORT_VGA_SWITCHER */
2832
2833 /*
2834 * destructor
2835 */
2836 static int azx_free(struct azx *chip)
2837 {
2838 int i;
2839
2840 azx_del_card_list(chip);
2841
2842 azx_notifier_unregister(chip);
2843
2844 if (use_vga_switcheroo(chip)) {
2845 if (chip->disabled && chip->bus)
2846 snd_hda_unlock_devices(chip->bus);
2847 if (chip->vga_switcheroo_registered)
2848 vga_switcheroo_unregister_client(chip->pci);
2849 }
2850
2851 if (chip->initialized) {
2852 azx_clear_irq_pending(chip);
2853 for (i = 0; i < chip->num_streams; i++)
2854 azx_stream_stop(chip, &chip->azx_dev[i]);
2855 azx_stop_chip(chip);
2856 }
2857
2858 if (chip->irq >= 0)
2859 free_irq(chip->irq, (void*)chip);
2860 if (chip->msi)
2861 pci_disable_msi(chip->pci);
2862 if (chip->remap_addr)
2863 iounmap(chip->remap_addr);
2864
2865 if (chip->azx_dev) {
2866 for (i = 0; i < chip->num_streams; i++)
2867 if (chip->azx_dev[i].bdl.area) {
2868 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2869 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2870 }
2871 }
2872 if (chip->rb.area) {
2873 mark_pages_wc(chip, &chip->rb, false);
2874 snd_dma_free_pages(&chip->rb);
2875 }
2876 if (chip->posbuf.area) {
2877 mark_pages_wc(chip, &chip->posbuf, false);
2878 snd_dma_free_pages(&chip->posbuf);
2879 }
2880 if (chip->region_requested)
2881 pci_release_regions(chip->pci);
2882 pci_disable_device(chip->pci);
2883 kfree(chip->azx_dev);
2884 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2885 if (chip->fw)
2886 release_firmware(chip->fw);
2887 #endif
2888 kfree(chip);
2889
2890 return 0;
2891 }
2892
2893 static int azx_dev_free(struct snd_device *device)
2894 {
2895 return azx_free(device->device_data);
2896 }
2897
2898 #ifdef SUPPORT_VGA_SWITCHEROO
2899 /*
2900 * Check of disabled HDMI controller by vga-switcheroo
2901 */
2902 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2903 {
2904 struct pci_dev *p;
2905
2906 /* check only discrete GPU */
2907 switch (pci->vendor) {
2908 case PCI_VENDOR_ID_ATI:
2909 case PCI_VENDOR_ID_AMD:
2910 case PCI_VENDOR_ID_NVIDIA:
2911 if (pci->devfn == 1) {
2912 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2913 pci->bus->number, 0);
2914 if (p) {
2915 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2916 return p;
2917 pci_dev_put(p);
2918 }
2919 }
2920 break;
2921 }
2922 return NULL;
2923 }
2924
2925 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2926 {
2927 bool vga_inactive = false;
2928 struct pci_dev *p = get_bound_vga(pci);
2929
2930 if (p) {
2931 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2932 vga_inactive = true;
2933 pci_dev_put(p);
2934 }
2935 return vga_inactive;
2936 }
2937 #endif /* SUPPORT_VGA_SWITCHEROO */
2938
2939 /*
2940 * white/black-listing for position_fix
2941 */
2942 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2943 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2944 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2945 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2946 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2947 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2948 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2949 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2950 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2951 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2952 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2953 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2954 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2955 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2956 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2957 {}
2958 };
2959
2960 static int __devinit check_position_fix(struct azx *chip, int fix)
2961 {
2962 const struct snd_pci_quirk *q;
2963
2964 switch (fix) {
2965 case POS_FIX_AUTO:
2966 case POS_FIX_LPIB:
2967 case POS_FIX_POSBUF:
2968 case POS_FIX_VIACOMBO:
2969 case POS_FIX_COMBO:
2970 return fix;
2971 }
2972
2973 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2974 if (q) {
2975 printk(KERN_INFO
2976 "hda_intel: position_fix set to %d "
2977 "for device %04x:%04x\n",
2978 q->value, q->subvendor, q->subdevice);
2979 return q->value;
2980 }
2981
2982 /* Check VIA/ATI HD Audio Controller exist */
2983 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2984 snd_printd(SFX "Using VIACOMBO position fix\n");
2985 return POS_FIX_VIACOMBO;
2986 }
2987 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2988 snd_printd(SFX "Using LPIB position fix\n");
2989 return POS_FIX_LPIB;
2990 }
2991 return POS_FIX_AUTO;
2992 }
2993
2994 /*
2995 * black-lists for probe_mask
2996 */
2997 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2998 /* Thinkpad often breaks the controller communication when accessing
2999 * to the non-working (or non-existing) modem codec slot.
3000 */
3001 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3002 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3003 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3004 /* broken BIOS */
3005 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3006 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3007 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3008 /* forced codec slots */
3009 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3010 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3011 /* WinFast VP200 H (Teradici) user reported broken communication */
3012 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3013 {}
3014 };
3015
3016 #define AZX_FORCE_CODEC_MASK 0x100
3017
3018 static void __devinit check_probe_mask(struct azx *chip, int dev)
3019 {
3020 const struct snd_pci_quirk *q;
3021
3022 chip->codec_probe_mask = probe_mask[dev];
3023 if (chip->codec_probe_mask == -1) {
3024 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3025 if (q) {
3026 printk(KERN_INFO
3027 "hda_intel: probe_mask set to 0x%x "
3028 "for device %04x:%04x\n",
3029 q->value, q->subvendor, q->subdevice);
3030 chip->codec_probe_mask = q->value;
3031 }
3032 }
3033
3034 /* check forced option */
3035 if (chip->codec_probe_mask != -1 &&
3036 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3037 chip->codec_mask = chip->codec_probe_mask & 0xff;
3038 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3039 chip->codec_mask);
3040 }
3041 }
3042
3043 /*
3044 * white/black-list for enable_msi
3045 */
3046 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
3047 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3048 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3049 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3050 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3051 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3052 {}
3053 };
3054
3055 static void __devinit check_msi(struct azx *chip)
3056 {
3057 const struct snd_pci_quirk *q;
3058
3059 if (enable_msi >= 0) {
3060 chip->msi = !!enable_msi;
3061 return;
3062 }
3063 chip->msi = 1; /* enable MSI as default */
3064 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3065 if (q) {
3066 printk(KERN_INFO
3067 "hda_intel: msi for device %04x:%04x set to %d\n",
3068 q->subvendor, q->subdevice, q->value);
3069 chip->msi = q->value;
3070 return;
3071 }
3072
3073 /* NVidia chipsets seem to cause troubles with MSI */
3074 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3075 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3076 chip->msi = 0;
3077 }
3078 }
3079
3080 /* check the snoop mode availability */
3081 static void __devinit azx_check_snoop_available(struct azx *chip)
3082 {
3083 bool snoop = chip->snoop;
3084
3085 switch (chip->driver_type) {
3086 case AZX_DRIVER_VIA:
3087 /* force to non-snoop mode for a new VIA controller
3088 * when BIOS is set
3089 */
3090 if (snoop) {
3091 u8 val;
3092 pci_read_config_byte(chip->pci, 0x42, &val);
3093 if (!(val & 0x80) && chip->pci->revision == 0x30)
3094 snoop = false;
3095 }
3096 break;
3097 case AZX_DRIVER_ATIHDMI_NS:
3098 /* new ATI HDMI requires non-snoop */
3099 snoop = false;
3100 break;
3101 }
3102
3103 if (snoop != chip->snoop) {
3104 snd_printk(KERN_INFO SFX "Force to %s mode\n",
3105 snoop ? "snoop" : "non-snoop");
3106 chip->snoop = snoop;
3107 }
3108 }
3109
3110 /*
3111 * constructor
3112 */
3113 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
3114 int dev, unsigned int driver_caps,
3115 struct azx **rchip)
3116 {
3117 static struct snd_device_ops ops = {
3118 .dev_free = azx_dev_free,
3119 };
3120 struct azx *chip;
3121 int err;
3122
3123 *rchip = NULL;
3124
3125 err = pci_enable_device(pci);
3126 if (err < 0)
3127 return err;
3128
3129 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3130 if (!chip) {
3131 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
3132 pci_disable_device(pci);
3133 return -ENOMEM;
3134 }
3135
3136 spin_lock_init(&chip->reg_lock);
3137 mutex_init(&chip->open_mutex);
3138 chip->card = card;
3139 chip->pci = pci;
3140 chip->irq = -1;
3141 chip->driver_caps = driver_caps;
3142 chip->driver_type = driver_caps & 0xff;
3143 check_msi(chip);
3144 chip->dev_index = dev;
3145 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3146 INIT_LIST_HEAD(&chip->pcm_list);
3147 INIT_LIST_HEAD(&chip->list);
3148 init_vga_switcheroo(chip);
3149
3150 chip->position_fix[0] = chip->position_fix[1] =
3151 check_position_fix(chip, position_fix[dev]);
3152 /* combo mode uses LPIB for playback */
3153 if (chip->position_fix[0] == POS_FIX_COMBO) {
3154 chip->position_fix[0] = POS_FIX_LPIB;
3155 chip->position_fix[1] = POS_FIX_AUTO;
3156 }
3157
3158 check_probe_mask(chip, dev);
3159
3160 chip->single_cmd = single_cmd;
3161 chip->snoop = hda_snoop;
3162 azx_check_snoop_available(chip);
3163
3164 if (bdl_pos_adj[dev] < 0) {
3165 switch (chip->driver_type) {
3166 case AZX_DRIVER_ICH:
3167 case AZX_DRIVER_PCH:
3168 bdl_pos_adj[dev] = 1;
3169 break;
3170 default:
3171 bdl_pos_adj[dev] = 32;
3172 break;
3173 }
3174 }
3175
3176 if (check_hdmi_disabled(pci)) {
3177 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3178 pci_name(pci));
3179 if (use_vga_switcheroo(chip)) {
3180 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3181 chip->disabled = true;
3182 goto ok;
3183 }
3184 kfree(chip);
3185 pci_disable_device(pci);
3186 return -ENXIO;
3187 }
3188
3189 err = azx_first_init(chip);
3190 if (err < 0) {
3191 azx_free(chip);
3192 return err;
3193 }
3194
3195 ok:
3196 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3197 if (err < 0) {
3198 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3199 azx_free(chip);
3200 return err;
3201 }
3202
3203 *rchip = chip;
3204 return 0;
3205 }
3206
3207 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3208 {
3209 int dev = chip->dev_index;
3210 struct pci_dev *pci = chip->pci;
3211 struct snd_card *card = chip->card;
3212 int i, err;
3213 unsigned short gcap;
3214
3215 #if BITS_PER_LONG != 64
3216 /* Fix up base address on ULI M5461 */
3217 if (chip->driver_type == AZX_DRIVER_ULI) {
3218 u16 tmp3;
3219 pci_read_config_word(pci, 0x40, &tmp3);
3220 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3221 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3222 }
3223 #endif
3224
3225 err = pci_request_regions(pci, "ICH HD audio");
3226 if (err < 0)
3227 return err;
3228 chip->region_requested = 1;
3229
3230 chip->addr = pci_resource_start(pci, 0);
3231 chip->remap_addr = pci_ioremap_bar(pci, 0);
3232 if (chip->remap_addr == NULL) {
3233 snd_printk(KERN_ERR SFX "ioremap error\n");
3234 return -ENXIO;
3235 }
3236
3237 if (chip->msi)
3238 if (pci_enable_msi(pci) < 0)
3239 chip->msi = 0;
3240
3241 if (azx_acquire_irq(chip, 0) < 0)
3242 return -EBUSY;
3243
3244 pci_set_master(pci);
3245 synchronize_irq(chip->irq);
3246
3247 gcap = azx_readw(chip, GCAP);
3248 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3249
3250 /* disable SB600 64bit support for safety */
3251 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3252 struct pci_dev *p_smbus;
3253 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3254 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3255 NULL);
3256 if (p_smbus) {
3257 if (p_smbus->revision < 0x30)
3258 gcap &= ~ICH6_GCAP_64OK;
3259 pci_dev_put(p_smbus);
3260 }
3261 }
3262
3263 /* disable 64bit DMA address on some devices */
3264 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3265 snd_printd(SFX "Disabling 64bit DMA\n");
3266 gcap &= ~ICH6_GCAP_64OK;
3267 }
3268
3269 /* disable buffer size rounding to 128-byte multiples if supported */
3270 if (align_buffer_size >= 0)
3271 chip->align_buffer_size = !!align_buffer_size;
3272 else {
3273 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3274 chip->align_buffer_size = 0;
3275 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3276 chip->align_buffer_size = 1;
3277 else
3278 chip->align_buffer_size = 1;
3279 }
3280
3281 /* allow 64bit DMA address if supported by H/W */
3282 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3283 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3284 else {
3285 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3286 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3287 }
3288
3289 /* read number of streams from GCAP register instead of using
3290 * hardcoded value
3291 */
3292 chip->capture_streams = (gcap >> 8) & 0x0f;
3293 chip->playback_streams = (gcap >> 12) & 0x0f;
3294 if (!chip->playback_streams && !chip->capture_streams) {
3295 /* gcap didn't give any info, switching to old method */
3296
3297 switch (chip->driver_type) {
3298 case AZX_DRIVER_ULI:
3299 chip->playback_streams = ULI_NUM_PLAYBACK;
3300 chip->capture_streams = ULI_NUM_CAPTURE;
3301 break;
3302 case AZX_DRIVER_ATIHDMI:
3303 case AZX_DRIVER_ATIHDMI_NS:
3304 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3305 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3306 break;
3307 case AZX_DRIVER_GENERIC:
3308 default:
3309 chip->playback_streams = ICH6_NUM_PLAYBACK;
3310 chip->capture_streams = ICH6_NUM_CAPTURE;
3311 break;
3312 }
3313 }
3314 chip->capture_index_offset = 0;
3315 chip->playback_index_offset = chip->capture_streams;
3316 chip->num_streams = chip->playback_streams + chip->capture_streams;
3317 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3318 GFP_KERNEL);
3319 if (!chip->azx_dev) {
3320 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3321 return -ENOMEM;
3322 }
3323
3324 for (i = 0; i < chip->num_streams; i++) {
3325 /* allocate memory for the BDL for each stream */
3326 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3327 snd_dma_pci_data(chip->pci),
3328 BDL_SIZE, &chip->azx_dev[i].bdl);
3329 if (err < 0) {
3330 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3331 return -ENOMEM;
3332 }
3333 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3334 }
3335 /* allocate memory for the position buffer */
3336 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3337 snd_dma_pci_data(chip->pci),
3338 chip->num_streams * 8, &chip->posbuf);
3339 if (err < 0) {
3340 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3341 return -ENOMEM;
3342 }
3343 mark_pages_wc(chip, &chip->posbuf, true);
3344 /* allocate CORB/RIRB */
3345 err = azx_alloc_cmd_io(chip);
3346 if (err < 0)
3347 return err;
3348
3349 /* initialize streams */
3350 azx_init_stream(chip);
3351
3352 /* initialize chip */
3353 azx_init_pci(chip);
3354 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3355
3356 /* codec detection */
3357 if (!chip->codec_mask) {
3358 snd_printk(KERN_ERR SFX "no codecs found!\n");
3359 return -ENODEV;
3360 }
3361
3362 strcpy(card->driver, "HDA-Intel");
3363 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3364 sizeof(card->shortname));
3365 snprintf(card->longname, sizeof(card->longname),
3366 "%s at 0x%lx irq %i",
3367 card->shortname, chip->addr, chip->irq);
3368
3369 return 0;
3370 }
3371
3372 static void power_down_all_codecs(struct azx *chip)
3373 {
3374 #ifdef CONFIG_PM
3375 /* The codecs were powered up in snd_hda_codec_new().
3376 * Now all initialization done, so turn them down if possible
3377 */
3378 struct hda_codec *codec;
3379 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3380 snd_hda_power_down(codec);
3381 }
3382 #endif
3383 }
3384
3385 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3386 /* callback from request_firmware_nowait() */
3387 static void azx_firmware_cb(const struct firmware *fw, void *context)
3388 {
3389 struct snd_card *card = context;
3390 struct azx *chip = card->private_data;
3391 struct pci_dev *pci = chip->pci;
3392
3393 if (!fw) {
3394 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3395 goto error;
3396 }
3397
3398 chip->fw = fw;
3399 if (!chip->disabled) {
3400 /* continue probing */
3401 if (azx_probe_continue(chip))
3402 goto error;
3403 }
3404 return; /* OK */
3405
3406 error:
3407 snd_card_free(card);
3408 pci_set_drvdata(pci, NULL);
3409 }
3410 #endif
3411
3412 static int __devinit azx_probe(struct pci_dev *pci,
3413 const struct pci_device_id *pci_id)
3414 {
3415 static int dev;
3416 struct snd_card *card;
3417 struct azx *chip;
3418 bool probe_now;
3419 int err;
3420
3421 if (dev >= SNDRV_CARDS)
3422 return -ENODEV;
3423 if (!enable[dev]) {
3424 dev++;
3425 return -ENOENT;
3426 }
3427
3428 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3429 if (err < 0) {
3430 snd_printk(KERN_ERR SFX "Error creating card!\n");
3431 return err;
3432 }
3433
3434 snd_card_set_dev(card, &pci->dev);
3435
3436 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3437 if (err < 0)
3438 goto out_free;
3439 card->private_data = chip;
3440 probe_now = !chip->disabled;
3441
3442 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3443 if (patch[dev] && *patch[dev]) {
3444 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3445 patch[dev]);
3446 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3447 &pci->dev, GFP_KERNEL, card,
3448 azx_firmware_cb);
3449 if (err < 0)
3450 goto out_free;
3451 probe_now = false; /* continued in azx_firmware_cb() */
3452 }
3453 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3454
3455 if (probe_now) {
3456 err = azx_probe_continue(chip);
3457 if (err < 0)
3458 goto out_free;
3459 }
3460
3461 pci_set_drvdata(pci, card);
3462
3463 if (pci_dev_run_wake(pci))
3464 pm_runtime_put_noidle(&pci->dev);
3465
3466 err = register_vga_switcheroo(chip);
3467 if (err < 0) {
3468 snd_printk(KERN_ERR SFX
3469 "Error registering VGA-switcheroo client\n");
3470 goto out_free;
3471 }
3472
3473 dev++;
3474 return 0;
3475
3476 out_free:
3477 snd_card_free(card);
3478 return err;
3479 }
3480
3481 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3482 {
3483 int dev = chip->dev_index;
3484 int err;
3485
3486 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3487 chip->beep_mode = beep_mode[dev];
3488 #endif
3489
3490 /* create codec instances */
3491 err = azx_codec_create(chip, model[dev]);
3492 if (err < 0)
3493 goto out_free;
3494 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3495 if (chip->fw) {
3496 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3497 chip->fw->data);
3498 if (err < 0)
3499 goto out_free;
3500 release_firmware(chip->fw); /* no longer needed */
3501 chip->fw = NULL;
3502 }
3503 #endif
3504 if ((probe_only[dev] & 1) == 0) {
3505 err = azx_codec_configure(chip);
3506 if (err < 0)
3507 goto out_free;
3508 }
3509
3510 /* create PCM streams */
3511 err = snd_hda_build_pcms(chip->bus);
3512 if (err < 0)
3513 goto out_free;
3514
3515 /* create mixer controls */
3516 err = azx_mixer_create(chip);
3517 if (err < 0)
3518 goto out_free;
3519
3520 err = snd_card_register(chip->card);
3521 if (err < 0)
3522 goto out_free;
3523
3524 chip->running = 1;
3525 power_down_all_codecs(chip);
3526 azx_notifier_register(chip);
3527 azx_add_card_list(chip);
3528
3529 return 0;
3530
3531 out_free:
3532 chip->init_failed = 1;
3533 return err;
3534 }
3535
3536 static void __devexit azx_remove(struct pci_dev *pci)
3537 {
3538 struct snd_card *card = pci_get_drvdata(pci);
3539
3540 if (pci_dev_run_wake(pci))
3541 pm_runtime_get_noresume(&pci->dev);
3542
3543 if (card)
3544 snd_card_free(card);
3545 pci_set_drvdata(pci, NULL);
3546 }
3547
3548 /* PCI IDs */
3549 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3550 /* CPT */
3551 { PCI_DEVICE(0x8086, 0x1c20),
3552 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3553 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3554 /* PBG */
3555 { PCI_DEVICE(0x8086, 0x1d20),
3556 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3557 AZX_DCAPS_BUFSIZE},
3558 /* Panther Point */
3559 { PCI_DEVICE(0x8086, 0x1e20),
3560 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3561 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3562 /* Lynx Point */
3563 { PCI_DEVICE(0x8086, 0x8c20),
3564 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3565 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3566 /* Lynx Point-LP */
3567 { PCI_DEVICE(0x8086, 0x9c20),
3568 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3569 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3570 /* Lynx Point-LP */
3571 { PCI_DEVICE(0x8086, 0x9c21),
3572 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3573 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3574 /* Haswell */
3575 { PCI_DEVICE(0x8086, 0x0c0c),
3576 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3577 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3578 { PCI_DEVICE(0x8086, 0x0d0c),
3579 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3580 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3581 /* 5 Series/3400 */
3582 { PCI_DEVICE(0x8086, 0x3b56),
3583 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3584 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3585 /* SCH */
3586 { PCI_DEVICE(0x8086, 0x811b),
3587 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3588 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3589 { PCI_DEVICE(0x8086, 0x080a),
3590 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3591 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3592 /* ICH */
3593 { PCI_DEVICE(0x8086, 0x2668),
3594 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3595 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3596 { PCI_DEVICE(0x8086, 0x27d8),
3597 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3598 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3599 { PCI_DEVICE(0x8086, 0x269a),
3600 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3601 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3602 { PCI_DEVICE(0x8086, 0x284b),
3603 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3604 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3605 { PCI_DEVICE(0x8086, 0x293e),
3606 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3607 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3608 { PCI_DEVICE(0x8086, 0x293f),
3609 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3610 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3611 { PCI_DEVICE(0x8086, 0x3a3e),
3612 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3613 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3614 { PCI_DEVICE(0x8086, 0x3a6e),
3615 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3616 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3617 /* Generic Intel */
3618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3619 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3620 .class_mask = 0xffffff,
3621 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3622 /* ATI SB 450/600/700/800/900 */
3623 { PCI_DEVICE(0x1002, 0x437b),
3624 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3625 { PCI_DEVICE(0x1002, 0x4383),
3626 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3627 /* AMD Hudson */
3628 { PCI_DEVICE(0x1022, 0x780d),
3629 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3630 /* ATI HDMI */
3631 { PCI_DEVICE(0x1002, 0x793b),
3632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3633 { PCI_DEVICE(0x1002, 0x7919),
3634 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3635 { PCI_DEVICE(0x1002, 0x960f),
3636 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3637 { PCI_DEVICE(0x1002, 0x970f),
3638 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3639 { PCI_DEVICE(0x1002, 0xaa00),
3640 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3641 { PCI_DEVICE(0x1002, 0xaa08),
3642 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3643 { PCI_DEVICE(0x1002, 0xaa10),
3644 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3645 { PCI_DEVICE(0x1002, 0xaa18),
3646 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3647 { PCI_DEVICE(0x1002, 0xaa20),
3648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3649 { PCI_DEVICE(0x1002, 0xaa28),
3650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3651 { PCI_DEVICE(0x1002, 0xaa30),
3652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3653 { PCI_DEVICE(0x1002, 0xaa38),
3654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3655 { PCI_DEVICE(0x1002, 0xaa40),
3656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3657 { PCI_DEVICE(0x1002, 0xaa48),
3658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3659 { PCI_DEVICE(0x1002, 0x9902),
3660 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3661 { PCI_DEVICE(0x1002, 0xaaa0),
3662 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3663 { PCI_DEVICE(0x1002, 0xaaa8),
3664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3665 { PCI_DEVICE(0x1002, 0xaab0),
3666 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3667 /* VIA VT8251/VT8237A */
3668 { PCI_DEVICE(0x1106, 0x3288),
3669 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3670 /* VIA GFX VT7122/VX900 */
3671 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3672 /* VIA GFX VT6122/VX11 */
3673 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3674 /* SIS966 */
3675 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3676 /* ULI M5461 */
3677 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3678 /* NVIDIA MCP */
3679 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3680 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3681 .class_mask = 0xffffff,
3682 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3683 /* Teradici */
3684 { PCI_DEVICE(0x6549, 0x1200),
3685 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3686 { PCI_DEVICE(0x6549, 0x2200),
3687 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3688 /* Creative X-Fi (CA0110-IBG) */
3689 /* CTHDA chips */
3690 { PCI_DEVICE(0x1102, 0x0010),
3691 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3692 { PCI_DEVICE(0x1102, 0x0012),
3693 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3694 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3695 /* the following entry conflicts with snd-ctxfi driver,
3696 * as ctxfi driver mutates from HD-audio to native mode with
3697 * a special command sequence.
3698 */
3699 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3700 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3701 .class_mask = 0xffffff,
3702 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3703 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3704 #else
3705 /* this entry seems still valid -- i.e. without emu20kx chip */
3706 { PCI_DEVICE(0x1102, 0x0009),
3707 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3708 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3709 #endif
3710 /* Vortex86MX */
3711 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3712 /* VMware HDAudio */
3713 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3714 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3715 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3716 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3717 .class_mask = 0xffffff,
3718 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3719 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3720 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3721 .class_mask = 0xffffff,
3722 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3723 { 0, }
3724 };
3725 MODULE_DEVICE_TABLE(pci, azx_ids);
3726
3727 /* pci_driver definition */
3728 static struct pci_driver azx_driver = {
3729 .name = KBUILD_MODNAME,
3730 .id_table = azx_ids,
3731 .probe = azx_probe,
3732 .remove = __devexit_p(azx_remove),
3733 .driver = {
3734 .pm = AZX_PM_OPS,
3735 },
3736 };
3737
3738 module_pci_driver(azx_driver);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree