2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/bitmap.h>
22 #include <linux/slab.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
32 #include <asm/amd_iommu_proto.h>
33 #include <asm/amd_iommu_types.h>
34 #include <asm/amd_iommu.h>
36 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
38 #define EXIT_LOOP_COUNT 10000000
40 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
42 /* A list of preallocated protection domains */
43 static LIST_HEAD(iommu_pd_list
);
44 static DEFINE_SPINLOCK(iommu_pd_list_lock
);
47 * Domain for untranslated devices - only allocated
48 * if iommu=pt passed on kernel cmd line.
50 static struct protection_domain
*pt_domain
;
52 static struct iommu_ops amd_iommu_ops
;
55 * general struct to manage commands send to an IOMMU
61 static void reset_iommu_command_buffer(struct amd_iommu
*iommu
);
62 static void update_domain(struct protection_domain
*domain
);
64 /****************************************************************************
68 ****************************************************************************/
70 static inline u16
get_device_id(struct device
*dev
)
72 struct pci_dev
*pdev
= to_pci_dev(dev
);
74 return calc_devid(pdev
->bus
->number
, pdev
->devfn
);
77 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
79 return dev
->archdata
.iommu
;
83 * In this function the list of preallocated protection domains is traversed to
84 * find the domain for a specific device
86 static struct dma_ops_domain
*find_protection_domain(u16 devid
)
88 struct dma_ops_domain
*entry
, *ret
= NULL
;
90 u16 alias
= amd_iommu_alias_table
[devid
];
92 if (list_empty(&iommu_pd_list
))
95 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
97 list_for_each_entry(entry
, &iommu_pd_list
, list
) {
98 if (entry
->target_dev
== devid
||
99 entry
->target_dev
== alias
) {
105 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
111 * This function checks if the driver got a valid device from the caller to
112 * avoid dereferencing invalid pointers.
114 static bool check_device(struct device
*dev
)
118 if (!dev
|| !dev
->dma_mask
)
121 /* No device or no PCI device */
122 if (dev
->bus
!= &pci_bus_type
)
125 devid
= get_device_id(dev
);
127 /* Out of our scope? */
128 if (devid
> amd_iommu_last_bdf
)
131 if (amd_iommu_rlookup_table
[devid
] == NULL
)
137 static int iommu_init_device(struct device
*dev
)
139 struct iommu_dev_data
*dev_data
;
140 struct pci_dev
*pdev
;
143 if (dev
->archdata
.iommu
)
146 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
152 devid
= get_device_id(dev
);
153 alias
= amd_iommu_alias_table
[devid
];
154 pdev
= pci_get_bus_and_slot(PCI_BUS(alias
), alias
& 0xff);
156 dev_data
->alias
= &pdev
->dev
;
162 atomic_set(&dev_data
->bind
, 0);
164 dev
->archdata
.iommu
= dev_data
;
170 static void iommu_ignore_device(struct device
*dev
)
174 devid
= get_device_id(dev
);
175 alias
= amd_iommu_alias_table
[devid
];
177 memset(&amd_iommu_dev_table
[devid
], 0, sizeof(struct dev_table_entry
));
178 memset(&amd_iommu_dev_table
[alias
], 0, sizeof(struct dev_table_entry
));
180 amd_iommu_rlookup_table
[devid
] = NULL
;
181 amd_iommu_rlookup_table
[alias
] = NULL
;
184 static void iommu_uninit_device(struct device
*dev
)
186 kfree(dev
->archdata
.iommu
);
189 void __init
amd_iommu_uninit_devices(void)
191 struct pci_dev
*pdev
= NULL
;
193 for_each_pci_dev(pdev
) {
195 if (!check_device(&pdev
->dev
))
198 iommu_uninit_device(&pdev
->dev
);
202 int __init
amd_iommu_init_devices(void)
204 struct pci_dev
*pdev
= NULL
;
207 for_each_pci_dev(pdev
) {
209 if (!check_device(&pdev
->dev
))
212 ret
= iommu_init_device(&pdev
->dev
);
213 if (ret
== -ENOTSUPP
)
214 iommu_ignore_device(&pdev
->dev
);
223 amd_iommu_uninit_devices();
227 #ifdef CONFIG_AMD_IOMMU_STATS
230 * Initialization code for statistics collection
233 DECLARE_STATS_COUNTER(compl_wait
);
234 DECLARE_STATS_COUNTER(cnt_map_single
);
235 DECLARE_STATS_COUNTER(cnt_unmap_single
);
236 DECLARE_STATS_COUNTER(cnt_map_sg
);
237 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
238 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
239 DECLARE_STATS_COUNTER(cnt_free_coherent
);
240 DECLARE_STATS_COUNTER(cross_page
);
241 DECLARE_STATS_COUNTER(domain_flush_single
);
242 DECLARE_STATS_COUNTER(domain_flush_all
);
243 DECLARE_STATS_COUNTER(alloced_io_mem
);
244 DECLARE_STATS_COUNTER(total_map_requests
);
246 static struct dentry
*stats_dir
;
247 static struct dentry
*de_fflush
;
249 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
251 if (stats_dir
== NULL
)
254 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
258 static void amd_iommu_stats_init(void)
260 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
261 if (stats_dir
== NULL
)
264 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
265 (u32
*)&amd_iommu_unmap_flush
);
267 amd_iommu_stats_add(&compl_wait
);
268 amd_iommu_stats_add(&cnt_map_single
);
269 amd_iommu_stats_add(&cnt_unmap_single
);
270 amd_iommu_stats_add(&cnt_map_sg
);
271 amd_iommu_stats_add(&cnt_unmap_sg
);
272 amd_iommu_stats_add(&cnt_alloc_coherent
);
273 amd_iommu_stats_add(&cnt_free_coherent
);
274 amd_iommu_stats_add(&cross_page
);
275 amd_iommu_stats_add(&domain_flush_single
);
276 amd_iommu_stats_add(&domain_flush_all
);
277 amd_iommu_stats_add(&alloced_io_mem
);
278 amd_iommu_stats_add(&total_map_requests
);
283 /****************************************************************************
285 * Interrupt handling functions
287 ****************************************************************************/
289 static void dump_dte_entry(u16 devid
)
293 for (i
= 0; i
< 8; ++i
)
294 pr_err("AMD-Vi: DTE[%d]: %08x\n", i
,
295 amd_iommu_dev_table
[devid
].data
[i
]);
298 static void dump_command(unsigned long phys_addr
)
300 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
303 for (i
= 0; i
< 4; ++i
)
304 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
307 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
310 int type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
311 int devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
312 int domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
313 int flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
314 u64 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
316 printk(KERN_ERR
"AMD-Vi: Event logged [");
319 case EVENT_TYPE_ILL_DEV
:
320 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
321 "address=0x%016llx flags=0x%04x]\n",
322 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
324 dump_dte_entry(devid
);
326 case EVENT_TYPE_IO_FAULT
:
327 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
328 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
329 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
330 domid
, address
, flags
);
332 case EVENT_TYPE_DEV_TAB_ERR
:
333 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
334 "address=0x%016llx flags=0x%04x]\n",
335 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
338 case EVENT_TYPE_PAGE_TAB_ERR
:
339 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
340 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
341 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
342 domid
, address
, flags
);
344 case EVENT_TYPE_ILL_CMD
:
345 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
346 iommu
->reset_in_progress
= true;
347 reset_iommu_command_buffer(iommu
);
348 dump_command(address
);
350 case EVENT_TYPE_CMD_HARD_ERR
:
351 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
352 "flags=0x%04x]\n", address
, flags
);
354 case EVENT_TYPE_IOTLB_INV_TO
:
355 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
356 "address=0x%016llx]\n",
357 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
360 case EVENT_TYPE_INV_DEV_REQ
:
361 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
362 "address=0x%016llx flags=0x%04x]\n",
363 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
367 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
371 static void iommu_poll_events(struct amd_iommu
*iommu
)
376 spin_lock_irqsave(&iommu
->lock
, flags
);
378 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
379 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
381 while (head
!= tail
) {
382 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
383 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
386 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
388 spin_unlock_irqrestore(&iommu
->lock
, flags
);
391 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
393 struct amd_iommu
*iommu
;
395 for_each_iommu(iommu
)
396 iommu_poll_events(iommu
);
401 /****************************************************************************
403 * IOMMU command queuing functions
405 ****************************************************************************/
408 * Writes the command to the IOMMUs command buffer and informs the
409 * hardware about the new command. Must be called with iommu->lock held.
411 static int __iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
416 WARN_ON(iommu
->cmd_buf_size
& CMD_BUFFER_UNINITIALIZED
);
417 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
418 target
= iommu
->cmd_buf
+ tail
;
419 memcpy_toio(target
, cmd
, sizeof(*cmd
));
420 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
421 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
424 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
430 * General queuing function for commands. Takes iommu->lock and calls
431 * __iommu_queue_command().
433 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
438 spin_lock_irqsave(&iommu
->lock
, flags
);
439 ret
= __iommu_queue_command(iommu
, cmd
);
441 iommu
->need_sync
= true;
442 spin_unlock_irqrestore(&iommu
->lock
, flags
);
448 * This function waits until an IOMMU has completed a completion
451 static void __iommu_wait_for_completion(struct amd_iommu
*iommu
)
457 INC_STATS_COUNTER(compl_wait
);
459 while (!ready
&& (i
< EXIT_LOOP_COUNT
)) {
461 /* wait for the bit to become one */
462 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
463 ready
= status
& MMIO_STATUS_COM_WAIT_INT_MASK
;
466 /* set bit back to zero */
467 status
&= ~MMIO_STATUS_COM_WAIT_INT_MASK
;
468 writel(status
, iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
470 if (unlikely(i
== EXIT_LOOP_COUNT
))
471 iommu
->reset_in_progress
= true;
475 * This function queues a completion wait command into the command
478 static int __iommu_completion_wait(struct amd_iommu
*iommu
)
480 struct iommu_cmd cmd
;
482 memset(&cmd
, 0, sizeof(cmd
));
483 cmd
.data
[0] = CMD_COMPL_WAIT_INT_MASK
;
484 CMD_SET_TYPE(&cmd
, CMD_COMPL_WAIT
);
486 return __iommu_queue_command(iommu
, &cmd
);
490 * This function is called whenever we need to ensure that the IOMMU has
491 * completed execution of all commands we sent. It sends a
492 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
493 * us about that by writing a value to a physical address we pass with
496 static int iommu_completion_wait(struct amd_iommu
*iommu
)
501 spin_lock_irqsave(&iommu
->lock
, flags
);
503 if (!iommu
->need_sync
)
506 ret
= __iommu_completion_wait(iommu
);
508 iommu
->need_sync
= false;
513 __iommu_wait_for_completion(iommu
);
516 spin_unlock_irqrestore(&iommu
->lock
, flags
);
518 if (iommu
->reset_in_progress
)
519 reset_iommu_command_buffer(iommu
);
524 static void iommu_flush_complete(struct protection_domain
*domain
)
528 for (i
= 0; i
< amd_iommus_present
; ++i
) {
529 if (!domain
->dev_iommu
[i
])
533 * Devices of this domain are behind this IOMMU
534 * We need to wait for completion of all commands.
536 iommu_completion_wait(amd_iommus
[i
]);
541 * Command send function for invalidating a device table entry
543 static int iommu_flush_device(struct device
*dev
)
545 struct amd_iommu
*iommu
;
546 struct iommu_cmd cmd
;
549 devid
= get_device_id(dev
);
550 iommu
= amd_iommu_rlookup_table
[devid
];
553 memset(&cmd
, 0, sizeof(cmd
));
554 CMD_SET_TYPE(&cmd
, CMD_INV_DEV_ENTRY
);
557 return iommu_queue_command(iommu
, &cmd
);
560 static void __iommu_build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
561 u16 domid
, int pde
, int s
)
563 memset(cmd
, 0, sizeof(*cmd
));
564 address
&= PAGE_MASK
;
565 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
566 cmd
->data
[1] |= domid
;
567 cmd
->data
[2] = lower_32_bits(address
);
568 cmd
->data
[3] = upper_32_bits(address
);
569 if (s
) /* size bit - we flush more than one 4kb page */
570 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
571 if (pde
) /* PDE bit - we wan't flush everything not only the PTEs */
572 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
576 * Generic command send function for invalidaing TLB entries
578 static int iommu_queue_inv_iommu_pages(struct amd_iommu
*iommu
,
579 u64 address
, u16 domid
, int pde
, int s
)
581 struct iommu_cmd cmd
;
584 __iommu_build_inv_iommu_pages(&cmd
, address
, domid
, pde
, s
);
586 ret
= iommu_queue_command(iommu
, &cmd
);
592 * TLB invalidation function which is called from the mapping functions.
593 * It invalidates a single PTE if the range to flush is within a single
594 * page. Otherwise it flushes the whole TLB of the IOMMU.
596 static void __iommu_flush_pages(struct protection_domain
*domain
,
597 u64 address
, size_t size
, int pde
)
600 unsigned long pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
602 address
&= PAGE_MASK
;
606 * If we have to flush more than one page, flush all
607 * TLB entries for this domain
609 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
614 for (i
= 0; i
< amd_iommus_present
; ++i
) {
615 if (!domain
->dev_iommu
[i
])
619 * Devices of this domain are behind this IOMMU
620 * We need a TLB flush
622 iommu_queue_inv_iommu_pages(amd_iommus
[i
], address
,
629 static void iommu_flush_pages(struct protection_domain
*domain
,
630 u64 address
, size_t size
)
632 __iommu_flush_pages(domain
, address
, size
, 0);
635 /* Flush the whole IO/TLB for a given protection domain */
636 static void iommu_flush_tlb(struct protection_domain
*domain
)
638 __iommu_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
641 /* Flush the whole IO/TLB for a given protection domain - including PDE */
642 static void iommu_flush_tlb_pde(struct protection_domain
*domain
)
644 __iommu_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
649 * This function flushes the DTEs for all devices in domain
651 static void iommu_flush_domain_devices(struct protection_domain
*domain
)
653 struct iommu_dev_data
*dev_data
;
656 spin_lock_irqsave(&domain
->lock
, flags
);
658 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
659 iommu_flush_device(dev_data
->dev
);
661 spin_unlock_irqrestore(&domain
->lock
, flags
);
664 static void iommu_flush_all_domain_devices(void)
666 struct protection_domain
*domain
;
669 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
671 list_for_each_entry(domain
, &amd_iommu_pd_list
, list
) {
672 iommu_flush_domain_devices(domain
);
673 iommu_flush_complete(domain
);
676 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
679 void amd_iommu_flush_all_devices(void)
681 iommu_flush_all_domain_devices();
685 * This function uses heavy locking and may disable irqs for some time. But
686 * this is no issue because it is only called during resume.
688 void amd_iommu_flush_all_domains(void)
690 struct protection_domain
*domain
;
693 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
695 list_for_each_entry(domain
, &amd_iommu_pd_list
, list
) {
696 spin_lock(&domain
->lock
);
697 iommu_flush_tlb_pde(domain
);
698 iommu_flush_complete(domain
);
699 spin_unlock(&domain
->lock
);
702 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
705 static void reset_iommu_command_buffer(struct amd_iommu
*iommu
)
707 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
709 if (iommu
->reset_in_progress
)
710 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
712 amd_iommu_reset_cmd_buffer(iommu
);
713 amd_iommu_flush_all_devices();
714 amd_iommu_flush_all_domains();
716 iommu
->reset_in_progress
= false;
719 /****************************************************************************
721 * The functions below are used the create the page table mappings for
722 * unity mapped regions.
724 ****************************************************************************/
727 * This function is used to add another level to an IO page table. Adding
728 * another level increases the size of the address space by 9 bits to a size up
731 static bool increase_address_space(struct protection_domain
*domain
,
736 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
737 /* address space already 64 bit large */
740 pte
= (void *)get_zeroed_page(gfp
);
744 *pte
= PM_LEVEL_PDE(domain
->mode
,
745 virt_to_phys(domain
->pt_root
));
746 domain
->pt_root
= pte
;
748 domain
->updated
= true;
753 static u64
*alloc_pte(struct protection_domain
*domain
,
754 unsigned long address
,
755 unsigned long page_size
,
762 BUG_ON(!is_power_of_2(page_size
));
764 while (address
> PM_LEVEL_SIZE(domain
->mode
))
765 increase_address_space(domain
, gfp
);
767 level
= domain
->mode
- 1;
768 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
769 address
= PAGE_SIZE_ALIGN(address
, page_size
);
770 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
772 while (level
> end_lvl
) {
773 if (!IOMMU_PTE_PRESENT(*pte
)) {
774 page
= (u64
*)get_zeroed_page(gfp
);
777 *pte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
780 /* No level skipping support yet */
781 if (PM_PTE_LEVEL(*pte
) != level
)
786 pte
= IOMMU_PTE_PAGE(*pte
);
788 if (pte_page
&& level
== end_lvl
)
791 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
798 * This function checks if there is a PTE for a given dma address. If
799 * there is one, it returns the pointer to it.
801 static u64
*fetch_pte(struct protection_domain
*domain
, unsigned long address
)
806 if (address
> PM_LEVEL_SIZE(domain
->mode
))
809 level
= domain
->mode
- 1;
810 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
815 if (!IOMMU_PTE_PRESENT(*pte
))
819 if (PM_PTE_LEVEL(*pte
) == 0x07) {
820 unsigned long pte_mask
, __pte
;
823 * If we have a series of large PTEs, make
824 * sure to return a pointer to the first one.
826 pte_mask
= PTE_PAGE_SIZE(*pte
);
827 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
828 __pte
= ((unsigned long)pte
) & pte_mask
;
833 /* No level skipping support yet */
834 if (PM_PTE_LEVEL(*pte
) != level
)
839 /* Walk to the next level */
840 pte
= IOMMU_PTE_PAGE(*pte
);
841 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
848 * Generic mapping functions. It maps a physical address into a DMA
849 * address space. It allocates the page table pages if necessary.
850 * In the future it can be extended to a generic mapping function
851 * supporting all features of AMD IOMMU page tables like level skipping
852 * and full 64 bit address spaces.
854 static int iommu_map_page(struct protection_domain
*dom
,
855 unsigned long bus_addr
,
856 unsigned long phys_addr
,
858 unsigned long page_size
)
863 if (!(prot
& IOMMU_PROT_MASK
))
866 bus_addr
= PAGE_ALIGN(bus_addr
);
867 phys_addr
= PAGE_ALIGN(phys_addr
);
868 count
= PAGE_SIZE_PTE_COUNT(page_size
);
869 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, GFP_KERNEL
);
871 for (i
= 0; i
< count
; ++i
)
872 if (IOMMU_PTE_PRESENT(pte
[i
]))
875 if (page_size
> PAGE_SIZE
) {
876 __pte
= PAGE_SIZE_PTE(phys_addr
, page_size
);
877 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_P
| IOMMU_PTE_FC
;
879 __pte
= phys_addr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
881 if (prot
& IOMMU_PROT_IR
)
882 __pte
|= IOMMU_PTE_IR
;
883 if (prot
& IOMMU_PROT_IW
)
884 __pte
|= IOMMU_PTE_IW
;
886 for (i
= 0; i
< count
; ++i
)
894 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
895 unsigned long bus_addr
,
896 unsigned long page_size
)
898 unsigned long long unmap_size
, unmapped
;
901 BUG_ON(!is_power_of_2(page_size
));
905 while (unmapped
< page_size
) {
907 pte
= fetch_pte(dom
, bus_addr
);
911 * No PTE for this address
912 * move forward in 4kb steps
914 unmap_size
= PAGE_SIZE
;
915 } else if (PM_PTE_LEVEL(*pte
) == 0) {
916 /* 4kb PTE found for this address */
917 unmap_size
= PAGE_SIZE
;
922 /* Large PTE found which maps this address */
923 unmap_size
= PTE_PAGE_SIZE(*pte
);
924 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
925 for (i
= 0; i
< count
; i
++)
929 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
930 unmapped
+= unmap_size
;
933 BUG_ON(!is_power_of_2(unmapped
));
939 * This function checks if a specific unity mapping entry is needed for
940 * this specific IOMMU.
942 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
943 struct unity_map_entry
*entry
)
947 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
948 bdf
= amd_iommu_alias_table
[i
];
949 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
957 * This function actually applies the mapping to the page table of the
960 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
961 struct unity_map_entry
*e
)
966 for (addr
= e
->address_start
; addr
< e
->address_end
;
968 ret
= iommu_map_page(&dma_dom
->domain
, addr
, addr
, e
->prot
,
973 * if unity mapping is in aperture range mark the page
974 * as allocated in the aperture
976 if (addr
< dma_dom
->aperture_size
)
977 __set_bit(addr
>> PAGE_SHIFT
,
978 dma_dom
->aperture
[0]->bitmap
);
985 * Init the unity mappings for a specific IOMMU in the system
987 * Basically iterates over all unity mapping entries and applies them to
988 * the default domain DMA of that IOMMU if necessary.
990 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
992 struct unity_map_entry
*entry
;
995 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
996 if (!iommu_for_unity_map(iommu
, entry
))
998 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
1007 * Inits the unity mappings required for a specific device
1009 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
1012 struct unity_map_entry
*e
;
1015 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
1016 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
1018 ret
= dma_ops_unity_map(dma_dom
, e
);
1026 /****************************************************************************
1028 * The next functions belong to the address allocator for the dma_ops
1029 * interface functions. They work like the allocators in the other IOMMU
1030 * drivers. Its basically a bitmap which marks the allocated pages in
1031 * the aperture. Maybe it could be enhanced in the future to a more
1032 * efficient allocator.
1034 ****************************************************************************/
1037 * The address allocator core functions.
1039 * called with domain->lock held
1043 * Used to reserve address ranges in the aperture (e.g. for exclusion
1046 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
1047 unsigned long start_page
,
1050 unsigned int i
, last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
1052 if (start_page
+ pages
> last_page
)
1053 pages
= last_page
- start_page
;
1055 for (i
= start_page
; i
< start_page
+ pages
; ++i
) {
1056 int index
= i
/ APERTURE_RANGE_PAGES
;
1057 int page
= i
% APERTURE_RANGE_PAGES
;
1058 __set_bit(page
, dom
->aperture
[index
]->bitmap
);
1063 * This function is used to add a new aperture range to an existing
1064 * aperture in case of dma_ops domain allocation or address allocation
1067 static int alloc_new_range(struct dma_ops_domain
*dma_dom
,
1068 bool populate
, gfp_t gfp
)
1070 int index
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1071 struct amd_iommu
*iommu
;
1074 #ifdef CONFIG_IOMMU_STRESS
1078 if (index
>= APERTURE_MAX_RANGES
)
1081 dma_dom
->aperture
[index
] = kzalloc(sizeof(struct aperture_range
), gfp
);
1082 if (!dma_dom
->aperture
[index
])
1085 dma_dom
->aperture
[index
]->bitmap
= (void *)get_zeroed_page(gfp
);
1086 if (!dma_dom
->aperture
[index
]->bitmap
)
1089 dma_dom
->aperture
[index
]->offset
= dma_dom
->aperture_size
;
1092 unsigned long address
= dma_dom
->aperture_size
;
1093 int i
, num_ptes
= APERTURE_RANGE_PAGES
/ 512;
1094 u64
*pte
, *pte_page
;
1096 for (i
= 0; i
< num_ptes
; ++i
) {
1097 pte
= alloc_pte(&dma_dom
->domain
, address
, PAGE_SIZE
,
1102 dma_dom
->aperture
[index
]->pte_pages
[i
] = pte_page
;
1104 address
+= APERTURE_RANGE_SIZE
/ 64;
1108 dma_dom
->aperture_size
+= APERTURE_RANGE_SIZE
;
1110 /* Initialize the exclusion range if necessary */
1111 for_each_iommu(iommu
) {
1112 if (iommu
->exclusion_start
&&
1113 iommu
->exclusion_start
>= dma_dom
->aperture
[index
]->offset
1114 && iommu
->exclusion_start
< dma_dom
->aperture_size
) {
1115 unsigned long startpage
;
1116 int pages
= iommu_num_pages(iommu
->exclusion_start
,
1117 iommu
->exclusion_length
,
1119 startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
1120 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
1125 * Check for areas already mapped as present in the new aperture
1126 * range and mark those pages as reserved in the allocator. Such
1127 * mappings may already exist as a result of requested unity
1128 * mappings for devices.
1130 for (i
= dma_dom
->aperture
[index
]->offset
;
1131 i
< dma_dom
->aperture_size
;
1133 u64
*pte
= fetch_pte(&dma_dom
->domain
, i
);
1134 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
1137 dma_ops_reserve_addresses(dma_dom
, i
<< PAGE_SHIFT
, 1);
1140 update_domain(&dma_dom
->domain
);
1145 update_domain(&dma_dom
->domain
);
1147 free_page((unsigned long)dma_dom
->aperture
[index
]->bitmap
);
1149 kfree(dma_dom
->aperture
[index
]);
1150 dma_dom
->aperture
[index
] = NULL
;
1155 static unsigned long dma_ops_area_alloc(struct device
*dev
,
1156 struct dma_ops_domain
*dom
,
1158 unsigned long align_mask
,
1160 unsigned long start
)
1162 unsigned long next_bit
= dom
->next_address
% APERTURE_RANGE_SIZE
;
1163 int max_index
= dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1164 int i
= start
>> APERTURE_RANGE_SHIFT
;
1165 unsigned long boundary_size
;
1166 unsigned long address
= -1;
1167 unsigned long limit
;
1169 next_bit
>>= PAGE_SHIFT
;
1171 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
1172 PAGE_SIZE
) >> PAGE_SHIFT
;
1174 for (;i
< max_index
; ++i
) {
1175 unsigned long offset
= dom
->aperture
[i
]->offset
>> PAGE_SHIFT
;
1177 if (dom
->aperture
[i
]->offset
>= dma_mask
)
1180 limit
= iommu_device_max_index(APERTURE_RANGE_PAGES
, offset
,
1181 dma_mask
>> PAGE_SHIFT
);
1183 address
= iommu_area_alloc(dom
->aperture
[i
]->bitmap
,
1184 limit
, next_bit
, pages
, 0,
1185 boundary_size
, align_mask
);
1186 if (address
!= -1) {
1187 address
= dom
->aperture
[i
]->offset
+
1188 (address
<< PAGE_SHIFT
);
1189 dom
->next_address
= address
+ (pages
<< PAGE_SHIFT
);
1199 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
1200 struct dma_ops_domain
*dom
,
1202 unsigned long align_mask
,
1205 unsigned long address
;
1207 #ifdef CONFIG_IOMMU_STRESS
1208 dom
->next_address
= 0;
1209 dom
->need_flush
= true;
1212 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1213 dma_mask
, dom
->next_address
);
1215 if (address
== -1) {
1216 dom
->next_address
= 0;
1217 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1219 dom
->need_flush
= true;
1222 if (unlikely(address
== -1))
1223 address
= DMA_ERROR_CODE
;
1225 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
1231 * The address free function.
1233 * called with domain->lock held
1235 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
1236 unsigned long address
,
1239 unsigned i
= address
>> APERTURE_RANGE_SHIFT
;
1240 struct aperture_range
*range
= dom
->aperture
[i
];
1242 BUG_ON(i
>= APERTURE_MAX_RANGES
|| range
== NULL
);
1244 #ifdef CONFIG_IOMMU_STRESS
1249 if (address
>= dom
->next_address
)
1250 dom
->need_flush
= true;
1252 address
= (address
% APERTURE_RANGE_SIZE
) >> PAGE_SHIFT
;
1254 bitmap_clear(range
->bitmap
, address
, pages
);
1258 /****************************************************************************
1260 * The next functions belong to the domain allocation. A domain is
1261 * allocated for every IOMMU as the default domain. If device isolation
1262 * is enabled, every device get its own domain. The most important thing
1263 * about domains is the page table mapping the DMA address space they
1266 ****************************************************************************/
1269 * This function adds a protection domain to the global protection domain list
1271 static void add_domain_to_list(struct protection_domain
*domain
)
1273 unsigned long flags
;
1275 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1276 list_add(&domain
->list
, &amd_iommu_pd_list
);
1277 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1281 * This function removes a protection domain to the global
1282 * protection domain list
1284 static void del_domain_from_list(struct protection_domain
*domain
)
1286 unsigned long flags
;
1288 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1289 list_del(&domain
->list
);
1290 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1293 static u16
domain_id_alloc(void)
1295 unsigned long flags
;
1298 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1299 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1301 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1302 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1305 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1310 static void domain_id_free(int id
)
1312 unsigned long flags
;
1314 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1315 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1316 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1317 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1320 static void free_pagetable(struct protection_domain
*domain
)
1325 p1
= domain
->pt_root
;
1330 for (i
= 0; i
< 512; ++i
) {
1331 if (!IOMMU_PTE_PRESENT(p1
[i
]))
1334 p2
= IOMMU_PTE_PAGE(p1
[i
]);
1335 for (j
= 0; j
< 512; ++j
) {
1336 if (!IOMMU_PTE_PRESENT(p2
[j
]))
1338 p3
= IOMMU_PTE_PAGE(p2
[j
]);
1339 free_page((unsigned long)p3
);
1342 free_page((unsigned long)p2
);
1345 free_page((unsigned long)p1
);
1347 domain
->pt_root
= NULL
;
1351 * Free a domain, only used if something went wrong in the
1352 * allocation path and we need to free an already allocated page table
1354 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1361 del_domain_from_list(&dom
->domain
);
1363 free_pagetable(&dom
->domain
);
1365 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
1366 if (!dom
->aperture
[i
])
1368 free_page((unsigned long)dom
->aperture
[i
]->bitmap
);
1369 kfree(dom
->aperture
[i
]);
1376 * Allocates a new protection domain usable for the dma_ops functions.
1377 * It also initializes the page table and the address allocator data
1378 * structures required for the dma_ops interface
1380 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1382 struct dma_ops_domain
*dma_dom
;
1384 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
1388 spin_lock_init(&dma_dom
->domain
.lock
);
1390 dma_dom
->domain
.id
= domain_id_alloc();
1391 if (dma_dom
->domain
.id
== 0)
1393 INIT_LIST_HEAD(&dma_dom
->domain
.dev_list
);
1394 dma_dom
->domain
.mode
= PAGE_MODE_2_LEVEL
;
1395 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1396 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
1397 dma_dom
->domain
.priv
= dma_dom
;
1398 if (!dma_dom
->domain
.pt_root
)
1401 dma_dom
->need_flush
= false;
1402 dma_dom
->target_dev
= 0xffff;
1404 add_domain_to_list(&dma_dom
->domain
);
1406 if (alloc_new_range(dma_dom
, true, GFP_KERNEL
))
1410 * mark the first page as allocated so we never return 0 as
1411 * a valid dma-address. So we can use 0 as error value
1413 dma_dom
->aperture
[0]->bitmap
[0] = 1;
1414 dma_dom
->next_address
= 0;
1420 dma_ops_domain_free(dma_dom
);
1426 * little helper function to check whether a given protection domain is a
1429 static bool dma_ops_domain(struct protection_domain
*domain
)
1431 return domain
->flags
& PD_DMA_OPS_MASK
;
1434 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
)
1436 u64 pte_root
= virt_to_phys(domain
->pt_root
);
1438 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
1439 << DEV_ENTRY_MODE_SHIFT
;
1440 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
1442 amd_iommu_dev_table
[devid
].data
[2] = domain
->id
;
1443 amd_iommu_dev_table
[devid
].data
[1] = upper_32_bits(pte_root
);
1444 amd_iommu_dev_table
[devid
].data
[0] = lower_32_bits(pte_root
);
1447 static void clear_dte_entry(u16 devid
)
1449 /* remove entry from the device table seen by the hardware */
1450 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
1451 amd_iommu_dev_table
[devid
].data
[1] = 0;
1452 amd_iommu_dev_table
[devid
].data
[2] = 0;
1454 amd_iommu_apply_erratum_63(devid
);
1457 static void do_attach(struct device
*dev
, struct protection_domain
*domain
)
1459 struct iommu_dev_data
*dev_data
;
1460 struct amd_iommu
*iommu
;
1463 devid
= get_device_id(dev
);
1464 iommu
= amd_iommu_rlookup_table
[devid
];
1465 dev_data
= get_dev_data(dev
);
1467 /* Update data structures */
1468 dev_data
->domain
= domain
;
1469 list_add(&dev_data
->list
, &domain
->dev_list
);
1470 set_dte_entry(devid
, domain
);
1472 /* Do reference counting */
1473 domain
->dev_iommu
[iommu
->index
] += 1;
1474 domain
->dev_cnt
+= 1;
1476 /* Flush the DTE entry */
1477 iommu_flush_device(dev
);
1480 static void do_detach(struct device
*dev
)
1482 struct iommu_dev_data
*dev_data
;
1483 struct amd_iommu
*iommu
;
1486 devid
= get_device_id(dev
);
1487 iommu
= amd_iommu_rlookup_table
[devid
];
1488 dev_data
= get_dev_data(dev
);
1490 /* decrease reference counters */
1491 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
1492 dev_data
->domain
->dev_cnt
-= 1;
1494 /* Update data structures */
1495 dev_data
->domain
= NULL
;
1496 list_del(&dev_data
->list
);
1497 clear_dte_entry(devid
);
1499 /* Flush the DTE entry */
1500 iommu_flush_device(dev
);
1504 * If a device is not yet associated with a domain, this function does
1505 * assigns it visible for the hardware
1507 static int __attach_device(struct device
*dev
,
1508 struct protection_domain
*domain
)
1510 struct iommu_dev_data
*dev_data
, *alias_data
;
1513 dev_data
= get_dev_data(dev
);
1514 alias_data
= get_dev_data(dev_data
->alias
);
1520 spin_lock(&domain
->lock
);
1522 /* Some sanity checks */
1524 if (alias_data
->domain
!= NULL
&&
1525 alias_data
->domain
!= domain
)
1528 if (dev_data
->domain
!= NULL
&&
1529 dev_data
->domain
!= domain
)
1532 /* Do real assignment */
1533 if (dev_data
->alias
!= dev
) {
1534 alias_data
= get_dev_data(dev_data
->alias
);
1535 if (alias_data
->domain
== NULL
)
1536 do_attach(dev_data
->alias
, domain
);
1538 atomic_inc(&alias_data
->bind
);
1541 if (dev_data
->domain
== NULL
)
1542 do_attach(dev
, domain
);
1544 atomic_inc(&dev_data
->bind
);
1551 spin_unlock(&domain
->lock
);
1557 * If a device is not yet associated with a domain, this function does
1558 * assigns it visible for the hardware
1560 static int attach_device(struct device
*dev
,
1561 struct protection_domain
*domain
)
1563 unsigned long flags
;
1566 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1567 ret
= __attach_device(dev
, domain
);
1568 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1571 * We might boot into a crash-kernel here. The crashed kernel
1572 * left the caches in the IOMMU dirty. So we have to flush
1573 * here to evict all dirty stuff.
1575 iommu_flush_tlb_pde(domain
);
1581 * Removes a device from a protection domain (unlocked)
1583 static void __detach_device(struct device
*dev
)
1585 struct iommu_dev_data
*dev_data
= get_dev_data(dev
);
1586 struct iommu_dev_data
*alias_data
;
1587 struct protection_domain
*domain
;
1588 unsigned long flags
;
1590 BUG_ON(!dev_data
->domain
);
1592 domain
= dev_data
->domain
;
1594 spin_lock_irqsave(&domain
->lock
, flags
);
1596 if (dev_data
->alias
!= dev
) {
1597 alias_data
= get_dev_data(dev_data
->alias
);
1598 if (atomic_dec_and_test(&alias_data
->bind
))
1599 do_detach(dev_data
->alias
);
1602 if (atomic_dec_and_test(&dev_data
->bind
))
1605 spin_unlock_irqrestore(&domain
->lock
, flags
);
1608 * If we run in passthrough mode the device must be assigned to the
1609 * passthrough domain if it is detached from any other domain.
1610 * Make sure we can deassign from the pt_domain itself.
1612 if (iommu_pass_through
&&
1613 (dev_data
->domain
== NULL
&& domain
!= pt_domain
))
1614 __attach_device(dev
, pt_domain
);
1618 * Removes a device from a protection domain (with devtable_lock held)
1620 static void detach_device(struct device
*dev
)
1622 unsigned long flags
;
1624 /* lock device table */
1625 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1626 __detach_device(dev
);
1627 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1631 * Find out the protection domain structure for a given PCI device. This
1632 * will give us the pointer to the page table root for example.
1634 static struct protection_domain
*domain_for_device(struct device
*dev
)
1636 struct protection_domain
*dom
;
1637 struct iommu_dev_data
*dev_data
, *alias_data
;
1638 unsigned long flags
;
1641 devid
= get_device_id(dev
);
1642 alias
= amd_iommu_alias_table
[devid
];
1643 dev_data
= get_dev_data(dev
);
1644 alias_data
= get_dev_data(dev_data
->alias
);
1648 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1649 dom
= dev_data
->domain
;
1651 alias_data
->domain
!= NULL
) {
1652 __attach_device(dev
, alias_data
->domain
);
1653 dom
= alias_data
->domain
;
1656 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1661 static int device_change_notifier(struct notifier_block
*nb
,
1662 unsigned long action
, void *data
)
1664 struct device
*dev
= data
;
1666 struct protection_domain
*domain
;
1667 struct dma_ops_domain
*dma_domain
;
1668 struct amd_iommu
*iommu
;
1669 unsigned long flags
;
1671 if (!check_device(dev
))
1674 devid
= get_device_id(dev
);
1675 iommu
= amd_iommu_rlookup_table
[devid
];
1678 case BUS_NOTIFY_UNBOUND_DRIVER
:
1680 domain
= domain_for_device(dev
);
1684 if (iommu_pass_through
)
1688 case BUS_NOTIFY_ADD_DEVICE
:
1690 iommu_init_device(dev
);
1692 domain
= domain_for_device(dev
);
1694 /* allocate a protection domain if a device is added */
1695 dma_domain
= find_protection_domain(devid
);
1698 dma_domain
= dma_ops_domain_alloc();
1701 dma_domain
->target_dev
= devid
;
1703 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
1704 list_add_tail(&dma_domain
->list
, &iommu_pd_list
);
1705 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
1708 case BUS_NOTIFY_DEL_DEVICE
:
1710 iommu_uninit_device(dev
);
1716 iommu_flush_device(dev
);
1717 iommu_completion_wait(iommu
);
1723 static struct notifier_block device_nb
= {
1724 .notifier_call
= device_change_notifier
,
1727 void amd_iommu_init_notifier(void)
1729 bus_register_notifier(&pci_bus_type
, &device_nb
);
1732 /*****************************************************************************
1734 * The next functions belong to the dma_ops mapping/unmapping code.
1736 *****************************************************************************/
1739 * In the dma_ops path we only have the struct device. This function
1740 * finds the corresponding IOMMU, the protection domain and the
1741 * requestor id for a given device.
1742 * If the device is not yet associated with a domain this is also done
1745 static struct protection_domain
*get_domain(struct device
*dev
)
1747 struct protection_domain
*domain
;
1748 struct dma_ops_domain
*dma_dom
;
1749 u16 devid
= get_device_id(dev
);
1751 if (!check_device(dev
))
1752 return ERR_PTR(-EINVAL
);
1754 domain
= domain_for_device(dev
);
1755 if (domain
!= NULL
&& !dma_ops_domain(domain
))
1756 return ERR_PTR(-EBUSY
);
1761 /* Device not bount yet - bind it */
1762 dma_dom
= find_protection_domain(devid
);
1764 dma_dom
= amd_iommu_rlookup_table
[devid
]->default_dom
;
1765 attach_device(dev
, &dma_dom
->domain
);
1766 DUMP_printk("Using protection domain %d for device %s\n",
1767 dma_dom
->domain
.id
, dev_name(dev
));
1769 return &dma_dom
->domain
;
1772 static void update_device_table(struct protection_domain
*domain
)
1774 struct iommu_dev_data
*dev_data
;
1776 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1777 u16 devid
= get_device_id(dev_data
->dev
);
1778 set_dte_entry(devid
, domain
);
1782 static void update_domain(struct protection_domain
*domain
)
1784 if (!domain
->updated
)
1787 update_device_table(domain
);
1788 iommu_flush_domain_devices(domain
);
1789 iommu_flush_tlb_pde(domain
);
1791 domain
->updated
= false;
1795 * This function fetches the PTE for a given address in the aperture
1797 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
1798 unsigned long address
)
1800 struct aperture_range
*aperture
;
1801 u64
*pte
, *pte_page
;
1803 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
1807 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
1809 pte
= alloc_pte(&dom
->domain
, address
, PAGE_SIZE
, &pte_page
,
1811 aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)] = pte_page
;
1813 pte
+= PM_LEVEL_INDEX(0, address
);
1815 update_domain(&dom
->domain
);
1821 * This is the generic map function. It maps one 4kb page at paddr to
1822 * the given address in the DMA address space for the domain.
1824 static dma_addr_t
dma_ops_domain_map(struct dma_ops_domain
*dom
,
1825 unsigned long address
,
1831 WARN_ON(address
> dom
->aperture_size
);
1835 pte
= dma_ops_get_pte(dom
, address
);
1837 return DMA_ERROR_CODE
;
1839 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1841 if (direction
== DMA_TO_DEVICE
)
1842 __pte
|= IOMMU_PTE_IR
;
1843 else if (direction
== DMA_FROM_DEVICE
)
1844 __pte
|= IOMMU_PTE_IW
;
1845 else if (direction
== DMA_BIDIRECTIONAL
)
1846 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
1852 return (dma_addr_t
)address
;
1856 * The generic unmapping function for on page in the DMA address space.
1858 static void dma_ops_domain_unmap(struct dma_ops_domain
*dom
,
1859 unsigned long address
)
1861 struct aperture_range
*aperture
;
1864 if (address
>= dom
->aperture_size
)
1867 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
1871 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
1875 pte
+= PM_LEVEL_INDEX(0, address
);
1883 * This function contains common code for mapping of a physically
1884 * contiguous memory region into DMA address space. It is used by all
1885 * mapping functions provided with this IOMMU driver.
1886 * Must be called with the domain lock held.
1888 static dma_addr_t
__map_single(struct device
*dev
,
1889 struct dma_ops_domain
*dma_dom
,
1896 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
1897 dma_addr_t address
, start
, ret
;
1899 unsigned long align_mask
= 0;
1902 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
1905 INC_STATS_COUNTER(total_map_requests
);
1908 INC_STATS_COUNTER(cross_page
);
1911 align_mask
= (1UL << get_order(size
)) - 1;
1914 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
1916 if (unlikely(address
== DMA_ERROR_CODE
)) {
1918 * setting next_address here will let the address
1919 * allocator only scan the new allocated range in the
1920 * first run. This is a small optimization.
1922 dma_dom
->next_address
= dma_dom
->aperture_size
;
1924 if (alloc_new_range(dma_dom
, false, GFP_ATOMIC
))
1928 * aperture was successfully enlarged by 128 MB, try
1935 for (i
= 0; i
< pages
; ++i
) {
1936 ret
= dma_ops_domain_map(dma_dom
, start
, paddr
, dir
);
1937 if (ret
== DMA_ERROR_CODE
)
1945 ADD_STATS_COUNTER(alloced_io_mem
, size
);
1947 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
1948 iommu_flush_tlb(&dma_dom
->domain
);
1949 dma_dom
->need_flush
= false;
1950 } else if (unlikely(amd_iommu_np_cache
))
1951 iommu_flush_pages(&dma_dom
->domain
, address
, size
);
1958 for (--i
; i
>= 0; --i
) {
1960 dma_ops_domain_unmap(dma_dom
, start
);
1963 dma_ops_free_addresses(dma_dom
, address
, pages
);
1965 return DMA_ERROR_CODE
;
1969 * Does the reverse of the __map_single function. Must be called with
1970 * the domain lock held too
1972 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
1973 dma_addr_t dma_addr
,
1977 dma_addr_t flush_addr
;
1978 dma_addr_t i
, start
;
1981 if ((dma_addr
== DMA_ERROR_CODE
) ||
1982 (dma_addr
+ size
> dma_dom
->aperture_size
))
1985 flush_addr
= dma_addr
;
1986 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
1987 dma_addr
&= PAGE_MASK
;
1990 for (i
= 0; i
< pages
; ++i
) {
1991 dma_ops_domain_unmap(dma_dom
, start
);
1995 SUB_STATS_COUNTER(alloced_io_mem
, size
);
1997 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
1999 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
2000 iommu_flush_pages(&dma_dom
->domain
, flush_addr
, size
);
2001 dma_dom
->need_flush
= false;
2006 * The exported map_single function for dma_ops.
2008 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
2009 unsigned long offset
, size_t size
,
2010 enum dma_data_direction dir
,
2011 struct dma_attrs
*attrs
)
2013 unsigned long flags
;
2014 struct protection_domain
*domain
;
2017 phys_addr_t paddr
= page_to_phys(page
) + offset
;
2019 INC_STATS_COUNTER(cnt_map_single
);
2021 domain
= get_domain(dev
);
2022 if (PTR_ERR(domain
) == -EINVAL
)
2023 return (dma_addr_t
)paddr
;
2024 else if (IS_ERR(domain
))
2025 return DMA_ERROR_CODE
;
2027 dma_mask
= *dev
->dma_mask
;
2029 spin_lock_irqsave(&domain
->lock
, flags
);
2031 addr
= __map_single(dev
, domain
->priv
, paddr
, size
, dir
, false,
2033 if (addr
== DMA_ERROR_CODE
)
2036 iommu_flush_complete(domain
);
2039 spin_unlock_irqrestore(&domain
->lock
, flags
);
2045 * The exported unmap_single function for dma_ops.
2047 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2048 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
2050 unsigned long flags
;
2051 struct protection_domain
*domain
;
2053 INC_STATS_COUNTER(cnt_unmap_single
);
2055 domain
= get_domain(dev
);
2059 spin_lock_irqsave(&domain
->lock
, flags
);
2061 __unmap_single(domain
->priv
, dma_addr
, size
, dir
);
2063 iommu_flush_complete(domain
);
2065 spin_unlock_irqrestore(&domain
->lock
, flags
);
2069 * This is a special map_sg function which is used if we should map a
2070 * device which is not handled by an AMD IOMMU in the system.
2072 static int map_sg_no_iommu(struct device
*dev
, struct scatterlist
*sglist
,
2073 int nelems
, int dir
)
2075 struct scatterlist
*s
;
2078 for_each_sg(sglist
, s
, nelems
, i
) {
2079 s
->dma_address
= (dma_addr_t
)sg_phys(s
);
2080 s
->dma_length
= s
->length
;
2087 * The exported map_sg function for dma_ops (handles scatter-gather
2090 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2091 int nelems
, enum dma_data_direction dir
,
2092 struct dma_attrs
*attrs
)
2094 unsigned long flags
;
2095 struct protection_domain
*domain
;
2097 struct scatterlist
*s
;
2099 int mapped_elems
= 0;
2102 INC_STATS_COUNTER(cnt_map_sg
);
2104 domain
= get_domain(dev
);
2105 if (PTR_ERR(domain
) == -EINVAL
)
2106 return map_sg_no_iommu(dev
, sglist
, nelems
, dir
);
2107 else if (IS_ERR(domain
))
2110 dma_mask
= *dev
->dma_mask
;
2112 spin_lock_irqsave(&domain
->lock
, flags
);
2114 for_each_sg(sglist
, s
, nelems
, i
) {
2117 s
->dma_address
= __map_single(dev
, domain
->priv
,
2118 paddr
, s
->length
, dir
, false,
2121 if (s
->dma_address
) {
2122 s
->dma_length
= s
->length
;
2128 iommu_flush_complete(domain
);
2131 spin_unlock_irqrestore(&domain
->lock
, flags
);
2133 return mapped_elems
;
2135 for_each_sg(sglist
, s
, mapped_elems
, i
) {
2137 __unmap_single(domain
->priv
, s
->dma_address
,
2138 s
->dma_length
, dir
);
2139 s
->dma_address
= s
->dma_length
= 0;
2148 * The exported map_sg function for dma_ops (handles scatter-gather
2151 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2152 int nelems
, enum dma_data_direction dir
,
2153 struct dma_attrs
*attrs
)
2155 unsigned long flags
;
2156 struct protection_domain
*domain
;
2157 struct scatterlist
*s
;
2160 INC_STATS_COUNTER(cnt_unmap_sg
);
2162 domain
= get_domain(dev
);
2166 spin_lock_irqsave(&domain
->lock
, flags
);
2168 for_each_sg(sglist
, s
, nelems
, i
) {
2169 __unmap_single(domain
->priv
, s
->dma_address
,
2170 s
->dma_length
, dir
);
2171 s
->dma_address
= s
->dma_length
= 0;
2174 iommu_flush_complete(domain
);
2176 spin_unlock_irqrestore(&domain
->lock
, flags
);
2180 * The exported alloc_coherent function for dma_ops.
2182 static void *alloc_coherent(struct device
*dev
, size_t size
,
2183 dma_addr_t
*dma_addr
, gfp_t flag
)
2185 unsigned long flags
;
2187 struct protection_domain
*domain
;
2189 u64 dma_mask
= dev
->coherent_dma_mask
;
2191 INC_STATS_COUNTER(cnt_alloc_coherent
);
2193 domain
= get_domain(dev
);
2194 if (PTR_ERR(domain
) == -EINVAL
) {
2195 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
2196 *dma_addr
= __pa(virt_addr
);
2198 } else if (IS_ERR(domain
))
2201 dma_mask
= dev
->coherent_dma_mask
;
2202 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2205 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
2209 paddr
= virt_to_phys(virt_addr
);
2212 dma_mask
= *dev
->dma_mask
;
2214 spin_lock_irqsave(&domain
->lock
, flags
);
2216 *dma_addr
= __map_single(dev
, domain
->priv
, paddr
,
2217 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
2219 if (*dma_addr
== DMA_ERROR_CODE
) {
2220 spin_unlock_irqrestore(&domain
->lock
, flags
);
2224 iommu_flush_complete(domain
);
2226 spin_unlock_irqrestore(&domain
->lock
, flags
);
2232 free_pages((unsigned long)virt_addr
, get_order(size
));
2238 * The exported free_coherent function for dma_ops.
2240 static void free_coherent(struct device
*dev
, size_t size
,
2241 void *virt_addr
, dma_addr_t dma_addr
)
2243 unsigned long flags
;
2244 struct protection_domain
*domain
;
2246 INC_STATS_COUNTER(cnt_free_coherent
);
2248 domain
= get_domain(dev
);
2252 spin_lock_irqsave(&domain
->lock
, flags
);
2254 __unmap_single(domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2256 iommu_flush_complete(domain
);
2258 spin_unlock_irqrestore(&domain
->lock
, flags
);
2261 free_pages((unsigned long)virt_addr
, get_order(size
));
2265 * This function is called by the DMA layer to find out if we can handle a
2266 * particular device. It is part of the dma_ops.
2268 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
2270 return check_device(dev
);
2274 * The function for pre-allocating protection domains.
2276 * If the driver core informs the DMA layer if a driver grabs a device
2277 * we don't need to preallocate the protection domains anymore.
2278 * For now we have to.
2280 static void prealloc_protection_domains(void)
2282 struct pci_dev
*dev
= NULL
;
2283 struct dma_ops_domain
*dma_dom
;
2286 for_each_pci_dev(dev
) {
2288 /* Do we handle this device? */
2289 if (!check_device(&dev
->dev
))
2292 /* Is there already any domain for it? */
2293 if (domain_for_device(&dev
->dev
))
2296 devid
= get_device_id(&dev
->dev
);
2298 dma_dom
= dma_ops_domain_alloc();
2301 init_unity_mappings_for_device(dma_dom
, devid
);
2302 dma_dom
->target_dev
= devid
;
2304 attach_device(&dev
->dev
, &dma_dom
->domain
);
2306 list_add_tail(&dma_dom
->list
, &iommu_pd_list
);
2310 static struct dma_map_ops amd_iommu_dma_ops
= {
2311 .alloc_coherent
= alloc_coherent
,
2312 .free_coherent
= free_coherent
,
2313 .map_page
= map_page
,
2314 .unmap_page
= unmap_page
,
2316 .unmap_sg
= unmap_sg
,
2317 .dma_supported
= amd_iommu_dma_supported
,
2320 static unsigned device_dma_ops_init(void)
2322 struct pci_dev
*pdev
= NULL
;
2323 unsigned unhandled
= 0;
2325 for_each_pci_dev(pdev
) {
2326 if (!check_device(&pdev
->dev
)) {
2331 pdev
->dev
.archdata
.dma_ops
= &amd_iommu_dma_ops
;
2338 * The function which clues the AMD IOMMU driver into dma_ops.
2341 void __init
amd_iommu_init_api(void)
2343 register_iommu(&amd_iommu_ops
);
2346 int __init
amd_iommu_init_dma_ops(void)
2348 struct amd_iommu
*iommu
;
2352 * first allocate a default protection domain for every IOMMU we
2353 * found in the system. Devices not assigned to any other
2354 * protection domain will be assigned to the default one.
2356 for_each_iommu(iommu
) {
2357 iommu
->default_dom
= dma_ops_domain_alloc();
2358 if (iommu
->default_dom
== NULL
)
2360 iommu
->default_dom
->domain
.flags
|= PD_DEFAULT_MASK
;
2361 ret
= iommu_init_unity_mappings(iommu
);
2367 * Pre-allocate the protection domains for each device.
2369 prealloc_protection_domains();
2374 /* Make the driver finally visible to the drivers */
2375 unhandled
= device_dma_ops_init();
2376 if (unhandled
&& max_pfn
> MAX_DMA32_PFN
) {
2377 /* There are unhandled devices - initialize swiotlb for them */
2381 amd_iommu_stats_init();
2387 for_each_iommu(iommu
) {
2388 if (iommu
->default_dom
)
2389 dma_ops_domain_free(iommu
->default_dom
);
2395 /*****************************************************************************
2397 * The following functions belong to the exported interface of AMD IOMMU
2399 * This interface allows access to lower level functions of the IOMMU
2400 * like protection domain handling and assignement of devices to domains
2401 * which is not possible with the dma_ops interface.
2403 *****************************************************************************/
2405 static void cleanup_domain(struct protection_domain
*domain
)
2407 struct iommu_dev_data
*dev_data
, *next
;
2408 unsigned long flags
;
2410 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2412 list_for_each_entry_safe(dev_data
, next
, &domain
->dev_list
, list
) {
2413 struct device
*dev
= dev_data
->dev
;
2415 __detach_device(dev
);
2416 atomic_set(&dev_data
->bind
, 0);
2419 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2422 static void protection_domain_free(struct protection_domain
*domain
)
2427 del_domain_from_list(domain
);
2430 domain_id_free(domain
->id
);
2435 static struct protection_domain
*protection_domain_alloc(void)
2437 struct protection_domain
*domain
;
2439 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
2443 spin_lock_init(&domain
->lock
);
2444 mutex_init(&domain
->api_lock
);
2445 domain
->id
= domain_id_alloc();
2448 INIT_LIST_HEAD(&domain
->dev_list
);
2450 add_domain_to_list(domain
);
2460 static int amd_iommu_domain_init(struct iommu_domain
*dom
)
2462 struct protection_domain
*domain
;
2464 domain
= protection_domain_alloc();
2468 domain
->mode
= PAGE_MODE_3_LEVEL
;
2469 domain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2470 if (!domain
->pt_root
)
2478 protection_domain_free(domain
);
2483 static void amd_iommu_domain_destroy(struct iommu_domain
*dom
)
2485 struct protection_domain
*domain
= dom
->priv
;
2490 if (domain
->dev_cnt
> 0)
2491 cleanup_domain(domain
);
2493 BUG_ON(domain
->dev_cnt
!= 0);
2495 free_pagetable(domain
);
2497 protection_domain_free(domain
);
2502 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
2505 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
2506 struct amd_iommu
*iommu
;
2509 if (!check_device(dev
))
2512 devid
= get_device_id(dev
);
2514 if (dev_data
->domain
!= NULL
)
2517 iommu
= amd_iommu_rlookup_table
[devid
];
2521 iommu_flush_device(dev
);
2522 iommu_completion_wait(iommu
);
2525 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
2528 struct protection_domain
*domain
= dom
->priv
;
2529 struct iommu_dev_data
*dev_data
;
2530 struct amd_iommu
*iommu
;
2534 if (!check_device(dev
))
2537 dev_data
= dev
->archdata
.iommu
;
2539 devid
= get_device_id(dev
);
2541 iommu
= amd_iommu_rlookup_table
[devid
];
2545 if (dev_data
->domain
)
2548 ret
= attach_device(dev
, domain
);
2550 iommu_completion_wait(iommu
);
2555 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
2556 phys_addr_t paddr
, int gfp_order
, int iommu_prot
)
2558 unsigned long page_size
= 0x1000UL
<< gfp_order
;
2559 struct protection_domain
*domain
= dom
->priv
;
2563 if (iommu_prot
& IOMMU_READ
)
2564 prot
|= IOMMU_PROT_IR
;
2565 if (iommu_prot
& IOMMU_WRITE
)
2566 prot
|= IOMMU_PROT_IW
;
2568 mutex_lock(&domain
->api_lock
);
2569 ret
= iommu_map_page(domain
, iova
, paddr
, prot
, page_size
);
2570 mutex_unlock(&domain
->api_lock
);
2575 static int amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
2578 struct protection_domain
*domain
= dom
->priv
;
2579 unsigned long page_size
, unmap_size
;
2581 page_size
= 0x1000UL
<< gfp_order
;
2583 mutex_lock(&domain
->api_lock
);
2584 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
2585 mutex_unlock(&domain
->api_lock
);
2587 iommu_flush_tlb_pde(domain
);
2589 return get_order(unmap_size
);
2592 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
2595 struct protection_domain
*domain
= dom
->priv
;
2596 unsigned long offset_mask
;
2600 pte
= fetch_pte(domain
, iova
);
2602 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
2605 if (PM_PTE_LEVEL(*pte
) == 0)
2606 offset_mask
= PAGE_SIZE
- 1;
2608 offset_mask
= PTE_PAGE_SIZE(*pte
) - 1;
2610 __pte
= *pte
& PM_ADDR_MASK
;
2611 paddr
= (__pte
& ~offset_mask
) | (iova
& offset_mask
);
2616 static int amd_iommu_domain_has_cap(struct iommu_domain
*domain
,
2620 case IOMMU_CAP_CACHE_COHERENCY
:
2627 static struct iommu_ops amd_iommu_ops
= {
2628 .domain_init
= amd_iommu_domain_init
,
2629 .domain_destroy
= amd_iommu_domain_destroy
,
2630 .attach_dev
= amd_iommu_attach_device
,
2631 .detach_dev
= amd_iommu_detach_device
,
2632 .map
= amd_iommu_map
,
2633 .unmap
= amd_iommu_unmap
,
2634 .iova_to_phys
= amd_iommu_iova_to_phys
,
2635 .domain_has_cap
= amd_iommu_domain_has_cap
,
2638 /*****************************************************************************
2640 * The next functions do a basic initialization of IOMMU for pass through
2643 * In passthrough mode the IOMMU is initialized and enabled but not used for
2644 * DMA-API translation.
2646 *****************************************************************************/
2648 int __init
amd_iommu_init_passthrough(void)
2650 struct amd_iommu
*iommu
;
2651 struct pci_dev
*dev
= NULL
;
2654 /* allocate passthrough domain */
2655 pt_domain
= protection_domain_alloc();
2659 pt_domain
->mode
|= PAGE_MODE_NONE
;
2661 for_each_pci_dev(dev
) {
2662 if (!check_device(&dev
->dev
))
2665 devid
= get_device_id(&dev
->dev
);
2667 iommu
= amd_iommu_rlookup_table
[devid
];
2671 attach_device(&dev
->dev
, pt_domain
);
2674 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");