2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
4 * This driver is heavily based upon:
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
14 * Look into engine reset on timeout errors. Should not be required.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/blkdev.h>
22 #include <linux/delay.h>
23 #include <scsi/scsi_host.h>
24 #include <linux/libata.h>
26 #define DRV_NAME "pata_hpt37x"
27 #define DRV_VERSION "0.6.15"
37 struct hpt_clock
const *clocks
[4];
40 /* key for bus clock timings
42 * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
44 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
46 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
48 * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
50 * 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
51 * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
52 * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
53 * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
57 * 30 PIO_MST enable. If set, the chip is in bus master mode during
59 * 31 FIFO enable. Only for PIO.
62 static struct hpt_clock hpt37x_timings_33
[] = {
63 { XFER_UDMA_6
, 0x12446231 }, /* 0x12646231 ?? */
64 { XFER_UDMA_5
, 0x12446231 },
65 { XFER_UDMA_4
, 0x12446231 },
66 { XFER_UDMA_3
, 0x126c6231 },
67 { XFER_UDMA_2
, 0x12486231 },
68 { XFER_UDMA_1
, 0x124c6233 },
69 { XFER_UDMA_0
, 0x12506297 },
71 { XFER_MW_DMA_2
, 0x22406c31 },
72 { XFER_MW_DMA_1
, 0x22406c33 },
73 { XFER_MW_DMA_0
, 0x22406c97 },
75 { XFER_PIO_4
, 0x06414e31 },
76 { XFER_PIO_3
, 0x06414e42 },
77 { XFER_PIO_2
, 0x06414e53 },
78 { XFER_PIO_1
, 0x06814e93 },
79 { XFER_PIO_0
, 0x06814ea7 }
82 static struct hpt_clock hpt37x_timings_50
[] = {
83 { XFER_UDMA_6
, 0x12848242 },
84 { XFER_UDMA_5
, 0x12848242 },
85 { XFER_UDMA_4
, 0x12ac8242 },
86 { XFER_UDMA_3
, 0x128c8242 },
87 { XFER_UDMA_2
, 0x120c8242 },
88 { XFER_UDMA_1
, 0x12148254 },
89 { XFER_UDMA_0
, 0x121882ea },
91 { XFER_MW_DMA_2
, 0x22808242 },
92 { XFER_MW_DMA_1
, 0x22808254 },
93 { XFER_MW_DMA_0
, 0x228082ea },
95 { XFER_PIO_4
, 0x0a81f442 },
96 { XFER_PIO_3
, 0x0a81f443 },
97 { XFER_PIO_2
, 0x0a81f454 },
98 { XFER_PIO_1
, 0x0ac1f465 },
99 { XFER_PIO_0
, 0x0ac1f48a }
102 static struct hpt_clock hpt37x_timings_66
[] = {
103 { XFER_UDMA_6
, 0x1c869c62 },
104 { XFER_UDMA_5
, 0x1cae9c62 }, /* 0x1c8a9c62 */
105 { XFER_UDMA_4
, 0x1c8a9c62 },
106 { XFER_UDMA_3
, 0x1c8e9c62 },
107 { XFER_UDMA_2
, 0x1c929c62 },
108 { XFER_UDMA_1
, 0x1c9a9c62 },
109 { XFER_UDMA_0
, 0x1c829c62 },
111 { XFER_MW_DMA_2
, 0x2c829c62 },
112 { XFER_MW_DMA_1
, 0x2c829c66 },
113 { XFER_MW_DMA_0
, 0x2c829d2e },
115 { XFER_PIO_4
, 0x0c829c62 },
116 { XFER_PIO_3
, 0x0c829c84 },
117 { XFER_PIO_2
, 0x0c829ca6 },
118 { XFER_PIO_1
, 0x0d029d26 },
119 { XFER_PIO_0
, 0x0d029d5e }
123 static const struct hpt_chip hpt370
= {
134 static const struct hpt_chip hpt370a
= {
145 static const struct hpt_chip hpt372
= {
156 static const struct hpt_chip hpt302
= {
167 static const struct hpt_chip hpt371
= {
178 static const struct hpt_chip hpt372a
= {
189 static const struct hpt_chip hpt374
= {
201 * hpt37x_find_mode - reset the hpt37x bus
203 * @speed: transfer mode
205 * Return the 32bit register programming information for this channel
206 * that matches the speed provided.
209 static u32
hpt37x_find_mode(struct ata_port
*ap
, int speed
)
211 struct hpt_clock
*clocks
= ap
->host
->private_data
;
213 while(clocks
->xfer_speed
) {
214 if (clocks
->xfer_speed
== speed
)
215 return clocks
->timing
;
219 return 0xffffffffU
; /* silence compiler warning */
222 static int hpt_dma_blacklisted(const struct ata_device
*dev
, char *modestr
, const char *list
[])
224 unsigned char model_num
[ATA_ID_PROD_LEN
+ 1];
227 ata_id_c_string(dev
->id
, model_num
, ATA_ID_PROD
, sizeof(model_num
));
229 while (list
[i
] != NULL
) {
230 if (!strcmp(list
[i
], model_num
)) {
231 printk(KERN_WARNING DRV_NAME
": %s is not supported for %s.\n",
240 static const char *bad_ata33
[] = {
241 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
242 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
243 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
245 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
246 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
247 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
251 static const char *bad_ata100_5
[] = {
271 * hpt370_filter - mode selection filter
274 * Block UDMA on devices that cause trouble with this controller.
277 static unsigned long hpt370_filter(struct ata_device
*adev
, unsigned long mask
)
279 if (adev
->class == ATA_DEV_ATA
) {
280 if (hpt_dma_blacklisted(adev
, "UDMA", bad_ata33
))
281 mask
&= ~ATA_MASK_UDMA
;
282 if (hpt_dma_blacklisted(adev
, "UDMA100", bad_ata100_5
))
283 mask
&= ~(0xE0 << ATA_SHIFT_UDMA
);
285 return ata_bmdma_mode_filter(adev
, mask
);
289 * hpt370a_filter - mode selection filter
292 * Block UDMA on devices that cause trouble with this controller.
295 static unsigned long hpt370a_filter(struct ata_device
*adev
, unsigned long mask
)
297 if (adev
->class == ATA_DEV_ATA
) {
298 if (hpt_dma_blacklisted(adev
, "UDMA100", bad_ata100_5
))
299 mask
&= ~(0xE0 << ATA_SHIFT_UDMA
);
301 return ata_bmdma_mode_filter(adev
, mask
);
305 * hpt37x_cable_detect - Detect the cable type
306 * @ap: ATA port to detect on
308 * Return the cable type attached to this port
311 static int hpt37x_cable_detect(struct ata_port
*ap
)
313 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
316 pci_read_config_byte(pdev
, 0x5B, &scr2
);
317 pci_write_config_byte(pdev
, 0x5B, scr2
& ~0x01);
319 udelay(10); /* debounce */
321 /* Cable register now active */
322 pci_read_config_byte(pdev
, 0x5A, &ata66
);
324 pci_write_config_byte(pdev
, 0x5B, scr2
);
326 if (ata66
& (2 >> ap
->port_no
))
327 return ATA_CBL_PATA40
;
329 return ATA_CBL_PATA80
;
333 * hpt374_fn1_cable_detect - Detect the cable type
334 * @ap: ATA port to detect on
336 * Return the cable type attached to this port
339 static int hpt374_fn1_cable_detect(struct ata_port
*ap
)
341 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
342 unsigned int mcrbase
= 0x50 + 4 * ap
->port_no
;
346 /* Do the extra channel work */
347 pci_read_config_word(pdev
, mcrbase
+ 2, &mcr3
);
348 /* Set bit 15 of 0x52 to enable TCBLID as input */
349 pci_write_config_word(pdev
, mcrbase
+ 2, mcr3
| 0x8000);
350 pci_read_config_byte(pdev
, 0x5A, &ata66
);
351 /* Reset TCBLID/FCBLID to output */
352 pci_write_config_word(pdev
, mcrbase
+ 2, mcr3
);
354 if (ata66
& (2 >> ap
->port_no
))
355 return ATA_CBL_PATA40
;
357 return ATA_CBL_PATA80
;
361 * hpt37x_pre_reset - reset the hpt37x bus
362 * @link: ATA link to reset
363 * @deadline: deadline jiffies for the operation
365 * Perform the initial reset handling for the HPT37x.
368 static int hpt37x_pre_reset(struct ata_link
*link
, unsigned long deadline
)
370 struct ata_port
*ap
= link
->ap
;
371 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
372 static const struct pci_bits hpt37x_enable_bits
[] = {
373 { 0x50, 1, 0x04, 0x04 },
374 { 0x54, 1, 0x04, 0x04 }
376 if (!pci_test_config_bits(pdev
, &hpt37x_enable_bits
[ap
->port_no
]))
379 /* Reset the state machine */
380 pci_write_config_byte(pdev
, 0x50 + 4 * ap
->port_no
, 0x37);
383 return ata_sff_prereset(link
, deadline
);
386 static void hpt370_set_mode(struct ata_port
*ap
, struct ata_device
*adev
,
389 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
391 u32 reg
, timing
, mask
;
394 addr1
= 0x40 + 4 * (adev
->devno
+ 2 * ap
->port_no
);
395 addr2
= 0x51 + 4 * ap
->port_no
;
397 /* Fast interrupt prediction disable, hold off interrupt disable */
398 pci_read_config_byte(pdev
, addr2
, &fast
);
401 pci_write_config_byte(pdev
, addr2
, fast
);
403 /* Determine timing mask and find matching mode entry */
404 if (mode
< XFER_MW_DMA_0
)
406 else if (mode
< XFER_UDMA_0
)
411 timing
= hpt37x_find_mode(ap
, mode
);
413 pci_read_config_dword(pdev
, addr1
, ®
);
414 reg
= (reg
& ~mask
) | (timing
& mask
);
415 pci_write_config_dword(pdev
, addr1
, reg
);
418 * hpt370_set_piomode - PIO setup
420 * @adev: device on the interface
422 * Perform PIO mode setup.
425 static void hpt370_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
427 hpt370_set_mode(ap
, adev
, adev
->pio_mode
);
431 * hpt370_set_dmamode - DMA timing setup
433 * @adev: Device being configured
435 * Set up the channel for MWDMA or UDMA modes.
438 static void hpt370_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
440 hpt370_set_mode(ap
, adev
, adev
->dma_mode
);
444 * hpt370_bmdma_end - DMA engine stop
447 * Work around the HPT370 DMA engine.
450 static void hpt370_bmdma_stop(struct ata_queued_cmd
*qc
)
452 struct ata_port
*ap
= qc
->ap
;
453 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
454 void __iomem
*bmdma
= ap
->ioaddr
.bmdma_addr
;
455 u8 dma_stat
= ioread8(bmdma
+ ATA_DMA_STATUS
);
458 if (dma_stat
& ATA_DMA_ACTIVE
) {
460 dma_stat
= ioread8(bmdma
+ ATA_DMA_STATUS
);
462 if (dma_stat
& ATA_DMA_ACTIVE
) {
463 /* Clear the engine */
464 pci_write_config_byte(pdev
, 0x50 + 4 * ap
->port_no
, 0x37);
467 dma_cmd
= ioread8(bmdma
+ ATA_DMA_CMD
);
468 iowrite8(dma_cmd
& ~ATA_DMA_START
, bmdma
+ ATA_DMA_CMD
);
470 dma_stat
= ioread8(bmdma
+ ATA_DMA_STATUS
);
471 iowrite8(dma_stat
| ATA_DMA_INTR
| ATA_DMA_ERR
,
472 bmdma
+ ATA_DMA_STATUS
);
473 /* Clear the engine */
474 pci_write_config_byte(pdev
, 0x50 + 4 * ap
->port_no
, 0x37);
480 static void hpt372_set_mode(struct ata_port
*ap
, struct ata_device
*adev
,
483 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
485 u32 reg
, timing
, mask
;
488 addr1
= 0x40 + 4 * (adev
->devno
+ 2 * ap
->port_no
);
489 addr2
= 0x51 + 4 * ap
->port_no
;
491 /* Fast interrupt prediction disable, hold off interrupt disable */
492 pci_read_config_byte(pdev
, addr2
, &fast
);
494 pci_write_config_byte(pdev
, addr2
, fast
);
496 /* Determine timing mask and find matching mode entry */
497 if (mode
< XFER_MW_DMA_0
)
499 else if (mode
< XFER_UDMA_0
)
504 timing
= hpt37x_find_mode(ap
, mode
);
506 pci_read_config_dword(pdev
, addr1
, ®
);
507 reg
= (reg
& ~mask
) | (timing
& mask
);
508 pci_write_config_dword(pdev
, addr1
, reg
);
512 * hpt372_set_piomode - PIO setup
514 * @adev: device on the interface
516 * Perform PIO mode setup.
519 static void hpt372_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
521 hpt372_set_mode(ap
, adev
, adev
->pio_mode
);
525 * hpt372_set_dmamode - DMA timing setup
527 * @adev: Device being configured
529 * Set up the channel for MWDMA or UDMA modes.
532 static void hpt372_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
534 hpt372_set_mode(ap
, adev
, adev
->dma_mode
);
538 * hpt37x_bmdma_end - DMA engine stop
541 * Clean up after the HPT372 and later DMA engine
544 static void hpt37x_bmdma_stop(struct ata_queued_cmd
*qc
)
546 struct ata_port
*ap
= qc
->ap
;
547 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
548 int mscreg
= 0x50 + 4 * ap
->port_no
;
549 u8 bwsr_stat
, msc_stat
;
551 pci_read_config_byte(pdev
, 0x6A, &bwsr_stat
);
552 pci_read_config_byte(pdev
, mscreg
, &msc_stat
);
553 if (bwsr_stat
& (1 << ap
->port_no
))
554 pci_write_config_byte(pdev
, mscreg
, msc_stat
| 0x30);
559 static struct scsi_host_template hpt37x_sht
= {
560 ATA_BMDMA_SHT(DRV_NAME
),
564 * Configuration for HPT370
567 static struct ata_port_operations hpt370_port_ops
= {
568 .inherits
= &ata_bmdma_port_ops
,
570 .bmdma_stop
= hpt370_bmdma_stop
,
572 .mode_filter
= hpt370_filter
,
573 .cable_detect
= hpt37x_cable_detect
,
574 .set_piomode
= hpt370_set_piomode
,
575 .set_dmamode
= hpt370_set_dmamode
,
576 .prereset
= hpt37x_pre_reset
,
580 * Configuration for HPT370A. Close to 370 but less filters
583 static struct ata_port_operations hpt370a_port_ops
= {
584 .inherits
= &hpt370_port_ops
,
585 .mode_filter
= hpt370a_filter
,
589 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
590 * and DMA mode setting functionality.
593 static struct ata_port_operations hpt372_port_ops
= {
594 .inherits
= &ata_bmdma_port_ops
,
596 .bmdma_stop
= hpt37x_bmdma_stop
,
598 .cable_detect
= hpt37x_cable_detect
,
599 .set_piomode
= hpt372_set_piomode
,
600 .set_dmamode
= hpt372_set_dmamode
,
601 .prereset
= hpt37x_pre_reset
,
605 * Configuration for HPT374. Mode setting works like 372 and friends
606 * but we have a different cable detection procedure for function 1.
609 static struct ata_port_operations hpt374_fn1_port_ops
= {
610 .inherits
= &hpt372_port_ops
,
611 .cable_detect
= hpt374_fn1_cable_detect
,
612 .prereset
= hpt37x_pre_reset
,
616 * hpt37x_clock_slot - Turn timing to PC clock entry
617 * @freq: Reported frequency timing
620 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
624 static int hpt37x_clock_slot(unsigned int freq
, unsigned int base
)
626 unsigned int f
= (base
* freq
) / 192; /* Mhz */
628 return 0; /* 33Mhz slot */
630 return 1; /* 40Mhz slot */
632 return 2; /* 50Mhz slot */
633 return 3; /* 60Mhz slot */
637 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
640 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
644 static int hpt37x_calibrate_dpll(struct pci_dev
*dev
)
650 for(tries
= 0; tries
< 0x5000; tries
++) {
652 pci_read_config_byte(dev
, 0x5b, ®5b
);
654 /* See if it stays set */
655 for(tries
= 0; tries
< 0x1000; tries
++) {
656 pci_read_config_byte(dev
, 0x5b, ®5b
);
658 if ((reg5b
& 0x80) == 0)
661 /* Turn off tuning, we have the DPLL set */
662 pci_read_config_dword(dev
, 0x5c, ®5c
);
663 pci_write_config_dword(dev
, 0x5c, reg5c
& ~ 0x100);
667 /* Never went stable */
671 static u32
hpt374_read_freq(struct pci_dev
*pdev
)
674 unsigned long io_base
= pci_resource_start(pdev
, 4);
675 if (PCI_FUNC(pdev
->devfn
) & 1) {
676 struct pci_dev
*pdev_0
;
678 pdev_0
= pci_get_slot(pdev
->bus
, pdev
->devfn
- 1);
679 /* Someone hot plugged the controller on us ? */
682 io_base
= pci_resource_start(pdev_0
, 4);
683 freq
= inl(io_base
+ 0x90);
686 freq
= inl(io_base
+ 0x90);
691 * hpt37x_init_one - Initialise an HPT37X/302
693 * @id: Entry in match table
695 * Initialise an HPT37x device. There are some interesting complications
696 * here. Firstly the chip may report 366 and be one of several variants.
697 * Secondly all the timings depend on the clock for the chip which we must
700 * This is the known chip mappings. It may be missing a couple of later
703 * Chip version PCI Rev Notes
704 * HPT366 4 (HPT366) 0 Other driver
705 * HPT366 4 (HPT366) 1 Other driver
706 * HPT368 4 (HPT366) 2 Other driver
707 * HPT370 4 (HPT366) 3 UDMA100
708 * HPT370A 4 (HPT366) 4 UDMA100
709 * HPT372 4 (HPT366) 5 UDMA133 (1)
710 * HPT372N 4 (HPT366) 6 Other driver
711 * HPT372A 5 (HPT372) 1 UDMA133 (1)
712 * HPT372N 5 (HPT372) 2 Other driver
713 * HPT302 6 (HPT302) 1 UDMA133
714 * HPT302N 6 (HPT302) 2 Other driver
715 * HPT371 7 (HPT371) * UDMA133
716 * HPT374 8 (HPT374) * UDMA133 4 channel
717 * HPT372N 9 (HPT372N) * Other driver
719 * (1) UDMA133 support depends on the bus clock
722 static int hpt37x_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
724 /* HPT370 - UDMA100 */
725 static const struct ata_port_info info_hpt370
= {
726 .flags
= ATA_FLAG_SLAVE_POSS
,
727 .pio_mask
= ATA_PIO4
,
728 .mwdma_mask
= ATA_MWDMA2
,
729 .udma_mask
= ATA_UDMA5
,
730 .port_ops
= &hpt370_port_ops
732 /* HPT370A - UDMA100 */
733 static const struct ata_port_info info_hpt370a
= {
734 .flags
= ATA_FLAG_SLAVE_POSS
,
735 .pio_mask
= ATA_PIO4
,
736 .mwdma_mask
= ATA_MWDMA2
,
737 .udma_mask
= ATA_UDMA5
,
738 .port_ops
= &hpt370a_port_ops
740 /* HPT370 - UDMA100 */
741 static const struct ata_port_info info_hpt370_33
= {
742 .flags
= ATA_FLAG_SLAVE_POSS
,
743 .pio_mask
= ATA_PIO4
,
744 .mwdma_mask
= ATA_MWDMA2
,
745 .udma_mask
= ATA_UDMA5
,
746 .port_ops
= &hpt370_port_ops
748 /* HPT370A - UDMA100 */
749 static const struct ata_port_info info_hpt370a_33
= {
750 .flags
= ATA_FLAG_SLAVE_POSS
,
751 .pio_mask
= ATA_PIO4
,
752 .mwdma_mask
= ATA_MWDMA2
,
753 .udma_mask
= ATA_UDMA5
,
754 .port_ops
= &hpt370a_port_ops
756 /* HPT371, 372 and friends - UDMA133 */
757 static const struct ata_port_info info_hpt372
= {
758 .flags
= ATA_FLAG_SLAVE_POSS
,
759 .pio_mask
= ATA_PIO4
,
760 .mwdma_mask
= ATA_MWDMA2
,
761 .udma_mask
= ATA_UDMA6
,
762 .port_ops
= &hpt372_port_ops
764 /* HPT374 - UDMA100, function 1 uses different prereset method */
765 static const struct ata_port_info info_hpt374_fn0
= {
766 .flags
= ATA_FLAG_SLAVE_POSS
,
767 .pio_mask
= ATA_PIO4
,
768 .mwdma_mask
= ATA_MWDMA2
,
769 .udma_mask
= ATA_UDMA5
,
770 .port_ops
= &hpt372_port_ops
772 static const struct ata_port_info info_hpt374_fn1
= {
773 .flags
= ATA_FLAG_SLAVE_POSS
,
774 .pio_mask
= ATA_PIO4
,
775 .mwdma_mask
= ATA_MWDMA2
,
776 .udma_mask
= ATA_UDMA5
,
777 .port_ops
= &hpt374_fn1_port_ops
780 static const int MHz
[4] = { 33, 40, 50, 66 };
781 void *private_data
= NULL
;
782 const struct ata_port_info
*ppi
[] = { NULL
, NULL
};
783 u8 rev
= dev
->revision
;
789 unsigned long iobase
= pci_resource_start(dev
, 4);
791 const struct hpt_chip
*chip_table
;
795 rc
= pcim_enable_device(dev
);
799 if (dev
->device
== PCI_DEVICE_ID_TTI_HPT366
) {
800 /* May be a later chip in disguise. Check */
801 /* Older chips are in the HPT366 driver. Ignore them */
804 /* N series chips have their own driver. Ignore */
810 ppi
[0] = &info_hpt370
;
811 chip_table
= &hpt370
;
815 ppi
[0] = &info_hpt370a
;
816 chip_table
= &hpt370a
;
820 ppi
[0] = &info_hpt372
;
821 chip_table
= &hpt372
;
824 printk(KERN_ERR
"pata_hpt37x: Unknown HPT366 "
825 "subtype, please report (%d).\n", rev
);
829 switch(dev
->device
) {
830 case PCI_DEVICE_ID_TTI_HPT372
:
831 /* 372N if rev >= 2*/
834 ppi
[0] = &info_hpt372
;
835 chip_table
= &hpt372a
;
837 case PCI_DEVICE_ID_TTI_HPT302
:
838 /* 302N if rev > 1 */
841 ppi
[0] = &info_hpt372
;
843 chip_table
= &hpt302
;
845 case PCI_DEVICE_ID_TTI_HPT371
:
848 ppi
[0] = &info_hpt372
;
849 chip_table
= &hpt371
;
850 /* Single channel device, master is not present
851 but the BIOS (or us for non x86) must mark it
853 pci_read_config_byte(dev
, 0x50, &mcr1
);
855 pci_write_config_byte(dev
, 0x50, mcr1
);
857 case PCI_DEVICE_ID_TTI_HPT374
:
858 chip_table
= &hpt374
;
859 if (!(PCI_FUNC(dev
->devfn
) & 1))
860 *ppi
= &info_hpt374_fn0
;
862 *ppi
= &info_hpt374_fn1
;
865 printk(KERN_ERR
"pata_hpt37x: PCI table is bogus please report (%d).\n", dev
->device
);
869 /* Ok so this is a chip we support */
871 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (L1_CACHE_BYTES
/ 4));
872 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x78);
873 pci_write_config_byte(dev
, PCI_MIN_GNT
, 0x08);
874 pci_write_config_byte(dev
, PCI_MAX_LAT
, 0x08);
876 pci_read_config_byte(dev
, 0x5A, &irqmask
);
878 pci_write_config_byte(dev
, 0x5a, irqmask
);
881 * default to pci clock. make sure MA15/16 are set to output
882 * to prevent drives having problems with 40-pin cables. Needed
883 * for some drives such as IBM-DTLA which will not enter ready
884 * state on reset when PDIAG is a input.
887 pci_write_config_byte(dev
, 0x5b, 0x23);
890 * HighPoint does this for HPT372A.
891 * NOTE: This register is only writeable via I/O space.
893 if (chip_table
== &hpt372a
)
894 outb(0x0e, iobase
+ 0x9c);
896 /* Some devices do not let this value be accessed via PCI space
897 according to the old driver. In addition we must use the value
898 from FN 0 on the HPT374 */
900 if (chip_table
== &hpt374
) {
901 freq
= hpt374_read_freq(dev
);
905 freq
= inl(iobase
+ 0x90);
907 if ((freq
>> 12) != 0xABCDE) {
912 printk(KERN_WARNING
"pata_hpt37x: BIOS has not set timing clocks.\n");
914 /* This is the process the HPT371 BIOS is reported to use */
915 for(i
= 0; i
< 128; i
++) {
916 pci_read_config_byte(dev
, 0x78, &sr
);
925 * Turn the frequency check into a band and then find a timing
929 clock_slot
= hpt37x_clock_slot(freq
, chip_table
->base
);
930 if (chip_table
->clocks
[clock_slot
] == NULL
|| prefer_dpll
) {
932 * We need to try PLL mode instead
934 * For non UDMA133 capable devices we should
935 * use a 50MHz DPLL by choice
937 unsigned int f_low
, f_high
;
941 dpll
= (ppi
[0]->udma_mask
& 0xC0) ? 3 : 2;
943 f_low
= (MHz
[clock_slot
] * 48) / MHz
[dpll
];
948 /* Select the DPLL clock. */
949 pci_write_config_byte(dev
, 0x5b, 0x21);
950 pci_write_config_dword(dev
, 0x5C, (f_high
<< 16) | f_low
| 0x100);
952 for(adjust
= 0; adjust
< 8; adjust
++) {
953 if (hpt37x_calibrate_dpll(dev
))
955 /* See if it'll settle at a fractionally different clock */
957 f_low
-= adjust
>> 1;
959 f_high
+= adjust
>> 1;
960 pci_write_config_dword(dev
, 0x5C, (f_high
<< 16) | f_low
| 0x100);
963 printk(KERN_ERR
"pata_hpt37x: DPLL did not stabilize!\n");
967 private_data
= (void *)hpt37x_timings_66
;
969 private_data
= (void *)hpt37x_timings_50
;
971 printk(KERN_INFO
"pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
972 MHz
[clock_slot
], MHz
[dpll
]);
974 private_data
= (void *)chip_table
->clocks
[clock_slot
];
976 * Perform a final fixup. Note that we will have used the
977 * DPLL on the HPT372 which means we don't have to worry
978 * about lack of UDMA133 support on lower clocks
981 if (clock_slot
< 2 && ppi
[0] == &info_hpt370
)
982 ppi
[0] = &info_hpt370_33
;
983 if (clock_slot
< 2 && ppi
[0] == &info_hpt370a
)
984 ppi
[0] = &info_hpt370a_33
;
985 printk(KERN_INFO
"pata_hpt37x: %s using %dMHz bus clock.\n",
986 chip_table
->name
, MHz
[clock_slot
]);
989 /* Now kick off ATA set up */
990 return ata_pci_sff_init_one(dev
, ppi
, &hpt37x_sht
, private_data
, 0);
993 static const struct pci_device_id hpt37x
[] = {
994 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT366
), },
995 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT371
), },
996 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT372
), },
997 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT374
), },
998 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT302
), },
1003 static struct pci_driver hpt37x_pci_driver
= {
1006 .probe
= hpt37x_init_one
,
1007 .remove
= ata_pci_remove_one
1010 static int __init
hpt37x_init(void)
1012 return pci_register_driver(&hpt37x_pci_driver
);
1015 static void __exit
hpt37x_exit(void)
1017 pci_unregister_driver(&hpt37x_pci_driver
);
1020 MODULE_AUTHOR("Alan Cox");
1021 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1022 MODULE_LICENSE("GPL");
1023 MODULE_DEVICE_TABLE(pci
, hpt37x
);
1024 MODULE_VERSION(DRV_VERSION
);
1026 module_init(hpt37x_init
);
1027 module_exit(hpt37x_exit
);