drivers/scsi/mpt2sas/mpi/mpi2.h

   1 /*
   2  *  Copyright (c) 2000-2009 LSI Corporation.
   3  *
   4  *
   5  *           Name:  mpi2.h
   6  *          Title:  MPI Message independent structures and definitions
   7  *                  including System Interface Register Set and
   8  *                  scatter/gather formats.
   9  *  Creation Date:  June 21, 2006
  10  *
  11  *  mpi2.h Version:  02.00.12
  12  *
  13  *  Version History
  14  *  ---------------
  15  *
  16  *  Date      Version   Description
  17  *  --------  --------  ------------------------------------------------------
  18  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  19  *  06-04-07  02.00.01  Bumped MPI2_HEADER_VERSION_UNIT.
  20  *  06-26-07  02.00.02  Bumped MPI2_HEADER_VERSION_UNIT.
  21  *  08-31-07  02.00.03  Bumped MPI2_HEADER_VERSION_UNIT.
  22  *                      Moved ReplyPostHostIndex register to offset 0x6C of the
  23  *                      MPI2_SYSTEM_INTERFACE_REGS and modified the define for
  24  *                      MPI2_REPLY_POST_HOST_INDEX_OFFSET.
  25  *                      Added union of request descriptors.
  26  *                      Added union of reply descriptors.
  27  *  10-31-07  02.00.04  Bumped MPI2_HEADER_VERSION_UNIT.
  28  *                      Added define for MPI2_VERSION_02_00.
  29  *                      Fixed the size of the FunctionDependent5 field in the
  30  *                      MPI2_DEFAULT_REPLY structure.
  31  *  12-18-07  02.00.05  Bumped MPI2_HEADER_VERSION_UNIT.
  32  *                      Removed the MPI-defined Fault Codes and extended the
  33  *                      product specific codes up to 0xEFFF.
  34  *                      Added a sixth key value for the WriteSequence register
  35  *                      and changed the flush value to 0x0.
  36  *                      Added message function codes for Diagnostic Buffer Post
  37  *                      and Diagnsotic Release.
  38  *                      New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
  39  *                      Moved MPI2_VERSION_UNION from mpi2_ioc.h.
  40  *  02-29-08  02.00.06  Bumped MPI2_HEADER_VERSION_UNIT.
  41  *  03-03-08  02.00.07  Bumped MPI2_HEADER_VERSION_UNIT.
  42  *  05-21-08  02.00.08  Bumped MPI2_HEADER_VERSION_UNIT.
  43  *                      Added #defines for marking a reply descriptor as unused.
  44  *  06-27-08  02.00.09  Bumped MPI2_HEADER_VERSION_UNIT.
  45  *  10-02-08  02.00.10  Bumped MPI2_HEADER_VERSION_UNIT.
  46  *                      Moved LUN field defines from mpi2_init.h.
  47  *  01-19-09  02.00.11  Bumped MPI2_HEADER_VERSION_UNIT.
  48  *  05-06-09  02.00.12  Bumped MPI2_HEADER_VERSION_UNIT.
  49  *                      In all request and reply descriptors, replaced VF_ID
  50  *                      field with MSIxIndex field.
  51  *                      Removed DevHandle field from
  52  *                      MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
  53  *                      bytes reserved.
  54  *                      Added RAID Accelerator functionality.
  55  *  --------------------------------------------------------------------------
  56  */
  57
  58 #ifndef MPI2_H
  59 #define MPI2_H
  60
  61
  62 /*****************************************************************************
  63 *
  64 *        MPI Version Definitions
  65 *
  66 *****************************************************************************/
  67
  68 #define MPI2_VERSION_MAJOR                  (0x02)
  69 #define MPI2_VERSION_MINOR                  (0x00)
  70 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
  71 #define MPI2_VERSION_MAJOR_SHIFT            (8)
  72 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
  73 #define MPI2_VERSION_MINOR_SHIFT            (0)
  74 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) |   \
  75                                       MPI2_VERSION_MINOR)
  76
  77 #define MPI2_VERSION_02_00                  (0x0200)
  78
  79 /* versioning for this MPI header set */
  80 #define MPI2_HEADER_VERSION_UNIT            (0x0C)
  81 #define MPI2_HEADER_VERSION_DEV             (0x00)
  82 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
  83 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
  84 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
  85 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
  86 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
  87
  88
  89 /*****************************************************************************
  90 *
  91 *        IOC State Definitions
  92 *
  93 *****************************************************************************/
  94
  95 #define MPI2_IOC_STATE_RESET               (0x00000000)
  96 #define MPI2_IOC_STATE_READY               (0x10000000)
  97 #define MPI2_IOC_STATE_OPERATIONAL         (0x20000000)
  98 #define MPI2_IOC_STATE_FAULT               (0x40000000)
  99
 100 #define MPI2_IOC_STATE_MASK                (0xF0000000)
 101 #define MPI2_IOC_STATE_SHIFT               (28)
 102
 103 /* Fault state range for prodcut specific codes */
 104 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN                 (0x0000)
 105 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX                 (0xEFFF)
 106
 107
 108 /*****************************************************************************
 109 *
 110 *        System Interface Register Definitions
 111 *
 112 *****************************************************************************/
 113
 114 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
 115 {
 116     U32         Doorbell;                   /* 0x00 */
 117     U32         WriteSequence;              /* 0x04 */
 118     U32         HostDiagnostic;             /* 0x08 */
 119     U32         Reserved1;                  /* 0x0C */
 120     U32         DiagRWData;                 /* 0x10 */
 121     U32         DiagRWAddressLow;           /* 0x14 */
 122     U32         DiagRWAddressHigh;          /* 0x18 */
 123     U32         Reserved2[5];               /* 0x1C */
 124     U32         HostInterruptStatus;        /* 0x30 */
 125     U32         HostInterruptMask;          /* 0x34 */
 126     U32         DCRData;                    /* 0x38 */
 127     U32         DCRAddress;                 /* 0x3C */
 128     U32         Reserved3[2];               /* 0x40 */
 129     U32         ReplyFreeHostIndex;         /* 0x48 */
 130     U32         Reserved4[8];               /* 0x4C */
 131     U32         ReplyPostHostIndex;         /* 0x6C */
 132     U32         Reserved5;                  /* 0x70 */
 133     U32         HCBSize;                    /* 0x74 */
 134     U32         HCBAddressLow;              /* 0x78 */
 135     U32         HCBAddressHigh;             /* 0x7C */
 136     U32         Reserved6[16];              /* 0x80 */
 137     U32         RequestDescriptorPostLow;   /* 0xC0 */
 138     U32         RequestDescriptorPostHigh;  /* 0xC4 */
 139     U32         Reserved7[14];              /* 0xC8 */
 140 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
 141   Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
 142
 143 /*
 144  * Defines for working with the Doorbell register.
 145  */
 146 #define MPI2_DOORBELL_OFFSET                    (0x00000000)
 147
 148 /* IOC --> System values */
 149 #define MPI2_DOORBELL_USED                      (0x08000000)
 150 #define MPI2_DOORBELL_WHO_INIT_MASK             (0x07000000)
 151 #define MPI2_DOORBELL_WHO_INIT_SHIFT            (24)
 152 #define MPI2_DOORBELL_FAULT_CODE_MASK           (0x0000FFFF)
 153 #define MPI2_DOORBELL_DATA_MASK                 (0x0000FFFF)
 154
 155 /* System --> IOC values */
 156 #define MPI2_DOORBELL_FUNCTION_MASK             (0xFF000000)
 157 #define MPI2_DOORBELL_FUNCTION_SHIFT            (24)
 158 #define MPI2_DOORBELL_ADD_DWORDS_MASK           (0x00FF0000)
 159 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT          (16)
 160
 161
 162 /*
 163  * Defines for the WriteSequence register
 164  */
 165 #define MPI2_WRITE_SEQUENCE_OFFSET              (0x00000004)
 166 #define MPI2_WRSEQ_KEY_VALUE_MASK               (0x0000000F)
 167 #define MPI2_WRSEQ_FLUSH_KEY_VALUE              (0x0)
 168 #define MPI2_WRSEQ_1ST_KEY_VALUE                (0xF)
 169 #define MPI2_WRSEQ_2ND_KEY_VALUE                (0x4)
 170 #define MPI2_WRSEQ_3RD_KEY_VALUE                (0xB)
 171 #define MPI2_WRSEQ_4TH_KEY_VALUE                (0x2)
 172 #define MPI2_WRSEQ_5TH_KEY_VALUE                (0x7)
 173 #define MPI2_WRSEQ_6TH_KEY_VALUE                (0xD)
 174
 175 /*
 176  * Defines for the HostDiagnostic register
 177  */
 178 #define MPI2_HOST_DIAGNOSTIC_OFFSET             (0x00000008)
 179
 180 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK       (0x00001800)
 181 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT    (0x00000000)
 182 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW       (0x00000800)
 183
 184 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG           (0x00000400)
 185 #define MPI2_DIAG_FORCE_HCB_ON_RESET            (0x00000200)
 186 #define MPI2_DIAG_HCB_MODE                      (0x00000100)
 187 #define MPI2_DIAG_DIAG_WRITE_ENABLE             (0x00000080)
 188 #define MPI2_DIAG_FLASH_BAD_SIG                 (0x00000040)
 189 #define MPI2_DIAG_RESET_HISTORY                 (0x00000020)
 190 #define MPI2_DIAG_DIAG_RW_ENABLE                (0x00000010)
 191 #define MPI2_DIAG_RESET_ADAPTER                 (0x00000004)
 192 #define MPI2_DIAG_HOLD_IOC_RESET                (0x00000002)
 193
 194 /*
 195  * Offsets for DiagRWData and address
 196  */
 197 #define MPI2_DIAG_RW_DATA_OFFSET                (0x00000010)
 198 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET         (0x00000014)
 199 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET        (0x00000018)
 200
 201 /*
 202  * Defines for the HostInterruptStatus register
 203  */
 204 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET       (0x00000030)
 205 #define MPI2_HIS_SYS2IOC_DB_STATUS              (0x80000000)
 206 #define MPI2_HIS_IOP_DOORBELL_STATUS            MPI2_HIS_SYS2IOC_DB_STATUS
 207 #define MPI2_HIS_RESET_IRQ_STATUS               (0x40000000)
 208 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT     (0x00000008)
 209 #define MPI2_HIS_IOC2SYS_DB_STATUS              (0x00000001)
 210 #define MPI2_HIS_DOORBELL_INTERRUPT             MPI2_HIS_IOC2SYS_DB_STATUS
 211
 212 /*
 213  * Defines for the HostInterruptMask register
 214  */
 215 #define MPI2_HOST_INTERRUPT_MASK_OFFSET         (0x00000034)
 216 #define MPI2_HIM_RESET_IRQ_MASK                 (0x40000000)
 217 #define MPI2_HIM_REPLY_INT_MASK                 (0x00000008)
 218 #define MPI2_HIM_RIM                            MPI2_HIM_REPLY_INT_MASK
 219 #define MPI2_HIM_IOC2SYS_DB_MASK                (0x00000001)
 220 #define MPI2_HIM_DIM                            MPI2_HIM_IOC2SYS_DB_MASK
 221
 222 /*
 223  * Offsets for DCRData and address
 224  */
 225 #define MPI2_DCR_DATA_OFFSET                    (0x00000038)
 226 #define MPI2_DCR_ADDRESS_OFFSET                 (0x0000003C)
 227
 228 /*
 229  * Offset for the Reply Free Queue
 230  */
 231 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET       (0x00000048)
 232
 233 /*
 234  * Offset for the Reply Descriptor Post Queue
 235  */
 236 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET       (0x0000006C)
 237
 238 /*
 239  * Defines for the HCBSize and address
 240  */
 241 #define MPI2_HCB_SIZE_OFFSET                    (0x00000074)
 242 #define MPI2_HCB_SIZE_SIZE_MASK                 (0xFFFFF000)
 243 #define MPI2_HCB_SIZE_HCB_ENABLE                (0x00000001)
 244
 245 #define MPI2_HCB_ADDRESS_LOW_OFFSET             (0x00000078)
 246 #define MPI2_HCB_ADDRESS_HIGH_OFFSET            (0x0000007C)
 247
 248 /*
 249  * Offsets for the Request Queue
 250  */
 251 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET     (0x000000C0)
 252 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET    (0x000000C4)
 253
 254
 255 /*****************************************************************************
 256 *
 257 *        Message Descriptors
 258 *
 259 *****************************************************************************/
 260
 261 /* Request Descriptors */
 262
 263 /* Default Request Descriptor */
 264 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
 265 {
 266     U8              RequestFlags;               /* 0x00 */
 267     U8              MSIxIndex;                  /* 0x01 */
 268     U16             SMID;                       /* 0x02 */
 269     U16             LMID;                       /* 0x04 */
 270     U16             DescriptorTypeDependent;    /* 0x06 */
 271 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 272   MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 273   Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
 274
 275 /* defines for the RequestFlags field */
 276 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK               (0x0E)
 277 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 278 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET             (0x02)
 279 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY           (0x06)
 280 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE            (0x08)
 281 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR        (0x0A)
 282
 283 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
 284
 285
 286 /* High Priority Request Descriptor */
 287 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
 288 {
 289     U8              RequestFlags;               /* 0x00 */
 290     U8              MSIxIndex;                  /* 0x01 */
 291     U16             SMID;                       /* 0x02 */
 292     U16             LMID;                       /* 0x04 */
 293     U16             Reserved1;                  /* 0x06 */
 294 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 295   MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 296   Mpi2HighPriorityRequestDescriptor_t,
 297   MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
 298
 299
 300 /* SCSI IO Request Descriptor */
 301 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
 302 {
 303     U8              RequestFlags;               /* 0x00 */
 304     U8              MSIxIndex;                  /* 0x01 */
 305     U16             SMID;                       /* 0x02 */
 306     U16             LMID;                       /* 0x04 */
 307     U16             DevHandle;                  /* 0x06 */
 308 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 309   MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 310   Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
 311
 312
 313 /* SCSI Target Request Descriptor */
 314 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
 315 {
 316     U8              RequestFlags;               /* 0x00 */
 317     U8              MSIxIndex;                  /* 0x01 */
 318     U16             SMID;                       /* 0x02 */
 319     U16             LMID;                       /* 0x04 */
 320     U16             IoIndex;                    /* 0x06 */
 321 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 322   MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 323   Mpi2SCSITargetRequestDescriptor_t,
 324   MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
 325
 326
 327 /* RAID Accelerator Request Descriptor */
 328 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 329     U8              RequestFlags;               /* 0x00 */
 330     U8              MSIxIndex;                  /* 0x01 */
 331     U16             SMID;                       /* 0x02 */
 332     U16             LMID;                       /* 0x04 */
 333     U16             Reserved;                   /* 0x06 */
 334 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 335   MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 336   Mpi2RAIDAcceleratorRequestDescriptor_t,
 337   MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
 338
 339
 340 /* union of Request Descriptors */
 341 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
 342 {
 343     MPI2_DEFAULT_REQUEST_DESCRIPTOR             Default;
 344     MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR       HighPriority;
 345     MPI2_SCSI_IO_REQUEST_DESCRIPTOR             SCSIIO;
 346     MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR         SCSITarget;
 347     MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR          RAIDAccelerator;
 348     U64                                         Words;
 349 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
 350   Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
 351
 352
 353 /* Reply Descriptors */
 354
 355 /* Default Reply Descriptor */
 356 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
 357 {
 358     U8              ReplyFlags;                 /* 0x00 */
 359     U8              MSIxIndex;                  /* 0x01 */
 360     U16             DescriptorTypeDependent1;   /* 0x02 */
 361     U32             DescriptorTypeDependent2;   /* 0x04 */
 362 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
 363   Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
 364
 365 /* defines for the ReplyFlags field */
 366 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK                   (0x0F)
 367 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS             (0x00)
 368 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY               (0x01)
 369 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS        (0x02)
 370 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER       (0x03)
 371 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS    (0x05)
 372 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED                      (0x0F)
 373
 374 /* values for marking a reply descriptor as unused */
 375 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK             (0xFFFFFFFF)
 376 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK             (0xFFFFFFFF)
 377
 378 /* Address Reply Descriptor */
 379 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
 380 {
 381     U8              ReplyFlags;                 /* 0x00 */
 382     U8              MSIxIndex;                  /* 0x01 */
 383     U16             SMID;                       /* 0x02 */
 384     U32             ReplyFrameAddress;          /* 0x04 */
 385 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
 386   Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
 387
 388 #define MPI2_ADDRESS_REPLY_SMID_INVALID                 (0x00)
 389
 390
 391 /* SCSI IO Success Reply Descriptor */
 392 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
 393 {
 394     U8              ReplyFlags;                 /* 0x00 */
 395     U8              MSIxIndex;                  /* 0x01 */
 396     U16             SMID;                       /* 0x02 */
 397     U16             TaskTag;                    /* 0x04 */
 398     U16             Reserved1;                  /* 0x06 */
 399 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 400   MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 401   Mpi2SCSIIOSuccessReplyDescriptor_t,
 402   MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
 403
 404
 405 /* TargetAssist Success Reply Descriptor */
 406 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
 407 {
 408     U8              ReplyFlags;                 /* 0x00 */
 409     U8              MSIxIndex;                  /* 0x01 */
 410     U16             SMID;                       /* 0x02 */
 411     U8              SequenceNumber;             /* 0x04 */
 412     U8              Reserved1;                  /* 0x05 */
 413     U16             IoIndex;                    /* 0x06 */
 414 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 415   MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 416   Mpi2TargetAssistSuccessReplyDescriptor_t,
 417   MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
 418
 419
 420 /* Target Command Buffer Reply Descriptor */
 421 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
 422 {
 423     U8              ReplyFlags;                 /* 0x00 */
 424     U8              MSIxIndex;                  /* 0x01 */
 425     U8              VP_ID;                      /* 0x02 */
 426     U8              Flags;                      /* 0x03 */
 427     U16             InitiatorDevHandle;         /* 0x04 */
 428     U16             IoIndex;                    /* 0x06 */
 429 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 430   MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 431   Mpi2TargetCommandBufferReplyDescriptor_t,
 432   MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
 433
 434 /* defines for Flags field */
 435 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK     (0x3F)
 436
 437
 438 /* RAID Accelerator Success Reply Descriptor */
 439 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 440     U8              ReplyFlags;                 /* 0x00 */
 441     U8              MSIxIndex;                  /* 0x01 */
 442     U16             SMID;                       /* 0x02 */
 443     U32             Reserved;                   /* 0x04 */
 444 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 445   MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 446   Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
 447   MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
 448
 449
 450 /* union of Reply Descriptors */
 451 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
 452 {
 453     MPI2_DEFAULT_REPLY_DESCRIPTOR                   Default;
 454     MPI2_ADDRESS_REPLY_DESCRIPTOR                   AddressReply;
 455     MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR           SCSIIOSuccess;
 456     MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR      TargetAssistSuccess;
 457     MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR     TargetCommandBuffer;
 458     MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR  RAIDAcceleratorSuccess;
 459     U64                                             Words;
 460 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
 461   Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
 462
 463
 464
 465 /*****************************************************************************
 466 *
 467 *        Message Functions
 468 *              0x80 -> 0x8F reserved for private message use per product
 469 *
 470 *
 471 *****************************************************************************/
 472
 473 #define MPI2_FUNCTION_SCSI_IO_REQUEST               (0x00) /* SCSI IO */
 474 #define MPI2_FUNCTION_SCSI_TASK_MGMT                (0x01) /* SCSI Task Management */
 475 #define MPI2_FUNCTION_IOC_INIT                      (0x02) /* IOC Init */
 476 #define MPI2_FUNCTION_IOC_FACTS                     (0x03) /* IOC Facts */
 477 #define MPI2_FUNCTION_CONFIG                        (0x04) /* Configuration */
 478 #define MPI2_FUNCTION_PORT_FACTS                    (0x05) /* Port Facts */
 479 #define MPI2_FUNCTION_PORT_ENABLE                   (0x06) /* Port Enable */
 480 #define MPI2_FUNCTION_EVENT_NOTIFICATION            (0x07) /* Event Notification */
 481 #define MPI2_FUNCTION_EVENT_ACK                     (0x08) /* Event Acknowledge */
 482 #define MPI2_FUNCTION_FW_DOWNLOAD                   (0x09) /* FW Download */
 483 #define MPI2_FUNCTION_TARGET_ASSIST                 (0x0B) /* Target Assist */
 484 #define MPI2_FUNCTION_TARGET_STATUS_SEND            (0x0C) /* Target Status Send */
 485 #define MPI2_FUNCTION_TARGET_MODE_ABORT             (0x0D) /* Target Mode Abort */
 486 #define MPI2_FUNCTION_FW_UPLOAD                     (0x12) /* FW Upload */
 487 #define MPI2_FUNCTION_RAID_ACTION                   (0x15) /* RAID Action */
 488 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH      (0x16) /* SCSI IO RAID Passthrough */
 489 #define MPI2_FUNCTION_TOOLBOX                       (0x17) /* Toolbox */
 490 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR      (0x18) /* SCSI Enclosure Processor */
 491 #define MPI2_FUNCTION_SMP_PASSTHROUGH               (0x1A) /* SMP Passthrough */
 492 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL           (0x1B) /* SAS IO Unit Control */
 493 #define MPI2_FUNCTION_SATA_PASSTHROUGH              (0x1C) /* SATA Passthrough */
 494 #define MPI2_FUNCTION_DIAG_BUFFER_POST              (0x1D) /* Diagnostic Buffer Post */
 495 #define MPI2_FUNCTION_DIAG_RELEASE                  (0x1E) /* Diagnostic Release */
 496 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST      (0x24) /* Target Command Buffer Post Base */
 497 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST      (0x25) /* Target Command Buffer Post List */
 498 #define MPI2_FUNCTION_RAID_ACCELERATOR              (0x2C) /* RAID Accelerator*/
 499
 500
 501
 502 /* Doorbell functions */
 503 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET        (0x40)
 504 /* #define MPI2_FUNCTION_IO_UNIT_RESET                 (0x41) */
 505 #define MPI2_FUNCTION_HANDSHAKE                     (0x42)
 506
 507
 508 /*****************************************************************************
 509 *
 510 *        IOC Status Values
 511 *
 512 *****************************************************************************/
 513
 514 /* mask for IOCStatus status value */
 515 #define MPI2_IOCSTATUS_MASK                     (0x7FFF)
 516
 517 /****************************************************************************
 518 *  Common IOCStatus values for all replies
 519 ****************************************************************************/
 520
 521 #define MPI2_IOCSTATUS_SUCCESS                      (0x0000)
 522 #define MPI2_IOCSTATUS_INVALID_FUNCTION             (0x0001)
 523 #define MPI2_IOCSTATUS_BUSY                         (0x0002)
 524 #define MPI2_IOCSTATUS_INVALID_SGL                  (0x0003)
 525 #define MPI2_IOCSTATUS_INTERNAL_ERROR               (0x0004)
 526 #define MPI2_IOCSTATUS_INVALID_VPID                 (0x0005)
 527 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES       (0x0006)
 528 #define MPI2_IOCSTATUS_INVALID_FIELD                (0x0007)
 529 #define MPI2_IOCSTATUS_INVALID_STATE                (0x0008)
 530 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED       (0x0009)
 531
 532 /****************************************************************************
 533 *  Config IOCStatus values
 534 ****************************************************************************/
 535
 536 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION        (0x0020)
 537 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE          (0x0021)
 538 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE          (0x0022)
 539 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA          (0x0023)
 540 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS           (0x0024)
 541 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT           (0x0025)
 542
 543 /****************************************************************************
 544 *  SCSI IO Reply
 545 ****************************************************************************/
 546
 547 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR         (0x0040)
 548 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE       (0x0042)
 549 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE        (0x0043)
 550 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN            (0x0044)
 551 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN           (0x0045)
 552 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR           (0x0046)
 553 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR          (0x0047)
 554 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED         (0x0048)
 555 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH       (0x0049)
 556 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED        (0x004A)
 557 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED          (0x004B)
 558 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED          (0x004C)
 559
 560 /****************************************************************************
 561 *  For use by SCSI Initiator and SCSI Target end-to-end data protection
 562 ****************************************************************************/
 563
 564 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR             (0x004D)
 565 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR           (0x004E)
 566 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR           (0x004F)
 567
 568 /****************************************************************************
 569 *  SCSI Target values
 570 ****************************************************************************/
 571
 572 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX      (0x0062)
 573 #define MPI2_IOCSTATUS_TARGET_ABORTED               (0x0063)
 574 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE     (0x0064)
 575 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION         (0x0065)
 576 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH   (0x006A)
 577 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR     (0x006D)
 578 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA   (0x006E)
 579 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT          (0x006F)
 580 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT       (0x0070)
 581 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED          (0x0071)
 582
 583 /****************************************************************************
 584 *  Serial Attached SCSI values
 585 ****************************************************************************/
 586
 587 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED       (0x0090)
 588 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN         (0x0091)
 589
 590 /****************************************************************************
 591 *  Diagnostic Buffer Post / Diagnostic Release values
 592 ****************************************************************************/
 593
 594 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED          (0x00A0)
 595
 596 /****************************************************************************
 597 *  RAID Accelerator values
 598 ****************************************************************************/
 599
 600 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR             (0x00B0)
 601
 602 /****************************************************************************
 603 *  IOCStatus flag to indicate that log info is available
 604 ****************************************************************************/
 605
 606 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE      (0x8000)
 607
 608 /****************************************************************************
 609 *  IOCLogInfo Types
 610 ****************************************************************************/
 611
 612 #define MPI2_IOCLOGINFO_TYPE_MASK               (0xF0000000)
 613 #define MPI2_IOCLOGINFO_TYPE_SHIFT              (28)
 614 #define MPI2_IOCLOGINFO_TYPE_NONE               (0x0)
 615 #define MPI2_IOCLOGINFO_TYPE_SCSI               (0x1)
 616 #define MPI2_IOCLOGINFO_TYPE_FC                 (0x2)
 617 #define MPI2_IOCLOGINFO_TYPE_SAS                (0x3)
 618 #define MPI2_IOCLOGINFO_TYPE_ISCSI              (0x4)
 619 #define MPI2_IOCLOGINFO_LOG_DATA_MASK           (0x0FFFFFFF)
 620
 621
 622 /*****************************************************************************
 623 *
 624 *        Standard Message Structures
 625 *
 626 *****************************************************************************/
 627
 628 /****************************************************************************
 629 * Request Message Header for all request messages
 630 ****************************************************************************/
 631
 632 typedef struct _MPI2_REQUEST_HEADER
 633 {
 634     U16             FunctionDependent1;         /* 0x00 */
 635     U8              ChainOffset;                /* 0x02 */
 636     U8              Function;                   /* 0x03 */
 637     U16             FunctionDependent2;         /* 0x04 */
 638     U8              FunctionDependent3;         /* 0x06 */
 639     U8              MsgFlags;                   /* 0x07 */
 640     U8              VP_ID;                      /* 0x08 */
 641     U8              VF_ID;                      /* 0x09 */
 642     U16             Reserved1;                  /* 0x0A */
 643 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
 644   MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
 645
 646
 647 /****************************************************************************
 648 *  Default Reply
 649 ****************************************************************************/
 650
 651 typedef struct _MPI2_DEFAULT_REPLY
 652 {
 653     U16             FunctionDependent1;         /* 0x00 */
 654     U8              MsgLength;                  /* 0x02 */
 655     U8              Function;                   /* 0x03 */
 656     U16             FunctionDependent2;         /* 0x04 */
 657     U8              FunctionDependent3;         /* 0x06 */
 658     U8              MsgFlags;                   /* 0x07 */
 659     U8              VP_ID;                      /* 0x08 */
 660     U8              VF_ID;                      /* 0x09 */
 661     U16             Reserved1;                  /* 0x0A */
 662     U16             FunctionDependent5;         /* 0x0C */
 663     U16             IOCStatus;                  /* 0x0E */
 664     U32             IOCLogInfo;                 /* 0x10 */
 665 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
 666   MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
 667
 668
 669 /* common version structure/union used in messages and configuration pages */
 670
 671 typedef struct _MPI2_VERSION_STRUCT
 672 {
 673     U8                      Dev;                        /* 0x00 */
 674     U8                      Unit;                       /* 0x01 */
 675     U8                      Minor;                      /* 0x02 */
 676     U8                      Major;                      /* 0x03 */
 677 } MPI2_VERSION_STRUCT;
 678
 679 typedef union _MPI2_VERSION_UNION
 680 {
 681     MPI2_VERSION_STRUCT     Struct;
 682     U32                     Word;
 683 } MPI2_VERSION_UNION;
 684
 685
 686 /* LUN field defines, common to many structures */
 687 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING             (0x0000FFFF)
 688 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING            (0xFFFF0000)
 689 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING             (0x0000FFFF)
 690 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING            (0xFFFF0000)
 691 #define MPI2_LUN_LEVEL_1_WORD                       (0xFF00)
 692 #define MPI2_LUN_LEVEL_1_DWORD                      (0x0000FF00)
 693
 694
 695 /*****************************************************************************
 696 *
 697 *        Fusion-MPT MPI Scatter Gather Elements
 698 *
 699 *****************************************************************************/
 700
 701 /****************************************************************************
 702 *  MPI Simple Element structures
 703 ****************************************************************************/
 704
 705 typedef struct _MPI2_SGE_SIMPLE32
 706 {
 707     U32                     FlagsLength;
 708     U32                     Address;
 709 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
 710   Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
 711
 712 typedef struct _MPI2_SGE_SIMPLE64
 713 {
 714     U32                     FlagsLength;
 715     U64                     Address;
 716 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
 717   Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
 718
 719 typedef struct _MPI2_SGE_SIMPLE_UNION
 720 {
 721     U32                     FlagsLength;
 722     union
 723     {
 724         U32                 Address32;
 725         U64                 Address64;
 726     } u;
 727 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
 728   Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
 729
 730
 731 /****************************************************************************
 732 *  MPI Chain Element structures
 733 ****************************************************************************/
 734
 735 typedef struct _MPI2_SGE_CHAIN32
 736 {
 737     U16                     Length;
 738     U8                      NextChainOffset;
 739     U8                      Flags;
 740     U32                     Address;
 741 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
 742   Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
 743
 744 typedef struct _MPI2_SGE_CHAIN64
 745 {
 746     U16                     Length;
 747     U8                      NextChainOffset;
 748     U8                      Flags;
 749     U64                     Address;
 750 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
 751   Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
 752
 753 typedef struct _MPI2_SGE_CHAIN_UNION
 754 {
 755     U16                     Length;
 756     U8                      NextChainOffset;
 757     U8                      Flags;
 758     union
 759     {
 760         U32                 Address32;
 761         U64                 Address64;
 762     } u;
 763 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
 764   Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
 765
 766
 767 /****************************************************************************
 768 *  MPI Transaction Context Element structures
 769 ****************************************************************************/
 770
 771 typedef struct _MPI2_SGE_TRANSACTION32
 772 {
 773     U8                      Reserved;
 774     U8                      ContextSize;
 775     U8                      DetailsLength;
 776     U8                      Flags;
 777     U32                     TransactionContext[1];
 778     U32                     TransactionDetails[1];
 779 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
 780   Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
 781
 782 typedef struct _MPI2_SGE_TRANSACTION64
 783 {
 784     U8                      Reserved;
 785     U8                      ContextSize;
 786     U8                      DetailsLength;
 787     U8                      Flags;
 788     U32                     TransactionContext[2];
 789     U32                     TransactionDetails[1];
 790 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
 791   Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
 792
 793 typedef struct _MPI2_SGE_TRANSACTION96
 794 {
 795     U8                      Reserved;
 796     U8                      ContextSize;
 797     U8                      DetailsLength;
 798     U8                      Flags;
 799     U32                     TransactionContext[3];
 800     U32                     TransactionDetails[1];
 801 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
 802   Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
 803
 804 typedef struct _MPI2_SGE_TRANSACTION128
 805 {
 806     U8                      Reserved;
 807     U8                      ContextSize;
 808     U8                      DetailsLength;
 809     U8                      Flags;
 810     U32                     TransactionContext[4];
 811     U32                     TransactionDetails[1];
 812 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
 813   Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
 814
 815 typedef struct _MPI2_SGE_TRANSACTION_UNION
 816 {
 817     U8                      Reserved;
 818     U8                      ContextSize;
 819     U8                      DetailsLength;
 820     U8                      Flags;
 821     union
 822     {
 823         U32                 TransactionContext32[1];
 824         U32                 TransactionContext64[2];
 825         U32                 TransactionContext96[3];
 826         U32                 TransactionContext128[4];
 827     } u;
 828     U32                     TransactionDetails[1];
 829 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
 830   Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
 831
 832
 833 /****************************************************************************
 834 *  MPI SGE union for IO SGL's
 835 ****************************************************************************/
 836
 837 typedef struct _MPI2_MPI_SGE_IO_UNION
 838 {
 839     union
 840     {
 841         MPI2_SGE_SIMPLE_UNION   Simple;
 842         MPI2_SGE_CHAIN_UNION    Chain;
 843     } u;
 844 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
 845   Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
 846
 847
 848 /****************************************************************************
 849 *  MPI SGE union for SGL's with Simple and Transaction elements
 850 ****************************************************************************/
 851
 852 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
 853 {
 854     union
 855     {
 856         MPI2_SGE_SIMPLE_UNION       Simple;
 857         MPI2_SGE_TRANSACTION_UNION  Transaction;
 858     } u;
 859 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
 860   Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
 861
 862
 863 /****************************************************************************
 864 *  All MPI SGE types union
 865 ****************************************************************************/
 866
 867 typedef struct _MPI2_MPI_SGE_UNION
 868 {
 869     union
 870     {
 871         MPI2_SGE_SIMPLE_UNION       Simple;
 872         MPI2_SGE_CHAIN_UNION        Chain;
 873         MPI2_SGE_TRANSACTION_UNION  Transaction;
 874     } u;
 875 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
 876   Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
 877
 878
 879 /****************************************************************************
 880 *  MPI SGE field definition and masks
 881 ****************************************************************************/
 882
 883 /* Flags field bit definitions */
 884
 885 #define MPI2_SGE_FLAGS_LAST_ELEMENT             (0x80)
 886 #define MPI2_SGE_FLAGS_END_OF_BUFFER            (0x40)
 887 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK        (0x30)
 888 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS            (0x08)
 889 #define MPI2_SGE_FLAGS_DIRECTION                (0x04)
 890 #define MPI2_SGE_FLAGS_ADDRESS_SIZE             (0x02)
 891 #define MPI2_SGE_FLAGS_END_OF_LIST              (0x01)
 892
 893 #define MPI2_SGE_FLAGS_SHIFT                    (24)
 894
 895 #define MPI2_SGE_LENGTH_MASK                    (0x00FFFFFF)
 896 #define MPI2_SGE_CHAIN_LENGTH_MASK              (0x0000FFFF)
 897
 898 /* Element Type */
 899
 900 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT      (0x00)
 901 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT           (0x10)
 902 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT            (0x30)
 903 #define MPI2_SGE_FLAGS_ELEMENT_MASK             (0x30)
 904
 905 /* Address location */
 906
 907 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS           (0x00)
 908
 909 /* Direction */
 910
 911 #define MPI2_SGE_FLAGS_IOC_TO_HOST              (0x00)
 912 #define MPI2_SGE_FLAGS_HOST_TO_IOC              (0x04)
 913
 914 /* Address Size */
 915
 916 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING        (0x00)
 917 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
 918
 919 /* Context Size */
 920
 921 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT           (0x00)
 922 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT           (0x02)
 923 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT           (0x04)
 924 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT          (0x06)
 925
 926 #define MPI2_SGE_CHAIN_OFFSET_MASK              (0x00FF0000)
 927 #define MPI2_SGE_CHAIN_OFFSET_SHIFT             (16)
 928
 929 /****************************************************************************
 930 *  MPI SGE operation Macros
 931 ****************************************************************************/
 932
 933 /* SIMPLE FlagsLength manipulations... */
 934 #define MPI2_SGE_SET_FLAGS(f)          ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
 935 #define MPI2_SGE_GET_FLAGS(f)          (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
 936 #define MPI2_SGE_LENGTH(f)             ((f) & MPI2_SGE_LENGTH_MASK)
 937 #define MPI2_SGE_CHAIN_LENGTH(f)       ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
 938
 939 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
 940
 941 #define MPI2_pSGE_GET_FLAGS(psg)            MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
 942 #define MPI2_pSGE_GET_LENGTH(psg)           MPI2_SGE_LENGTH((psg)->FlagsLength)
 943 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
 944
 945 /* CAUTION - The following are READ-MODIFY-WRITE! */
 946 #define MPI2_pSGE_SET_FLAGS(psg,f)      (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
 947 #define MPI2_pSGE_SET_LENGTH(psg,l)     (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
 948
 949 #define MPI2_GET_CHAIN_OFFSET(x)    ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
 950
 951
 952 /*****************************************************************************
 953 *
 954 *        Fusion-MPT IEEE Scatter Gather Elements
 955 *
 956 *****************************************************************************/
 957
 958 /****************************************************************************
 959 *  IEEE Simple Element structures
 960 ****************************************************************************/
 961
 962 typedef struct _MPI2_IEEE_SGE_SIMPLE32
 963 {
 964     U32                     Address;
 965     U32                     FlagsLength;
 966 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
 967   Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
 968
 969 typedef struct _MPI2_IEEE_SGE_SIMPLE64
 970 {
 971     U64                     Address;
 972     U32                     Length;
 973     U16                     Reserved1;
 974     U8                      Reserved2;
 975     U8                      Flags;
 976 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
 977   Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
 978
 979 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
 980 {
 981     MPI2_IEEE_SGE_SIMPLE32  Simple32;
 982     MPI2_IEEE_SGE_SIMPLE64  Simple64;
 983 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
 984   Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
 985
 986
 987 /****************************************************************************
 988 *  IEEE Chain Element structures
 989 ****************************************************************************/
 990
 991 typedef MPI2_IEEE_SGE_SIMPLE32  MPI2_IEEE_SGE_CHAIN32;
 992
 993 typedef MPI2_IEEE_SGE_SIMPLE64  MPI2_IEEE_SGE_CHAIN64;
 994
 995 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
 996 {
 997     MPI2_IEEE_SGE_CHAIN32   Chain32;
 998     MPI2_IEEE_SGE_CHAIN64   Chain64;
 999 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1000   Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1001
1002
1003 /****************************************************************************
1004 *  All IEEE SGE types union
1005 ****************************************************************************/
1006
1007 typedef struct _MPI2_IEEE_SGE_UNION
1008 {
1009     union
1010     {
1011         MPI2_IEEE_SGE_SIMPLE_UNION  Simple;
1012         MPI2_IEEE_SGE_CHAIN_UNION   Chain;
1013     } u;
1014 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1015   Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1016
1017
1018 /****************************************************************************
1019 *  IEEE SGE field definitions and masks
1020 ****************************************************************************/
1021
1022 /* Flags field bit definitions */
1023
1024 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK   (0x80)
1025
1026 #define MPI2_IEEE32_SGE_FLAGS_SHIFT             (24)
1027
1028 #define MPI2_IEEE32_SGE_LENGTH_MASK             (0x00FFFFFF)
1029
1030 /* Element Type */
1031
1032 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT      (0x00)
1033 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT       (0x80)
1034
1035 /* Data Location Address Space */
1036
1037 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK           (0x03)
1038 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR         (0x00)
1039 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR         (0x01)
1040 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR         (0x02)
1041 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
1042
1043
1044 /****************************************************************************
1045 *  IEEE SGE operation Macros
1046 ****************************************************************************/
1047
1048 /* SIMPLE FlagsLength manipulations... */
1049 #define MPI2_IEEE32_SGE_SET_FLAGS(f)     ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1050 #define MPI2_IEEE32_SGE_GET_FLAGS(f)     (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1051 #define MPI2_IEEE32_SGE_LENGTH(f)        ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1052
1053 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l)      (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1054
1055 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg)             MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1056 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg)            MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1057 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l)  (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1058
1059 /* CAUTION - The following are READ-MODIFY-WRITE! */
1060 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f)    (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1061 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l)   (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1062
1063
1064
1065
1066 /*****************************************************************************
1067 *
1068 *        Fusion-MPT MPI/IEEE Scatter Gather Unions
1069 *
1070 *****************************************************************************/
1071
1072 typedef union _MPI2_SIMPLE_SGE_UNION
1073 {
1074     MPI2_SGE_SIMPLE_UNION       MpiSimple;
1075     MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
1076 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1077   Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1078
1079
1080 typedef union _MPI2_SGE_IO_UNION
1081 {
1082     MPI2_SGE_SIMPLE_UNION       MpiSimple;
1083     MPI2_SGE_CHAIN_UNION        MpiChain;
1084     MPI2_IEEE_SGE_SIMPLE_UNION  IeeeSimple;
1085     MPI2_IEEE_SGE_CHAIN_UNION   IeeeChain;
1086 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1087   Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1088
1089
1090 /****************************************************************************
1091 *
1092 *  Values for SGLFlags field, used in many request messages with an SGL
1093 *
1094 ****************************************************************************/
1095
1096 /* values for MPI SGL Data Location Address Space subfield */
1097 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK            (0x0C)
1098 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE          (0x00)
1099 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE          (0x04)
1100 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE          (0x08)
1101 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE       (0x0C)
1102 /* values for SGL Type subfield */
1103 #define MPI2_SGLFLAGS_SGL_TYPE_MASK                 (0x03)
1104 #define MPI2_SGLFLAGS_SGL_TYPE_MPI                  (0x00)
1105 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32               (0x01)
1106 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64               (0x02)
1107
1108
1109 #endif
1110