2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
36 #define wrmsrl(msr, val) \
38 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39 (unsigned long)(val)); \
40 native_write_msr((msr), (u32)((u64)(val)), \
41 (u32)((u64)(val) >> 32)); \
46 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
49 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
51 unsigned long offset
, addr
= (unsigned long)from
;
52 unsigned long size
, len
= 0;
58 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
62 offset
= addr
& (PAGE_SIZE
- 1);
63 size
= min(PAGE_SIZE
- offset
, n
- len
);
65 map
= kmap_atomic(page
);
66 memcpy(to
, map
+offset
, size
);
79 struct event_constraint
{
81 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
90 int nb_id
; /* NorthBridge id */
91 int refcnt
; /* reference count */
92 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
93 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
96 #define MAX_LBR_ENTRIES 16
98 struct cpu_hw_events
{
100 * Generic x86 PMC bits
102 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
103 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
104 unsigned long running
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
110 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
111 u64 tags
[X86_PMC_IDX_MAX
];
112 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
114 unsigned int group_flag
;
117 * Intel DebugStore bits
119 struct debug_store
*ds
;
127 struct perf_branch_stack lbr_stack
;
128 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
133 struct amd_nb
*amd_nb
;
136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
137 { .idxmsk64 = (n) }, \
143 #define EVENT_CONSTRAINT(c, n, m) \
144 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
147 * Constraint on the Event code.
149 #define INTEL_EVENT_CONSTRAINT(c, n) \
150 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
153 * Constraint on the Event code + UMask + fixed-mask
155 * filter mask to validate fixed counter events.
156 * the following filters disqualify for fixed counters:
160 * The other filters are supported by fixed counters.
161 * The any-thread option is supported starting with v3.
163 #define FIXED_EVENT_CONSTRAINT(c, n) \
164 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
167 * Constraint on the Event code + UMask
169 #define PEBS_EVENT_CONSTRAINT(c, n) \
170 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
172 #define EVENT_CONSTRAINT_END \
173 EVENT_CONSTRAINT(0, 0, 0)
175 #define for_each_event_constraint(e, c) \
176 for ((e) = (c); (e)->weight; (e)++)
178 union perf_capabilities
{
182 u64 pebs_arch_reg
: 1;
190 * struct x86_pmu - generic x86 pmu
194 * Generic x86 PMC bits
198 int (*handle_irq
)(struct pt_regs
*);
199 void (*disable_all
)(void);
200 void (*enable_all
)(int added
);
201 void (*enable
)(struct perf_event
*);
202 void (*disable
)(struct perf_event
*);
203 int (*hw_config
)(struct perf_event
*event
);
204 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
207 u64 (*event_map
)(int);
210 int num_counters_fixed
;
215 struct event_constraint
*
216 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
217 struct perf_event
*event
);
219 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
220 struct perf_event
*event
);
221 struct event_constraint
*event_constraints
;
222 void (*quirks
)(void);
223 int perfctr_second_write
;
225 int (*cpu_prepare
)(int cpu
);
226 void (*cpu_starting
)(int cpu
);
227 void (*cpu_dying
)(int cpu
);
228 void (*cpu_dead
)(int cpu
);
231 * Intel Arch Perfmon v2+
234 union perf_capabilities intel_cap
;
237 * Intel DebugStore bits
240 int bts_active
, pebs_active
;
241 int pebs_record_size
;
242 void (*drain_pebs
)(struct pt_regs
*regs
);
243 struct event_constraint
*pebs_constraints
;
248 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
249 int lbr_nr
; /* hardware stack size */
252 static struct x86_pmu x86_pmu __read_mostly
;
254 static DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
258 static int x86_perf_event_set_period(struct perf_event
*event
);
261 * Generalized hw caching related hw_event table, filled
262 * in on a per model basis. A value of 0 means
263 * 'not supported', -1 means 'hw_event makes no sense on
264 * this CPU', any other value means the raw hw_event
268 #define C(x) PERF_COUNT_HW_CACHE_##x
270 static u64 __read_mostly hw_cache_event_ids
271 [PERF_COUNT_HW_CACHE_MAX
]
272 [PERF_COUNT_HW_CACHE_OP_MAX
]
273 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
276 * Propagate event elapsed time into the generic event.
277 * Can only be executed on the CPU where the event is active.
278 * Returns the delta events processed.
281 x86_perf_event_update(struct perf_event
*event
)
283 struct hw_perf_event
*hwc
= &event
->hw
;
284 int shift
= 64 - x86_pmu
.cntval_bits
;
285 u64 prev_raw_count
, new_raw_count
;
289 if (idx
== X86_PMC_IDX_FIXED_BTS
)
293 * Careful: an NMI might modify the previous event value.
295 * Our tactic to handle this is to first atomically read and
296 * exchange a new raw count - then add that new-prev delta
297 * count to the generic event atomically:
300 prev_raw_count
= local64_read(&hwc
->prev_count
);
301 rdmsrl(hwc
->event_base
+ idx
, new_raw_count
);
303 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
304 new_raw_count
) != prev_raw_count
)
308 * Now we have the new raw value and have updated the prev
309 * timestamp already. We can now calculate the elapsed delta
310 * (event-)time and add that to the generic event.
312 * Careful, not all hw sign-extends above the physical width
315 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
318 local64_add(delta
, &event
->count
);
319 local64_sub(delta
, &hwc
->period_left
);
321 return new_raw_count
;
324 static atomic_t active_events
;
325 static DEFINE_MUTEX(pmc_reserve_mutex
);
327 #ifdef CONFIG_X86_LOCAL_APIC
329 static bool reserve_pmc_hardware(void)
333 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
334 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
338 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
339 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
346 for (i
--; i
>= 0; i
--)
347 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
349 i
= x86_pmu
.num_counters
;
352 for (i
--; i
>= 0; i
--)
353 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
358 static void release_pmc_hardware(void)
362 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
363 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
364 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
370 static bool reserve_pmc_hardware(void) { return true; }
371 static void release_pmc_hardware(void) {}
375 static bool check_hw_exists(void)
377 u64 val
, val_new
= 0;
381 * Check to see if the BIOS enabled any of the counters, if so
384 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
385 reg
= x86_pmu
.eventsel
+ i
;
386 ret
= rdmsrl_safe(reg
, &val
);
389 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
)
393 if (x86_pmu
.num_counters_fixed
) {
394 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
395 ret
= rdmsrl_safe(reg
, &val
);
398 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
399 if (val
& (0x03 << i
*4))
405 * Now write a value and read it back to see if it matches,
406 * this is needed to detect certain hardware emulators (qemu/kvm)
407 * that don't trap on the MSR access and always return 0s.
410 ret
= checking_wrmsrl(x86_pmu
.perfctr
, val
);
411 ret
|= rdmsrl_safe(x86_pmu
.perfctr
, &val_new
);
412 if (ret
|| val
!= val_new
)
418 printk(KERN_CONT
"Broken BIOS detected, using software events only.\n");
419 printk(KERN_ERR FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg
, val
);
423 printk(KERN_CONT
"Broken PMU hardware detected, using software events only.\n");
427 static void reserve_ds_buffers(void);
428 static void release_ds_buffers(void);
430 static void hw_perf_event_destroy(struct perf_event
*event
)
432 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
433 release_pmc_hardware();
434 release_ds_buffers();
435 mutex_unlock(&pmc_reserve_mutex
);
439 static inline int x86_pmu_initialized(void)
441 return x86_pmu
.handle_irq
!= NULL
;
445 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event_attr
*attr
)
447 unsigned int cache_type
, cache_op
, cache_result
;
450 config
= attr
->config
;
452 cache_type
= (config
>> 0) & 0xff;
453 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
456 cache_op
= (config
>> 8) & 0xff;
457 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
460 cache_result
= (config
>> 16) & 0xff;
461 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
464 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
477 static int x86_setup_perfctr(struct perf_event
*event
)
479 struct perf_event_attr
*attr
= &event
->attr
;
480 struct hw_perf_event
*hwc
= &event
->hw
;
483 if (!is_sampling_event(event
)) {
484 hwc
->sample_period
= x86_pmu
.max_period
;
485 hwc
->last_period
= hwc
->sample_period
;
486 local64_set(&hwc
->period_left
, hwc
->sample_period
);
489 * If we have a PMU initialized but no APIC
490 * interrupts, we cannot sample hardware
491 * events (user-space has to fall back and
492 * sample via a hrtimer based software event):
498 if (attr
->type
== PERF_TYPE_RAW
)
501 if (attr
->type
== PERF_TYPE_HW_CACHE
)
502 return set_ext_hw_attr(hwc
, attr
);
504 if (attr
->config
>= x86_pmu
.max_events
)
510 config
= x86_pmu
.event_map(attr
->config
);
521 if ((attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
) &&
522 (hwc
->sample_period
== 1)) {
523 /* BTS is not supported by this architecture. */
524 if (!x86_pmu
.bts_active
)
527 /* BTS is currently only allowed for user-mode. */
528 if (!attr
->exclude_kernel
)
532 hwc
->config
|= config
;
537 static int x86_pmu_hw_config(struct perf_event
*event
)
539 if (event
->attr
.precise_ip
) {
542 /* Support for constant skid */
543 if (x86_pmu
.pebs_active
) {
546 /* Support for IP fixup */
551 if (event
->attr
.precise_ip
> precise
)
557 * (keep 'enabled' bit clear for now)
559 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
562 * Count user and OS events unless requested not to
564 if (!event
->attr
.exclude_user
)
565 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
566 if (!event
->attr
.exclude_kernel
)
567 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
569 if (event
->attr
.type
== PERF_TYPE_RAW
)
570 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
572 return x86_setup_perfctr(event
);
576 * Setup the hardware configuration for a given attr_type
578 static int __x86_pmu_event_init(struct perf_event
*event
)
582 if (!x86_pmu_initialized())
586 if (!atomic_inc_not_zero(&active_events
)) {
587 mutex_lock(&pmc_reserve_mutex
);
588 if (atomic_read(&active_events
) == 0) {
589 if (!reserve_pmc_hardware())
592 reserve_ds_buffers();
595 atomic_inc(&active_events
);
596 mutex_unlock(&pmc_reserve_mutex
);
601 event
->destroy
= hw_perf_event_destroy
;
604 event
->hw
.last_cpu
= -1;
605 event
->hw
.last_tag
= ~0ULL;
607 return x86_pmu
.hw_config(event
);
610 static void x86_pmu_disable_all(void)
612 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
615 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
618 if (!test_bit(idx
, cpuc
->active_mask
))
620 rdmsrl(x86_pmu
.eventsel
+ idx
, val
);
621 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
623 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
624 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
628 static void x86_pmu_disable(struct pmu
*pmu
)
630 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
632 if (!x86_pmu_initialized())
642 x86_pmu
.disable_all();
645 static void x86_pmu_enable_all(int added
)
647 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
650 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
651 struct perf_event
*event
= cpuc
->events
[idx
];
654 if (!test_bit(idx
, cpuc
->active_mask
))
657 val
= event
->hw
.config
;
658 val
|= ARCH_PERFMON_EVENTSEL_ENABLE
;
659 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
663 static struct pmu pmu
;
665 static inline int is_x86_event(struct perf_event
*event
)
667 return event
->pmu
== &pmu
;
670 static int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
672 struct event_constraint
*c
, *constraints
[X86_PMC_IDX_MAX
];
673 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
674 int i
, j
, w
, wmax
, num
= 0;
675 struct hw_perf_event
*hwc
;
677 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
679 for (i
= 0; i
< n
; i
++) {
680 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
685 * fastpath, try to reuse previous register
687 for (i
= 0; i
< n
; i
++) {
688 hwc
= &cpuc
->event_list
[i
]->hw
;
695 /* constraint still honored */
696 if (!test_bit(hwc
->idx
, c
->idxmsk
))
699 /* not already used */
700 if (test_bit(hwc
->idx
, used_mask
))
703 __set_bit(hwc
->idx
, used_mask
);
705 assign
[i
] = hwc
->idx
;
714 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
717 * weight = number of possible counters
719 * 1 = most constrained, only works on one counter
720 * wmax = least constrained, works on any counter
722 * assign events to counters starting with most
723 * constrained events.
725 wmax
= x86_pmu
.num_counters
;
728 * when fixed event counters are present,
729 * wmax is incremented by 1 to account
730 * for one more choice
732 if (x86_pmu
.num_counters_fixed
)
735 for (w
= 1, num
= n
; num
&& w
<= wmax
; w
++) {
737 for (i
= 0; num
&& i
< n
; i
++) {
739 hwc
= &cpuc
->event_list
[i
]->hw
;
744 for_each_set_bit(j
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
745 if (!test_bit(j
, used_mask
))
749 if (j
== X86_PMC_IDX_MAX
)
752 __set_bit(j
, used_mask
);
761 * scheduling failed or is just a simulation,
762 * free resources if necessary
764 if (!assign
|| num
) {
765 for (i
= 0; i
< n
; i
++) {
766 if (x86_pmu
.put_event_constraints
)
767 x86_pmu
.put_event_constraints(cpuc
, cpuc
->event_list
[i
]);
770 return num
? -ENOSPC
: 0;
774 * dogrp: true if must collect siblings events (group)
775 * returns total number of events and error code
777 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
779 struct perf_event
*event
;
782 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
784 /* current number of events already accepted */
787 if (is_x86_event(leader
)) {
790 cpuc
->event_list
[n
] = leader
;
796 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
797 if (!is_x86_event(event
) ||
798 event
->state
<= PERF_EVENT_STATE_OFF
)
804 cpuc
->event_list
[n
] = event
;
810 static inline void x86_assign_hw_event(struct perf_event
*event
,
811 struct cpu_hw_events
*cpuc
, int i
)
813 struct hw_perf_event
*hwc
= &event
->hw
;
815 hwc
->idx
= cpuc
->assign
[i
];
816 hwc
->last_cpu
= smp_processor_id();
817 hwc
->last_tag
= ++cpuc
->tags
[i
];
819 if (hwc
->idx
== X86_PMC_IDX_FIXED_BTS
) {
820 hwc
->config_base
= 0;
822 } else if (hwc
->idx
>= X86_PMC_IDX_FIXED
) {
823 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
825 * We set it so that event_base + idx in wrmsr/rdmsr maps to
826 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
829 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
831 hwc
->config_base
= x86_pmu
.eventsel
;
832 hwc
->event_base
= x86_pmu
.perfctr
;
836 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
837 struct cpu_hw_events
*cpuc
,
840 return hwc
->idx
== cpuc
->assign
[i
] &&
841 hwc
->last_cpu
== smp_processor_id() &&
842 hwc
->last_tag
== cpuc
->tags
[i
];
845 static void x86_pmu_start(struct perf_event
*event
, int flags
);
846 static void x86_pmu_stop(struct perf_event
*event
, int flags
);
848 static void x86_pmu_enable(struct pmu
*pmu
)
850 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
851 struct perf_event
*event
;
852 struct hw_perf_event
*hwc
;
853 int i
, added
= cpuc
->n_added
;
855 if (!x86_pmu_initialized())
862 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
864 * apply assignment obtained either from
865 * hw_perf_group_sched_in() or x86_pmu_enable()
867 * step1: save events moving to new counters
868 * step2: reprogram moved events into new counters
870 for (i
= 0; i
< n_running
; i
++) {
871 event
= cpuc
->event_list
[i
];
875 * we can avoid reprogramming counter if:
876 * - assigned same counter as last time
877 * - running on same CPU as last time
878 * - no other event has used the counter since
880 if (hwc
->idx
== -1 ||
881 match_prev_assignment(hwc
, cpuc
, i
))
885 * Ensure we don't accidentally enable a stopped
886 * counter simply because we rescheduled.
888 if (hwc
->state
& PERF_HES_STOPPED
)
889 hwc
->state
|= PERF_HES_ARCH
;
891 x86_pmu_stop(event
, PERF_EF_UPDATE
);
894 for (i
= 0; i
< cpuc
->n_events
; i
++) {
895 event
= cpuc
->event_list
[i
];
898 if (!match_prev_assignment(hwc
, cpuc
, i
))
899 x86_assign_hw_event(event
, cpuc
, i
);
900 else if (i
< n_running
)
903 if (hwc
->state
& PERF_HES_ARCH
)
906 x86_pmu_start(event
, PERF_EF_RELOAD
);
909 perf_events_lapic_init();
915 x86_pmu
.enable_all(added
);
918 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
,
921 wrmsrl(hwc
->config_base
+ hwc
->idx
, hwc
->config
| enable_mask
);
924 static inline void x86_pmu_disable_event(struct perf_event
*event
)
926 struct hw_perf_event
*hwc
= &event
->hw
;
928 wrmsrl(hwc
->config_base
+ hwc
->idx
, hwc
->config
);
931 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
934 * Set the next IRQ period, based on the hwc->period_left value.
935 * To be called with the event disabled in hw:
938 x86_perf_event_set_period(struct perf_event
*event
)
940 struct hw_perf_event
*hwc
= &event
->hw
;
941 s64 left
= local64_read(&hwc
->period_left
);
942 s64 period
= hwc
->sample_period
;
943 int ret
= 0, idx
= hwc
->idx
;
945 if (idx
== X86_PMC_IDX_FIXED_BTS
)
949 * If we are way outside a reasonable range then just skip forward:
951 if (unlikely(left
<= -period
)) {
953 local64_set(&hwc
->period_left
, left
);
954 hwc
->last_period
= period
;
958 if (unlikely(left
<= 0)) {
960 local64_set(&hwc
->period_left
, left
);
961 hwc
->last_period
= period
;
965 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
967 if (unlikely(left
< 2))
970 if (left
> x86_pmu
.max_period
)
971 left
= x86_pmu
.max_period
;
973 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
976 * The hw event starts counting from this event offset,
977 * mark it to be able to extra future deltas:
979 local64_set(&hwc
->prev_count
, (u64
)-left
);
981 wrmsrl(hwc
->event_base
+ idx
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
984 * Due to erratum on certan cpu we need
985 * a second write to be sure the register
986 * is updated properly
988 if (x86_pmu
.perfctr_second_write
) {
989 wrmsrl(hwc
->event_base
+ idx
,
990 (u64
)(-left
) & x86_pmu
.cntval_mask
);
993 perf_event_update_userpage(event
);
998 static void x86_pmu_enable_event(struct perf_event
*event
)
1000 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1002 __x86_pmu_enable_event(&event
->hw
,
1003 ARCH_PERFMON_EVENTSEL_ENABLE
);
1007 * Add a single event to the PMU.
1009 * The event is added to the group of enabled events
1010 * but only if it can be scehduled with existing events.
1012 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1014 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1015 struct hw_perf_event
*hwc
;
1016 int assign
[X86_PMC_IDX_MAX
];
1021 perf_pmu_disable(event
->pmu
);
1022 n0
= cpuc
->n_events
;
1023 ret
= n
= collect_events(cpuc
, event
, false);
1027 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1028 if (!(flags
& PERF_EF_START
))
1029 hwc
->state
|= PERF_HES_ARCH
;
1032 * If group events scheduling transaction was started,
1033 * skip the schedulability test here, it will be peformed
1034 * at commit time (->commit_txn) as a whole
1036 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1039 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1043 * copy new assignment, now we know it is possible
1044 * will be used by hw_perf_enable()
1046 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1050 cpuc
->n_added
+= n
- n0
;
1051 cpuc
->n_txn
+= n
- n0
;
1055 perf_pmu_enable(event
->pmu
);
1059 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1061 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1062 int idx
= event
->hw
.idx
;
1064 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1067 if (WARN_ON_ONCE(idx
== -1))
1070 if (flags
& PERF_EF_RELOAD
) {
1071 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1072 x86_perf_event_set_period(event
);
1075 event
->hw
.state
= 0;
1077 cpuc
->events
[idx
] = event
;
1078 __set_bit(idx
, cpuc
->active_mask
);
1079 __set_bit(idx
, cpuc
->running
);
1080 x86_pmu
.enable(event
);
1081 perf_event_update_userpage(event
);
1084 void perf_event_print_debug(void)
1086 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1088 struct cpu_hw_events
*cpuc
;
1089 unsigned long flags
;
1092 if (!x86_pmu
.num_counters
)
1095 local_irq_save(flags
);
1097 cpu
= smp_processor_id();
1098 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1100 if (x86_pmu
.version
>= 2) {
1101 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1102 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1103 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1104 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1105 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1108 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1109 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1110 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1111 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1112 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1114 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1116 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1117 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
1118 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
1120 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1122 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1123 cpu
, idx
, pmc_ctrl
);
1124 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1125 cpu
, idx
, pmc_count
);
1126 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1127 cpu
, idx
, prev_left
);
1129 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1130 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1132 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1133 cpu
, idx
, pmc_count
);
1135 local_irq_restore(flags
);
1138 static void x86_pmu_stop(struct perf_event
*event
, int flags
)
1140 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1141 struct hw_perf_event
*hwc
= &event
->hw
;
1143 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1144 x86_pmu
.disable(event
);
1145 cpuc
->events
[hwc
->idx
] = NULL
;
1146 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1147 hwc
->state
|= PERF_HES_STOPPED
;
1150 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1152 * Drain the remaining delta count out of a event
1153 * that we are disabling:
1155 x86_perf_event_update(event
);
1156 hwc
->state
|= PERF_HES_UPTODATE
;
1160 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1162 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1166 * If we're called during a txn, we don't need to do anything.
1167 * The events never got scheduled and ->cancel_txn will truncate
1170 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1173 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1175 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1176 if (event
== cpuc
->event_list
[i
]) {
1178 if (x86_pmu
.put_event_constraints
)
1179 x86_pmu
.put_event_constraints(cpuc
, event
);
1181 while (++i
< cpuc
->n_events
)
1182 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1188 perf_event_update_userpage(event
);
1191 static int x86_pmu_handle_irq(struct pt_regs
*regs
)
1193 struct perf_sample_data data
;
1194 struct cpu_hw_events
*cpuc
;
1195 struct perf_event
*event
;
1196 int idx
, handled
= 0;
1199 perf_sample_data_init(&data
, 0);
1201 cpuc
= &__get_cpu_var(cpu_hw_events
);
1203 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1204 if (!test_bit(idx
, cpuc
->active_mask
)) {
1206 * Though we deactivated the counter some cpus
1207 * might still deliver spurious interrupts still
1208 * in flight. Catch them:
1210 if (__test_and_clear_bit(idx
, cpuc
->running
))
1215 event
= cpuc
->events
[idx
];
1217 val
= x86_perf_event_update(event
);
1218 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1225 data
.period
= event
->hw
.last_period
;
1227 if (!x86_perf_event_set_period(event
))
1230 if (perf_event_overflow(event
, 1, &data
, regs
))
1231 x86_pmu_stop(event
, 0);
1235 inc_irq_stat(apic_perf_irqs
);
1240 void perf_events_lapic_init(void)
1242 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1246 * Always use NMI for PMU
1248 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1251 struct pmu_nmi_state
{
1252 unsigned int marked
;
1256 static DEFINE_PER_CPU(struct pmu_nmi_state
, pmu_nmi
);
1258 static int __kprobes
1259 perf_event_nmi_handler(struct notifier_block
*self
,
1260 unsigned long cmd
, void *__args
)
1262 struct die_args
*args
= __args
;
1263 unsigned int this_nmi
;
1266 if (!atomic_read(&active_events
))
1273 case DIE_NMIUNKNOWN
:
1274 this_nmi
= percpu_read(irq_stat
.__nmi_count
);
1275 if (this_nmi
!= __get_cpu_var(pmu_nmi
).marked
)
1276 /* let the kernel handle the unknown nmi */
1279 * This one is a PMU back-to-back nmi. Two events
1280 * trigger 'simultaneously' raising two back-to-back
1281 * NMIs. If the first NMI handles both, the latter
1282 * will be empty and daze the CPU. So, we drop it to
1283 * avoid false-positive 'unknown nmi' messages.
1290 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1292 handled
= x86_pmu
.handle_irq(args
->regs
);
1296 this_nmi
= percpu_read(irq_stat
.__nmi_count
);
1297 if ((handled
> 1) ||
1298 /* the next nmi could be a back-to-back nmi */
1299 ((__get_cpu_var(pmu_nmi
).marked
== this_nmi
) &&
1300 (__get_cpu_var(pmu_nmi
).handled
> 1))) {
1302 * We could have two subsequent back-to-back nmis: The
1303 * first handles more than one counter, the 2nd
1304 * handles only one counter and the 3rd handles no
1307 * This is the 2nd nmi because the previous was
1308 * handling more than one counter. We will mark the
1309 * next (3rd) and then drop it if unhandled.
1311 __get_cpu_var(pmu_nmi
).marked
= this_nmi
+ 1;
1312 __get_cpu_var(pmu_nmi
).handled
= handled
;
1318 static __read_mostly
struct notifier_block perf_event_nmi_notifier
= {
1319 .notifier_call
= perf_event_nmi_handler
,
1321 .priority
= NMI_LOCAL_LOW_PRIOR
,
1324 static struct event_constraint unconstrained
;
1325 static struct event_constraint emptyconstraint
;
1327 static struct event_constraint
*
1328 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
)
1330 struct event_constraint
*c
;
1332 if (x86_pmu
.event_constraints
) {
1333 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1334 if ((event
->hw
.config
& c
->cmask
) == c
->code
)
1339 return &unconstrained
;
1342 #include "perf_event_amd.c"
1343 #include "perf_event_p6.c"
1344 #include "perf_event_p4.c"
1345 #include "perf_event_intel_lbr.c"
1346 #include "perf_event_intel_ds.c"
1347 #include "perf_event_intel.c"
1349 static int __cpuinit
1350 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1352 unsigned int cpu
= (long)hcpu
;
1353 int ret
= NOTIFY_OK
;
1355 switch (action
& ~CPU_TASKS_FROZEN
) {
1356 case CPU_UP_PREPARE
:
1357 if (x86_pmu
.cpu_prepare
)
1358 ret
= x86_pmu
.cpu_prepare(cpu
);
1362 if (x86_pmu
.cpu_starting
)
1363 x86_pmu
.cpu_starting(cpu
);
1367 if (x86_pmu
.cpu_dying
)
1368 x86_pmu
.cpu_dying(cpu
);
1371 case CPU_UP_CANCELED
:
1373 if (x86_pmu
.cpu_dead
)
1374 x86_pmu
.cpu_dead(cpu
);
1384 static void __init
pmu_check_apic(void)
1390 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1391 pr_info("no hardware sampling interrupt available.\n");
1394 int __init
init_hw_perf_events(void)
1396 struct event_constraint
*c
;
1399 pr_info("Performance Events: ");
1401 switch (boot_cpu_data
.x86_vendor
) {
1402 case X86_VENDOR_INTEL
:
1403 err
= intel_pmu_init();
1405 case X86_VENDOR_AMD
:
1406 err
= amd_pmu_init();
1412 pr_cont("no PMU driver, software events only.\n");
1418 /* sanity check that the hardware exists or is emulated */
1419 if (!check_hw_exists())
1422 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1427 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
1428 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
1429 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
1430 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
1432 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1434 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
1435 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
1436 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
1437 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
1440 x86_pmu
.intel_ctrl
|=
1441 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1443 perf_events_lapic_init();
1444 register_die_notifier(&perf_event_nmi_notifier
);
1446 unconstrained
= (struct event_constraint
)
1447 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1448 0, x86_pmu
.num_counters
);
1450 if (x86_pmu
.event_constraints
) {
1451 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1452 if (c
->cmask
!= X86_RAW_EVENT_MASK
)
1455 c
->idxmsk64
|= (1ULL << x86_pmu
.num_counters
) - 1;
1456 c
->weight
+= x86_pmu
.num_counters
;
1460 pr_info("... version: %d\n", x86_pmu
.version
);
1461 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1462 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1463 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1464 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1465 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1466 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1468 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1469 perf_cpu_notifier(x86_pmu_notifier
);
1473 early_initcall(init_hw_perf_events
);
1475 static inline void x86_pmu_read(struct perf_event
*event
)
1477 x86_perf_event_update(event
);
1481 * Start group events scheduling transaction
1482 * Set the flag to make pmu::enable() not perform the
1483 * schedulability test, it will be performed at commit time
1485 static void x86_pmu_start_txn(struct pmu
*pmu
)
1487 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1489 perf_pmu_disable(pmu
);
1490 cpuc
->group_flag
|= PERF_EVENT_TXN
;
1495 * Stop group events scheduling transaction
1496 * Clear the flag and pmu::enable() will perform the
1497 * schedulability test.
1499 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1501 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1503 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1505 * Truncate the collected events.
1507 cpuc
->n_added
-= cpuc
->n_txn
;
1508 cpuc
->n_events
-= cpuc
->n_txn
;
1509 perf_pmu_enable(pmu
);
1513 * Commit group events scheduling transaction
1514 * Perform the group schedulability test as a whole
1515 * Return 0 if success
1517 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1519 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1520 int assign
[X86_PMC_IDX_MAX
];
1525 if (!x86_pmu_initialized())
1528 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1533 * copy new assignment, now we know it is possible
1534 * will be used by hw_perf_enable()
1536 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1538 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1539 perf_pmu_enable(pmu
);
1544 * validate that we can schedule this event
1546 static int validate_event(struct perf_event
*event
)
1548 struct cpu_hw_events
*fake_cpuc
;
1549 struct event_constraint
*c
;
1552 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1556 c
= x86_pmu
.get_event_constraints(fake_cpuc
, event
);
1558 if (!c
|| !c
->weight
)
1561 if (x86_pmu
.put_event_constraints
)
1562 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1570 * validate a single event group
1572 * validation include:
1573 * - check events are compatible which each other
1574 * - events do not compete for the same counter
1575 * - number of events <= number of counters
1577 * validation ensures the group can be loaded onto the
1578 * PMU if it was the only group available.
1580 static int validate_group(struct perf_event
*event
)
1582 struct perf_event
*leader
= event
->group_leader
;
1583 struct cpu_hw_events
*fake_cpuc
;
1587 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1592 * the event is not yet connected with its
1593 * siblings therefore we must first collect
1594 * existing siblings, then add the new event
1595 * before we can simulate the scheduling
1598 n
= collect_events(fake_cpuc
, leader
, true);
1602 fake_cpuc
->n_events
= n
;
1603 n
= collect_events(fake_cpuc
, event
, false);
1607 fake_cpuc
->n_events
= n
;
1609 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1617 int x86_pmu_event_init(struct perf_event
*event
)
1622 switch (event
->attr
.type
) {
1624 case PERF_TYPE_HARDWARE
:
1625 case PERF_TYPE_HW_CACHE
:
1632 err
= __x86_pmu_event_init(event
);
1635 * we temporarily connect event to its pmu
1636 * such that validate_group() can classify
1637 * it as an x86 event using is_x86_event()
1642 if (event
->group_leader
!= event
)
1643 err
= validate_group(event
);
1645 err
= validate_event(event
);
1651 event
->destroy(event
);
1657 static struct pmu pmu
= {
1658 .pmu_enable
= x86_pmu_enable
,
1659 .pmu_disable
= x86_pmu_disable
,
1661 .event_init
= x86_pmu_event_init
,
1665 .start
= x86_pmu_start
,
1666 .stop
= x86_pmu_stop
,
1667 .read
= x86_pmu_read
,
1669 .start_txn
= x86_pmu_start_txn
,
1670 .cancel_txn
= x86_pmu_cancel_txn
,
1671 .commit_txn
= x86_pmu_commit_txn
,
1679 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1681 /* Ignore warnings */
1684 static void backtrace_warning(void *data
, char *msg
)
1686 /* Ignore warnings */
1689 static int backtrace_stack(void *data
, char *name
)
1694 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1696 struct perf_callchain_entry
*entry
= data
;
1698 perf_callchain_store(entry
, addr
);
1701 static const struct stacktrace_ops backtrace_ops
= {
1702 .warning
= backtrace_warning
,
1703 .warning_symbol
= backtrace_warning_symbol
,
1704 .stack
= backtrace_stack
,
1705 .address
= backtrace_address
,
1706 .walk_stack
= print_context_stack_bp
,
1710 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1712 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1713 /* TODO: We don't support guest os callchain now */
1717 perf_callchain_store(entry
, regs
->ip
);
1719 dump_trace(NULL
, regs
, NULL
, &backtrace_ops
, entry
);
1722 #ifdef CONFIG_COMPAT
1724 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1726 /* 32-bit process in 64-bit kernel. */
1727 struct stack_frame_ia32 frame
;
1728 const void __user
*fp
;
1730 if (!test_thread_flag(TIF_IA32
))
1733 fp
= compat_ptr(regs
->bp
);
1734 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1735 unsigned long bytes
;
1736 frame
.next_frame
= 0;
1737 frame
.return_address
= 0;
1739 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1740 if (bytes
!= sizeof(frame
))
1743 if (fp
< compat_ptr(regs
->sp
))
1746 perf_callchain_store(entry
, frame
.return_address
);
1747 fp
= compat_ptr(frame
.next_frame
);
1753 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1760 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1762 struct stack_frame frame
;
1763 const void __user
*fp
;
1765 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1766 /* TODO: We don't support guest os callchain now */
1770 fp
= (void __user
*)regs
->bp
;
1772 perf_callchain_store(entry
, regs
->ip
);
1774 if (perf_callchain_user32(regs
, entry
))
1777 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1778 unsigned long bytes
;
1779 frame
.next_frame
= NULL
;
1780 frame
.return_address
= 0;
1782 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1783 if (bytes
!= sizeof(frame
))
1786 if ((unsigned long)fp
< regs
->sp
)
1789 perf_callchain_store(entry
, frame
.return_address
);
1790 fp
= frame
.next_frame
;
1794 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
1798 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
1799 ip
= perf_guest_cbs
->get_guest_ip();
1801 ip
= instruction_pointer(regs
);
1806 unsigned long perf_misc_flags(struct pt_regs
*regs
)
1810 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1811 if (perf_guest_cbs
->is_user_mode())
1812 misc
|= PERF_RECORD_MISC_GUEST_USER
;
1814 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
1816 if (user_mode(regs
))
1817 misc
|= PERF_RECORD_MISC_USER
;
1819 misc
|= PERF_RECORD_MISC_KERNEL
;
1822 if (regs
->flags
& PERF_EFLAGS_EXACT
)
1823 misc
|= PERF_RECORD_MISC_EXACT_IP
;