2 * Copyright (C) 2003-2004 Intel
3 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
10 * MSI-X Address Register
12 #define PCI_MSIX_FLAGS_QSIZE 0x7FF
13 #define PCI_MSIX_FLAGS_ENABLE (1 << 15)
14 #define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
15 #define PCI_MSIX_FLAGS_BITMASK (1 << 0)
17 #define PCI_MSIX_ENTRY_SIZE 16
18 #define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
19 #define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
20 #define PCI_MSIX_ENTRY_DATA_OFFSET 8
21 #define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12
23 #define msi_control_reg(base) (base + PCI_MSI_FLAGS)
24 #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
25 #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
26 #define msi_data_reg(base, is64bit) \
27 ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
28 #define msi_mask_bits_reg(base, is64bit) \
29 ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
30 #define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE
31 #define multi_msi_capable(control) \
32 (1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
33 #define multi_msi_enable(control, num) \
34 control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
35 #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT))
36 #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT))
37 #define msi_enable(control, num) multi_msi_enable(control, num); \
38 control |= PCI_MSI_FLAGS_ENABLE
40 #define msix_table_offset_reg(base) (base + 0x04)
41 #define msix_pba_offset_reg(base) (base + 0x08)
42 #define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE
43 #define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE
44 #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
45 #define multi_msix_capable msix_table_size
46 #define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK)
47 #define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
48 #define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)